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Sat, 11 Jul 2026 15:28:47 -0400 (EDT) From: Samuel Holland To: Heiko Stuebner , Conor Dooley , Krzysztof Kozlowski , Rob Herring Cc: linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-leds@vger.kernel.org, Lee Jones , Pavel Machek , linux-arm-kernel@lists.infradead.org, Samuel Holland Subject: [PATCH 1/4] dt-bindings: leds: Document "gpio" trigger Date: Sat, 11 Jul 2026 14:28:25 -0500 Message-ID: <20260711192842.845048-2-samuel@sholland.org> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260711192842.845048-1-samuel@sholland.org> References: <20260711192842.845048-1-samuel@sholland.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The "gpio" trigger is used to control LEDs by the level of a GPIO input referenced by the trigger-sources property. This is already documented in the trigger-sources property description and is used in at least one devicetree (am335x-regor.dtsi). Document it so validation of those and future DTs will pass. Signed-off-by: Samuel Holland Acked-by: Conor Dooley --- Documentation/devicetree/bindings/leds/common.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/leds/common.yaml b/Documenta= tion/devicetree/bindings/leds/common.yaml index f4e44b33f56d..e148b4277a6f 100644 --- a/Documentation/devicetree/bindings/leds/common.yaml +++ b/Documentation/devicetree/bindings/leds/common.yaml @@ -106,6 +106,8 @@ properties: - bluetooth-power # LED indicates camera flash state - flash + # LED indicates level of GPIO input referenced by trigger-sour= ces + - gpio # LED indicated keyboard capslock - kbd-capslock # LED indicates MTD memory activity --=20 2.54.0 From nobody Sat Jul 25 23:05:53 2026 Received: from fhigh-b7-smtp.messagingengine.com (fhigh-b7-smtp.messagingengine.com [202.12.124.158]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8E741231A3B; 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Sat, 11 Jul 2026 15:28:50 -0400 (EDT) From: Samuel Holland To: Heiko Stuebner , Conor Dooley , Krzysztof Kozlowski , Rob Herring Cc: linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-leds@vger.kernel.org, Lee Jones , Pavel Machek , linux-arm-kernel@lists.infradead.org, Samuel Holland Subject: [PATCH 2/4] dt-bindings: vendor-prefixes: Add techvision Date: Sat, 11 Jul 2026 14:28:26 -0500 Message-ID: <20260711192842.845048-3-samuel@sholland.org> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260711192842.845048-1-samuel@sholland.org> References: <20260711192842.845048-1-samuel@sholland.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Techvision Intelligent Technology Co., Ltd[1] aka Shenzhen Huiwei Intelligent Technology Co., Ltd[2] is a manufacturer of single-board computers. Link: https://cn.techvision.com.cn/ [1] Link: https://www.techvision.com.cn/ [2] Signed-off-by: Samuel Holland Acked-by: Conor Dooley --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Docum= entation/devicetree/bindings/vendor-prefixes.yaml index 396044f368e7..2355505013a0 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -1662,6 +1662,8 @@ patternProperties: description: Technologic Systems "^techstar,.*": description: Shenzhen Techstar Electronics Co., Ltd. + "^techvision,.*": + description: Techvision Intelligent Technology Co., Ltd "^techwell,.*": description: Techwell, Inc. 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Sat, 11 Jul 2026 15:28:53 -0400 (EDT) From: Samuel Holland To: Heiko Stuebner , Conor Dooley , Krzysztof Kozlowski , Rob Herring Cc: linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-leds@vger.kernel.org, Lee Jones , Pavel Machek , linux-arm-kernel@lists.infradead.org, Samuel Holland Subject: [PATCH 3/4] dt-bindings: arm: rockchip: Add LincStation E1 Date: Sat, 11 Jul 2026 14:28:27 -0500 Message-ID: <20260711192842.845048-4-samuel@sholland.org> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260711192842.845048-1-samuel@sholland.org> References: <20260711192842.845048-1-samuel@sholland.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" LincStation E1 is an entry-level NAS device powered by the RK3568B2 SoC with two 3.5" HDD slots and two m.2 2280 slots for SSDs. It is marketed under the LincPlus[1] brand, but the OEM appears to be Techvision Intelligent Technology Co., Ltd[2]. The OEM model number is TVD8322R, which is referenced by the vendor devicetree, a sticker on the board, and a design patent (CN309443154S) matching the system chassis. Link: https://www.lincplustech.com/products/lincstation-e1-network-attached= -storage.html [1] Link: https://cn.techvision.com.cn [2] Signed-off-by: Samuel Holland Acked-by: Conor Dooley --- Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Document= ation/devicetree/bindings/arm/rockchip.yaml index 1a9dde18626d..ca2e4327ac3f 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -779,6 +779,11 @@ properties: - const: lckfb,tspi-rk3566 - const: rockchip,rk3566 =20 + - description: LincPlus LincStation E1 + items: + - const: techvision,tvd8322r + - const: rockchip,rk3568 + - description: LinkEase EasePi R1 items: - const: linkease,easepi-r1 --=20 2.54.0 From nobody Sat Jul 25 23:05:53 2026 Received: from fhigh-b7-smtp.messagingengine.com (fhigh-b7-smtp.messagingengine.com [202.12.124.158]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6B1DA1F3BAC; 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Sat, 11 Jul 2026 15:28:56 -0400 (EDT) From: Samuel Holland To: Heiko Stuebner , Conor Dooley , Krzysztof Kozlowski , Rob Herring Cc: linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-leds@vger.kernel.org, Lee Jones , Pavel Machek , linux-arm-kernel@lists.infradead.org, Samuel Holland Subject: [PATCH 4/4] arm64: dts: rockchip: Add LincStation E1 Date: Sat, 11 Jul 2026 14:28:28 -0500 Message-ID: <20260711192842.845048-5-samuel@sholland.org> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260711192842.845048-1-samuel@sholland.org> References: <20260711192842.845048-1-samuel@sholland.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable LincStation E1 is an entry-level NAS device powered by the RK3568B2 SoC with two 3.5" HDD slots (behind a SATA port multiplier) and two m.2 2280 slots for SSDs (each PCIe 3.0 x1). Other major features include: - 4 GiB DRAM / 64 GB eMMC - RTL8125 2.5 Gb Ethernet - Fn-Link 6222B-SRC Wi-Fi 5 / Bluetooth module - 1 USB 5 Gbps + 2 USB high speed ports - HDMI output Each HDD slot provides a GPIO input for disk presence detection and an output for power control. Since the disks are behind a port multiplier, there is no way to describe them in the devicetree, so the disk power is enabled at all times by GPIO hogs, and the detection inputs are used only as LED triggers. The board contains several pairs of amber/white LEDs for power, disk, m.2 slot, and network status. These are configured to use triggers when possible. The PWM fan uses a relatively aggressive fan curve to keep the hard disks within a safe temperature range. It may benefit from further tuning. The pinhole reset button is multiplexed between the SoC reset pin and an ADC input. The mux is configured here to drive the SoC reset pin, as this works reliably without polling by software. The adc-keys description is included for use by a devicetree overlay if desired. Signed-off-by: Samuel Holland --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../dts/rockchip/rk3568-lincstation-e1.dts | 1004 +++++++++++++++++ 2 files changed, 1005 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-lincstation-e1.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/ro= ckchip/Makefile index 761d82b4f4f2..d0d675892196 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -146,6 +146,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-fastrhino-r66s.= dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-fastrhino-r68s.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-hinlink-h66k.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-hinlink-h68k.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-lincstation-e1.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-lubancat-2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-mecsbc.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-nanopi-r5c.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3568-lincstation-e1.dts b/arch/= arm64/boot/dts/rockchip/rk3568-lincstation-e1.dts new file mode 100644 index 000000000000..ad81b892b00c --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568-lincstation-e1.dts @@ -0,0 +1,1004 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +/dts-v1/; + +#include +#include +#include +#include +#include + +#include "rk3568.dtsi" + +/ { + model =3D "LincPlus LincStation E1"; + compatible =3D "techvision,tvd8322r", "rockchip,rk3568"; + + aliases { + mmc0 =3D &sdhci; + mmc1 =3D &sdmmc1; + rtc0 =3D &hym8563; + }; + + chosen { + stdout-path =3D "serial2:1500000n8"; + }; + + /* This device is only available when reset-button-mux is driven high */ + adc-keys { + compatible =3D "adc-keys"; + io-channels =3D <&saradc 5>; + io-channel-names =3D "buttons"; + keyup-threshold-microvolt =3D <1800000>; + poll-interval =3D <100>; + status =3D "disabled"; + + button-reset { + label =3D "reset"; + linux,code =3D ; + press-threshold-microvolt =3D <0>; + }; + }; + + gpio-leds { + compatible =3D "gpio-leds"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&gpio_leds &sata1_detect &sata2_detect>; + + led-2 { + color =3D ; + function =3D LED_FUNCTION_LAN; + gpios =3D <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>; + linux,default-trigger =3D "netdev"; + }; + + led-3 { + color =3D ; + function =3D LED_FUNCTION_LAN; + gpios =3D <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; + linux,default-trigger =3D "netdev"; + }; + + led-4 { + color =3D ; + function =3D "m1"; + gpios =3D <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; + }; + + led-5 { + color =3D ; + function =3D "m1"; + gpios =3D <&gpio1 RK_PA5 GPIO_ACTIVE_HIGH>; + }; + + led-6 { + color =3D ; + function =3D "m2"; + gpios =3D <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>; + }; + + led-7 { + color =3D ; + function =3D "m2"; + gpios =3D <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>; + }; + + led-8 { + color =3D ; + function =3D "s1"; + gpios =3D <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>; + linux,default-trigger =3D "disk-activity"; + }; + + led-9 { + color =3D ; + function =3D "s1"; + gpios =3D <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>; + linux,default-trigger =3D "gpio"; + trigger-sources =3D <&gpio1 RK_PD6 GPIO_ACTIVE_LOW>; + }; + + led-a { + color =3D ; + function =3D "s2"; + gpios =3D <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + linux,default-trigger =3D "disk-activity"; + }; + + led-b { + color =3D ; + function =3D "s2"; + gpios =3D <&gpio1 RK_PB3 GPIO_ACTIVE_HIGH>; + linux,default-trigger =3D "gpio"; + trigger-sources =3D <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>; + }; + }; + + hdmi-con { + compatible =3D "hdmi-connector"; + type =3D "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint =3D <&hdmi_out_con>; + }; + }; + }; + + fan: pwm-fan { + compatible =3D "pwm-fan"; + interrupt-parent =3D <&gpio0>; + interrupts =3D ; + #cooling-cells =3D <2>; + cooling-levels =3D <0 20 50 90 130 170 210 225 240 255>; + fan-supply =3D <&vcc12v0_sys>; + fan-stop-to-start-percent =3D <8>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&fan_tach>; + pulses-per-revolution =3D <2>; + pwms =3D <&pwm0 0 50000 0>; + }; + + pwm-leds { + compatible =3D "pwm-leds"; + + led-0 { + color =3D ; + default-state =3D "off"; + function =3D LED_FUNCTION_STANDBY; + max-brightness =3D <255>; + pwms =3D <&pwm4 0 25000 0>; + }; + + led-1 { + color =3D ; + default-brightness =3D <127>; + default-state =3D "on"; + function =3D LED_FUNCTION_POWER; + max-brightness =3D <255>; + pwms =3D <&pwm5 0 25000 0>; + }; + }; + + dc_12v: regulator-dc-12v { + compatible =3D "regulator-fixed"; + regulator-name =3D "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <12000000>; + regulator-max-microvolt =3D <12000000>; + }; + + vcc12v0_sys: regulator-vcc12v0-sys { + compatible =3D "regulator-fixed"; + enable-active-high; + gpio =3D <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&vcc12v0_sys_en>; + regulator-name =3D "vcc12v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <12000000>; + regulator-max-microvolt =3D <12000000>; + vin-supply =3D <&dc_12v>; + }; + + vcc3v3_lan: regulator-vcc3v3-lan { + compatible =3D "regulator-fixed"; + enable-active-high; + gpio =3D <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&vcc3v3_lan_en>; + regulator-name =3D "vcc3v3_lan"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + vin-supply =3D <&vcc5v0_sys>; + }; + + vcc3v3_pcie: regulator-vcc3v3-pcie { + compatible =3D "regulator-fixed"; + enable-active-high; + gpio =3D <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&vcc3v3_pcie_en>; + off-on-delay-us =3D <500000>; + regulator-name =3D "vcc3v3_pcie"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + startup-delay-us =3D <5000>; + vin-supply =3D <&dc_12v>; + }; + + vcc3v3_sys: regulator-vcc3v3-sys { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + vin-supply =3D <&dc_12v>; + }; + + vcc5v0_sata: regulator-vcc5v0-sata { + compatible =3D "regulator-fixed"; + enable-active-high; + gpio =3D <&gpio2 RK_PA2 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&vcc5v0_sata_en>; + regulator-name =3D "vcc5v0_sata"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <&dc_12v>; + }; + + vcc5v0_sys: regulator-vcc5v0-sys { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <&dc_12v>; + }; + + vcc5v0_usb: regulator-vcc5v0-usb { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <&dc_12v>; + }; + + vcc5v0_usb_host: regulator-vcc5v0-usb-host { + compatible =3D "regulator-fixed"; + enable-active-high; + gpio =3D <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&vcc5v0_usb_host_en>; + regulator-name =3D "vcc5v0_usb_host"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <&vcc5v0_usb>; + }; + + vcc5v0_usb_otg: regulator-vcc5v0-usb-otg { + compatible =3D "regulator-fixed"; + enable-active-high; + gpio =3D <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&vcc5v0_usb_otg_en>; + regulator-name =3D "vcc5v0_usb_otg"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <&vcc5v0_usb>; + }; + + vcc_wl: regulator-vcc-wl { + compatible =3D "regulator-fixed"; + enable-active-high; + gpio =3D <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&vcc_wl_en>; + regulator-name =3D "vcc_wl"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + vin-supply =3D <&vcc5v0_sys>; + }; + + vccio_wl: regulator-vccio-wl { + compatible =3D "regulator-fixed"; + enable-active-high; + gpio =3D <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&vccio_wl_en>; + regulator-name =3D "vccio_wl"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + vin-supply =3D <&vcc5v0_sys>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible =3D "mmc-pwrseq-simple"; + clocks =3D <&rk809 1>; + clock-names =3D "ext_clock"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&wifi_enable_h>; + post-power-on-delay-ms =3D <200>; + reset-gpios =3D <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>; + }; +}; + +&combphy0 { + status =3D "okay"; +}; + +&combphy1 { + status =3D "okay"; +}; + +&combphy2 { + status =3D "okay"; +}; + +&cpu0 { + cpu-supply =3D <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply =3D <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply =3D <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply =3D <&vdd_cpu>; +}; + +/* + * The fan pulls hot air from the CPU and m.2 slot heat sinks and blows it + * across the hard disks. To keep the disks from overheating (below 50 =C2= =B0C), + * their ambient air, and thus the CPU heat sink, must be kept quite cool. + */ +&cpu_thermal { + trips { + sys_fan1: sys-fan1 { + hysteresis =3D <2000>; + temperature =3D <25000>; + type =3D "active"; + }; + + sys_fan2: sys-fan2 { + hysteresis =3D <2000>; + temperature =3D <35000>; + type =3D "active"; + }; + + sys_fan3: sys-fan3 { + hysteresis =3D <2000>; + temperature =3D <45000>; + type =3D "active"; + }; + }; + + cooling-maps { + map1 { + cooling-device =3D <&fan 1 3>; + trip =3D <&sys_fan1>; + }; + + map2 { + cooling-device =3D <&fan 4 5>; + trip =3D <&sys_fan2>; + }; + + map3 { + cooling-device =3D <&fan 6 THERMAL_NO_LIMIT>; + trip =3D <&sys_fan3>; + }; + }; +}; + +&gpio1 { + /* ata1.01 is the slot labeled HDD2 */ + sata1-power-control-hog { + gpio-hog; + gpios =3D ; + line-name =3D "sata1-power-control"; + output-high; + }; +}; + +&gpio2 { + /* ata1.02 is the slot labeled HDD1 */ + sata2-power-control-hog { + gpio-hog; + gpios =3D ; + line-name =3D "sata2-power-control"; + output-high; + }; +}; + +&gpio4 { + /* low =3D SoC reset, high =3D saradc input */ + reset-button-mux-hog { + gpio-hog; + gpios =3D ; + line-name =3D "reset-button-mux"; + output-low; + }; + + sata-pm-reset-hog { + gpio-hog; + gpios =3D ; + line-name =3D "sata-pm-reset"; + output-low; + }; +}; + +&gpu { + mali-supply =3D <&vdd_gpu>; + status =3D "okay"; +}; + +&hdmi { + avdd-0v9-supply =3D <&vdda0v9_image>; + avdd-1v8-supply =3D <&vcca1v8_image>; + status =3D "okay"; +}; + +&hdmi_in { + hdmi_in_vp0: endpoint { + remote-endpoint =3D <&vp0_out_hdmi>; + }; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint =3D <&hdmi_con_in>; + }; +}; + +&hdmi_sound { + status =3D "okay"; +}; + +&i2c0 { + status =3D "okay"; + + vdd_cpu: regulator@40 { + compatible =3D "silergy,syr827"; + reg =3D <0x40>; + fcs,suspend-voltage-selector =3D <1>; + regulator-name =3D "vdd_cpu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <712500>; + regulator-max-microvolt =3D <1500000>; + regulator-ramp-delay =3D <1000>; + vin-supply =3D <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk809: pmic@20 { + compatible =3D "rockchip,rk809"; + reg =3D <0x20>; + interrupt-parent =3D <&gpio0>; + interrupts =3D ; + #clock-cells =3D <1>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pmic_int>; + system-power-controller; + vcc1-supply =3D <&vcc3v3_sys>; + vcc2-supply =3D <&vcc3v3_sys>; + vcc3-supply =3D <&vcc3v3_sys>; + vcc4-supply =3D <&vcc3v3_sys>; + vcc5-supply =3D <&vcc3v3_sys>; + vcc6-supply =3D <&vcc5v0_sys>; + vcc7-supply =3D <&vcc3v3_sys>; + vcc8-supply =3D <&vcc3v3_sys>; + vcc9-supply =3D <&vcc3v3_sys>; + wakeup-source; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-name =3D "vdd_logic"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode =3D <0x2>; + regulator-min-microvolt =3D <500000>; + regulator-max-microvolt =3D <1350000>; + regulator-ramp-delay =3D <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-name =3D "vdd_gpu"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode =3D <0x2>; + regulator-min-microvolt =3D <500000>; + regulator-max-microvolt =3D <1350000>; + regulator-ramp-delay =3D <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name =3D "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode =3D <0x2>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_npu: DCDC_REG4 { + regulator-name =3D "vdd_npu"; + regulator-initial-mode =3D <0x2>; + regulator-min-microvolt =3D <500000>; + regulator-max-microvolt =3D <1350000>; + regulator-ramp-delay =3D <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG5 { + regulator-name =3D "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <1800000>; + }; + }; + + vdda0v9_image: LDO_REG1 { + regulator-name =3D "vdda0v9_image"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-name =3D "vdda_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-name =3D "vdda0v9_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <900000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-name =3D "vccio_acodec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-name =3D "vccio_sd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-name =3D "vcc3v3_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <3300000>; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-name =3D "vcca_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG8 { + regulator-name =3D "vcca1v8_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <1800000>; + }; + }; + + vcca1v8_image: LDO_REG9 { + regulator-name =3D "vcca1v8_image"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3: SWITCH_REG1 { + regulator-name =3D "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: SWITCH_REG2 { + regulator-name =3D "vcc3v3_sd"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&i2c1 { + status =3D "okay"; + + hym8563: rtc@51 { + compatible =3D "haoyu,hym8563"; + reg =3D <0x51>; + interrupt-parent =3D <&gpio0>; + interrupts =3D ; + #clock-cells =3D <0>; + clock-output-names =3D "rtcic_32kout"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&hym8563_int>; + wakeup-source; + }; +}; + +&i2s0_8ch { + status =3D "okay"; +}; + +&pcie2x1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pcie2x1_rst>; + reset-gpios =3D <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply =3D <&vcc3v3_lan>; + status =3D "okay"; +}; + +&pcie30phy { + data-lanes =3D <1 2>; + status =3D "okay"; +}; + +&pcie3x1 { + reset-gpios =3D <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply =3D <&vcc3v3_pcie>; + status =3D "okay"; +}; + +&pcie3x2 { + num-lanes =3D <1>; + reset-gpios =3D <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply =3D <&vcc3v3_pcie>; + status =3D "okay"; +}; + +&pinctrl { + bluetooth { + bt_device_wake_h: bt-device-wake-h { + rockchip,pins =3D <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_enable_h: bt-enable-h { + rockchip,pins =3D <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_host_wake_h: bt-host-wake-h { + rockchip,pins =3D <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + gpio-leds { + gpio_leds: gpio-leds { + rockchip,pins =3D <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>, + <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>, + <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>, + <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>, + <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>, + <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>, + <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>, + <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>, + <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>, + <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins =3D <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + pcie { + pcie2x1_rst: pcie2x1-rst { + rockchip,pins =3D <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc3v3_lan_en: vcc3v3-lan-en { + rockchip,pins =3D <4 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc3v3_pcie_en: vcc3v3-pcie-en { + rockchip,pins =3D <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int: pmic-int { + rockchip,pins =3D <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + pwm-fan { + fan_tach: fan-tach { + rockchip,pins =3D <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc12v0_sys_en: vcc12v0-sys-en { + rockchip,pins =3D <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sata { + sata1_detect: sata1-detect { + rockchip,pins =3D <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + sata2_detect: sata2-detect { + rockchip,pins =3D <1 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + vcc5v0_sata_en: vcc5v0-sata-en { + rockchip,pins =3D <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + vcc5v0_usb_host_en: vcc5v0-usb-host-en { + rockchip,pins =3D <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_usb_otg_en: vcc5v0-usb-otg-en { + rockchip,pins =3D <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wlan { + vcc_wl_en: vcc-wl-en { + rockchip,pins =3D <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vccio_wl_en: vccio-wl-en { + rockchip,pins =3D <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wifi_enable_h: wifi-enable-h { + rockchip,pins =3D <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wifi_host_wake_h: wifi-host-wake-h { + rockchip,pins =3D <2 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; +}; + +&pmu_io_domains { + pmuio1-supply =3D <&vcc3v3_pmu>; + pmuio2-supply =3D <&vcc3v3_pmu>; + vccio1-supply =3D <&vccio_acodec>; + vccio2-supply =3D <&vcc_1v8>; + vccio3-supply =3D <&vccio_sd>; + vccio4-supply =3D <&vcc_1v8>; + vccio5-supply =3D <&vcc_3v3>; + vccio6-supply =3D <&vcc_1v8>; + vccio7-supply =3D <&vcc_3v3>; + status =3D "okay"; +}; + +&pwm0 { + status =3D "okay"; +}; + +&pwm4 { + status =3D "okay"; +}; + +&pwm5 { + status =3D "okay"; +}; + +&saradc { + vref-supply =3D <&vcca_1v8>; + status =3D "disabled"; +}; + +&sata1 { + target-supply =3D <&vcc5v0_sata>; + status =3D "okay"; +}; + +&sdhci { + bus-width =3D <8>; + max-frequency =3D <200000000>; + non-removable; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; + status =3D "okay"; +}; + +&sdmmc1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + bus-width =3D <4>; + cap-sd-highspeed; + cap-sdio-irq; + disable-wp; + keep-power-in-suspend; + max-frequency =3D <208000000>; + mmc-pwrseq =3D <&sdio_pwrseq>; + no-mmc; + no-sd; + non-removable; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&sdmmc1_bus4 &sdmmc1_clk &sdmmc1_cmd>; + sd-uhs-sdr104; + vmmc-supply =3D <&vcc_wl>; + vqmmc-supply =3D <&vccio_wl>; + status =3D "okay"; + + rtl8822cs: wifi@1 { + reg =3D <1>; + interrupt-parent =3D <&gpio2>; + interrupts =3D ; + interrupt-names =3D "host-wake"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&wifi_host_wake_h>; + }; +}; + +&tsadc { + rockchip,hw-tshut-mode =3D <0>; + rockchip,hw-tshut-polarity =3D <0>; + status =3D "okay"; +}; + +&uart1 { + dma-names =3D "tx", "rx"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>; + uart-has-rtscts; + status =3D "okay"; + + bluetooth { + compatible =3D "realtek,rtl8822cs-bt"; + device-wake-gpios =3D <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; + enable-gpios =3D <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; + host-wake-gpios =3D <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&bt_device_wake_h &bt_enable_h &bt_host_wake_h>; + }; +}; + +&uart2 { + status =3D "okay"; +}; + +&usb_host0_ehci { + status =3D "okay"; +}; + +&usb_host0_ohci { + status =3D "okay"; +}; + +&usb_host0_xhci { + dr_mode =3D "host"; + extcon =3D <&usb2phy0>; + status =3D "okay"; +}; + +&usb_host1_ehci { + status =3D "okay"; +}; + +&usb_host1_ohci { + status =3D "okay"; +}; + +&usb2phy0 { + status =3D "okay"; +}; + +&usb2phy0_otg { + phy-supply =3D <&vcc5v0_usb_otg>; + status =3D "okay"; +}; + +&usb2phy1 { + status =3D "okay"; +}; + +&usb2phy1_host { + phy-supply =3D <&vcc5v0_usb_host>; + status =3D "okay"; +}; + +&usb2phy1_otg { + phy-supply =3D <&vcc5v0_usb_host>; + status =3D "okay"; +}; + +&vop { + assigned-clocks =3D <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents =3D <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; + status =3D "okay"; +}; + +&vop_mmu { + status =3D "okay"; +}; + +&vp0 { + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg =3D ; + remote-endpoint =3D <&hdmi_in_vp0>; + }; +}; --=20 2.54.0