From nobody Sat Jul 25 23:42:32 2026 Received: from mail-106111.protonmail.ch (mail-106111.protonmail.ch [79.135.106.111]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5347D3C1966 for ; Sat, 11 Jul 2026 11:51:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=79.135.106.111 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783770702; cv=none; b=IIlTZwP3z0YTnJFaOr78kIZGyKayRMpcQRK3idCjZGaezAhlFsgxVc36vc18zsTxrjO+pABKT5zGAiMZr/UcQHTHdnBzk6b97X0o/JGp55Id1KC9IydXXbSdsGiBLWHOY8rCy3ME0TEL7yqN9sdiE2oEJ63afH7RnZ2mD3Gh5wA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783770702; c=relaxed/simple; bh=QPpYnR3y0mFDtMnLcMOYzNGpstvDfBWQWT030+mFtEU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=hml6Xeikb1ygr7LxFpfCy2FHvrS95Vo6Zp3U6tlzcdw5l7uojvRJooanFFMN0Psgh7jExARm6AlOlLXESjsL4Rsn6GLzxnVfajpMTvq/+Q9uZf/dvz8xB6MRLnEuJNgUv15ZMaEmmJZAgZ/X8UZDauDqaVfK2aVeuR5v3LgYxhs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=geanix.com; spf=pass smtp.mailfrom=geanix.com; dkim=pass (2048-bit key) header.d=geanix.com header.i=@geanix.com header.b=bHQgNdWi; arc=none smtp.client-ip=79.135.106.111 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=geanix.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=geanix.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=geanix.com header.i=@geanix.com header.b="bHQgNdWi" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=geanix.com; s=protonmail3; t=1783770680; x=1784029880; bh=dmd+hjkAb7MWciNOGHEOno701LYYfMaU7ApAgjUWx+E=; h=From:Date:Subject:Message-Id:References:In-Reply-To:To:Cc:From:To: Cc:Date:Subject:Reply-To:Feedback-ID:Message-ID:BIMI-Selector; b=bHQgNdWiRID3VfJfCIpHlrG48Mob6d25fYO8g4ztv/K9I5pQCfaylDPyHXzJ5TfEf 5mqpjL6UksOf4YVkFFw8okYdXBFE6xjBIN/YY5fcJavzdukAWSDSLVJJZKu0eTOOlN dJcv+hw3p7HrJ67LLyQRhBmyN3okJoY5EjTQxoJDAnE0ulbsf4oFTOjdfU+OI3qp7L U5Ot1LLq9L8bY5GHtdSw6yD4i2V2bcGLP0dxaRBSyoAovEDttvLh36b9k8Atb5fPze ytraBIrODvE+DZbbg2WkA1HLQCnpOqhKb87IM1758lzisIWKaN/xik1Re3hFELO1EO KkV3AQ1bYH7Pw== X-Pm-Submission-Id: 4gy6VH04Ldz2ScNw From: Esben Haabendal Date: Sat, 11 Jul 2026 13:51:14 +0200 Subject: [PATCH 1/2] drm/bridge: ti-sn65dsi83: Support LVDS Channel B on SN65DSI84 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260711-ti-sn65dsi83-fixes-v1-1-d85eb5342b98@geanix.com> References: <20260711-ti-sn65dsi83-fixes-v1-0-d85eb5342b98@geanix.com> In-Reply-To: <20260711-ti-sn65dsi83-fixes-v1-0-d85eb5342b98@geanix.com> To: Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Luca Ceresoli , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Esben Haabendal X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1783770676; l=3933; i=esben@geanix.com; s=20240523; h=from:subject:message-id; bh=QPpYnR3y0mFDtMnLcMOYzNGpstvDfBWQWT030+mFtEU=; b=xxjDC1B4XDEtj+VbLfTnbt3RJlQ/k7QhZ2IeSFjVjiJ/4Z8wz8JQ3aEXCp1fMNwknNq++VB+X 7PvMI38B1GxBw0ChtZyBhNEInrlr0gunEwxsQzyScLdCCnXjcKj0KJQ X-Developer-Key: i=esben@geanix.com; a=ed25519; pk=PbXoezm+CERhtgVeF/QAgXtEzSkDIahcWfC7RIXNdEk= This adds support for using SN65DSI84 in single-link mode with output to LVDS Channel B. Signed-off-by: Esben Haabendal --- drivers/gpu/drm/bridge/ti-sn65dsi83.c | 36 ++++++++++++++++++++++++-------= ---- 1 file changed, 25 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi83.c b/drivers/gpu/drm/bridge= /ti-sn65dsi83.c index 42b451432bbb..32e9eadd7452 100644 --- a/drivers/gpu/drm/bridge/ti-sn65dsi83.c +++ b/drivers/gpu/drm/bridge/ti-sn65dsi83.c @@ -11,6 +11,8 @@ * =3D 1x Single-link DSI ~ 2x Single-link or 1x Dual-link LVDS * - Supported * - Dual-link LVDS mode tested + * - Single-link to LVDS Channel A tested. + * - Single-link to LVDS Channel B tested. * - 2x Single-link LVDS mode unsupported * (should be easy to add by someone who has the HW) * - SN65DSI85 @@ -162,7 +164,7 @@ struct sn65dsi83 { struct gpio_desc *enable_gpio; struct regulator *vcc; bool lvds_dual_link; - bool lvds_dual_link_even_odd_swap; + bool lvds_channel_swap; int lvds_vod_swing_conf[2]; int lvds_term_conf[2]; int irq; @@ -642,7 +644,7 @@ static void sn65dsi83_atomic_pre_enable(struct drm_brid= ge *bridge, REG_LVDS_VCOM_CHA_LVDS_VOD_SWING(ctx->lvds_vod_swing_conf[CHANNEL_A]) | REG_LVDS_VCOM_CHB_LVDS_VOD_SWING(ctx->lvds_vod_swing_conf[CHANNEL_B])); regmap_write(ctx->regmap, REG_LVDS_LANE, - (ctx->lvds_dual_link_even_odd_swap ? + (ctx->lvds_channel_swap ? REG_LVDS_LANE_EVEN_ODD_SWAP : 0) | (ctx->lvds_term_conf[CHANNEL_A] ? REG_LVDS_LANE_CHA_LVDS_TERM : 0) | @@ -893,6 +895,7 @@ static int sn65dsi83_parse_dt(struct sn65dsi83 *ctx, en= um sn65dsi83_model model) { struct drm_bridge *panel_bridge; struct device *dev =3D ctx->dev; + u32 panel_port =3D 2; int ret; =20 ret =3D sn65dsi83_parse_lvds_endpoint(ctx, CHANNEL_A); @@ -904,29 +907,40 @@ static int sn65dsi83_parse_dt(struct sn65dsi83 *ctx, = enum sn65dsi83_model model) return ret; =20 ctx->lvds_dual_link =3D false; - ctx->lvds_dual_link_even_odd_swap =3D false; + ctx->lvds_channel_swap =3D false; if (model !=3D MODEL_SN65DSI83) { - struct device_node *port2, *port3; + struct device_node *port0, *port1, *port2, *port3; int dual_link; =20 + port0 =3D of_graph_get_port_by_id(dev->of_node, 0); + port1 =3D of_graph_get_port_by_id(dev->of_node, 1); port2 =3D of_graph_get_port_by_id(dev->of_node, 2); port3 =3D of_graph_get_port_by_id(dev->of_node, 3); dual_link =3D drm_of_lvds_get_dual_link_pixel_order(port2, port3); - of_node_put(port2); - of_node_put(port3); =20 if (dual_link =3D=3D DRM_LVDS_DUAL_LINK_ODD_EVEN_PIXELS) { - ctx->lvds_dual_link =3D true; /* Odd pixels to LVDS Channel A, even pixels to B */ - ctx->lvds_dual_link_even_odd_swap =3D false; - } else if (dual_link =3D=3D DRM_LVDS_DUAL_LINK_EVEN_ODD_PIXELS) { ctx->lvds_dual_link =3D true; + } else if (dual_link =3D=3D DRM_LVDS_DUAL_LINK_EVEN_ODD_PIXELS) { /* Even pixels to LVDS Channel A, odd pixels to B */ - ctx->lvds_dual_link_even_odd_swap =3D true; + ctx->lvds_dual_link =3D true; + ctx->lvds_channel_swap =3D true; + } else if (port0 && !port1 && port2 && !port3) { + /* DSI Channel A to LVDS Channel A */ + pr_warn("%s: DSI Channel A to LVDS Channel A\n", __func__); + } else if (port0 && !port1 && !port2 && port3) { + /* DSI Channel A to LVDS Channel B */ + pr_warn("%s: DSI Channel A to LVDS Channel B\n", __func__); + ctx->lvds_channel_swap =3D true; + panel_port =3D 3; } + of_node_put(port0); + of_node_put(port1); + of_node_put(port2); + of_node_put(port3); } =20 - panel_bridge =3D devm_drm_of_get_bridge(dev, dev->of_node, 2, 0); + panel_bridge =3D devm_drm_of_get_bridge(dev, dev->of_node, panel_port, 0); if (IS_ERR(panel_bridge)) return dev_err_probe(dev, PTR_ERR(panel_bridge), "Failed to get panel br= idge\n"); =20 --=20 2.55.0 From nobody Sat Jul 25 23:42:32 2026 Received: from mail-43171.protonmail.ch (mail-43171.protonmail.ch [185.70.43.171]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EC3AD3A4505 for ; Sat, 11 Jul 2026 11:51:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.70.43.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783770700; cv=none; b=piPySNI9MRcAUI9GeAer2HJyS1XWx4gbJY3w3+0rFRkDx22g4vMrvpDHNAEUycXFLWdhVtVmq2ai7fu8tA6FpQL/dACsiHkk2fmsXxj6f7FD46ATD34+75ylImh/LrXKOx1QHyJzXMyx83SzF5Rh7vbpmnncEot5fNyV3X7Enes= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783770700; c=relaxed/simple; bh=pH/nP0E0g44vrK+eBi+bD71JRmcKQtkCWV8Og7DM+O0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; 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b=y5of0RWZcF83id1QiD72MHhseqvKDP9+SmIog8Z7eAJjFXvxqjK3APMu5a6entU5w zVifFHBLGFanDAXMOAFPUYet+eFwelcGeJSAnSq5YYftC9bn4sEuYsWsF20GE5jI8F UEU5s1WcAIKKUqAQRapuT8sf8Uhsbjv88ZH3yZoE7M4s30zCRyOOWl22ui0g/55hoL 95O8DLsjG9e3MukBH357CiDNGyL3eSuMWQImAc8Fih2HC0SaiVQY3PphHVENZfWr4X LDQza6ESNi9eTzRK5em8jL00fTxqlxUW0NmEzMmgsnDlYmyp/z/I4vz0P78wQ6tD8H i074JNFQwElUQ== X-Pm-Submission-Id: 4gy6VK14ZJz1DDLC From: Esben Haabendal Date: Sat, 11 Jul 2026 13:51:15 +0200 Subject: [PATCH 2/2] drm/bridge: ti-sn65dsi83: Fix problem with premature PLL locking Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260711-ti-sn65dsi83-fixes-v1-2-d85eb5342b98@geanix.com> References: <20260711-ti-sn65dsi83-fixes-v1-0-d85eb5342b98@geanix.com> In-Reply-To: <20260711-ti-sn65dsi83-fixes-v1-0-d85eb5342b98@geanix.com> To: Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Luca Ceresoli , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Esben Haabendal X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1783770676; l=3251; i=esben@geanix.com; s=20240523; h=from:subject:message-id; bh=pH/nP0E0g44vrK+eBi+bD71JRmcKQtkCWV8Og7DM+O0=; b=rld/PWuwaIB3p5dCOKhYC03tMTkQCLfuHAfHEKYG4cLtKAUYaDXZXYXDzdFtGcIlMcDsIEl7h 0B7bNG/hmjEDuBfA0mBSPku9PdiafBRHKOYt/YeC/+MsuJbU2AZ6oTL X-Developer-Key: i=esben@geanix.com; a=ed25519; pk=PbXoezm+CERhtgVeF/QAgXtEzSkDIahcWfC7RIXNdEk= Locking PLL requires the DSI HS clock to be running, which it might not be in probe(), but should be in atomic_enable(). This resolves issues like this: sn65dsi83 1-002c: failed to lock PLL, ret=3D-110 sn65dsi83 1-002c: Unexpected link status 0x01 sn65dsi83 1-002c: Unexpected link status 0x01 sn65dsi83 1-002c: reset the pipe as seen with nwl-dsi bridge and others. This is the same issue as addressed in the patch by Gary Bisson [1], but changing the ti-sn65dsi83 driver instead, so we don't have to change all other drivers that could potentially be used with this chip. [1] https://lore.kernel.org/all/20260120-mtkdsi-v1-1-b0f4094f3ac3@gmail.com/ Signed-off-by: Esben Haabendal Tested-by: Gary Bisson --- drivers/gpu/drm/bridge/ti-sn65dsi83.c | 30 ++++++++++++++---------------- 1 file changed, 14 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi83.c b/drivers/gpu/drm/bridge= /ti-sn65dsi83.c index 32e9eadd7452..e87bed3a6640 100644 --- a/drivers/gpu/drm/bridge/ti-sn65dsi83.c +++ b/drivers/gpu/drm/bridge/ti-sn65dsi83.c @@ -532,7 +532,6 @@ static void sn65dsi83_atomic_pre_enable(struct drm_brid= ge *bridge, bool test_pattern =3D sn65dsi83_test_pattern; bool lvds_format_24bpp; bool lvds_format_jeida; - unsigned int pval; __le16 le16val; u16 val; int ret; @@ -682,26 +681,12 @@ static void sn65dsi83_atomic_pre_enable(struct drm_br= idge *bridge, regmap_write(ctx->regmap, REG_VID_CHA_TEST_PATTERN, test_pattern ? REG_VID_CHA_TEST_PATTERN_EN : 0); =20 - /* Enable PLL */ - regmap_write(ctx->regmap, REG_RC_PLL_EN, REG_RC_PLL_EN_PLL_EN); - usleep_range(3000, 4000); - ret =3D regmap_read_poll_timeout(ctx->regmap, REG_RC_LVDS_PLL, pval, - pval & REG_RC_LVDS_PLL_PLL_EN_STAT, - 1000, 100000); - if (ret) { - dev_err(ctx->dev, "failed to lock PLL, ret=3D%i\n", ret); - /* On failure, disable PLL again and exit. */ - regmap_write(ctx->regmap, REG_RC_PLL_EN, 0x00); - goto err_add_action; - } - /* Trigger reset after CSR register update. */ regmap_write(ctx->regmap, REG_RC_RESET, REG_RC_RESET_SOFT_RESET); =20 /* Wait for 10ms after soft reset as specified in datasheet */ usleep_range(10000, 12000); =20 -err_add_action: devm_add_action(ctx->dev, sn65dsi83_release_resources, ctx); err_exit: drm_bridge_exit(idx); @@ -712,11 +697,24 @@ static void sn65dsi83_atomic_enable(struct drm_bridge= *bridge, { struct sn65dsi83 *ctx =3D bridge_to_sn65dsi83(bridge); unsigned int pval; - int idx; + int idx, ret; =20 if (!drm_bridge_enter(bridge, &idx)) return; =20 + /* Enable PLL */ + regmap_write(ctx->regmap, REG_RC_PLL_EN, REG_RC_PLL_EN_PLL_EN); + usleep_range(3000, 4000); + ret =3D regmap_read_poll_timeout(ctx->regmap, REG_RC_LVDS_PLL, pval, + pval & REG_RC_LVDS_PLL_PLL_EN_STAT, + 1000, 100000); + if (ret) { + dev_err(ctx->dev, "failed to lock PLL, ret=3D%i\n", ret); + /* On failure, disable PLL again and exit. */ + regmap_write(ctx->regmap, REG_RC_PLL_EN, 0x00); + return; + } + /* Clear all errors that got asserted during initialization. */ regmap_read(ctx->regmap, REG_IRQ_STAT, &pval); regmap_write(ctx->regmap, REG_IRQ_STAT, pval); --=20 2.55.0