From nobody Sat Jul 25 23:11:59 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 74A182DC32C; Sun, 12 Jul 2026 03:11:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783825893; cv=none; b=uWeF9iqOpW0VOoMHZb7QCu7eEvwg8gNU9T4b541H0xAC4O4KatZKfu4zg50QhKsQfweYyDgoN73qNtzKRJUrid62wwLtTkm12mpHhuf7gBFvJnQzpL80phMG/aOfNuMcq204T4dzgVwumiQZbG8X7YQtbVGUDiH2C0HgCrpYhFQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783825893; c=relaxed/simple; bh=B29H+U+1LjMs/wUCNbZFPdXBSrzHHixAvE4yWLt60IQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=GDCag8YLliV1u4FUX1s3PL2XftC7TbGCB1s8eIkGPkhxNnCGrCEWCUz/lask+ohFX0ZrAUbqHzWqQO/uF8m3u+LRfLJBDGyxEGnh6n286Es0wGIYjQUQn2jx3zQgd2+rm2LPex+Xi9hWPvpM8DqhUVmjCA9jQmXaZljAE8eNfqs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=CmHklcsZ; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="CmHklcsZ" Received: by smtp.kernel.org (Postfix) with ESMTPS id 22013C2BCF5; Sun, 12 Jul 2026 03:11:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1783825893; bh=B29H+U+1LjMs/wUCNbZFPdXBSrzHHixAvE4yWLt60IQ=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=CmHklcsZxjy/bH1dZ1p2aat3NDssdSIVOkipjTX+IiX5ESQ9VG4dwSYoeNrRmT/aN /KK1h6S2AU9DXAIwc9v+NRYaJP31qNGK09tzAtkDONnCjOczlI9Q2hs21u+EnScUh1 0k0cSbWtJ2+hQA1DE5JIfu1cHkoqCPQp09wlQ4Bt5GTl0bNtNgHncfMxO/0gxlcOI8 h4Z4ULc3bj3pTFsY24fW8s3U0yWam/CvhPwTuK+znbI0nRse1NpAAUNn2CaZImr/6b oWOKqXBCo3D3ldHOv8aYBXR/bx2Cz3s1oLA3VbFPu6jjEtHzxE14MizPWfMw8/Y68y guhshv8QNho+Q== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 029A2C44506; Sun, 12 Jul 2026 03:11:33 +0000 (UTC) From: Esteban Urrutia via B4 Relay Date: Sat, 11 Jul 2026 23:10:35 -0400 Subject: [PATCH v2 1/3] clk: qcom: dispcc-sm8450: Fix disp_cc_mdss_mdp_clk_src ops Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260711-sm8450-qol-dispcc-v2-1-fc1a07ac5601@proton.me> References: <20260711-sm8450-qol-dispcc-v2-0-fc1a07ac5601@proton.me> In-Reply-To: <20260711-sm8450-qol-dispcc-v2-0-fc1a07ac5601@proton.me> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney , Dmitry Baryshkov , Danila Tikhonov Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, phone-devel@vger.kernel.org, Esteban Urrutia X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1783825891; l=904; i=esteuwu@proton.me; s=20260622; h=from:subject:message-id; bh=hS4a1nL7vtDd38+h02lWuV/41dvOpOZ27ua71QXzKRU=; b=YYuSwzjliP3WYJJYB+n2z2/X4z3ZGGPhihZdXDZ83HLiaC0nsMH+N5k4FZhC0kiURSgpb4OvQ INpALlmIVueDz8haY6+7lNWq++52SfQ07XY4Utd7NTG54BGIij/ljqw X-Developer-Key: i=esteuwu@proton.me; a=ed25519; pk=wToFt4mOAWkzbqb15Ye1hrhevI13vK9BcMUFiQ/me1M= X-Endpoint-Received: by B4 Relay for esteuwu@proton.me/20260622 with auth_id=835 X-Original-From: Esteban Urrutia Reply-To: esteuwu@proton.me From: Esteban Urrutia If the clock frequency is changed at registration time, a flicker will be visible at boot. Switching to clk_rcg2_shared_no_init_park_ops fixes this. Fixes: 16fb89f92ec4 ("clk: qcom: Add support for Display Clock Controller o= n SM8450") Signed-off-by: Esteban Urrutia Reviewed-by: Konrad Dybcio --- drivers/clk/qcom/dispcc-sm8450.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/qcom/dispcc-sm8450.c b/drivers/clk/qcom/dispcc-sm8= 450.c index 3af120e54cdd..c7e04bd315d5 100644 --- a/drivers/clk/qcom/dispcc-sm8450.c +++ b/drivers/clk/qcom/dispcc-sm8450.c @@ -613,7 +613,7 @@ static struct clk_rcg2 disp_cc_mdss_mdp_clk_src =3D { .parent_data =3D disp_cc_parent_data_5, .num_parents =3D ARRAY_SIZE(disp_cc_parent_data_5), .flags =3D CLK_SET_RATE_PARENT, - .ops =3D &clk_rcg2_shared_ops, + .ops =3D &clk_rcg2_shared_no_init_park_ops, }, }; =20 --=20 2.55.0 From nobody Sat Jul 25 23:11:59 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7496A27A476; Sun, 12 Jul 2026 03:11:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783825893; cv=none; b=AlFM36phfKZGs035XRMcvJGjYv59ZjBxdAQSCDCpp6ATSZuxb9Qlei26se0C0OKGYD7bIPyvjqM5SOkz3CKb4h56QRM36pVCB1U8brbzCzt97DdGVLbRUQwi6F3/Ij8M8YXgnoFrYM2CrlimYaVbBNclNT9bcrvrSeuBWSALXL8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783825893; c=relaxed/simple; bh=ffpRq/yZnNx7YKIkRIAyqqnKBxqhvOWldlUoQ94VLnk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=R/dwtgePOa4X8q4ut1pm6nl+ktDaSbciOBwyPdQT3CkMLHdphxB4KOoUjgdHk8YS/lXkRtL6rGLdbsgDiYN77yoPCdqKhW9OsaYAirOyRVB62a2jyu6fb/v6HcAQ/RShxV1QwGeVUirVXTm9wM5r5daLbWb+RrlN43lBqnaTBZQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=o2d95Jog; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="o2d95Jog" Received: by smtp.kernel.org (Postfix) with ESMTPS id 34C8EC2BCF6; Sun, 12 Jul 2026 03:11:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1783825893; bh=ffpRq/yZnNx7YKIkRIAyqqnKBxqhvOWldlUoQ94VLnk=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=o2d95Joggp4+N+ZF3j0sgXJORMij/S5XGVOskw7gJJl+88k89z1HlVNG813EByfq4 a9jyIGR3iteMzhm4D2bibPGN/sT84dMNsIBnAAVFUqDGCsh6XzbMWaVIIPY2pDJWO4 lXHZzEgFw37R/PZPIIIjZGc8mt1sp7CT+IqEfi5Z10vn/6sET7BjZ9CSwI9cvKy5ME I30SBbTVxXLrmbeSZtaCgxEL8i2k5TE2e1+GvESKrFOE/asuyAc/RBv6ukR0iTnKtc RRL1RNHy6oESkXFj2WIuMcpMQJxn4mPW+HosYMfqKiXQcc3OW6ifiePhbyDCeOBU7B oQEjf7Ys/rCqA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0FCC6C44501; Sun, 12 Jul 2026 03:11:33 +0000 (UTC) From: Esteban Urrutia via B4 Relay Date: Sat, 11 Jul 2026 23:10:36 -0400 Subject: [PATCH v2 2/3] clk: qcom: dispcc-sm8450: Migrate to qcom_cc_driver_data Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260711-sm8450-qol-dispcc-v2-2-fc1a07ac5601@proton.me> References: <20260711-sm8450-qol-dispcc-v2-0-fc1a07ac5601@proton.me> In-Reply-To: <20260711-sm8450-qol-dispcc-v2-0-fc1a07ac5601@proton.me> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney , Dmitry Baryshkov , Danila Tikhonov Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, phone-devel@vger.kernel.org, Esteban Urrutia X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1783825891; l=2649; i=esteuwu@proton.me; s=20260622; h=from:subject:message-id; bh=PwdqzjnMeRdkC7srNPy0ZM+7B2sU0GfwVPACjedCviQ=; b=U7SJM3IHNt/ZbMXtLZBCf07N4fRMeZlzSSaaIkpejagx9223suGXBIVnqXw4mL6ANATt8Hcvx HY4UtxlMrFuDaFVM1pigThWj/KkNYYtvNuI/D7ZNMBTi7aSYh5c6ncM X-Developer-Key: i=esteuwu@proton.me; a=ed25519; pk=wToFt4mOAWkzbqb15Ye1hrhevI13vK9BcMUFiQ/me1M= X-Endpoint-Received: by B4 Relay for esteuwu@proton.me/20260622 with auth_id=835 X-Original-From: Esteban Urrutia Reply-To: esteuwu@proton.me From: Esteban Urrutia Migrate to qcom_cc_driver_data, which is used by other clock controller drivers. Signed-off-by: Esteban Urrutia Reviewed-by: Konrad Dybcio --- drivers/clk/qcom/dispcc-sm8450.c | 28 +++++++++++++++++++++------- 1 file changed, 21 insertions(+), 7 deletions(-) diff --git a/drivers/clk/qcom/dispcc-sm8450.c b/drivers/clk/qcom/dispcc-sm8= 450.c index c7e04bd315d5..07f22b5b5ee5 100644 --- a/drivers/clk/qcom/dispcc-sm8450.c +++ b/drivers/clk/qcom/dispcc-sm8450.c @@ -1778,6 +1778,22 @@ static const struct regmap_config disp_cc_sm8450_reg= map_config =3D { .fast_io =3D true, }; =20 +static struct clk_alpha_pll *disp_cc_sm8450_plls[] =3D { + &disp_cc_pll0, + &disp_cc_pll1, +}; + +static const u32 disp_cc_sm8450_critical_cbcrs[] =3D { + 0xe05c, /* DISP_CC_XO_CLK */ +}; + +static const struct qcom_cc_driver_data disp_cc_sm8450_driver_data =3D { + .alpha_plls =3D disp_cc_sm8450_plls, + .num_alpha_plls =3D ARRAY_SIZE(disp_cc_sm8450_plls), + .clk_cbcrs =3D disp_cc_sm8450_critical_cbcrs, + .num_clk_cbcrs =3D ARRAY_SIZE(disp_cc_sm8450_critical_cbcrs), +}; + static const struct qcom_cc_desc disp_cc_sm8450_desc =3D { .config =3D &disp_cc_sm8450_regmap_config, .clks =3D disp_cc_sm8450_clocks, @@ -1786,6 +1802,7 @@ static const struct qcom_cc_desc disp_cc_sm8450_desc = =3D { .num_resets =3D ARRAY_SIZE(disp_cc_sm8450_resets), .gdscs =3D disp_cc_sm8450_gdscs, .num_gdscs =3D ARRAY_SIZE(disp_cc_sm8450_gdscs), + .driver_data =3D &disp_cc_sm8450_driver_data, }; =20 static const struct of_device_id disp_cc_sm8450_match_table[] =3D { @@ -1823,19 +1840,16 @@ static int disp_cc_sm8450_probe(struct platform_dev= ice *pdev) disp_cc_pll1.regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE]; disp_cc_pll1.clkr.hw.init =3D &sm8475_disp_cc_pll1_init; =20 - clk_lucid_ole_pll_configure(&disp_cc_pll0, regmap, &sm8475_disp_cc_pll0_= config); - clk_lucid_ole_pll_configure(&disp_cc_pll1, regmap, &sm8475_disp_cc_pll1_= config); + disp_cc_pll0.config =3D &sm8475_disp_cc_pll0_config; + disp_cc_pll1.config =3D &sm8475_disp_cc_pll1_config; } else { - clk_lucid_evo_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config); - clk_lucid_evo_pll_configure(&disp_cc_pll1, regmap, &disp_cc_pll1_config); + disp_cc_pll0.config =3D &disp_cc_pll0_config; + disp_cc_pll1.config =3D &disp_cc_pll1_config; } =20 /* Enable clock gating for MDP clocks */ regmap_update_bits(regmap, DISP_CC_MISC_CMD, 0x10, 0x10); =20 - /* Keep some clocks always-on */ - qcom_branch_set_clk_en(regmap, 0xe05c); /* DISP_CC_XO_CLK */ - ret =3D qcom_cc_really_probe(&pdev->dev, &disp_cc_sm8450_desc, regmap); if (ret) goto err_put_rpm; --=20 2.55.0 From nobody Sat Jul 25 23:11:59 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 753452DCC1F; Sun, 12 Jul 2026 03:11:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783825893; cv=none; b=d7n+cEUYX/cavx9ttuPNKBTP1d9OfQQl5PWvx7px41a0wKYsioOqwb8tEN3P65hJpRfWhnfjkdGhI/uk3YgIKS3sT2GGVz+1rB94/HcKekEw/MbXRV8iphoguG+SZde4PDVHASDGVUvZylVoi5pN4LSV2oFOwMX4H7bbb0O+b9g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783825893; c=relaxed/simple; bh=OfkIYbB3usR2r/HeTYEeAnKhUpEXwsYjhvtLM/7J64k=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; 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Sun, 12 Jul 2026 03:11:33 +0000 (UTC) From: Esteban Urrutia via B4 Relay Date: Sat, 11 Jul 2026 23:10:37 -0400 Subject: [PATCH v2 3/3] clk: qcom: dispcc-sm8450: Keep pll types as is for SM8475 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260711-sm8450-qol-dispcc-v2-3-fc1a07ac5601@proton.me> References: <20260711-sm8450-qol-dispcc-v2-0-fc1a07ac5601@proton.me> In-Reply-To: <20260711-sm8450-qol-dispcc-v2-0-fc1a07ac5601@proton.me> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney , Dmitry Baryshkov , Danila Tikhonov Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, phone-devel@vger.kernel.org, Esteban Urrutia X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1783825891; l=1363; i=esteuwu@proton.me; s=20260622; h=from:subject:message-id; bh=t+lNjNa2t6HZO8sfj5j22+PtdnnFFxNblbhbO/qadd0=; b=Bj9RlBDSAQxg8KVWCWBDlK+W6DILMgAvBoBCOjSG+SkJQ/cXRWofqsgfJAT3JPEDb+hlrE1ui eAx32OOZCQZAnrSdhZglC3MU5gEL+tXYESGra/ckMRRMsugNEG8+xWV X-Developer-Key: i=esteuwu@proton.me; a=ed25519; pk=wToFt4mOAWkzbqb15Ye1hrhevI13vK9BcMUFiQ/me1M= X-Endpoint-Received: by B4 Relay for esteuwu@proton.me/20260622 with auth_id=835 X-Original-From: Esteban Urrutia Reply-To: esteuwu@proton.me From: Esteban Urrutia While using an OLE PLL type is correct according to downstream code, this results in the display flickering at boot for SM8475 because downstream uses EVO type configurations for both clocks, while, for some reason, upstream uses EVO type configurations for SM8450 and OLE type configurations for SM8475. So far, no regressions have been observed and the display no longer flickers. Fixes: 7c0e8764dc33 ("clk: qcom: dispcc-sm8450: Add SM8475 support") Signed-off-by: Esteban Urrutia --- drivers/clk/qcom/dispcc-sm8450.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/clk/qcom/dispcc-sm8450.c b/drivers/clk/qcom/dispcc-sm8= 450.c index 07f22b5b5ee5..2c0edc23eeb1 100644 --- a/drivers/clk/qcom/dispcc-sm8450.c +++ b/drivers/clk/qcom/dispcc-sm8450.c @@ -1833,11 +1833,9 @@ static int disp_cc_sm8450_probe(struct platform_devi= ce *pdev) =20 if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8475-dispcc")) { /* Update DISPCC PLL0 */ - disp_cc_pll0.regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE]; disp_cc_pll0.clkr.hw.init =3D &sm8475_disp_cc_pll0_init; =20 /* Update DISPCC PLL1 */ - disp_cc_pll1.regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE]; disp_cc_pll1.clkr.hw.init =3D &sm8475_disp_cc_pll1_init; =20 disp_cc_pll0.config =3D &sm8475_disp_cc_pll0_config; --=20 2.55.0