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bh=UCxBH8XTLqZLh53kCc2mC0OKwjriiIwFPSjZgfKY0Hs=; b=jqQZAQTHz3W/0Yg1gT1D+vbBqOm/n5JWWNSutX6S3psjJRG+3PszlUBrrym/r8tDObMbIX 2y6PF7T716fIP68Nm6fM/WRyX6b9hN8fjBnhYmV+l5KhpTEKGCcvbgQJtZcrtAPXQENYAQ jhQvsTJ8ABPcueXAjnfVFVMELr1kV4EsyrTPqVeRSA7fLEMU4EKJjEBSBiehxpGATYtkUq LoQYNJSYiWzOJP5abHZHLGxPn0/l/xX1yF4ygyY52doNEzsj0O8AwMEithDlO+37QEWScr uqqpWp6eqTawrRMtp3Pb8/F/QxHne86vv2wKCS3/tbBOrLjLlkvxlbLqLYlBrg== Date: Sat, 11 Jul 2026 12:16:29 +0200 Subject: [PATCH v4 1/2] rust: clk: Add `ExclusiveClk` wrapper for `clk_rate_exclusive_get` Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260711-rate-exclusive-get-th1520-v4-1-8244a0666a71@mailbox.org> References: <20260711-rate-exclusive-get-th1520-v4-0-8244a0666a71@mailbox.org> In-Reply-To: <20260711-rate-exclusive-get-th1520-v4-0-8244a0666a71@mailbox.org> To: Michael Turquette , Stephen Boyd , Miguel Ojeda , Boqun Feng , Gary Guo , =?utf-8?q?Bj=C3=B6rn_Roy_Baron?= , Benno Lossin , Andreas Hindborg , Alice Ryhl , Trevor Gross , Danilo Krummrich , Drew Fustini , Guo Ren , Fu Wei , Michal Wilczynski , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Brian Masney Cc: Daniel Almeida , linux-clk@vger.kernel.org, rust-for-linux@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-pwm@vger.kernel.org, Maurice Hieronymus X-Developer-Signature: v=1; a=ed25519-sha256; t=1783765003; l=3768; i=mhi@mailbox.org; s=20260525; h=from:subject:message-id; bh=2i565GZEt7CtYaWPQAS6HCVyhDNjGn7E4LXA8bkXTno=; b=YD8iP2otPa9/+5EnZK5SMiUG+u+YWJDS4nsYJPN5E6gVR2OtDYxHwHzWBJ/fyHDvjc+cuyX67 tpetJ3aZhHSDhRRg1nOwOOlgIlgxcAfRY+8YenNMY2D4kNfn1Hklv0h X-Developer-Key: i=mhi@mailbox.org; a=ed25519; pk=AHlEkGG3hpXZHntlEzF42Ip/LFyXWOgsNUvaHqAnV80= X-MBO-RS-ID: a2a2aa3e636b3a76154 X-MBO-RS-META: qawtzmuw3yd8chbb6he14dj844ybn7rx Add Rust bindings for `clk_rate_exclusive_get()` and `clk_rate_exclusive_put()`. `Clk::rate_exclusive_get()` consumes the `Clk` and returns an `ExclusiveClk`. The matching put is issued from its Drop impl. `ExclusiveClk` derefs to `Clk` so existing APIs remain available on the locked handle. Reviewed-by: Alice Ryhl Signed-off-by: Maurice Hieronymus --- rust/kernel/clk.rs | 67 ++++++++++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 67 insertions(+) diff --git a/rust/kernel/clk.rs b/rust/kernel/clk.rs index e677156ffd21..18e4c1fb0937 100644 --- a/rust/kernel/clk.rs +++ b/rust/kernel/clk.rs @@ -95,6 +95,7 @@ mod common_clk { use core::{ marker::PhantomData, mem::ManuallyDrop, + ops::Deref, ptr, // }; =20 @@ -682,6 +683,23 @@ pub fn disable(self) -> Clk { _phantom: PhantomData, } } + + /// Acquire exclusive control over the clock's rate. + /// + /// Consumes the [`Clk`] and returns an [`ExclusiveClk`] = that releases + /// the exclusivity when dropped. While held, no other consumer ma= y change the clock's rate. + /// + /// Equivalent to the kernel's [`clk_rate_exclusive_get`] API. Mus= t not be called from + /// atomic context. + /// + /// [`clk_rate_exclusive_get`]: https://docs.kernel.org/core-api/k= ernel-api.html#c.clk_rate_exclusive_get + #[inline] + pub fn rate_exclusive_get(self) -> Result { + // SAFETY: By the type invariants, self.as_raw() is a valid ar= gument for + // clk_rate_exclusive_get. + to_result(unsafe { bindings::clk_rate_exclusive_get(self.as_ra= w()) })?; + Ok(ExclusiveClk(self)) + } } =20 impl Clk { @@ -767,6 +785,55 @@ fn clone(&self) -> Self { } } } + + /// A [`Clk`] with exclusive control over its rate. + /// + /// While an [`ExclusiveClk`] exists, no other consumer of the same cl= ock may change its rate. + /// Obtained by calling [`Clk::rate_exclusive_get`]; the exclusivity i= s released automatically + /// when the value is dropped, after which the inner [`Clk`] = is dropped as usual. + /// + /// # Invariants + /// + /// An [`ExclusiveClk`] instance owns a [`Clk`] for which `cl= k_rate_exclusive_get` has + /// been called and the matching `clk_rate_exclusive_put` has not yet = been called. + /// + /// # Examples + /// + /// ``` + /// use kernel::clk::{ + /// Clk, + /// ExclusiveClk, + /// Enabled // + /// }; + /// use kernel::device::{ + /// Bound, + /// Device, // + /// }; + /// use kernel::error::Result; + /// + /// fn lock_rate(dev: &Device) -> Result { + /// let clk =3D Clk::::get(dev, None)?; + /// clk.rate_exclusive_get() + /// } + /// ``` + pub struct ExclusiveClk(Clk); + + impl Deref for ExclusiveClk { + type Target =3D Clk; + + fn deref(&self) -> &Clk { + &self.0 + } + } + + impl Drop for ExclusiveClk { + fn drop(&mut self) { + // SAFETY: By the type invariants, self.as_raw() is a valid ar= gument for + // clk_rate_exclusive_put and balances the clk_rate_exclusive_= get call from + // Clk::rate_exclusive_get. + unsafe { bindings::clk_rate_exclusive_put(self.as_raw()) }; + } + } } =20 #[cfg(CONFIG_COMMON_CLK)] --=20 2.51.2 From nobody Sat Jul 25 23:42:30 2026 Received: from mout-p-201.mailbox.org (mout-p-201.mailbox.org [80.241.56.171]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F277239A045; 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bh=YRjPBjPuglGnWcYt2EDxgR0fDCyPIyJQtIkqBiIfQ2Q=; b=JfbgCxB9TRUQa2kRRu6/cJGU0wPjcmv7fX55qqEmbHZ0ZBPsmvahGxERdI3w8yHgLceIw/ v3WIO+frbIBOxtCnc882BIRJtf6A+PRthCeNqjvmfUP7ueRDcxnYYxEuIcJtNG7JmhD+QK wRK7ct47rQoNnK5r0sBtjXF106cTsV7uPDxh5F2r1JYXfuohK26BmOLzxYqCY8SoVDpGrX HBojyS7/Eg4VFqHmRQlvKX+DzTljQ52TC3OpPEZ/Cthg9BMF6pquBDCG/f7awW6w1LsQ/J fx6lTEQnJpaKU9EgJIpAFeRr8ziEwSICtESWDb36pUS3Oo5ENoYDO6A9XSQDDw== From: Maurice Hieronymus DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mailbox.org; s=mail20150812; t=1783765026; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=YRjPBjPuglGnWcYt2EDxgR0fDCyPIyJQtIkqBiIfQ2Q=; b=q70adOaIXLu0oeDkLv60N190Se0roRpqKdZ65Koz+f/N4vmnnBmjXKqMg5d0umux/Urlam sIl0OPc4e4dW/omhOsgG5BaazlM1UGO2u10Boy7Fmk400mNdbbQlLsf4ovRMFFm8i8Krvr cAYeJ/bStSQt+HfsysQEZ8OhOwXsp+OzmG1vuE6rF73pM5h9l7bxDKHd5oPIpdAsk8oL3P UFMUyKvLomcPDcO33xP0pvpZESKWdO9fmmB0YOhLK0jCW1aoFCpgmdFMjfKzLSUnwhNefR KaPmy71mCxx+yjtUl45uEAmRmPReMsWrpg4x5LJaRPiXhLLQ8wp+ghSQ1iT/eA== Date: Sat, 11 Jul 2026 12:16:30 +0200 Subject: [PATCH v4 2/2] pwm: th1520: Lock clock rate with clk_rate_exclusive_get Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260711-rate-exclusive-get-th1520-v4-2-8244a0666a71@mailbox.org> References: <20260711-rate-exclusive-get-th1520-v4-0-8244a0666a71@mailbox.org> In-Reply-To: <20260711-rate-exclusive-get-th1520-v4-0-8244a0666a71@mailbox.org> To: Michael Turquette , Stephen Boyd , Miguel Ojeda , Boqun Feng , Gary Guo , =?utf-8?q?Bj=C3=B6rn_Roy_Baron?= , Benno Lossin , Andreas Hindborg , Alice Ryhl , Trevor Gross , Danilo Krummrich , Drew Fustini , Guo Ren , Fu Wei , Michal Wilczynski , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Brian Masney Cc: Daniel Almeida , linux-clk@vger.kernel.org, rust-for-linux@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-pwm@vger.kernel.org, Maurice Hieronymus X-Developer-Signature: v=1; a=ed25519-sha256; t=1783765003; l=1864; i=mhi@mailbox.org; s=20260525; h=from:subject:message-id; bh=XTt9Wb3t8dMkZzuvXmoKi5n+eeWfIrk4FFd5V+XRvs8=; b=WvdYOvOJeyFL1eIjD68+q/wUtv03eytEyxUw7mCbEVVNZnghVv3RC/d32QX6gAzQhzT91VZV+ 1dPp67NmmvQB3aPwHyICcmbvq/5iFCpDGSCjr5QxraWFOMRDMVvRr/1 X-Developer-Key: i=mhi@mailbox.org; a=ed25519; pk=AHlEkGG3hpXZHntlEzF42Ip/LFyXWOgsNUvaHqAnV80= X-MBO-RS-ID: c60d8243f9904d1ba72 X-MBO-RS-META: yus6awgdopfyu6x8nzir3j1jsbja9zx7 The driver derives period and duty cycle from the clock rate read at probe, so a later rate change would silently miscompute waveforms. Switch to the new ExclusiveClk wrapper to hold the rate for the lifetime of the driver data and drop the corresponding TODO. Reviewed-by: Alice Ryhl Reviewed-by: Michal Wilczynski Signed-off-by: Maurice Hieronymus --- drivers/pwm/pwm_th1520.rs | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/drivers/pwm/pwm_th1520.rs b/drivers/pwm/pwm_th1520.rs index 343a1178c5e7..8f9d3fa39200 100644 --- a/drivers/pwm/pwm_th1520.rs +++ b/drivers/pwm/pwm_th1520.rs @@ -22,8 +22,16 @@ =20 use core::ops::Deref; use kernel::{ - clk::{Clk, Enabled}, - device::{Bound, Core, Device}, + clk::{ + Clk, + Enabled, + ExclusiveClk, // + }, + device::{ + Bound, + Core, + Device, // + }, devres, io::{ mem::IoMem, @@ -93,7 +101,7 @@ struct Th1520WfHw { struct Th1520PwmDriverData { #[pin] iomem: devres::Devres>, - clk: Clk, + clk: ExclusiveClk, } =20 impl pwm::PwmOps for Th1520PwmDriverData { @@ -319,10 +327,8 @@ fn probe( let request =3D pdev.io_request_by_index(0).ok_or(ENODEV)?; =20 let clk =3D Clk::::get(dev, None)?; + let clk =3D clk.rate_exclusive_get()?; =20 - // TODO: Get exclusive ownership of the clock to prevent rate chan= ges. - // The Rust equivalent of `clk_rate_exclusive_get()` is not yet av= ailable. - // This should be updated once it is implemented. let rate_hz =3D clk.rate().as_hz(); if rate_hz =3D=3D 0 { dev_err!(dev, "Clock rate is zero\n"); --=20 2.51.2