From nobody Sun Jul 26 01:48:11 2026 Received: from mail-ej1-f53.google.com (mail-ej1-f53.google.com [209.85.218.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A82363DD522 for ; Fri, 10 Jul 2026 09:22:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783675379; cv=none; b=NaxwBTyz0tX6AKc/8YEaWVi8UzgZEDyF057Aaf5MgKAlSTBDElRvoDD2zDzCbqRbT4/yQIE+iCQld48QkwcLmdlVFiQ4XcKQ7Kr01hYoJHibWzJZywmcX71eP7TE1XkGKfbQrL/z1jAQX/ZsubCau2Z36A7pwEzTogBxRuu9D2I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783675379; c=relaxed/simple; bh=2/pH/58ZPSVPRJvZYePDwwn0y2ezcvuAOg6I4e2E1hc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=UXfZsJH5bY2RNt3SsP/IIE7UIv6hIwRkjVjUQIqFvvGYvwJHV5I+BXvNk8EKrLLGWNMDOIzTpU44j66Anpzq1r5BwHxaBkg0X3pEDJ/ixN25wJ8QLAEn5dJlgjqnKq3XC7o0/xRMbkBiOXXK7g4HKt2UMVYIbAGjVdJX5+I7yDA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=fairphone.com; spf=pass smtp.mailfrom=fairphone.com; dkim=pass (2048-bit key) header.d=fairphone.com header.i=@fairphone.com header.b=5rRUqhHl; arc=none smtp.client-ip=209.85.218.53 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=fairphone.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=fairphone.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=fairphone.com header.i=@fairphone.com header.b="5rRUqhHl" Received: by mail-ej1-f53.google.com with SMTP id a640c23a62f3a-c15f6de6cdfso112194066b.0 for ; Fri, 10 Jul 2026 02:22:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fairphone.com; s=fair; t=1783675375; x=1784280175; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=iUnfFgpx3dZdJM3zV3PHug4HTfilmgNZwXGP6vHMpiQ=; b=5rRUqhHl7SM6pxnfM1MmKT1RlmNQ6e8/fPiixj2PM+RS759VgmCUgz82HvjEiDJN4Q a2R6Bp9FMOv5V/wR0mXIC2HvuxYiJdoCuMSj6sDP4JKC9TGAVXqG298w95aOVBJSKuLK G9IN8aPfrCIEyg6RO/ISWneH5hFVJ3Qw4vJpQM4RljnZVLyiJCeabLL5L9djMp9MRvU1 y3xrV2ATEzr5pvbrD3UWuR+eRqRjuIqjnpKC8JoGi5J2j2tnn0YqwcDu2Emd/AN+ghDa 9lFM7o2bA1DYBVCyLQ1qeTm9RVIupGVHPnW1c1yy1CPy7MdoTfPvPrlSqiQVd6ofAzg2 Xg2A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1783675375; x=1784280175; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=iUnfFgpx3dZdJM3zV3PHug4HTfilmgNZwXGP6vHMpiQ=; b=sHuliQ7E+UaG1tpv+KhbsAdszxvj+lCQVM1QMHDuSUJOIojQ/DS5J0rUbkLCci8Uh5 rW9uy+77K28uF9qA9Z6Bkd9N67wbQV6B9nsBMBYxpfTWR7glMwlYj7BXEFTUb9OrH1/A Ney2apc4mizEezGSBNY/YKqyQfnq3nIiRcwZLkL59lsXwisc8Qdr74j13NWG3CnI3gFz f2WLgJ6OBroWrPg6XqEW8Cj0/DNQuVdapvXOC8QIUOpQdsBuzGhSWcPBBK/nUqcd3+gh oBhHUs/rAusInrGgoNw1MpNkBFY3ArWjcOI61qucaaUKwV590/2RaoD9VJRn74aonvLI fiYA== X-Forwarded-Encrypted: i=1; AHgh+RoGTGKD6GeD6gjcAt8i9vo+71y/hG3ME0Fdp5u0qYZZX/sVuHuWwNfqu192R7+jP4IuKffeRbLbnsg1azw=@vger.kernel.org X-Gm-Message-State: AOJu0YzUmB+yt7Ncvkc27hU1WsvTtVet8xMM+P5CL6ZYV1QMXcVUtX75 JUwuorjoud+XE9qKhqAef1/qCbmPT/KTAwTK3/BgqJIcTI3o9rV0W5thUN/91TuP6OE= X-Gm-Gg: AfdE7cmJbblBpPrfKNXYI/xmLhbrjf9pgqi+rkgNVGe40MISu8NInWo4btS2TKqcyFS DcjIgRVIxLAhpjOCQas78FxMgvwbpZ7yorkJqAIhKTumgTVSYW+Zj5xdyaGZzUHb9Jvf1C4OIp0 j/AqO7Bqf6GXHoHXKyG+VZFmOP6011KHhK7pfllOaaebY6oH+sDoypmBo3OT0QZEZylGz8brz2+ Dr2X+8tn8kWM74/X1lcZWy9b5zYEA8KTAQL39dQn55xnjifCx1jb0cWNYTtvMSt8jZ+QyC0Ctnb vhymBcXPfgR3ajXThek9TT+TzBwTj5+uz3OO8eKDF+LUOxBKlUzJKFfD05x2/UbugQgnN/2Az4X LmXiiseFxJOAC1uPtsFpjUSukDmtIfC1zXPGqZRiziHX4q3pR+35Sl7Q2dEivZc7Ba+GF3qSm6t Gg4B+y68phAntwbtPAQZUlhinPnpfHe8zdMVokv8OSF1J4GkrYdGgh2IXvwsHAhlMHdag= X-Received: by 2002:a17:907:971f:b0:c12:7f25:cc59 with SMTP id a640c23a62f3a-c15ce0ab923mr383566866b.16.1783675374892; Fri, 10 Jul 2026 02:22:54 -0700 (PDT) Received: from [172.16.220.101] (144-178-202-138.static.ef-service.nl. [144.178.202.138]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c15dfda815dsm261785566b.36.2026.07.10.02.22.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Jul 2026 02:22:54 -0700 (PDT) From: Luca Weiss Date: Fri, 10 Jul 2026 11:22:39 +0200 Subject: [PATCH 1/4] dt-bindings: interconnect: OSM L3: Document Milos OSM L3 compatible Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260710-milos-cpu-opp-v1-1-ae7f4b09bc77@fairphone.com> References: <20260710-milos-cpu-opp-v1-0-ae7f4b09bc77@fairphone.com> In-Reply-To: <20260710-milos-cpu-opp-v1-0-ae7f4b09bc77@fairphone.com> To: Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sibi Sankar , Bjorn Andersson , Konrad Dybcio , Alexander Koskovich Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Luca Weiss X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1783675372; l=823; i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id; bh=2/pH/58ZPSVPRJvZYePDwwn0y2ezcvuAOg6I4e2E1hc=; b=mZje+eL9LnFEwjHLlmoyphuamb10BC+qArdJFGRuLfUvjg0fKeVUXAEx0HydxxY9D0RU6A61U iSsZJ2nnMRAAkMGX/QEf0uNPmQyplh7YaCMfQrso3oCzBoGdCKnf6Fp X-Developer-Key: i=luca.weiss@fairphone.com; a=ed25519; pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8= Document the OSM L3 found in the Qualcomm Milos SoC. Signed-off-by: Luca Weiss Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yam= l b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml index 41b9f758bf8b..17690ff34489 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml @@ -29,6 +29,7 @@ properties: - items: - enum: - qcom,eliza-epss-l3 + - qcom,milos-epss-l3 - qcom,sa8775p-epss-l3 - qcom,sc7280-epss-l3 - qcom,sc8280xp-epss-l3 --=20 2.55.0 From nobody Sun Jul 26 01:48:11 2026 Received: from mail-ej1-f44.google.com (mail-ej1-f44.google.com [209.85.218.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BDB983DDB13 for ; Fri, 10 Jul 2026 09:22:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.44 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783675379; cv=none; b=keoNn3A2/5M+mGQj07WI8n8BpOxwHaIQm+Gc88nsYXMhhM7ydM/1CjIaq082lbMH2mu8+sAR72/VKJ60/LtpuQXhsfTdBUOn10Pd6f11OuIPvNepklQTcw+v8eGEbRLFyQ2JIIN7v/2gPeilvzyIeIgEMgE31weoNyfBH20jpz0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783675379; c=relaxed/simple; bh=+1KKaNTX/P7/V53JMeGAGQ8XdMuCS7KUkR2X20QbUvM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=sjmGbLJigufgpFz5aU2vCCV0bt6oqJ6NkUajVRlDTAuQYgeCaTds33uDVPJCVav/MOABbrTAYlnadsftPeF+DFfF1OqvcYpZdZtW7/hG0kKi1yr6CUvKAiGccaLos60dohtoJqSm780uvRBo1f/jnDEe5xpQJ6Vp/5Oz56p3akA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=fairphone.com; spf=pass smtp.mailfrom=fairphone.com; dkim=pass (2048-bit key) header.d=fairphone.com header.i=@fairphone.com header.b=ULUXSBda; arc=none smtp.client-ip=209.85.218.44 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=fairphone.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=fairphone.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=fairphone.com header.i=@fairphone.com header.b="ULUXSBda" Received: by mail-ej1-f44.google.com with SMTP id a640c23a62f3a-c15cb6f5c12so128620566b.0 for ; Fri, 10 Jul 2026 02:22:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fairphone.com; s=fair; t=1783675376; x=1784280176; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=eqGhNzdohMFEPYe7rGIYSH65iapoiPfmEbyHAub7vT4=; b=ULUXSBdakKBgzIKKDtxc9hO2VcEF5rjtdCxiQsO0LtNItmWo2M5wGx2KbkkVIy1M7f gSAL88ZJW/R68wXxoaf7+yHfwLU+L/jL/kJZLRdmcoxkOJcpeF6Mti2j4UlJKZTQUWXC QCOll0caRl/lQphqeVkQyXT6uaBMhFKD5JsPl2pOwAMTR6wGU7PNhJL/shSZ2MYNgr/8 U4RybdnHk4/Y2gBvlCbY7eyXte29fra/4dVE/NiEPKiLHkA2rJD1sfowNMxMW15yh4cW sQmPlCCd3k1T/4redMfj4hhoMsnfeWXIjVsdF3V1wP0pz0QVR5QdVvVpHyTydkIYdKvr fYvQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1783675376; x=1784280176; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=eqGhNzdohMFEPYe7rGIYSH65iapoiPfmEbyHAub7vT4=; b=VadGKCSZkFsdiUVI782pPSI6VH4spCt4F3bUxYe3y9IuGulTazxYMijW3fUKQDk8Q9 q+4cwy7EsSUZZkuYHtrZq1bOHBJXzp2NlwqDjN97PbkPifSTuiOlMC6rd3KXUjuZHH7m 8M/RYFpazXLJtEge/i9QLt0WKWoG1YpQKoJ1NYegNRbKWsZZFB8OyyA1Il+Nwh/nxsnC tSNoZTzVnhAn3dNTj+RvlkxjNG4vCvy4o2bXzyV0Nr/dHmnUQvcYLXT3cpcl04ZOh9Sb H831mennnS/Aw8OcfdQpyy4h0BJC1VhFc4ELEo2Y41Dw2j+2xrllTSgvkJj/kq8k/VE/ cY/w== X-Forwarded-Encrypted: i=1; AHgh+Rq/d/YuOgREV6GsRJb5udUc1TNPovO+/QrewPzki+JsuEwweGZsx4Ex9KNd+vJyMDNw1UL3UycDNqHe7E4=@vger.kernel.org X-Gm-Message-State: AOJu0YwxUuHhEj8VC4o4IiZgNgSNBdVjTsEApegl6H20W8Adt3QBi+Ef +5Nr77FoFWoi97U/CwhggUke5af+WS2xhdnZmjjxfHu3hkWc+CtZTiXjkniL18lD8Ok= X-Gm-Gg: AfdE7cnh7f2+t5PVFqfcu3NPPTiyc1njsgOWrtL5DV385Owqjeeo35VrO1hvckN4Zbv uNC/gO8RZNvp62PH1ylUzRRnWmi12HjFZ1tdTEe+e6z+JT4KaWyJ4+hxmwrNsgBWtsiOCy6ii0R Qbm20PcoumTjYP3On4jVZgR8IqPLWEtb8ldm8dTdAu/Bw9zIzpc3IQ2Lqn7X5D/idXRl014Y1OU b3sYP0bKiq/uokAVm6U8D+SSdVykBNOhZp4kpwGqeQWCINLF/j/CkxdpXxZPe4H6FElWiw5CzGp jxCMt+5T7iEarL23XQBbcYYQq/byQ4y+JyaNlmRs47FypbmQwvbgU/hfDYRXUHLM1QVcW0ITAk2 i1SLmLdfUjaOI70/TV2vimli0yQjftI73jZKI3GUyBWbE5RBHvrGSn56IPblIjsuXCPvUeie1y2 gHURl3lGOnli6vUcGnKJRApmSiD5QzCZFtsvW8eyTLbzl0+sz1BfPjpYTjbJ9wpkjI2PA3j/MhW QLFOg== X-Received: by 2002:a17:906:7303:b0:c15:dd38:7f26 with SMTP id a640c23a62f3a-c15dd387f5emr361970666b.31.1783675376105; Fri, 10 Jul 2026 02:22:56 -0700 (PDT) Received: from [172.16.220.101] (144-178-202-138.static.ef-service.nl. [144.178.202.138]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c15dfda815dsm261785566b.36.2026.07.10.02.22.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Jul 2026 02:22:55 -0700 (PDT) From: Luca Weiss Date: Fri, 10 Jul 2026 11:22:40 +0200 Subject: [PATCH 2/4] arm64: dts: qcom: milos: add OSM L3 node Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260710-milos-cpu-opp-v1-2-ae7f4b09bc77@fairphone.com> References: <20260710-milos-cpu-opp-v1-0-ae7f4b09bc77@fairphone.com> In-Reply-To: <20260710-milos-cpu-opp-v1-0-ae7f4b09bc77@fairphone.com> To: Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sibi Sankar , Bjorn Andersson , Konrad Dybcio , Alexander Koskovich Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Luca Weiss X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1783675372; l=931; i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id; bh=+1KKaNTX/P7/V53JMeGAGQ8XdMuCS7KUkR2X20QbUvM=; b=7KzlagRFrXe26etPJVuOlzaav3hBDxk223iegLY9WRmoMroFHuylAyvI6EIEvhMaF09DPfOs4 kH+zUzLWvF1DPyPHaQf9La7JjzSfvsNwTKQIMTt3BOFTQ5qTJFmhAAa X-Developer-Key: i=luca.weiss@fairphone.com; a=ed25519; pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8= Add the OSC L3 Cache controller node. Signed-off-by: Luca Weiss Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/milos.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/milos.dtsi b/arch/arm64/boot/dts/qcom= /milos.dtsi index 8c9232988953..1172a4f6adab 100644 --- a/arch/arm64/boot/dts/qcom/milos.dtsi +++ b/arch/arm64/boot/dts/qcom/milos.dtsi @@ -2639,6 +2639,18 @@ rpmhpd_opp_turbo_l1: opp-416 { }; }; =20 + epss_l3: interconnect@17d90000 { + compatible =3D "qcom,milos-epss-l3", "qcom,epss-l3"; + reg =3D <0x0 0x17d90000 0x0 0x1000>; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_GPLL0>; + clock-names =3D "xo", + "alternate"; + + #interconnect-cells =3D <1>; + }; + cpufreq_hw: cpufreq@17d91000 { compatible =3D "qcom,milos-cpufreq-epss", "qcom,cpufreq-epss"; reg =3D <0x0 0x17d91000 0x0 0x1000>, --=20 2.55.0 From nobody Sun Jul 26 01:48:11 2026 Received: from mail-ej1-f51.google.com (mail-ej1-f51.google.com [209.85.218.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AC9073DF018 for ; Fri, 10 Jul 2026 09:22:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.51 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783675380; cv=none; b=QIGvIG4LfmO9k1mJQUcR2z5j+v8XAjgH7WHAJnUYD9IpSekMEh4l+e/VKxGiUwtpXuMcnUWSI4zlWBllACh9E1TFdw/8udLB2p7DpRC3wkKcmYXvXwKTDpgnqQPu8ymtFT4mmOrmQbkdHhYCIOKUZKWbkNO2KGi/lUE1kM5ERfs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783675380; c=relaxed/simple; bh=MKOhRPK9BzP+Ba1kQzcE+8jxLp4Hbza+J3F5k7LQQLE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=nHWXFgiNFbOyXICMhSrPSZCXmKJ7nz1oko+QvDaLSpJs2msMv5iuUG/fClczItFTGB4D+7VqP0R2xKuh7XwgK4E44smFhWzmFjDbXV/8wKIISdJwJMvFyGt8Cgk9nk2YvwRYvDg1HGljpyy4Cblc47fmaAeyxS0qDXd5gpHbJSQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=fairphone.com; spf=pass smtp.mailfrom=fairphone.com; dkim=pass (2048-bit key) header.d=fairphone.com header.i=@fairphone.com header.b=FUrzNPQo; arc=none smtp.client-ip=209.85.218.51 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=fairphone.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=fairphone.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=fairphone.com header.i=@fairphone.com header.b="FUrzNPQo" Received: by mail-ej1-f51.google.com with SMTP id a640c23a62f3a-c15d47266baso88757866b.3 for ; Fri, 10 Jul 2026 02:22:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fairphone.com; s=fair; t=1783675377; x=1784280177; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=K2PljI4ZF98i/3jw94W7rpF3nBz83urTcSx2ZEy+Me0=; b=FUrzNPQosMBvoBVHxYq7yYmSg7EcDwfXQ1QSVG1BAUbTYsLEelQqmx0FtqUBR9JGo7 ffsfM067neuMHOWVbhNgFaH9e/yiKciWjXymaQRFd/Fjf3+EsMZGNbMl5ZTH8293XacJ 5uskzyP1w/mqfPnqT5UXxlsJkjEUDJhZ7TqCsVsyNRi0LyM84RdGfB6g+PE+23t25B2C xrSXUbHLJtG3SadijssjYzTnxqIFhwtd5rZuc0fFEevJJ9EfqLiBtdQEkoFAKws3YzdG 7Tfrqt9LxoXo8Q4m3rKp1J4pGj04X9V/uoGw3/Je0ZQl5SqXEsCHIm9zmmpfSArlGtDP mztw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1783675377; x=1784280177; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=K2PljI4ZF98i/3jw94W7rpF3nBz83urTcSx2ZEy+Me0=; b=UV9Em7p+FtVS3oyvcL4y8nCzviSQRILw32HJU2JYfytmFiC/LROZ9PVKfUgw6947Le VCSLArrhHy57yrjdsMGUaa1wnmlnvlNHLdks0gLyoNA2LONMqRvkfVYC/wR1L/3lMJKd 82ZVOabcTSc+65Nc21g6KvbJCCfLqqo8w6npRAPPwFfxTWdg7rLubCf3BzZK+iVPhtWJ Z0CyCs9QSE7wW5jmgXv+2RqzFabvFjCX5VZi9Rn0NUHqhI4eACDcwriG8G+dfTm6+/QI aXQbw3M1Ly5LoDNMdOClxPkjI+aObWJxSdOEPWnOhthclmF8yzTPbyODrk6pgk96kqsI vG9g== X-Forwarded-Encrypted: i=1; AHgh+Rr34SUTpQ7ImfkhecYfnUYunaZvE7ISVxAIyAND08cBdKrh2Mrms9MHYLlkuJ8AVKBA6FbJll/XQ+uB6Po=@vger.kernel.org X-Gm-Message-State: AOJu0YxusavNGSv68Y8BoYTDAo51vluSxy6u3R6DrUOZafGyk0Cvk1iL sx/HlSzZMzVfxAdxlSbJztIaJd7FrZdRxvBa+RE6J58it8/8gwm4/egOBaJfMBp5OXA= X-Gm-Gg: AfdE7cnHHpkZJ7Uznc0Wk6gxjd/Wwil+O+bP669a93b9aKfT0tXkSN3+HsXFLxXi3h3 am9jQFYI6FoNuBfiTrutXlUJsXbdcAkbGmeVvImYJq9l9uHsV4X8+ebEGohKP6Zef6FJlAzpuaZ nXxG9niGb3nF0uOqtA7Pf2k/Or1mjJKi9HxHjFmY0+f4fLS+k8OyBtO72g8lOpKWXy7cxx+nBgi V+7l0rPUxhe3n8HqXyesBQ7RBz2qqCNZBWZiGS5c8x8wxEOalmj0YG4SH1XYgCS8/6dQa2A6gqT hgwpTnIqYziJVMfSn4r0qULfd2b0EdzsUYUzh/NAxhNfSL6HgmVlU+tl/sdaoSpSaywM7IuefK2 BH3UP9C/zd3guq1grxIH0AaJEA0/xInzh4sp2KBNV2V8qUgiOfqS00Ncn63smNCYjXi7H4m2kM9 +OurVMpu3lmK+aP40J/0/jUWh2bOY416TPy2mtAf6PhzJ/a/N03ounx5WqngZNDOfHCEE= X-Received: by 2002:a17:907:76d2:b0:c12:7c80:8844 with SMTP id a640c23a62f3a-c15ce0c0b28mr312764666b.41.1783675377205; Fri, 10 Jul 2026 02:22:57 -0700 (PDT) Received: from [172.16.220.101] (144-178-202-138.static.ef-service.nl. [144.178.202.138]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c15dfda815dsm261785566b.36.2026.07.10.02.22.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Jul 2026 02:22:56 -0700 (PDT) From: Luca Weiss Date: Fri, 10 Jul 2026 11:22:41 +0200 Subject: [PATCH 3/4] arm64: dts: qcom: milos: add CPU interconnect properties Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260710-milos-cpu-opp-v1-3-ae7f4b09bc77@fairphone.com> References: <20260710-milos-cpu-opp-v1-0-ae7f4b09bc77@fairphone.com> In-Reply-To: <20260710-milos-cpu-opp-v1-0-ae7f4b09bc77@fairphone.com> To: Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sibi Sankar , Bjorn Andersson , Konrad Dybcio , Alexander Koskovich Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Luca Weiss X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1783675372; l=3619; i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id; bh=MKOhRPK9BzP+Ba1kQzcE+8jxLp4Hbza+J3F5k7LQQLE=; b=mJD3v2Seb0xmqYIKaKsx0e+KlFU1SZrgJW2OdoDBPr3JfIv9SYXWkvffUlTG+bZV5kOSR2efg 7uWrnUEnWqcCm5aUZf93Sz17FlJtoXMz/KpAWPvedkjxG4A2sd/PG/6 X-Developer-Key: i=luca.weiss@fairphone.com; a=ed25519; pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8= Add the interconnect entry for each CPU, with 2 different paths: - CPU to DDR - L3 Cache from CPU to DDR interface Signed-off-by: Luca Weiss --- arch/arm64/boot/dts/qcom/milos.dtsi | 41 +++++++++++++++++++++++++++++++++= ++++ 1 file changed, 41 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/milos.dtsi b/arch/arm64/boot/dts/qcom= /milos.dtsi index 1172a4f6adab..8e288b5dfc58 100644 --- a/arch/arm64/boot/dts/qcom/milos.dtsi +++ b/arch/arm64/boot/dts/qcom/milos.dtsi @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -65,6 +66,11 @@ cpu0: cpu@0 { =20 qcom,freq-domain =3D <&cpufreq_hw 0>; =20 + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; + #cooling-cells =3D <2>; =20 l2_0: l2-cache { @@ -98,6 +104,11 @@ cpu1: cpu@100 { =20 qcom,freq-domain =3D <&cpufreq_hw 0>; =20 + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; + #cooling-cells =3D <2>; }; =20 @@ -118,6 +129,11 @@ cpu2: cpu@200 { =20 qcom,freq-domain =3D <&cpufreq_hw 0>; =20 + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; + #cooling-cells =3D <2>; =20 l2_2: l2-cache { @@ -145,6 +161,11 @@ cpu3: cpu@300 { =20 qcom,freq-domain =3D <&cpufreq_hw 0>; =20 + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; + #cooling-cells =3D <2>; }; =20 @@ -165,6 +186,11 @@ cpu4: cpu@400 { =20 qcom,freq-domain =3D <&cpufreq_hw 1>; =20 + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; + #cooling-cells =3D <2>; =20 l2_4: l2-cache { @@ -192,6 +218,11 @@ cpu5: cpu@500 { =20 qcom,freq-domain =3D <&cpufreq_hw 1>; =20 + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; + #cooling-cells =3D <2>; =20 l2_5: l2-cache { @@ -219,6 +250,11 @@ cpu6: cpu@600 { =20 qcom,freq-domain =3D <&cpufreq_hw 1>; =20 + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; + #cooling-cells =3D <2>; =20 l2_6: l2-cache { @@ -246,6 +282,11 @@ cpu7: cpu@700 { =20 qcom,freq-domain =3D <&cpufreq_hw 2>; =20 + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; + #cooling-cells =3D <2>; =20 l2_7: l2-cache { --=20 2.55.0 From nobody Sun Jul 26 01:48:11 2026 Received: from mail-ed1-f53.google.com (mail-ed1-f53.google.com [209.85.208.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 251233EEAF0 for ; Fri, 10 Jul 2026 09:22:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783675382; cv=none; b=bNlyc75bOjlDe4sLjrwUl3Yf4WwnU9B0w4wk6O//3dHtn+VkjFHB7gcA0i0cK+HClnhw3pIQ0oQV7520+/nXlHbPcewjjBq+3zKKMGIROvF6KHH6mhzBA5PbSzObQN8mWEwcTuvcMfq6r49xuRKVaHUvpOGzg9nSGyIFz9qQrvQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783675382; c=relaxed/simple; bh=6vvvoS+Br7JM4+bO6PoXZDcYhJ0TxtZIz5yf5h8lYBI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=p7U3aUcv1nk9ZHl4S3GeYnoPGZ8PldpA8YmEuIt3UqwtzmZ3AuXurhxBWMuz1POhTMLRl0Iogq5hUTvUhfEGfZG1GtfdraGqSIsp+aSn7XPM0ZP3G20jJdrcVdBkU5J3G0VeH285oMmquvuZ+1cTBUovmYJjpemBZP608P4vCAw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=fairphone.com; spf=pass smtp.mailfrom=fairphone.com; dkim=pass (2048-bit key) header.d=fairphone.com header.i=@fairphone.com header.b=jjUNeS9/; arc=none smtp.client-ip=209.85.208.53 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=fairphone.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=fairphone.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=fairphone.com header.i=@fairphone.com header.b="jjUNeS9/" Received: by mail-ed1-f53.google.com with SMTP id 4fb4d7f45d1cf-698aa7ba3e6so1285783a12.1 for ; Fri, 10 Jul 2026 02:22:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fairphone.com; s=fair; t=1783675378; x=1784280178; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=Yg7ioh22XhaJVGdlXVxo6srFg4mbOi5uMGV4uuYdkyg=; b=jjUNeS9/hfWAi9hAA0YlXGQp5Cz7gFKWy/Ne7FzGYNLMi33sudxUlGYS2EtPs01nl6 cGIYxfPK0+d17zg6pScVd2aONuSJrIlukGpKrK6iDlbyJXxf6vWqKsBk6R9sbqxEApDG 51yPiXCa0q1WzlgiUC9SznzG4IplD/Yt1+P9Eju0fjbyoba+nnXd0+sJtK/AB6FTffuA 7LnMkFaqCQ0GgxfIEVE2ZT1NN1hCkNdrsvnC9gFI3jHWm2IWhG74QxRGl8MBqbrlsXNV sVgdxxjDKQsWmVkTf9lJgyoHtsUyc6rCJJEg7iRKKYfClbTey++8xqPRI+eIKrBPC0FL VcTQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1783675378; x=1784280178; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=Yg7ioh22XhaJVGdlXVxo6srFg4mbOi5uMGV4uuYdkyg=; b=XGkoYq4uuQabr7NXyHhCywY3AB7wmBNiVXO77R073MlNeeQOWdWbej5+xaGlqQNwAQ kVwr+j1edgeGaftdW4KGo3kQepU8H2uWDSCUKJyrz+lzJcFCa1mdIgoBiz+WA4JDwSQF bEh5nnIj7d0JMEp0PdCuJK0LWH8Zl3dNB8UeNeX4dou0zEqlf8m8GDTWoISf65LT4Ba8 mWij/oQKOA6Tsg0SPoaVLGfAIc3KGmTNjK3bmjS6fwm3riKIBdz6sbtTmvEMkw0QuE8A pnxxo9rdpYVADvvBWHjrvOQ+Bj9Bj9aPuDqGSi9lRVXLCRMtiS4MhYx88ncmcKcfMW9T XrcA== X-Forwarded-Encrypted: i=1; AHgh+RoYoGB00S/1pb+fllZqZta+QllHdTb+5yIP/R1muVBgvhSgI/4BNHNJNuTwNGDlVENMcNbx407cnew4PZI=@vger.kernel.org X-Gm-Message-State: AOJu0YwDRB0uWd4TVgEkxZ6x2fFSh/z8tq3co9an1+4pTwaTiz4dgOGl qBn9E0NnN980caeINnRWvrp1i5coWfOuWgzqEQ85GacA/cFMPihNOipYgpyPYa54BL0= X-Gm-Gg: AfdE7cllWUhjLecfWR69ZFE8UaSws6QqOgRDi+2Qt9cueq/FL8uk74b2XEgfk9YzEZJ 58iCRqehMc6CydBwSsdX+E6bmOxJOGFVE5Ul6c+cL0d60oNHARrZDnve2Q7PjwlSuVOeXnMkhMk kPZ53QrZEOrFpdu6iXqzuFu0ggrUV6AAWb4gxw6SSlf4+32Naw6Rqr1mwP1Wkm7Pb8WHCM70jtY pWdBlBUqSkAAKdBODSZXkJlKxez8SuCdOpkPgTtrfJEgDWcnMBbjbQtUaB9x8XBPFOBR9WBto3L H1p/kJ7vpSP2hEJM4ZBrSmPaxU8uRi1wvouGyE0ssOb+tniBYBwcPVoXDSoXKZnloMfp2uDR7wU 7Iz4PNIytCSaMWuMvLsY4OaXN1fry/bZYCY9UudxwLydaA4uhZFQqhX3RyfDfJ6ODni/vO7/OOC zmJvIN3fCv+i4UQbcL2tkB/uLIV3sddoZbddO1u4KiInWj2GrTgYsj0qmOC4q/aNzsmRo= X-Received: by 2002:a17:907:76f3:b0:c12:330e:ea76 with SMTP id a640c23a62f3a-c15ce18c17amr333319866b.37.1783675378323; Fri, 10 Jul 2026 02:22:58 -0700 (PDT) Received: from [172.16.220.101] (144-178-202-138.static.ef-service.nl. [144.178.202.138]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c15dfda815dsm261785566b.36.2026.07.10.02.22.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Jul 2026 02:22:57 -0700 (PDT) From: Luca Weiss Date: Fri, 10 Jul 2026 11:22:42 +0200 Subject: [PATCH 4/4] arm64: dts: qcom: milos: add CPU OPP table with DDR & L3 bandwidths Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260710-milos-cpu-opp-v1-4-ae7f4b09bc77@fairphone.com> References: <20260710-milos-cpu-opp-v1-0-ae7f4b09bc77@fairphone.com> In-Reply-To: <20260710-milos-cpu-opp-v1-0-ae7f4b09bc77@fairphone.com> To: Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sibi Sankar , Bjorn Andersson , Konrad Dybcio , Alexander Koskovich Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Luca Weiss X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1783675372; l=10846; i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id; bh=6vvvoS+Br7JM4+bO6PoXZDcYhJ0TxtZIz5yf5h8lYBI=; b=Yb7cyVD/7L9tLGDe6hKl9sNaOsQlKvBsiS9fkifLaKpyqyWG+flOdZL2RtSne7+2XIIDwbEAf icPmeNZ27FKCLt4BEeFtjzeN+6c6M5/YxtfWI2SO1Q+8lsYzXotXcy2 X-Developer-Key: i=luca.weiss@fairphone.com; a=ed25519; pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8= Add the OPP tables for each CPU clusters (cpu0-3, cpu4-6 & cpu7) to permit scaling the DDR and L3 cache frequency by aggregating bandwidth requests of all CPU core with reference to the current OPP they are configured in by the LMH/EPSS hardware. The effect is a proper caches & DDR frequency scaling when CPU cores change frequency. The OPP tables were built using the downstream memlat ddr & l3 tables for each cluster type with the actual EPSS cpufreq LUT tables from running devices. Note, that higher frequencies than SM7635 are available on QCS6690, those have been added here as far as possible but may not be fully complete. Additional OPPs may need to be added for that SoC. Signed-off-by: Luca Weiss Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/milos.dtsi | 291 ++++++++++++++++++++++++++++++++= ++++ 1 file changed, 291 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/milos.dtsi b/arch/arm64/boot/dts/qcom= /milos.dtsi index 8e288b5dfc58..974afd7a582e 100644 --- a/arch/arm64/boot/dts/qcom/milos.dtsi +++ b/arch/arm64/boot/dts/qcom/milos.dtsi @@ -66,6 +66,8 @@ cpu0: cpu@0 { =20 qcom,freq-domain =3D <&cpufreq_hw 0>; =20 + operating-points-v2 =3D <&cpu0_opp_table>; + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&epss_l3 MASTER_EPSS_L3_APPS @@ -104,6 +106,8 @@ cpu1: cpu@100 { =20 qcom,freq-domain =3D <&cpufreq_hw 0>; =20 + operating-points-v2 =3D <&cpu0_opp_table>; + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&epss_l3 MASTER_EPSS_L3_APPS @@ -129,6 +133,8 @@ cpu2: cpu@200 { =20 qcom,freq-domain =3D <&cpufreq_hw 0>; =20 + operating-points-v2 =3D <&cpu0_opp_table>; + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&epss_l3 MASTER_EPSS_L3_APPS @@ -161,6 +167,8 @@ cpu3: cpu@300 { =20 qcom,freq-domain =3D <&cpufreq_hw 0>; =20 + operating-points-v2 =3D <&cpu0_opp_table>; + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&epss_l3 MASTER_EPSS_L3_APPS @@ -186,6 +194,8 @@ cpu4: cpu@400 { =20 qcom,freq-domain =3D <&cpufreq_hw 1>; =20 + operating-points-v2 =3D <&cpu4_opp_table>; + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&epss_l3 MASTER_EPSS_L3_APPS @@ -218,6 +228,8 @@ cpu5: cpu@500 { =20 qcom,freq-domain =3D <&cpufreq_hw 1>; =20 + operating-points-v2 =3D <&cpu4_opp_table>; + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&epss_l3 MASTER_EPSS_L3_APPS @@ -250,6 +262,8 @@ cpu6: cpu@600 { =20 qcom,freq-domain =3D <&cpufreq_hw 1>; =20 + operating-points-v2 =3D <&cpu4_opp_table>; + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&epss_l3 MASTER_EPSS_L3_APPS @@ -282,6 +296,8 @@ cpu7: cpu@700 { =20 qcom,freq-domain =3D <&cpufreq_hw 2>; =20 + operating-points-v2 =3D <&cpu7_opp_table>; + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, <&epss_l3 MASTER_EPSS_L3_APPS @@ -435,6 +451,281 @@ memory@0 { reg =3D <0 0 0 0>; }; =20 + cpu0_opp_table: opp-table-cpu0 { + compatible =3D "operating-points-v2"; + opp-shared; + + opp-441600000 { + opp-hz =3D /bits/ 64 <441600000>; + opp-peak-kBps =3D <(547000 * 4) (364800 * 32)>; + }; + + opp-595200000 { + opp-hz =3D /bits/ 64 <595200000>; + opp-peak-kBps =3D <(547000 * 4) (556800 * 32)>; + }; + + opp-787200000 { + opp-hz =3D /bits/ 64 <787200000>; + opp-peak-kBps =3D <(547000 * 4) (710400 * 32)>; + }; + + opp-902400000 { + opp-hz =3D /bits/ 64 <902400000>; + opp-peak-kBps =3D <(547000 * 4) (806400 * 32)>; + }; + + opp-1017600000 { + opp-hz =3D /bits/ 64 <1017600000>; + opp-peak-kBps =3D <(547000 * 4) (998400 * 32)>; + }; + + opp-1113600000 { + opp-hz =3D /bits/ 64 <1113600000>; + opp-peak-kBps =3D <(547000 * 4) (998400 * 32)>; + }; + + opp-1228800000 { + opp-hz =3D /bits/ 64 <1228800000>; + opp-peak-kBps =3D <(768000 * 4) (1094400 * 32)>; + }; + + opp-1344000000 { + opp-hz =3D /bits/ 64 <1344000000>; + opp-peak-kBps =3D <(768000 * 4) (1209600 * 32)>; + }; + + opp-1497600000 { + opp-hz =3D /bits/ 64 <1497600000>; + opp-peak-kBps =3D <(768000 * 4) (1363200 * 32)>; + }; + + opp-1593600000 { + opp-hz =3D /bits/ 64 <1593600000>; + /* TODO: ddr4 =3D 1017000, ddr5 =3D 1555000 */ + opp-peak-kBps =3D <(1555000 * 4) (1363200 * 32)>; + }; + + opp-1708800000 { + opp-hz =3D /bits/ 64 <1708800000>; + /* TODO: ddr4 =3D 1017000, ddr5 =3D 1555000 */ + opp-peak-kBps =3D <(1555000 * 4) (1497600 * 32)>; + }; + + opp-1804800000 { + opp-hz =3D /bits/ 64 <1804800000>; + /* TODO: ddr4 =3D 1017000, ddr5 =3D 1555000 */ + opp-peak-kBps =3D <(1555000 * 4) (1516800 * 32)>; + }; + + opp-2054400000 { + opp-hz =3D /bits/ 64 <2054400000>; + /* TODO: ddr4 =3D 1017000, ddr5 =3D 1555000 */ + opp-peak-kBps =3D <(1555000 * 4) (1804800 * 32)>; + }; + }; + + cpu4_opp_table: opp-table-cpu4 { + compatible =3D "operating-points-v2"; + opp-shared; + + opp-480000000 { + opp-hz =3D /bits/ 64 <480000000>; + opp-peak-kBps =3D <(547000 * 4) (364800 * 32)>; + }; + + opp-633600000 { + opp-hz =3D /bits/ 64 <633600000>; + opp-peak-kBps =3D <(547000 * 4) (556800 * 32)>; + }; + + opp-787200000 { + opp-hz =3D /bits/ 64 <787200000>; + opp-peak-kBps =3D <(547000 * 4) (556800 * 32)>; + }; + + opp-940800000 { + opp-hz =3D /bits/ 64 <940800000>; + opp-peak-kBps =3D <(547000 * 4) (556800 * 32)>; + }; + + opp-1056000000 { + opp-hz =3D /bits/ 64 <1056000000>; + /* TODO: ddr4 =3D 1017000, ddr5 =3D 768000 */ + opp-peak-kBps =3D <(768000 * 4) (710400 * 32)>; + }; + + opp-1190400000 { + opp-hz =3D /bits/ 64 <1190400000>; + /* TODO: ddr4 =3D 1017000, ddr5 =3D 768000 */ + opp-peak-kBps =3D <(768000 * 4) (710400 * 32)>; + }; + + opp-1286400000 { + opp-hz =3D /bits/ 64 <1286400000>; + /* TODO: ddr4 =3D 1708000, ddr5 =3D 1555000 */ + opp-peak-kBps =3D <(1555000 * 4) (902400 * 32)>; + }; + + opp-1401600000 { + opp-hz =3D /bits/ 64 <1401600000>; + /* TODO: ddr4 =3D 1708000, ddr5 =3D 1555000 */ + opp-peak-kBps =3D <(1555000 * 4) (1209600 * 32)>; + }; + + opp-1497600000 { + opp-hz =3D /bits/ 64 <1497600000>; + /* TODO: ddr4 =3D 1708000, ddr5 =3D 1555000 */ + opp-peak-kBps =3D <(1555000 * 4) (1209600 * 32)>; + }; + + opp-1612800000 { + opp-hz =3D /bits/ 64 <1612800000>; + /* TODO: ddr4 =3D 1708000, ddr5 =3D 1555000 */ + opp-peak-kBps =3D <(1555000 * 4) (1363200 * 32)>; + }; + + opp-1708800000 { + opp-hz =3D /bits/ 64 <1708800000>; + opp-peak-kBps =3D <(1708000 * 4) (1363200 * 32)>; + }; + + opp-1824000000 { + opp-hz =3D /bits/ 64 <1824000000>; + opp-peak-kBps =3D <(1708000 * 4) (1497600 * 32)>; + }; + + opp-1920000000 { + opp-hz =3D /bits/ 64 <1920000000>; + /* TODO: ddr4 =3D 1708000, ddr5 =3D 2092000 */ + opp-peak-kBps =3D <(2092000 * 4) (1497600 * 32)>; + }; + + opp-2016000000 { + opp-hz =3D /bits/ 64 <2016000000>; + /* TODO: ddr4 =3D 1708000, ddr5 =3D 2092000 */ + opp-peak-kBps =3D <(2092000 * 4) (1497600 * 32)>; + }; + + opp-2073600000 { + opp-hz =3D /bits/ 64 <2073600000>; + /* TODO: ddr4 =3D 1708000, ddr5 =3D 2092000 */ + opp-peak-kBps =3D <(2092000 * 4) (1497600 * 32)>; + }; + + opp-2208000000 { + opp-hz =3D /bits/ 64 <2208000000>; + /* TODO: ddr4 =3D 1708000, ddr5 =3D 2092000 */ + opp-peak-kBps =3D <(2092000 * 4) (1516800 * 32)>; + }; + + opp-2400000000 { + opp-hz =3D /bits/ 64 <2400000000>; + /* TODO: ddr4 =3D 1708000, ddr5 =3D 3196000 */ + opp-peak-kBps =3D <(3196000 * 4) (1516800 * 32)>; + }; + + opp-2707200000 { + opp-hz =3D /bits/ 64 <2707200000>; + /* TODO: ddr4 =3D 1708000, ddr5 =3D 3196000 */ + opp-peak-kBps =3D <(3196000 * 4) (1804800 * 32)>; + }; + }; + + cpu7_opp_table: opp-table-cpu7 { + compatible =3D "operating-points-v2"; + opp-shared; + + opp-480000000 { + opp-hz =3D /bits/ 64 <480000000>; + opp-peak-kBps =3D <(547000 * 4) (364800 * 32)>; + }; + + opp-633600000 { + opp-hz =3D /bits/ 64 <633600000>; + opp-peak-kBps =3D <(547000 * 4) (556800 * 32)>; + }; + + opp-787200000 { + opp-hz =3D /bits/ 64 <787200000>; + opp-peak-kBps =3D <(547000 * 4) (806400 * 32)>; + }; + + opp-960000000 { + opp-hz =3D /bits/ 64 <960000000>; + opp-peak-kBps =3D <(547000 * 4) (806400 * 32)>; + }; + + opp-1094400000 { + opp-hz =3D /bits/ 64 <1094400000>; + /* TODO: ddr4 =3D 1017000, ddr5 =3D 768000 */ + opp-peak-kBps =3D <(768000 * 4) (998400 * 32)>; + }; + + opp-1209600000 { + opp-hz =3D /bits/ 64 <1209600000>; + /* TODO: ddr4 =3D 1017000, ddr5 =3D 768000 */ + opp-peak-kBps =3D <(768000 * 4) (998400 * 32)>; + }; + + opp-1324800000 { + opp-hz =3D /bits/ 64 <1324800000>; + opp-peak-kBps =3D <(1555000 * 4) (998400 * 32)>; + }; + + opp-1459200000 { + opp-hz =3D /bits/ 64 <1459200000>; + opp-peak-kBps =3D <(1555000 * 4) (1209600 * 32)>; + }; + + opp-1651200000 { + opp-hz =3D /bits/ 64 <1651200000>; + opp-peak-kBps =3D <(1708000 * 4) (1209600 * 32)>; + }; + + opp-1766400000 { + opp-hz =3D /bits/ 64 <1766400000>; + /* TODO: ddr4 =3D 1708000, ddr5 =3D 2092000 */ + opp-peak-kBps =3D <(2092000 * 4) (1363200 * 32)>; + }; + + opp-1900800000 { + opp-hz =3D /bits/ 64 <1900800000>; + /* TODO: ddr4 =3D 2092000, ddr5 =3D 3196000 */ + opp-peak-kBps =3D <(3196000 * 4) (1497600 * 32)>; + }; + + opp-2208000000 { + opp-hz =3D /bits/ 64 <2208000000>; + /* TODO: ddr4 =3D 2092000, ddr5 =3D 3196000 */ + opp-peak-kBps =3D <(3196000 * 4) (1497600 * 32)>; + }; + + opp-2304000000 { + opp-hz =3D /bits/ 64 <2304000000>; + /* TODO: ddr4 =3D 2092000, ddr5 =3D 3196000 */ + opp-peak-kBps =3D <(3196000 * 4) (1516800 * 32)>; + }; + + opp-2496000000 { + opp-hz =3D /bits/ 64 <2496000000>; + /* TODO: ddr4 =3D 2092000, ddr5 =3D 3196000 */ + opp-peak-kBps =3D <(3196000 * 4) (1516800 * 32)>; + }; + + opp-2707200000 { + opp-hz =3D /bits/ 64 <2707200000>; + /* TODO: ddr4 =3D 2092000, ddr5 =3D 3196000 */ + opp-peak-kBps =3D <(3196000 * 4) (1804800 * 32)>; + }; + + opp-2918400000 { + opp-hz =3D /bits/ 64 <2918400000>; + /* TODO: ddr4 =3D 2092000, ddr5 =3D 3196000 */ + opp-peak-kBps =3D <(3196000 * 4) (1804800 * 32)>; + }; + }; + pmu-a520 { compatible =3D "arm,cortex-a520-pmu"; interrupts =3D ; --=20 2.55.0