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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-31189cd8234sm33008273eec.9.2026.07.10.10.46.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Jul 2026 10:46:57 -0700 (PDT) From: Kathiravan Thirumoorthy Date: Fri, 10 Jul 2026 23:16:40 +0530 Subject: [PATCH v3 1/2] dt-bindings: phy: qcom,ipq8074-qmp-pcie: document IPQ9650 QMP PCIe PHYs Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260710-ipq9650_pcie_phy-v3-1-ef6018818d33@oss.qualcomm.com> References: <20260710-ipq9650_pcie_phy-v3-0-ef6018818d33@oss.qualcomm.com> In-Reply-To: <20260710-ipq9650_pcie_phy-v3-0-ef6018818d33@oss.qualcomm.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Kathiravan Thirumoorthy , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski X-Mailer: b4 0.15.2 X-Proofpoint-ORIG-GUID: n1JsEQmYnvcabZPq2nCPRqOdk11_jbhl X-Authority-Analysis: v=2.4 cv=PLg/P/qC c=1 sm=1 tr=0 ts=6a513013 cx=c_pps a=RP+M6JBNLl+fLTcSJhASfg==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=EUspDBNiAAAA:8 a=pO3CVo40WvI9-LPkYfMA:9 a=QEXdDO2ut3YA:10 a=iS9zxrgQBfv6-_F4QbHw:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwNzEwMDE3NyBTYWx0ZWRfXzromzcC6qWuV IutXNDxvTWX7kMuSUD4U1AfzRET3MvxRtEgSEhsfFFcqfsfAmMPNbh780M/yP0p5cEcadlqyug0 ifD61pXtFNcggOe+76FGPwqNMGt/cw4= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzEwMDE3NyBTYWx0ZWRfXyqIbnYmIJzN8 GmbO76p3bgwKLwqG3cUylxt7XnI8Ao9IEbNmyE0D7JH93IRv9+HS5JZXwwTPC/+BjRjBEqWDzQU JUntLoHmARYuEIqF0ScIn3CeIjLAps8PtqKIgSC0hUnqMDlMQONtGMz5L08+knNBm/nDDBqkRoc 8UbWAh264ijPfOi52V4O+Ciy4pDEskK6Jt3sBaNXop7HcloWZk4//ZCXbZKkoFJyBHMXEZqv6MP Io2Yrd9C2FIEy3MEvX7Mjh8TK89PnztwoKxmnukiw3qDTiPHQ3H4fso8Txf4C+sTgOSx6iSMPNA rXGCNPx/UG96Xv0IgztfNEPb9a742wCXvYi9WhUXa4YEnO0o4Vj9pfAoB/Z9SxJyzjoPFdnzTok KkTkYDZn2GUF1BwoxQc3T5DnNivsFXV08LrqzvSpsy07RE44kUvcwBx2/CoLYdDRppW7L52p1Eq rZQePkBIeDcj11soYqg== X-Proofpoint-GUID: n1JsEQmYnvcabZPq2nCPRqOdk11_jbhl X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-10_05,2026-07-10_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 phishscore=0 suspectscore=0 clxscore=1015 priorityscore=1501 impostorscore=0 malwarescore=0 adultscore=0 bulkscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607100177 Document the single-lane and dual-lane QMP PCIe PHYs found on the IPQ9650 SoC. Unlike the PHYs in the other supported IPQ SoCs, the IPQ9650 PHYs require the on-chip refgen supply to power up. Add the refgen-supply property and require it only for the IPQ9650 compatibles. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Kathiravan Thirumoorthy --- .../bindings/phy/qcom,ipq8074-qmp-pcie-phy.yaml | 19 +++++++++++++++= ++++ 1 file changed, 19 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/qcom,ipq8074-qmp-pcie-ph= y.yaml b/Documentation/devicetree/bindings/phy/qcom,ipq8074-qmp-pcie-phy.ya= ml index f60804687412..048b2e3ff0ef 100644 --- a/Documentation/devicetree/bindings/phy/qcom,ipq8074-qmp-pcie-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,ipq8074-qmp-pcie-phy.yaml @@ -22,6 +22,8 @@ properties: - qcom,ipq8074-qmp-pcie-phy - qcom,ipq9574-qmp-gen3x1-pcie-phy - qcom,ipq9574-qmp-gen3x2-pcie-phy + - qcom,ipq9650-qmp-gen3x1-pcie-phy + - qcom,ipq9650-qmp-gen3x2-pcie-phy - items: - enum: - qcom,ipq5424-qmp-gen3x1-pcie-phy @@ -61,6 +63,8 @@ properties: "#phy-cells": const: 0 =20 + refgen-supply: true + required: - compatible - reg @@ -72,6 +76,21 @@ required: - clock-output-names - "#phy-cells" =20 +allOf: + - if: + properties: + compatible: + contains: + enum: + - qcom,ipq9650-qmp-gen3x1-pcie-phy + - qcom,ipq9650-qmp-gen3x2-pcie-phy + then: + required: + - refgen-supply + else: + properties: + refgen-supply: false + additionalProperties: false =20 examples: --=20 2.34.1 From nobody Sun Jul 26 00:20:44 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 57D273C1992 for ; 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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-31189cd8234sm33008273eec.9.2026.07.10.10.46.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Jul 2026 10:47:01 -0700 (PDT) From: Kathiravan Thirumoorthy Date: Fri, 10 Jul 2026 23:16:41 +0530 Subject: [PATCH v3 2/2] phy: qcom: qmp-pcie: Add IPQ9650 PCIe PHY support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260710-ipq9650_pcie_phy-v3-2-ef6018818d33@oss.qualcomm.com> References: <20260710-ipq9650_pcie_phy-v3-0-ef6018818d33@oss.qualcomm.com> In-Reply-To: <20260710-ipq9650_pcie_phy-v3-0-ef6018818d33@oss.qualcomm.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Kathiravan Thirumoorthy , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov X-Mailer: b4 0.15.2 X-Authority-Analysis: v=2.4 cv=Ab2B2XXG c=1 sm=1 tr=0 ts=6a513018 cx=c_pps a=vVfyC5vLCtgYJKYeQD43oA==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=EUspDBNiAAAA:8 a=SzMj-Qgm2C8wWq0MGEoA:9 a=QEXdDO2ut3YA:10 a=rl5im9kqc5Lf4LNbBjHf:22 X-Proofpoint-ORIG-GUID: HO-qkebGW1add4LMV7KHQqbQGPYu_eAA X-Proofpoint-GUID: HO-qkebGW1add4LMV7KHQqbQGPYu_eAA X-Proofpoint-Spam-Info: AW1haW4tMjYwNzEwMDE3NyBTYWx0ZWRfX+vBKGsX98M8N q/M2NYDCgOQ2mL/PI9EPcV0m0vsnc3bptQL/xvnF9d5glHHI5V1yrUCx9DIAkXkwXiYXBGDOMEq 9ydA/z32V7SbMCGLMuMrxpYUEP3W8dU= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzEwMDE3NyBTYWx0ZWRfX2ud613s5h8xx 9KqzeXNfzLB4tZX6oxriat2tF8c17LJbx4i9Sb8WcKpwg/a+IZjncCfTdQNayuA3zCEZ+72U+Tq BNFUjIFyDetE7/oRqdNqdIJQgv3QEvXn95JUUDWr0rhatB9pFQtvtWw0v1Q5+k8mo0e3aw+MEZk QARnThB4ALPpZ7FhmDb2EY5aGEsRc3U+g0wfbiutHW/DhpKlvGzoNUJh5/nFj6tKYUh7BXPu4Sj Dfs+vs+pzSBZo3HAr/rll1MQsUhFa2xXwcId42JcU9NDRm315T+PRmmE+rgg6xcJ8qePvKgVxl5 a6B80K/kpK7VmbCzEEkAorcTED2iqumaAJXd+yPE+21vN/voLMyi4kdx0HU7dL+aF7tzTenB/LL Yccr0OPRXnDo5exXTik3Swq4hpdufrjDtWG9MCb/YqAGBbkRHRfOzgYOfu929qvx+jX2EzMC2Pw FU23mGxIruVOIQZ6h0A== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-10_05,2026-07-10_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 clxscore=1015 malwarescore=0 phishscore=0 bulkscore=0 suspectscore=0 impostorscore=0 lowpriorityscore=0 priorityscore=1501 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607100177 Add support for the IPQ9650 platform, which includes three Gen3 x2 PCIe controllers and two Gen3 x1 PCIe controllers. The PHY instances require the on-chip refgen supply. Add the IPQ9650 Gen3 x1 and x2 QMP PCIe PHY configurations along with the refgen regulator supply. Note that an on-chip LDO, driven by the SoC CX, supplies the PHY voltages without requiring software control. Note that IPQ9650 does not support CX power collapse or rail scaling. Reviewed-by: Dmitry Baryshkov Signed-off-by: Kathiravan Thirumoorthy --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 220 +++++++++++++++++++++++++++= ++++ 1 file changed, 220 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcom= m/phy-qcom-qmp-pcie.c index d3effad7a074..c832db6c8953 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -857,6 +857,152 @@ static const struct qmp_phy_init_tbl ipq9574_gen3x2_p= cie_pcs_misc_tbl[] =3D { QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), }; =20 +static const struct qmp_phy_init_tbl ipq9650_pcie_serdes_tbl[] =3D { + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CTRL_BY_PSM, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MODE, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_RESETSM_CNTRL, 0x20), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_TIMER1, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_TIMER2, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x68), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xaa), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0xd4), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE0, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x0b), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x53), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x05), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0x55), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0x55), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x29), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0xaa), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x7d), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x05), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x18), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xa2), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x13), + QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xb5), +}; + +static const struct qmp_phy_init_tbl ipq9650_pcie_tx_tbl[] =3D { + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_HIGHZ_DRVR_EN, 0x10), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xb5), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x00), +}; + +static const struct qmp_phy_init_tbl ipq9650_pcie_rx_tbl[] =3D { + QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0x30), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x11), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_VGA_GAIN2_LSB, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_VGA_GAIN2_MSB, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_2, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_TX_ADAPT_PRE_THRESH1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_TX_ADAPT_PRE_THRESH2, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_TX_ADAPT_POST_THRESH, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_TX_ADAPT_MAIN_THRESH, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x67), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x3a), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), +}; + +static const struct qmp_phy_init_tbl ipq9650_pcie_pcs_tbl[] =3D { + QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x25), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB, 0x10), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x03), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG2, 0x0f), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_DCC_CAL_CONFIG, 0x00), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0x77), +}; + +static const struct qmp_phy_init_tbl ipq9650_pcie_pcs_misc_tbl[] =3D { + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG1, 0x1c), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0x0b), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P2_P3_POST, 0x34), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE, 0x33), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P6_P7_POST, 0x40), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58), +}; + static const struct qmp_phy_init_tbl qcs615_pcie_serdes_tbl[] =3D { QMP_PHY_INIT_CFG(QSERDES_V2_COM_BIAS_EN_CLKBUFLR_EN, 0x18), QMP_PHY_INIT_CFG(QSERDES_V2_COM_CLK_ENABLE1, 0x10), @@ -3484,6 +3630,10 @@ static const char * const qmp_phy_vreg_l[] =3D { "vdda-phy", "vdda-pll", }; =20 +static const char * const ipq9650_qmp_phy_vreg_l[] =3D { + "refgen", +}; + static const char * const sm8550_qmp_phy_vreg_l[] =3D { "vdda-phy", "vdda-pll", "vdda-qref", }; @@ -3527,6 +3677,14 @@ static const struct qmp_pcie_offsets qmp_pcie_offset= s_v4x1 =3D { .rx =3D 0x0400, }; =20 +static const struct qmp_pcie_offsets qmp_pcie_offsets_9650_v4x1 =3D { + .serdes =3D 0, + .pcs =3D 0x0600, + .pcs_misc =3D 0x0a00, + .tx =3D 0x0200, + .rx =3D 0x0400, +}; + static const struct qmp_pcie_offsets qmp_pcie_offsets_v4x2 =3D { .serdes =3D 0, .pcs =3D 0x0a00, @@ -3802,6 +3960,62 @@ static const struct qmp_phy_cfg ipq9574_gen3x2_pciep= hy_cfg =3D { .pipe_clock_rate =3D 250000000, }; =20 +static const struct qmp_phy_cfg ipq9650_gen3x1_pciephy_cfg =3D { + .lanes =3D 1, + + .offsets =3D &qmp_pcie_offsets_9650_v4x1, + + .tbls =3D { + .serdes =3D ipq9650_pcie_serdes_tbl, + .serdes_num =3D ARRAY_SIZE(ipq9650_pcie_serdes_tbl), + .tx =3D ipq9650_pcie_tx_tbl, + .tx_num =3D ARRAY_SIZE(ipq9650_pcie_tx_tbl), + .rx =3D ipq9650_pcie_rx_tbl, + .rx_num =3D ARRAY_SIZE(ipq9650_pcie_rx_tbl), + .pcs =3D ipq9650_pcie_pcs_tbl, + .pcs_num =3D ARRAY_SIZE(ipq9650_pcie_pcs_tbl), + .pcs_misc =3D ipq9650_pcie_pcs_misc_tbl, + .pcs_misc_num =3D ARRAY_SIZE(ipq9650_pcie_pcs_misc_tbl), + }, + .reset_list =3D ipq8074_pciephy_reset_l, + .num_resets =3D ARRAY_SIZE(ipq8074_pciephy_reset_l), + .vreg_list =3D ipq9650_qmp_phy_vreg_l, + .num_vregs =3D ARRAY_SIZE(ipq9650_qmp_phy_vreg_l), + .regs =3D pciephy_v4_regs_layout, + + .pwrdn_ctrl =3D SW_PWRDN | REFCLK_DRV_DSBL, + .phy_status =3D PHYSTATUS, + .pipe_clock_rate =3D 250000000, +}; + +static const struct qmp_phy_cfg ipq9650_gen3x2_pciephy_cfg =3D { + .lanes =3D 2, + + .offsets =3D &qmp_pcie_offsets_v4x2, + + .tbls =3D { + .serdes =3D ipq9650_pcie_serdes_tbl, + .serdes_num =3D ARRAY_SIZE(ipq9650_pcie_serdes_tbl), + .tx =3D ipq9650_pcie_tx_tbl, + .tx_num =3D ARRAY_SIZE(ipq9650_pcie_tx_tbl), + .rx =3D ipq9650_pcie_rx_tbl, + .rx_num =3D ARRAY_SIZE(ipq9650_pcie_rx_tbl), + .pcs =3D ipq9650_pcie_pcs_tbl, + .pcs_num =3D ARRAY_SIZE(ipq9650_pcie_pcs_tbl), + .pcs_misc =3D ipq9650_pcie_pcs_misc_tbl, + .pcs_misc_num =3D ARRAY_SIZE(ipq9650_pcie_pcs_misc_tbl), + }, + .reset_list =3D ipq8074_pciephy_reset_l, + .num_resets =3D ARRAY_SIZE(ipq8074_pciephy_reset_l), + .vreg_list =3D ipq9650_qmp_phy_vreg_l, + .num_vregs =3D ARRAY_SIZE(ipq9650_qmp_phy_vreg_l), + .regs =3D pciephy_v4_regs_layout, + + .pwrdn_ctrl =3D SW_PWRDN | REFCLK_DRV_DSBL, + .phy_status =3D PHYSTATUS, + .pipe_clock_rate =3D 250000000, +}; + static const struct qmp_phy_cfg qcs615_pciephy_cfg =3D { .lanes =3D 1, =20 @@ -5558,6 +5772,12 @@ static const struct of_device_id qmp_pcie_of_match_t= able[] =3D { }, { .compatible =3D "qcom,ipq9574-qmp-gen3x2-pcie-phy", .data =3D &ipq9574_gen3x2_pciephy_cfg, + }, { + .compatible =3D "qcom,ipq9650-qmp-gen3x1-pcie-phy", + .data =3D &ipq9650_gen3x1_pciephy_cfg, + }, { + .compatible =3D "qcom,ipq9650-qmp-gen3x2-pcie-phy", + .data =3D &ipq9650_gen3x2_pciephy_cfg, }, { .compatible =3D "qcom,kaanapali-qmp-gen3x2-pcie-phy", .data =3D &qmp_v8_gen3x2_pciephy_cfg, --=20 2.34.1