From nobody Fri Jul 10 06:02:12 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 336954E3788; Thu, 9 Jul 2026 18:40:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783622412; cv=none; b=XHUZswwtG3qGExM9Dx+YwK9VFrhmiQSS3uHet+flUFOVTW/tuFyQpBUES0e42sg7jtqCcuLDvStLRL7swoLeTv81DAdEgSGYsG3rkgrDjOx9kFsyIpPOwOE8lD6cFTDA91JWyYlYaqM7n29SomeCmvlpF53bEI3KOMaZslDQAQU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783622412; c=relaxed/simple; bh=gzzsP4OMBAKH5syutaWFaVFk6QC8CDQSj953+mInO7w=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=OaBAR5XCP8cEa8Xh605RdW2y6PLNWM1ROK3RVPxOV6WOM8Bb3TCWuYbG/5Wc6Bk3wtrJoYs5S9Zv9DIsNekmoCRp57rbUWNEJQfKRVKHeFreCQlCWozK2bB1FhC9FfGO57u0G6Fk5oVL1LDlYOmc3zZayTP8uEM1BbtmdTLaZj8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ZbchbECU; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ZbchbECU" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 9B45A1F00A3A; Thu, 9 Jul 2026 18:40:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1783622410; bh=/QjA1AblP9L+Kt9SpYOOkyJVVOOzYmepn7GTlwZFelA=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=ZbchbECU3TgvDU9TfKk07SWKmdAeq0RpQ4u52YETSBtL4NVKmeqgzzVYiwlmp3gkR w7CWPmLyF1YuVVzrKg94orJD1cwQGwg0KaICevffgR2WZL8oCDUrE4zOLwq5hJKZfQ I3Swon6TGYL9TZVro/L/hbj5iDh/Mg/FFczzqtcg2c2EGYNe56HAPd1nedf8lEZX5g d9aNNf4mPQY5NSin65kAMqPBBY4cZER/WqgoCb2Jr7be67l1XjkMzZQ/ssZDMq4Rd+ CBZ0PbHkI2yy5xbaAIpJ39qc1MwO/TdWLMm+xsvjVlRc+q/uQNwV8xNT/YlNbZo2yv ruT96phC1mcvA== From: Mark Brown Date: Thu, 09 Jul 2026 19:27:22 +0100 Subject: [PATCH v12 01/29] arm64/sysreg: Define full value read/modify/write helpers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260709-kvm-arm64-sme-v12-1-d0301d79ef58@kernel.org> References: <20260709-kvm-arm64-sme-v12-0-d0301d79ef58@kernel.org> In-Reply-To: <20260709-kvm-arm64-sme-v12-0-d0301d79ef58@kernel.org> To: Marc Zyngier , Joey Gouly , Catalin Marinas , Suzuki K Poulose , Will Deacon , Paolo Bonzini , Jonathan Corbet , Shuah Khan , Oliver Upton Cc: Dave Martin , Fuad Tabba , Mark Rutland , Ben Horgan , Jean-Philippe Brucker , linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Peter Maydell , Eric Auger , Mark Brown X-Mailer: b4 0.16-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=951; i=broonie@kernel.org; h=from:subject:message-id; bh=gzzsP4OMBAKH5syutaWFaVFk6QC8CDQSj953+mInO7w=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBqT+rq2VgOet80BJWD6Xh/o3WcW28LRlhze8qrE b4cZrVNCe6JATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCak/q6gAKCRAk1otyXVSH 0F+yB/4mbTCi3gD2Q4fl6xZyQFLCtztRwO4QXcc69jR3p5oUmCZtxnfmfIMo48auy7toplQM1C2 nrebDOyEN4RGz+nbVuXPUjCTH7uPFygS7UJg8sEYC8+X/UtmvrwIrrMQE+8NUkrxSWXY+4qEeqo qDobBHmgPLc0AAz97bCvy5oDrv3tvHiJCRbFHShnb37WwZT5azCcL9hJFFWf/JYzQ13EW2OnWT0 kHqh2ke8cZvmG/BTRgwa//QcL508JNaftLrCNfhaTRCLQUdOGkZYfSRiYjj27SnR0Frh5VJeNAF 32iiyGcb6r+YYrtS2qrEKLEscDXE7FlEPTJNTWZJVGXgs7Dp X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB We have read/modify write helpers for updating bitfields in sysregs if they have changed but we do not have them for updating the whole register. Define sysreg_cond_update() for that. Signed-off-by: Mark Brown --- arch/arm64/include/asm/sysreg.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysre= g.h index 7aa08d59d494..4b96449e0ffa 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -1235,6 +1235,12 @@ write_sysreg_s(__scs_new, sysreg); \ } while (0) =20 +#define sysreg_cond_update(sysreg, val) \ + sysreg_clear_set(sysreg, ~0UL, val) + +#define sysreg_cond_update_s(sysreg, val) \ + sysreg_clear_set_s(sysreg, ~0UL, val) + #define write_sysreg_hcr(__val) do { \ if (IS_ENABLED(CONFIG_AMPERE_ERRATUM_AC04_CPU_23) && \ (!system_capabilities_finalized() || \ --=20 2.47.3 From nobody Fri Jul 10 06:02:12 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BA7864F7981; Thu, 9 Jul 2026 18:40:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783622417; cv=none; b=XpFtyaXBl3S6p+SDaUxpUbbmJ2uVB4/y7HGVDJF78xbTvQR6OU/cAVdZInQIMsJ8a0NGgcSybqI7bOglZ4xHWG+Lu88HDvgscODorcX9wpRlS/elMOYjptCwE2Y2F7wP4ssODfaAogRSzoF52s3ihv8bMdFVuZp8dPAamNXmYEs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783622417; c=relaxed/simple; bh=0XvV/YeRJrO9B2CFARjUgzNQGXMLM6qPBMtNGxGdbBc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Xr4Mpi44ipl/E1UWrHhyj6REpYnpVltgcTHfrKisBENMEjoSJVCtTj2Nx8gPJRlq3jZPIItsZukLtzDJmcu9dlEeodVi64YD7bw5WoAhBXo3ENISEkAZiwfVsUtlVS17MHKbb24gAvW3E8HU1CsTpGRBx0nxUx4F4HTsSauWya4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=P2IAErhd; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="P2IAErhd" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 3179B1F00AC4; Thu, 9 Jul 2026 18:40:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1783622415; bh=8qpVDx4UpWHjMsfsBGz1zwBdy92zZEuyHy7wmDCoc1U=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=P2IAErhdgKWTcjA8mSRwy0bSsJpispvTa7nU1cfWA/BfUqGEmh9tmOMdZwISvxsUd 557VhfBtJJ4dbPlBtMu8UD0HT03S3Qn2B4z1sFhv+/8kbF5VQ7ciiakxSX/2RlSE7m WNxMEYtykYDK51FDSu+UBhu5wO0JU/rIX2YAnR9zewuOk5oZw3+RognrQd4//qkyWl ABPYSw7mLyx2blvVl6VtoK71njdUcKaOSZjJJGJPEfG8Aovi/gUWXNmXOBXciXJGAq r4WAA7fCijYxAgbq8S11bUQ6rjpttvWUSpoZ30w/JkQvRK19giLtcXALiuXz2RU3Mo cKTaJ7jSZNiEg== From: Mark Brown Date: Thu, 09 Jul 2026 19:27:23 +0100 Subject: [PATCH v12 02/29] arm64/fpsimd: Update FA64 and ZT0 enables when loading SME state Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260709-kvm-arm64-sme-v12-2-d0301d79ef58@kernel.org> References: <20260709-kvm-arm64-sme-v12-0-d0301d79ef58@kernel.org> In-Reply-To: <20260709-kvm-arm64-sme-v12-0-d0301d79ef58@kernel.org> To: Marc Zyngier , Joey Gouly , Catalin Marinas , Suzuki K Poulose , Will Deacon , Paolo Bonzini , Jonathan Corbet , Shuah Khan , Oliver Upton Cc: Dave Martin , Fuad Tabba , Mark Rutland , Ben Horgan , Jean-Philippe Brucker , linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Peter Maydell , Eric Auger , Mark Brown X-Mailer: b4 0.16-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=6750; i=broonie@kernel.org; h=from:subject:message-id; bh=0XvV/YeRJrO9B2CFARjUgzNQGXMLM6qPBMtNGxGdbBc=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBqT+rrz/851J8pfXfj1JOEBY1LgOLZyhapWyk/3 iVX1huk2/OJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCak/q6wAKCRAk1otyXVSH 0KRkB/42+vniuyHSbVcH1FtK+u4Hcjqvg83pv5iQxKxgDhuxw6zdTdTG/WuMBGbPlervae/MycY fKuRFj0FYY0dGqwd28klFDeCtOJTIzGDZMBKLTeDpsmeSVyI4Mi17D6O/PIhs9MfQS7MVXlRIHn n3YhZDRL6OB9+0syjKlajuNyLM4V6UQCSa/cSmWPPjXU9jSOPAUV7CvBrC8I5XbHkspKSR0vJ3L yGQ0JBL1frzM65lo2ia4QI5RkkXGw0vih+Uye/e+hNolBzWWSstTsBdqLmWjTxrwplMYYuor7P9 b5/f2cuaLOOD7nwrxdzY9g3qXwPu8wVbR+jMi5DVLmvj5wKi X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB Currently we enable EL0 and EL1 access to FA64 and ZT0 at boot and leave them enabled throughout the runtime of the system. When we add KVM support we will need to make this configuration dynamic, these features may be disabled for some KVM guests. Since the host kernel saves the floating point state for non-protected guests and we wish to avoid KVM having to reload the floating point state needlessly on guest reentry let's move the configuration of these enables to the floating point state reload. Provide a helper task_smcr() which generates the value of SMCR_EL1 to use based on the task struct and use it when we set the vector length SMCR_EL1, currently while handling SME access traps or FP state load. For consistency handle ZCR_EL1 the same way, currently the only field it has is the LEN so the change is less meaningful there. Signed-off-by: Mark Brown --- arch/arm64/include/asm/fpsimd.h | 2 -- arch/arm64/kernel/cpufeature.c | 2 -- arch/arm64/kernel/fpsimd.c | 72 ++++++++++++++++++-------------------= ---- 3 files changed, 31 insertions(+), 45 deletions(-) diff --git a/arch/arm64/include/asm/fpsimd.h b/arch/arm64/include/asm/fpsim= d.h index a67d5774e672..8d2a3d63481b 100644 --- a/arch/arm64/include/asm/fpsimd.h +++ b/arch/arm64/include/asm/fpsimd.h @@ -360,8 +360,6 @@ struct arm64_cpu_capabilities; extern void cpu_enable_fpsimd(const struct arm64_cpu_capabilities *__unuse= d); extern void cpu_enable_sve(const struct arm64_cpu_capabilities *__unused); extern void cpu_enable_sme(const struct arm64_cpu_capabilities *__unused); -extern void cpu_enable_sme2(const struct arm64_cpu_capabilities *__unused); -extern void cpu_enable_fa64(const struct arm64_cpu_capabilities *__unused); extern void cpu_enable_fpmr(const struct arm64_cpu_capabilities *__unused); =20 /* diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 9a22df0c5120..0609dce1989e 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -2992,7 +2992,6 @@ static const struct arm64_cpu_capabilities arm64_feat= ures[] =3D { .type =3D ARM64_CPUCAP_SYSTEM_FEATURE, .capability =3D ARM64_SME_FA64, .matches =3D has_cpuid_feature, - .cpu_enable =3D cpu_enable_fa64, ARM64_CPUID_FIELDS(ID_AA64SMFR0_EL1, FA64, IMP) }, { @@ -3000,7 +2999,6 @@ static const struct arm64_cpu_capabilities arm64_feat= ures[] =3D { .type =3D ARM64_CPUCAP_SYSTEM_FEATURE, .capability =3D ARM64_SME2, .matches =3D has_cpuid_feature, - .cpu_enable =3D cpu_enable_sme2, ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, SME, SME2) }, #endif /* CONFIG_ARM64_SME */ diff --git a/arch/arm64/kernel/fpsimd.c b/arch/arm64/kernel/fpsimd.c index 25dc5afe9ba0..8009213288b1 100644 --- a/arch/arm64/kernel/fpsimd.c +++ b/arch/arm64/kernel/fpsimd.c @@ -277,6 +277,27 @@ void task_set_vl_onexec(struct task_struct *task, enum= vec_type type, task->thread.vl_onexec[type] =3D vl; } =20 +static unsigned long task_zcr(const struct task_struct *task) +{ + unsigned long vq =3D sve_vq_from_vl(task_get_sve_vl(task)); + unsigned long zcr =3D vq - 1; + + return zcr; +} + +static unsigned long task_smcr(const struct task_struct *task) +{ + unsigned long vq =3D sve_vq_from_vl(task_get_sme_vl(task)); + unsigned long smcr =3D vq - 1; + + if (system_supports_fa64()) + smcr |=3D SMCR_ELx_FA64; + if (system_supports_sme2()) + smcr |=3D SMCR_ELx_EZT0; + + return smcr; +} + /* * TIF_SME controls whether a task can use SME without trapping while * in userspace, when TIF_SME is set then we must have storage @@ -377,10 +398,8 @@ static void task_fpsimd_load(void) if (!thread_sm_enabled(¤t->thread)) WARN_ON_ONCE(!test_and_set_thread_flag(TIF_SVE)); =20 - if (test_thread_flag(TIF_SVE)) { - unsigned long vq =3D sve_vq_from_vl(task_get_sve_vl(current)); - sysreg_clear_set_s(SYS_ZCR_EL1, ZCR_ELx_LEN, vq - 1); - } + if (system_supports_sve()) + sysreg_cond_update_s(SYS_ZCR_EL1, task_zcr(current)); =20 restore_sve_regs =3D true; restore_ffr =3D true; @@ -402,12 +421,13 @@ static void task_fpsimd_load(void) =20 /* Restore SME, override SVE register configuration if needed */ if (system_supports_sme()) { - unsigned long sme_vl =3D task_get_sme_vl(current); - - /* Ensure VL is set up for restoring data */ + /* + * Ensure VL is set up for restoring data. KVM might + * disable subfeatures so we reset them each time. + */ if (test_thread_flag(TIF_SME)) { - unsigned long vq =3D sve_vq_from_vl(sme_vl); - sysreg_clear_set_s(SYS_SMCR_EL1, SMCR_ELx_LEN, vq - 1); + sysreg_cond_update_s(SYS_SMCR_EL1, task_smcr(current)); + isb(); } =20 write_sysreg_s(current->thread.svcr, SYS_SVCR); @@ -1217,26 +1237,6 @@ void cpu_enable_sme(const struct arm64_cpu_capabilit= ies *__always_unused p) isb(); } =20 -void cpu_enable_sme2(const struct arm64_cpu_capabilities *__always_unused = p) -{ - /* This must be enabled after SME */ - BUILD_BUG_ON(ARM64_SME2 <=3D ARM64_SME); - - /* Allow use of ZT0 */ - write_sysreg_s(read_sysreg_s(SYS_SMCR_EL1) | SMCR_ELx_EZT0_MASK, - SYS_SMCR_EL1); -} - -void cpu_enable_fa64(const struct arm64_cpu_capabilities *__always_unused = p) -{ - /* This must be enabled after SME */ - BUILD_BUG_ON(ARM64_SME_FA64 <=3D ARM64_SME); - - /* Allow use of FA64 */ - write_sysreg_s(read_sysreg_s(SYS_SMCR_EL1) | SMCR_ELx_FA64_MASK, - SYS_SMCR_EL1); -} - void __init sme_setup(void) { struct vl_info *info =3D &vl_info[ARM64_VEC_SME]; @@ -1281,17 +1281,9 @@ void __init sme_setup(void) =20 void sme_suspend_exit(void) { - u64 smcr =3D 0; - if (!system_supports_sme()) return; =20 - if (system_supports_fa64()) - smcr |=3D SMCR_ELx_FA64; - if (system_supports_sme2()) - smcr |=3D SMCR_ELx_EZT0; - - write_sysreg_s(smcr, SYS_SMCR_EL1); write_sysreg_s(0, SYS_SMPRI_EL1); } =20 @@ -1336,8 +1328,7 @@ void do_sve_acc(unsigned long esr, struct pt_regs *re= gs) * any effective streaming mode SVE state. */ if (!test_thread_flag(TIF_FOREIGN_FPSTATE)) { - unsigned long vq =3D sve_vq_from_vl(task_get_sve_vl(current)); - sysreg_clear_set_s(SYS_ZCR_EL1, ZCR_ELx_LEN, vq - 1); + sysreg_cond_update_s(SYS_ZCR_EL1, task_zcr(current)); sve_flush_live(); fpsimd_bind_task_to_cpu(); } else { @@ -1468,8 +1459,7 @@ void do_sme_acc(unsigned long esr, struct pt_regs *re= gs) WARN_ON(1); =20 if (!test_thread_flag(TIF_FOREIGN_FPSTATE)) { - unsigned long vq =3D sve_vq_from_vl(task_get_sme_vl(current)); - sysreg_clear_set_s(SYS_SMCR_EL1, SMCR_ELx_LEN, vq - 1); + sysreg_cond_update_s(SYS_SMCR_EL1, task_smcr(current)); =20 fpsimd_bind_task_to_cpu(); } else { --=20 2.47.3 From nobody Fri Jul 10 06:02:12 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 01CD3437475; Thu, 9 Jul 2026 18:40:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783622423; cv=none; b=JF+yiaB/a3+bKZGDTbCNhchdPzQ32skOV2FrjBFFrL/Zsxh4bLO3vrE6VXGR+d5bDKkcaf+kCFCbE8LRuDIuQb/dkCzDr3l/XEKm0veGCJMAO51KKmnjdF+E32OROsyFI+bsnayKEG/gvUCN4O6Lhi/ljc2MOV2KKGGdfncp8U0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783622423; c=relaxed/simple; bh=LWJU1DW0v04tDKSLTA3TrlLIRe48SZoL4LVSvdSUkiE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=mUi5zbjKzLWo/oyM+zVLhGERn1WC4ujEXouE5GmPIzazoAeiCQ5b3HrV+ZM8oeNDuJpJz/PwedIqavaeV8auamLInNcOrh+D5FGoBsfC39B8zg2Z9Qib9F+VJYBUK8izfhtDzN5tM1HEphJyvMAOF2RpfoD52GuR4a58oE1MbqA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=l2cmPnWH; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="l2cmPnWH" Received: by smtp.kernel.org (Postfix) with ESMTPSA id B91D01F000E9; Thu, 9 Jul 2026 18:40:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1783622419; bh=IePB7KK76qxAQZKa79z6gQ5nNy5ze/T0hxePNaWjw8A=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=l2cmPnWHFyYbPkDYyvLBK5Fi/6kooRZPCGFknTSS+nOdekx9qCSRwddCYNZ65NcL1 fif9v1Snw86W7mJXJc/fLlgUJ/Fr8MjDpajkKsyGe8DtA4zsrj3XCgqKDqNPaNwJa7 K1kOnl3j3gjk4jdoikgSiwHCcbK6WGqq/mu2EpQKN3LDARmwkb2LoLyTO8MaPrD7E7 ltV2ayheCMJ9jgP8Fyiq49k+k1Uvu+bpCQhw2q//QTXhvNCm7/HNC/s5d/WHYUaHK6 cfBcTxC4UuQGkgtUQmbNFBq39ptPZEeO2tLJR5pSsgAFlFpueQQZzKoO4IQcd4vGk2 Q/ts3lU1gO1bw== From: Mark Brown Date: Thu, 09 Jul 2026 19:27:24 +0100 Subject: [PATCH v12 03/29] arm64/fpsimd: Decide to save ZT0 and streaming mode FFR at bind time Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260709-kvm-arm64-sme-v12-3-d0301d79ef58@kernel.org> References: <20260709-kvm-arm64-sme-v12-0-d0301d79ef58@kernel.org> In-Reply-To: <20260709-kvm-arm64-sme-v12-0-d0301d79ef58@kernel.org> To: Marc Zyngier , Joey Gouly , Catalin Marinas , Suzuki K Poulose , Will Deacon , Paolo Bonzini , Jonathan Corbet , Shuah Khan , Oliver Upton Cc: Dave Martin , Fuad Tabba , Mark Rutland , Ben Horgan , Jean-Philippe Brucker , linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Peter Maydell , Eric Auger , Mark Brown X-Mailer: b4 0.16-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=4661; i=broonie@kernel.org; h=from:subject:message-id; bh=LWJU1DW0v04tDKSLTA3TrlLIRe48SZoL4LVSvdSUkiE=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBqT+rsH3CO5eCSYAwZpZpLlQCAO43p+RG46DeWJ i5+CW7cHHqJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCak/q7AAKCRAk1otyXVSH 0MzlB/4hewygpuTmbVfoDGlv6L6XoXc5eDfeCbFGfqBc2n+UAqwBQr9an8HUqeiwFy2B2DwLSxZ fvGt2yawkX6SuanEt7OcdyWoi7zLhGaoUsXhg7P+IADURnm0xkmr7kygZXg6O0Z2h2+bI5q8Rdv 0i60koBR1RCN6Gx/2x3RHrIla7g7+LqbIkhjAMnoqZxi7kjxxAWrHHvpJDvkOHCivWpbD+u/QDP ZyKlCg+SbqIzGJEtWLtCfjxUQ03+LACbvJd5OGDjtWgRJjK9wLEl1xwlEDOOlFVDKr47PCLuY0d unTqdbbLRutdhDKbmiGCk3OfI64iMf1OjaHNQ591px+f7eXW X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB Some parts of the SME state are optional, enabled by additional features on top of the base FEAT_SME and controlled with enable bits in SMCR_ELx. We unconditionally enable these for the host but for KVM we will allow the feature set exposed to guests to be restricted by the VMM. These are the FFR register (FEAT_SME_FA64) and ZT0 (FEAT_SME2). We defer saving of guest floating point state for non-protected guests to the host kernel. We also want to avoid having to reconfigure the guest floating point state if nothing used the floating point state while running the host. If the guest was running with the optional features disabled then traps will be enabled for them so the host kernel will need to skip accessing that state when saving state for the guest. Support this by moving the decision about saving this state to the point where we bind floating point state to the CPU, instead of only storing the SME VL to use we store the SMCR value. This includes all the enable controls for the subfeatures along the vector length. In order to keep the code paths for the vector extensions consistent also adjust the SVE path to store a ZCR value instead of the VL, since no fields other than LEN are currently defined for ZCR this is much less of a meaningful change. Signed-off-by: Mark Brown --- arch/arm64/include/asm/fpsimd.h | 4 ++-- arch/arm64/kernel/fpsimd.c | 16 ++++++++-------- arch/arm64/kvm/fpsimd.c | 3 ++- 3 files changed, 12 insertions(+), 11 deletions(-) diff --git a/arch/arm64/include/asm/fpsimd.h b/arch/arm64/include/asm/fpsim= d.h index 8d2a3d63481b..0a3299142683 100644 --- a/arch/arm64/include/asm/fpsimd.h +++ b/arch/arm64/include/asm/fpsimd.h @@ -166,8 +166,8 @@ struct cpu_fp_state { struct arm64_sme_state *sme_state; u64 *svcr; u64 *fpmr; - unsigned int sve_vl; - unsigned int sme_vl; + u64 smcr; + u64 zcr; enum fp_type *fp_type; enum fp_type to_save; }; diff --git a/arch/arm64/kernel/fpsimd.c b/arch/arm64/kernel/fpsimd.c index 8009213288b1..dc1ad10e39a2 100644 --- a/arch/arm64/kernel/fpsimd.c +++ b/arch/arm64/kernel/fpsimd.c @@ -470,7 +470,7 @@ static void fpsimd_save_user_state(void) /* set by fpsimd_bind_task_to_cpu() or fpsimd_bind_state_to_cpu() */ bool save_sve_regs =3D false; bool save_ffr; - unsigned int vl; + unsigned int vq; =20 WARN_ON(!system_supports_fpsimd()); WARN_ON(preemptible()); @@ -494,7 +494,7 @@ static void fpsimd_save_user_state(void) last->to_save =3D=3D FP_STATE_SVE) { save_sve_regs =3D true; save_ffr =3D true; - vl =3D last->sve_vl; + vq =3D SYS_FIELD_GET(ZCR_ELx, LEN, last->zcr) + 1; } =20 if (system_supports_sme()) { @@ -504,19 +504,19 @@ static void fpsimd_save_user_state(void) =20 if (*svcr & SVCR_ZA_MASK) sme_save_state(last->sme_state, - system_supports_sme2()); + last->smcr & SMCR_ELx_EZT0); =20 /* If we are in streaming mode override regular SVE. */ if (*svcr & SVCR_SM_MASK) { save_sve_regs =3D true; - save_ffr =3D system_supports_fa64(); - vl =3D last->sme_vl; + save_ffr =3D last->smcr & SMCR_ELx_FA64; + vq =3D SYS_FIELD_GET(SMCR_ELx, LEN, last->smcr) + 1; } } =20 if (IS_ENABLED(CONFIG_ARM64_SVE) && save_sve_regs) { /* Get the configured VL from RDVL, will account for SM */ - if (WARN_ON(sve_get_vl() !=3D vl)) { + if (WARN_ON(sve_get_vl() !=3D sve_vl_from_vq(vq))) { /* * Can't save the user regs, so current would * re-enter user with corrupt state. @@ -1704,8 +1704,8 @@ static void fpsimd_bind_task_to_cpu(void) last->st =3D ¤t->thread.uw.fpsimd_state; last->sve_state =3D current->thread.sve_state; last->sme_state =3D current->thread.sme_state; - last->sve_vl =3D task_get_sve_vl(current); - last->sme_vl =3D task_get_sme_vl(current); + last->zcr =3D task_zcr(current); + last->smcr =3D task_smcr(current); last->svcr =3D ¤t->thread.svcr; last->fpmr =3D ¤t->thread.uw.fpmr; last->fp_type =3D ¤t->thread.fp_type; diff --git a/arch/arm64/kvm/fpsimd.c b/arch/arm64/kvm/fpsimd.c index 3f6b1e29cd6b..567dd43970c5 100644 --- a/arch/arm64/kvm/fpsimd.c +++ b/arch/arm64/kvm/fpsimd.c @@ -89,7 +89,8 @@ void kvm_arch_vcpu_ctxsync_fp(struct kvm_vcpu *vcpu) */ fp_state.st =3D &vcpu->arch.ctxt.fp_regs; fp_state.sve_state =3D vcpu->arch.sve_state; - fp_state.sve_vl =3D vcpu->arch.sve_max_vl; + fp_state.zcr =3D vcpu_sve_max_vq(vcpu) - 1; + fp_state.smcr =3D 0; fp_state.sme_state =3D NULL; fp_state.svcr =3D __ctxt_sys_reg(&vcpu->arch.ctxt, SVCR); fp_state.fpmr =3D __ctxt_sys_reg(&vcpu->arch.ctxt, FPMR); --=20 2.47.3 From nobody Fri Jul 10 06:02:12 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7EAAD4F799E; Thu, 9 Jul 2026 18:40:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783622425; cv=none; b=qiVID4rxMOaBRPOd7mENjoXmmHLCqfEMZ50B2soyKFdGuf1xk/3g9CbkojXMuCOerRQuglVGeE3H4CL2+YG/JNiWhVZ6K38PhUaJlxhmOF3p6JNQVleC9GHmMLqsc4HXRzPxN1r92bp+s/r305H0Q/ySAWEfXmTVx0F3SKvXK/g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783622425; c=relaxed/simple; bh=neew/zQKQc9VPVi7macEuVISGaMZgaNeHcW5WvUvtiM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=q2/CZTY2ljCgR72drTsblkrmAw4A3tl4yGr+XEJwLgWNlWziYaopj/H7jGfCugktLvE3UX0hbjy1D8qShbejdUYeBmlfrH3SMUkFF/QG2QBy0awas02XeR2p/jsV4yf2S2wxpakL189XpOh6Vpui7RRqOExcwQUt2EU2AG0Zt6A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=F2uBsk/V; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="F2uBsk/V" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4A5C51F00A3A; Thu, 9 Jul 2026 18:40:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1783622424; bh=X4HlyMbyPhKCnIL3AvhZ79kxUeT3XQMJg0KjZKyp1dU=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=F2uBsk/Vwn+HtLHg3ciBoZS0lou2xWoDVEWwYesEEGBRK7yHGSN1NZHS1Jrxbdxs5 IN0kMOc28tqsmUQ+bpDWnBJ7wJE6Q236/KYjpHaFYTxV9ZJXxd0OKr+tOiEBFL51sC axNdt6JNehXGQEJmZc15VUCMQ9q9iBv82Rv4cTr47L/oLtaWpIoHDW/9Rec2y9+Twr PMs6FXk0fv1//EBA8O1bnYEsAKwCW6VdKrEWtyeVtiz4yfgCKLUI9iCObuMkLImd5S Pband2E0PPQ9+2+uijLBi6razJZCyMl/hSqIFEJ2dyDXFlraeaiq40Eto7JvxDkxYr D+tUwfFbnTZYg== From: Mark Brown Date: Thu, 09 Jul 2026 19:27:25 +0100 Subject: [PATCH v12 04/29] arm64/sve: Factor virtualizable VL discovery out of SVE specific code Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260709-kvm-arm64-sme-v12-4-d0301d79ef58@kernel.org> References: <20260709-kvm-arm64-sme-v12-0-d0301d79ef58@kernel.org> In-Reply-To: <20260709-kvm-arm64-sme-v12-0-d0301d79ef58@kernel.org> To: Marc Zyngier , Joey Gouly , Catalin Marinas , Suzuki K Poulose , Will Deacon , Paolo Bonzini , Jonathan Corbet , Shuah Khan , Oliver Upton Cc: Dave Martin , Fuad Tabba , Mark Rutland , Ben Horgan , Jean-Philippe Brucker , linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Peter Maydell , Eric Auger , Mark Brown X-Mailer: b4 0.16-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=2673; i=broonie@kernel.org; h=from:subject:message-id; bh=neew/zQKQc9VPVi7macEuVISGaMZgaNeHcW5WvUvtiM=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBqT+rtT/m0eK9SlRIe/SGmYC9t7dpPWB9eE/M37 +zo+6Cyb8iJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCak/q7QAKCRAk1otyXVSH 0IjnB/0eRU+G2bCmOTokgdLLuZk5znuDYAEAX60xA6kEE+As+EPR4JUgTHGmvY+RTA8i1ahwURI bOYucBN3owHKHVfVJd3XrX/q1mWLHpaTKjEzEEJqM7DYV6rC2VUB8CSEfuf+LeDudALLTw+aFXv 7FeWwsznBsXC0dYrWhjiQjTg48yFaQQKS/X7zgihckyIVGQF0YwLSsZSC5a7/JzOCtXWV5ZIf7C /Pn416eVKBHoxOyJdXIR7UcA6tqq5a4HjhL5H66uEAlaK8IK9Fmh0uT3qZl8WhesrMgFBa4a6Un sZ4PunDTGYt/42wYvDIOBIDq4lKlDt1pM3x+fW9TbJ7EUybX X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB In preparation for reuising it for SME pull the code for discovering the maximum virtualizable vector length out of sve_setup() into a separate function. Signed-off-by: Mark Brown --- arch/arm64/kernel/fpsimd.c | 41 ++++++++++++++++++++++++----------------- 1 file changed, 24 insertions(+), 17 deletions(-) diff --git a/arch/arm64/kernel/fpsimd.c b/arch/arm64/kernel/fpsimd.c index dc1ad10e39a2..5c156e2a47ea 100644 --- a/arch/arm64/kernel/fpsimd.c +++ b/arch/arm64/kernel/fpsimd.c @@ -1114,6 +1114,29 @@ int vec_verify_vq_map(enum vec_type type) return 0; } =20 +static int vec_virtualisable_vl(struct vl_info *info) +{ + DECLARE_BITMAP(partial_only_map, SVE_VQ_MAX); + unsigned long b_min_partial, b_max_virt; + + bitmap_andnot(partial_only_map, info->vq_partial_map, info->vq_map, + SVE_VQ_MAX); + b_min_partial =3D find_last_bit(partial_only_map, SVE_VQ_MAX); + + /* All implemented VLs are virtualisable */ + if (b_min_partial >=3D SVE_VQ_MAX) + return info->max_vl; + + b_max_virt =3D find_next_bit(info->vq_map, SVE_VQ_MAX, b_min_partial); + + /* No implemented VLs are virtualisable */ + if (b_max_virt >=3D SVE_VQ_MAX) + return 0; + + /* At least one virtualisable VL exists */ + return sve_vl_from_vq(__bit_to_vq(b_max_virt)); +} + void cpu_enable_sve(const struct arm64_cpu_capabilities *__always_unused p) { write_sysreg(read_sysreg(CPACR_EL1) | CPACR_EL1_ZEN_EL1EN, CPACR_EL1); @@ -1125,8 +1148,6 @@ void cpu_enable_sve(const struct arm64_cpu_capabiliti= es *__always_unused p) void __init sve_setup(void) { struct vl_info *info =3D &vl_info[ARM64_VEC_SVE]; - DECLARE_BITMAP(tmp_map, SVE_VQ_MAX); - unsigned long b; int max_bit; =20 if (!system_supports_sve()) @@ -1149,21 +1170,7 @@ void __init sve_setup(void) */ set_sve_default_vl(find_supported_vector_length(ARM64_VEC_SVE, 64)); =20 - bitmap_andnot(tmp_map, info->vq_partial_map, info->vq_map, - SVE_VQ_MAX); - - b =3D find_last_bit(tmp_map, SVE_VQ_MAX); - if (b >=3D SVE_VQ_MAX) - /* No non-virtualisable VLs found */ - info->max_virtualisable_vl =3D SVE_VQ_MAX; - else if (WARN_ON(b =3D=3D SVE_VQ_MAX - 1)) - /* No virtualisable VLs? This is architecturally forbidden. */ - info->max_virtualisable_vl =3D SVE_VQ_MIN; - else /* b + 1 < SVE_VQ_MAX */ - info->max_virtualisable_vl =3D sve_vl_from_vq(__bit_to_vq(b + 1)); - - if (info->max_virtualisable_vl > info->max_vl) - info->max_virtualisable_vl =3D info->max_vl; + info->max_virtualisable_vl =3D vec_virtualisable_vl(info); =20 pr_info("%s: maximum available vector length %u bytes per vector\n", info->name, info->max_vl); --=20 2.47.3 From nobody Fri Jul 10 06:02:12 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 351D243F8CD; Thu, 9 Jul 2026 18:40:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783622430; cv=none; b=NsDbNIiTBVtA6LCz7etGoJFjkzo+cT685I5ndM0AA81dgBZvUt+PM4xzaevkBKjeSn75LpRTktv9liRREtzjpnRMUejUpVy/0R4MMDEFcpM8uIXwS/qrukT9CZRlKOok0gS701O28TSFev8A/eC4tWh0duL7dgPK9sZA2i0Fi+Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783622430; c=relaxed/simple; bh=++3RupEjJl/hieRBq4Zb2DcRHMWp0Yu3DKnrxPa5BCI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=svxaZR2UZdFZoesVTZ7QEp/13Vg++aACja11/Wh3MHEwXOSrH0Ub9vQBbOvD3Juo0RHDHJayhY9kGRReUjr0V6GLqcWEjPWuxPakzr8WxFklF/hpJEoQhPre1CrfLR3/u1CFWuHdQzcY2GH3DpdXksSMu9nzXmStlOZ56Eunbg0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=KQAX3nei; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="KQAX3nei" Received: by smtp.kernel.org (Postfix) with ESMTPSA id CE1BC1F000E9; Thu, 9 Jul 2026 18:40:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1783622428; bh=ZRzgkCokkYWeOPF3FDrRjraYcAbGSe4f3k3UbSQ8tck=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=KQAX3neiOuz3j6XpyVScVIur7/tIYm48onAevH1WIPGExJHl5QKuPc1pG04LZ+YQ/ 4dVedeC0oERGdMtJ4F/+AJ/P9RtRYSus3ckR600OryhzGZ1C+b7pPC+l7NPHCZQUGv 73QQPjCM5xdZVmk5h3wUmPsn1UIf/hq6blUJzSAMcPvKFRlbuaplmIAhBnyhSYwfDI d7GMBo0AfcQXWJQwI423AYf7Jz1CAtmTX2lKrnEV/JGIz4iKhQm7GT8Ik1lVQD0gFp wZ1cIVttxAbFqXQXNOvPJXlyp81+3jNTvhfBz+yEwzKpxfGbEJVLuP+3wfLnPsKwpA M4GfUFY7AKV2Q== From: Mark Brown Date: Thu, 09 Jul 2026 19:27:26 +0100 Subject: [PATCH v12 05/29] arm64/fpsimd: Determine maximum virtualisable SME vector length Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260709-kvm-arm64-sme-v12-5-d0301d79ef58@kernel.org> References: <20260709-kvm-arm64-sme-v12-0-d0301d79ef58@kernel.org> In-Reply-To: <20260709-kvm-arm64-sme-v12-0-d0301d79ef58@kernel.org> To: Marc Zyngier , Joey Gouly , Catalin Marinas , Suzuki K Poulose , Will Deacon , Paolo Bonzini , Jonathan Corbet , Shuah Khan , Oliver Upton Cc: Dave Martin , Fuad Tabba , Mark Rutland , Ben Horgan , Jean-Philippe Brucker , linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Peter Maydell , Eric Auger , Mark Brown X-Mailer: b4 0.16-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=1382; i=broonie@kernel.org; h=from:subject:message-id; bh=++3RupEjJl/hieRBq4Zb2DcRHMWp0Yu3DKnrxPa5BCI=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBqT+ruBTZpBesslyexlMPN7whcGBMEloy+b7SKJ a0kvNcpKqWJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCak/q7gAKCRAk1otyXVSH 0P22B/9is+2aIzwfmXnfruqye5Q2jKLRQ694PLF/utH8NN9EBPjO7Tqz1AY6U4XIewi3lSOynAL jUGSASt11mw8AyZhP0ewUZOzBqD0VmkO7ELDd0Zt//yfYlJOGttyV5pGHLe4VH5hS4vS+XZQ2hH qIXS8UbT1SDpvwe4mmABAkBV0baO8woClIqVz0u6GKxoisC+sn++1HgDx3rrVGP1icwqrT3y72A 202AnsT8jabvhvcWIL/0p/aA4YnUjpkgAekX7frH36/TMHCl8NgW34Hz5ntVg2gyOWpZ7sMcgra kL1O0OMETpymbfTdqRWhmvUtDQ4f3XaQF8ScMZyOOEWVW14t X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB As with SVE we can only virtualise SME vector lengths that are supported by all CPUs in the system, implement similar checks to those for SVE. Since unlike SVE there are no specific vector lengths that are architecturally required the handling is subtly different, we report a system where this happens with a maximum vector length of 0. Signed-off-by: Mark Brown --- arch/arm64/kernel/fpsimd.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/kernel/fpsimd.c b/arch/arm64/kernel/fpsimd.c index 5c156e2a47ea..7c4e69fd3922 100644 --- a/arch/arm64/kernel/fpsimd.c +++ b/arch/arm64/kernel/fpsimd.c @@ -1277,6 +1277,7 @@ void __init sme_setup(void) * minimum available VL will be used. */ set_sme_default_vl(find_supported_vector_length(ARM64_VEC_SME, 32)); + info->max_virtualisable_vl =3D vec_virtualisable_vl(info); =20 pr_info("SME: minimum available vector length %u bytes per vector\n", info->min_vl); @@ -1284,6 +1285,10 @@ void __init sme_setup(void) info->max_vl); pr_info("SME: default vector length %u bytes per vector\n", get_sme_default_vl()); + + /* KVM decides whether to support mismatched systems. Just warn here: */ + if (info->max_virtualisable_vl < info->max_vl) + pr_warn("SME: unvirtualisable vector lengths present\n"); } =20 void sme_suspend_exit(void) --=20 2.47.3 From nobody Fri Jul 10 06:02:12 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D3224437440; Thu, 9 Jul 2026 18:40:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783622435; cv=none; b=EuDbkNIMgBydjjVpsMxMmkTmAi0qWyndO4Ut4CSaJKnuTqi9UzzQl9JaDG6Ejy4eNY2cADNaCy3K/FQH+ukr0cA1mb7CwybdOqGgDAFL1LeyW7HllhjBbGb3QfArznW9XbSRcN5CBi020mbs6uYiRmX3fuvXVxGTFmAC2EBOHz0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783622435; c=relaxed/simple; bh=u65dLobDDTfZ3Plqj3qN97beHdtUOk+/y5QgneNdn5w=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ceARquF0W6Dga+vn/mATHzL/nRGL/RJihYOdSbVDLyeJRjXCDxgwT1MkiTzUXCMKnaDubTNuK50l2XGBOx4CB0P6GcnZ4TjqEu41Za3NQUbfcMURgH5uUMrZyH/9sXyLqxjji88Ph3COM+dMx74Odq4jXyWk3V4IzLcg0FNH0dQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=KQ/2IKPr; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="KQ/2IKPr" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5CCEA1F00A3D; Thu, 9 Jul 2026 18:40:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1783622433; bh=Ng0eoSfPdDRfiXjYHgTRJSjiJJN1g/dJiDj1pJZB0R0=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=KQ/2IKPr5Ob10pw45hFyJrXrCQ3tsZfCUKD597YWJtKp6BIbsH2QLOn0Y9KkIwpq0 uh5YNf0Lrkv9XV40Y3w3tfFAETYr6GlSZVmMGs9WsrSHKHxr9MhUODWRI/gAidFoTP t6IaoMqw1IBeHG1vIIFwW6hsSWVAyjCzSikrU7MCMQFalxqosJvAU5R41TLHZt3Y8c wDXIkbanAipQFa4TU6AUx9I2G670zlECubGsDm1sSFEecD08LR8Ogs7yMN0fXp7CIz Z3JlwTDCjJ/f6YFcPeBpk4Bm5gWTVSX5weyCRfosCn0giPuSMe/qztNB0BCvHhUV3Y 010xA51u6w7KQ== From: Mark Brown Date: Thu, 09 Jul 2026 19:27:27 +0100 Subject: [PATCH v12 06/29] KVM: arm64: Handle FEAT_IDST for guest accesses to hidden registers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260709-kvm-arm64-sme-v12-6-d0301d79ef58@kernel.org> References: <20260709-kvm-arm64-sme-v12-0-d0301d79ef58@kernel.org> In-Reply-To: <20260709-kvm-arm64-sme-v12-0-d0301d79ef58@kernel.org> To: Marc Zyngier , Joey Gouly , Catalin Marinas , Suzuki K Poulose , Will Deacon , Paolo Bonzini , Jonathan Corbet , Shuah Khan , Oliver Upton Cc: Dave Martin , Fuad Tabba , Mark Rutland , Ben Horgan , Jean-Philippe Brucker , linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Peter Maydell , Eric Auger , Mark Brown X-Mailer: b4 0.16-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=3302; i=broonie@kernel.org; h=from:subject:message-id; bh=u65dLobDDTfZ3Plqj3qN97beHdtUOk+/y5QgneNdn5w=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBqT+ruW1dvvywWlnLeB5lO5vk3pCtv7FrJpOmzr fdiOqL5v/iJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCak/q7gAKCRAk1otyXVSH 0H53B/9DjwGh+7WiEKyEqNd1YLbu7bg1QDZDEYJU9yigMgacG2JCDcRupJ0/CDTO9//oGae1kb3 Aqq57j42vZ+Y6YtVlhqeVPGE0eM6QpgHZ8DHvwDkiuSFzZZLGS7GxGrpBi62W5yDqv6tndCHUS8 7OsspcZetqd6n0z7DHP4E3cT4dN7X/3JxC1DYGMsGB1QSv+LurK+NhpNwXjKVlCdKAXPYgMuxaY lBxoM14Mj3P/rLj+3qbEOvj6angfHtvEVGwjl9zJPHwSt5AG54zXGWPCGzdhhCFIAn/LnR4tNHf PD4N+MnHGPHiP+Jy13/Tj6mEsHCiagFj60ekOVm0WZjE1t0G X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB In preparation for adding support for SMIDR_EL1 which is only available in systems with SME factor out the FEAT_IDST injection from emulate-nested.c into a helper and use it when handling hidden ID registers, ensuring that we provide FEAT_IDST behaviour for them. Signed-off-by: Mark Brown --- arch/arm64/include/asm/kvm_emulate.h | 1 + arch/arm64/kvm/emulate-nested.c | 6 +----- arch/arm64/kvm/inject_fault.c | 15 +++++++++++++++ arch/arm64/kvm/sys_regs.c | 6 +++++- 4 files changed, 22 insertions(+), 6 deletions(-) diff --git a/arch/arm64/include/asm/kvm_emulate.h b/arch/arm64/include/asm/= kvm_emulate.h index 5bf3d7e1d92c..994afbf479fc 100644 --- a/arch/arm64/include/asm/kvm_emulate.h +++ b/arch/arm64/include/asm/kvm_emulate.h @@ -45,6 +45,7 @@ bool kvm_condition_valid32(const struct kvm_vcpu *vcpu); void kvm_skip_instr32(struct kvm_vcpu *vcpu); =20 void kvm_inject_undefined(struct kvm_vcpu *vcpu); +void kvm_inject_undefined_idreg(struct kvm_vcpu *vcpu); void kvm_inject_sync(struct kvm_vcpu *vcpu, u64 esr); int kvm_inject_serror_esr(struct kvm_vcpu *vcpu, u64 esr); int kvm_inject_sea(struct kvm_vcpu *vcpu, bool iabt, u64 addr); diff --git a/arch/arm64/kvm/emulate-nested.c b/arch/arm64/kvm/emulate-neste= d.c index e688bc5139c1..f49b7b311d09 100644 --- a/arch/arm64/kvm/emulate-nested.c +++ b/arch/arm64/kvm/emulate-nested.c @@ -2669,11 +2669,7 @@ bool triage_sysreg_trap(struct kvm_vcpu *vcpu, int *= sr_index) * helper for the purpose of dealing with FEAT_IDST. */ if (in_feat_id_space(¶ms)) { - if (kvm_has_feat(vcpu->kvm, ID_AA64MMFR2_EL1, IDS, IMP)) - kvm_inject_sync(vcpu, kvm_vcpu_get_esr(vcpu)); - else - kvm_inject_undefined(vcpu); - + kvm_inject_undefined_idreg(vcpu); return true; } =20 diff --git a/arch/arm64/kvm/inject_fault.c b/arch/arm64/kvm/inject_fault.c index 89982bd3345f..e2f519ca3045 100644 --- a/arch/arm64/kvm/inject_fault.c +++ b/arch/arm64/kvm/inject_fault.c @@ -331,6 +331,21 @@ void kvm_inject_undefined(struct kvm_vcpu *vcpu) inject_undef64(vcpu); } =20 +/** + * kvm_inject_undefined_idreg - emulate UnimplementedIDRegister() pseudoco= de + * @vcpu: The vCPU in which to inject the exception + * + * It is assumed that this code is called from the VCPU thread and that the + * VCPU therefore is not currently executing guest code. + */ +void kvm_inject_undefined_idreg(struct kvm_vcpu *vcpu) +{ + if (kvm_has_feat(vcpu->kvm, ID_AA64MMFR2_EL1, IDS, IMP)) + kvm_inject_sync(vcpu, kvm_vcpu_get_esr(vcpu)); + else + kvm_inject_undefined(vcpu); +} + static bool serror_is_masked(struct kvm_vcpu *vcpu) { return (*vcpu_cpsr(vcpu) & PSR_A_BIT) && !effective_sctlr2_nmea(vcpu); diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 5d5c579d4579..b352cd323e30 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -4759,7 +4759,11 @@ static void perform_access(struct kvm_vcpu *vcpu, =20 /* Check for regs disabled by runtime config */ if (sysreg_hidden(vcpu, r)) { - kvm_inject_undefined(vcpu); + if (in_feat_id_space(params)) { + kvm_inject_undefined_idreg(vcpu); + } else { + kvm_inject_undefined(vcpu); + } return; } =20 --=20 2.47.3 From nobody Fri Jul 10 06:02:12 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2114343745B; Thu, 9 Jul 2026 18:40:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783622439; cv=none; b=AQL8Zae/2ZtZS16fZ9lP7eGt8SWz3q6Z6porJVEIPzc5bRIaghXqUq/E0eAd/fHyy8u4zx953PYHsukabVuH/xtM0KMATmPq6wy5HW/e/wD8fMiSMxidxU9lmmRiS+ahfmIqBB21/GuZm2KxKbZnH8nUkbWTxM7u0vK/tn0MviM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783622439; c=relaxed/simple; bh=1qAIu+pXeO/t0Rjmal4q8j7FSwr2awFBos2cAAJK0lg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=i7K1Tn4UiuOxGxi5PFTI6oI5t1xoRptRhGY8x0Zg01UgWjJYEOX9mPdQpvZWQenW6YWIvStHLVBYX1+U/VhDiLbdC8/n13LbKTw5ZvhWZS4Ekqes2Pck2OmJw+clrwL1kFUD8nQGiF1HPQCHCgU21OHSTjvyOSR3V/EmBL/8I2k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ihfTHfp8; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ihfTHfp8" Received: by smtp.kernel.org (Postfix) with ESMTPSA id E148C1F000E9; Thu, 9 Jul 2026 18:40:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1783622438; bh=+YU88ZRUFkvSVuCkK74k+hG8HaktkRVNfkNeUzR+i14=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=ihfTHfp87MdYBmJMxHtgFose6qvgob6opLw+t2eNcVMQ9aukbr9PFuT5zLFRDQxon MFWoLUz8TKmgMge4d8xs95RbZp9tEzTKgW2ZrRJvMNI3i0E/e9gemLP9MYZv7ugXBJ LdqPl0ZcmpRGJtnNtu8MuEZ5JXLRncGkwxb1RLVG60fJrfvBZba8s1LcTALMqOh1Zk +mRGAIpe/4LltijI6QYtw8M9PYOTaC+D47L+YPmZnmHZ8evM84t8C4VNR49P78lAoA OlWQ8KZqTzugKwBx6hlzuXtFnRUxnR1p7DQdTl9jzE/Y5fdlW5qBZjQtV1OdSOsOD9 zhYQe9qdDojeg== From: Mark Brown Date: Thu, 09 Jul 2026 19:27:28 +0100 Subject: [PATCH v12 07/29] KVM: arm64: Pull ctxt_has_ helpers to start of sysreg-sr.h Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260709-kvm-arm64-sme-v12-7-d0301d79ef58@kernel.org> References: <20260709-kvm-arm64-sme-v12-0-d0301d79ef58@kernel.org> In-Reply-To: <20260709-kvm-arm64-sme-v12-0-d0301d79ef58@kernel.org> To: Marc Zyngier , Joey Gouly , Catalin Marinas , Suzuki K Poulose , Will Deacon , Paolo Bonzini , Jonathan Corbet , Shuah Khan , Oliver Upton Cc: Dave Martin , Fuad Tabba , Mark Rutland , Ben Horgan , Jean-Philippe Brucker , linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Peter Maydell , Eric Auger , Mark Brown X-Mailer: b4 0.16-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=4004; i=broonie@kernel.org; h=from:subject:message-id; bh=1qAIu+pXeO/t0Rjmal4q8j7FSwr2awFBos2cAAJK0lg=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBqT+rv0CVZZwhvdmr4w8M1D6/eLk7nCAkotHen7 paipmGSVSaJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCak/q7wAKCRAk1otyXVSH 0NOlB/9h/rb4vEOB1waSDv3vQ16SkU7O4lt+3wSt0PSB3b66FkebY62Q86k3v7tvxzuhfJzqwVj +wPYMe9WHg6A6qxbw7izS/lGW1s5LIg9xXZJis3QoJDFqdiZh6gNkNByHw4Sw/hmSB2YG9NAziP J46MN1Wo2hXY3vIBZjgOnSyjnGxeLPU14J4g7S6bTKSoAlMHf7rHl7bHBXqAjaC2rHb+EFG85cb jDuRspccrjL/qiJksEQzZaJTQN5WpT+Jtgj6qMS/q6I4u+eubQ7Ad7Ly8GJIslX/jNtYXqHgrvS r7uoHw+XEfoFCgDc5r9xYl/zjIdqV71ujCFEykpP/Xh1/ML1 X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB Rather than add earlier prototypes of specific ctxt_has_ helpers let's just pull all their definitions to the top of sysreg-sr.h so they're all available to all the individual save/restore functions. Reviewed-by: Fuad Tabba Reviewed-by: Jean-Philippe Brucker Signed-off-by: Mark Brown --- arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h | 84 +++++++++++++++-----------= ---- 1 file changed, 41 insertions(+), 43 deletions(-) diff --git a/arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h b/arch/arm64/kvm/hy= p/include/hyp/sysreg-sr.h index a17cbe7582de..5624fd705ae3 100644 --- a/arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h +++ b/arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h @@ -16,8 +16,6 @@ #include #include =20 -static inline bool ctxt_has_s1poe(struct kvm_cpu_context *ctxt); - static inline struct kvm_vcpu *ctxt_to_vcpu(struct kvm_cpu_context *ctxt) { struct kvm_vcpu *vcpu =3D ctxt->__hyp_running_vcpu; @@ -28,47 +26,6 @@ static inline struct kvm_vcpu *ctxt_to_vcpu(struct kvm_c= pu_context *ctxt) return vcpu; } =20 -static inline bool ctxt_is_guest(struct kvm_cpu_context *ctxt) -{ - return host_data_ptr(host_ctxt) !=3D ctxt; -} - -static inline u64 *ctxt_mdscr_el1(struct kvm_cpu_context *ctxt) -{ - struct kvm_vcpu *vcpu =3D ctxt_to_vcpu(ctxt); - - if (ctxt_is_guest(ctxt) && kvm_host_owns_debug_regs(vcpu)) - return &vcpu->arch.external_mdscr_el1; - - return &ctxt_sys_reg(ctxt, MDSCR_EL1); -} - -static inline u64 ctxt_midr_el1(struct kvm_cpu_context *ctxt) -{ - struct kvm *kvm =3D kern_hyp_va(ctxt_to_vcpu(ctxt)->kvm); - - if (!(ctxt_is_guest(ctxt) && - test_bit(KVM_ARCH_FLAG_WRITABLE_IMP_ID_REGS, &kvm->arch.flags))) - return read_cpuid_id(); - - return kvm_read_vm_id_reg(kvm, SYS_MIDR_EL1); -} - -static inline void __sysreg_save_common_state(struct kvm_cpu_context *ctxt) -{ - *ctxt_mdscr_el1(ctxt) =3D read_sysreg(mdscr_el1); - - // POR_EL0 can affect uaccess, so must be saved/restored early. - if (ctxt_has_s1poe(ctxt)) - ctxt_sys_reg(ctxt, POR_EL0) =3D read_sysreg_s(SYS_POR_EL0); -} - -static inline void __sysreg_save_user_state(struct kvm_cpu_context *ctxt) -{ - ctxt_sys_reg(ctxt, TPIDR_EL0) =3D read_sysreg(tpidr_el0); - ctxt_sys_reg(ctxt, TPIDRRO_EL0) =3D read_sysreg(tpidrro_el0); -} - static inline bool ctxt_has_mte(struct kvm_cpu_context *ctxt) { struct kvm_vcpu *vcpu =3D ctxt_to_vcpu(ctxt); @@ -131,6 +88,47 @@ static inline bool ctxt_has_sctlr2(struct kvm_cpu_conte= xt *ctxt) return kvm_has_sctlr2(kern_hyp_va(vcpu->kvm)); } =20 +static inline bool ctxt_is_guest(struct kvm_cpu_context *ctxt) +{ + return host_data_ptr(host_ctxt) !=3D ctxt; +} + +static inline u64 *ctxt_mdscr_el1(struct kvm_cpu_context *ctxt) +{ + struct kvm_vcpu *vcpu =3D ctxt_to_vcpu(ctxt); + + if (ctxt_is_guest(ctxt) && kvm_host_owns_debug_regs(vcpu)) + return &vcpu->arch.external_mdscr_el1; + + return &ctxt_sys_reg(ctxt, MDSCR_EL1); +} + +static inline u64 ctxt_midr_el1(struct kvm_cpu_context *ctxt) +{ + struct kvm *kvm =3D kern_hyp_va(ctxt_to_vcpu(ctxt)->kvm); + + if (!(ctxt_is_guest(ctxt) && + test_bit(KVM_ARCH_FLAG_WRITABLE_IMP_ID_REGS, &kvm->arch.flags))) + return read_cpuid_id(); + + return kvm_read_vm_id_reg(kvm, SYS_MIDR_EL1); +} + +static inline void __sysreg_save_common_state(struct kvm_cpu_context *ctxt) +{ + *ctxt_mdscr_el1(ctxt) =3D read_sysreg(mdscr_el1); + + // POR_EL0 can affect uaccess, so must be saved/restored early. + if (ctxt_has_s1poe(ctxt)) + ctxt_sys_reg(ctxt, POR_EL0) =3D read_sysreg_s(SYS_POR_EL0); +} + +static inline void __sysreg_save_user_state(struct kvm_cpu_context *ctxt) +{ + ctxt_sys_reg(ctxt, TPIDR_EL0) =3D read_sysreg(tpidr_el0); + ctxt_sys_reg(ctxt, TPIDRRO_EL0) =3D read_sysreg(tpidrro_el0); +} + static inline void __sysreg_save_el1_state(struct kvm_cpu_context *ctxt) { ctxt_sys_reg(ctxt, SCTLR_EL1) =3D read_sysreg_el1(SYS_SCTLR); --=20 2.47.3 From nobody Fri Jul 10 06:02:12 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E12B843B4A7; Thu, 9 Jul 2026 18:40:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783622444; cv=none; b=IkKf2XQibt+VxUjKi89r+eh5XE7Y/OuSWKYr/pL4qm56F//DkXrmVSplRGRCcAhu9gfaj6xJ8wy0Kei9P0+lSv6KvqxGB/XVLgyjCqWNvJBBb7Lnwzzy+/3k/D5A37BVvuNzNcR4ZwzOCPH0i3xCL8HSgza0csN6Qr+k8cJV6JQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783622444; c=relaxed/simple; bh=z7S7gabtTQubvf1C5BhMhuZ4burPUnffHou5hS57R50=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=i6FbYIo2xSp29FATZ1VIewSgon6J/8dc/QC6zINfUHRSyZ8QXfRe12jUitSuJzbEqIheGq1dlTvHe+V6BKHf5HsV/uOqKpub+C68qyUPVu4MEuXRjRDq3F1rv1SqIrktzl4Z/eeaVxw2B1qwCJ1jwPDl6niqrdlCkuzo/DuZkxk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=A777a5Xe; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="A777a5Xe" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7153F1F00A3A; Thu, 9 Jul 2026 18:40:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1783622442; bh=I4xrVSbCp5yAA6Gucb4v+xBsvRi+5+69PJv2auOuOQs=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=A777a5Xe71OPA97BNOYpb6Nw2XmrX/IDFyk/jBg4GWQknAL94ymV4TRHEyrwDZQNY Xu/sglIP2t5/QJzwMpcjdQaWyWdhJ0jWRRs/JmChHQKoU7WFgdHYBK39Riy4bmoO5N lulZADzw66CU36bxBgemgQWDKzL1PHqify83QghksYfbLMtiEf5Ri1+HHn6ej8tnfH 8xPLfE65gg0fTWdrsrGnrUHxPLh4GzPJIIZwF3heJSMrKFpkA94Ly6Xzo3s+2Q1ztB 2kQVrAvOGMRmiSufYrydXUfElZ+jkz4lZUHV4ZEx4m9SGTHaKx9j7BAkKE+jRnRJdk Elx1BwNaRgGrg== From: Mark Brown Date: Thu, 09 Jul 2026 19:27:29 +0100 Subject: [PATCH v12 08/29] KVM: arm64: Rename SVE finalization constants to be more general Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260709-kvm-arm64-sme-v12-8-d0301d79ef58@kernel.org> References: <20260709-kvm-arm64-sme-v12-0-d0301d79ef58@kernel.org> In-Reply-To: <20260709-kvm-arm64-sme-v12-0-d0301d79ef58@kernel.org> To: Marc Zyngier , Joey Gouly , Catalin Marinas , Suzuki K Poulose , Will Deacon , Paolo Bonzini , Jonathan Corbet , Shuah Khan , Oliver Upton Cc: Dave Martin , Fuad Tabba , Mark Rutland , Ben Horgan , Jean-Philippe Brucker , linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Peter Maydell , Eric Auger , Mark Brown X-Mailer: b4 0.16-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=7699; i=broonie@kernel.org; h=from:subject:message-id; bh=z7S7gabtTQubvf1C5BhMhuZ4burPUnffHou5hS57R50=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBqT+rwcLFiKREMHkNClLkm0GiWIjvDVkUs9e7mU HtHdqz3hiuJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCak/q8AAKCRAk1otyXVSH 0MxrB/986yIZRhNg58X00RlMfkV7fPpB98z/kXOxXf1ni0wr/xsdoOgpfCT07pXzzAFBkZj6Oqj Ro+hGgf38ztiZnNCluCtKv27z+HYS62dh0X4l1syKqFdjKwf1nt9MhPz0fSlf9P59GlJGQzqsuo jQyvAAbJH3pqENjB5Y2mmHAx1YrMGRxZ2OtQ8mfPm+0zaoZbDZ+ixIViMsr4Zei4UnLu6soDNPx fMQVLiuW7ugn98/Hu0ItQyU+dTudz9SxOd5vGHv1KMoSz9c69QrU77Hv0pHeGkTvMf/+V9fhmfv Or9ECRuSkzPr+yKBlc8F+iGiITb2/UYJXkkTVhKWKWCUDu4E X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB Due to the overlap between SVE and SME vector length configuration created by streaming mode SVE we will finalize both at once. Rename the existing finalization to use _VEC (vector) for the naming to avoid confusion. Since this includes the userspace API we create an alias KVM_ARM_VCPU_VEC for the existing KVM_ARM_VCPU_SVE capability, existing code which does not enable SME will be unaffected and any SME only code will not need to use SVE constants. No functional change. Reviewed-by: Fuad Tabba Reviewed-by: Jean-Philippe Brucker Signed-off-by: Mark Brown --- arch/arm64/include/asm/kvm_host.h | 8 +++++--- arch/arm64/include/uapi/asm/kvm.h | 6 ++++++ arch/arm64/kvm/guest.c | 12 ++++++------ arch/arm64/kvm/hyp/nvhe/pkvm.c | 2 +- arch/arm64/kvm/reset.c | 20 ++++++++++---------- 5 files changed, 28 insertions(+), 20 deletions(-) diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm= _host.h index bae2c4f92ef5..8b746b1a1e53 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -1037,8 +1037,8 @@ struct kvm_vcpu_arch { =20 /* KVM_ARM_VCPU_INIT completed */ #define VCPU_INITIALIZED __vcpu_single_flag(cflags, BIT(0)) -/* SVE config completed */ -#define VCPU_SVE_FINALIZED __vcpu_single_flag(cflags, BIT(1)) +/* Vector config completed */ +#define VCPU_VEC_FINALIZED __vcpu_single_flag(cflags, BIT(1)) /* pKVM VCPU setup completed */ #define VCPU_PKVM_FINALIZED __vcpu_single_flag(cflags, BIT(2)) =20 @@ -1133,6 +1133,8 @@ struct kvm_vcpu_arch { #define vcpu_has_sve(vcpu) kvm_has_sve((vcpu)->kvm) #endif =20 +#define vcpu_has_vec(vcpu) vcpu_has_sve(vcpu) + #ifdef CONFIG_ARM64_PTR_AUTH #define vcpu_has_ptrauth(vcpu) \ ((cpus_have_final_cap(ARM64_HAS_ADDRESS_AUTH) || \ @@ -1505,7 +1507,7 @@ struct kvm *kvm_arch_alloc_vm(void); int kvm_arm_vcpu_finalize(struct kvm_vcpu *vcpu, int feature); bool kvm_arm_vcpu_is_finalized(struct kvm_vcpu *vcpu); =20 -#define kvm_arm_vcpu_sve_finalized(vcpu) vcpu_get_flag(vcpu, VCPU_SVE_FINA= LIZED) +#define kvm_arm_vcpu_vec_finalized(vcpu) vcpu_get_flag(vcpu, VCPU_VEC_FINA= LIZED) =20 #define kvm_has_mte(kvm) \ (system_supports_mte() && \ diff --git a/arch/arm64/include/uapi/asm/kvm.h b/arch/arm64/include/uapi/as= m/kvm.h index 1c13bfa2d38a..83af99ca4e1b 100644 --- a/arch/arm64/include/uapi/asm/kvm.h +++ b/arch/arm64/include/uapi/asm/kvm.h @@ -107,6 +107,12 @@ struct kvm_regs { #define KVM_ARM_VCPU_HAS_EL2 7 /* Support nested virtualization */ #define KVM_ARM_VCPU_HAS_EL2_E2H0 8 /* Limit NV support to E2H RES0 */ =20 +/* + * An alias for _SVE since we finalize VL configuration for both SVE and S= ME + * simultaneously. + */ +#define KVM_ARM_VCPU_VEC KVM_ARM_VCPU_SVE + struct kvm_vcpu_init { __u32 target; __u32 features[7]; diff --git a/arch/arm64/kvm/guest.c b/arch/arm64/kvm/guest.c index b01d6622b872..0b789f73bf7c 100644 --- a/arch/arm64/kvm/guest.c +++ b/arch/arm64/kvm/guest.c @@ -342,7 +342,7 @@ static int set_sve_vls(struct kvm_vcpu *vcpu, const str= uct kvm_one_reg *reg) if (!vcpu_has_sve(vcpu)) return -ENOENT; =20 - if (kvm_arm_vcpu_sve_finalized(vcpu)) + if (kvm_arm_vcpu_vec_finalized(vcpu)) return -EPERM; /* too late! */ =20 if (WARN_ON(vcpu->arch.sve_state)) @@ -374,7 +374,7 @@ static int set_sve_vls(struct kvm_vcpu *vcpu, const str= uct kvm_one_reg *reg) if (max_vq < SVE_VQ_MIN) return -EINVAL; =20 - /* vcpu->arch.sve_state will be alloc'd by kvm_vcpu_finalize_sve() */ + /* vcpu->arch.sve_state will be alloc'd by kvm_vcpu_finalize_vec() */ vcpu->arch.sve_max_vl =3D sve_vl_from_vq(max_vq); =20 return 0; @@ -497,7 +497,7 @@ static int get_sve_reg(struct kvm_vcpu *vcpu, const str= uct kvm_one_reg *reg) if (ret) return ret; =20 - if (!kvm_arm_vcpu_sve_finalized(vcpu)) + if (!kvm_arm_vcpu_vec_finalized(vcpu)) return -EPERM; =20 if (copy_to_user(uptr, (void *)vcpu->arch.sve_state + region.koffset, @@ -523,7 +523,7 @@ static int set_sve_reg(struct kvm_vcpu *vcpu, const str= uct kvm_one_reg *reg) if (ret) return ret; =20 - if (!kvm_arm_vcpu_sve_finalized(vcpu)) + if (!kvm_arm_vcpu_vec_finalized(vcpu)) return -EPERM; =20 if (copy_from_user((void *)vcpu->arch.sve_state + region.koffset, uptr, @@ -599,7 +599,7 @@ static unsigned long num_sve_regs(const struct kvm_vcpu= *vcpu) return 0; =20 /* Policed by KVM_GET_REG_LIST: */ - WARN_ON(!kvm_arm_vcpu_sve_finalized(vcpu)); + WARN_ON(!kvm_arm_vcpu_vec_finalized(vcpu)); =20 return slices * (SVE_NUM_PREGS + SVE_NUM_ZREGS + 1 /* FFR */) + 1; /* KVM_REG_ARM64_SVE_VLS */ @@ -617,7 +617,7 @@ static int copy_sve_reg_indices(const struct kvm_vcpu *= vcpu, return 0; =20 /* Policed by KVM_GET_REG_LIST: */ - WARN_ON(!kvm_arm_vcpu_sve_finalized(vcpu)); + WARN_ON(!kvm_arm_vcpu_vec_finalized(vcpu)); =20 /* * Enumerate this first, so that userspace can save/restore in diff --git a/arch/arm64/kvm/hyp/nvhe/pkvm.c b/arch/arm64/kvm/hyp/nvhe/pkvm.c index 3b2c4fbc34d8..9d7f632f01f8 100644 --- a/arch/arm64/kvm/hyp/nvhe/pkvm.c +++ b/arch/arm64/kvm/hyp/nvhe/pkvm.c @@ -454,7 +454,7 @@ static int pkvm_vcpu_init_sve(struct pkvm_hyp_vcpu *hyp= _vcpu, struct kvm_vcpu *h int ret =3D 0; =20 if (!vcpu_has_feature(vcpu, KVM_ARM_VCPU_SVE)) { - vcpu_clear_flag(vcpu, VCPU_SVE_FINALIZED); + vcpu_clear_flag(vcpu, VCPU_VEC_FINALIZED); return 0; } =20 diff --git a/arch/arm64/kvm/reset.c b/arch/arm64/kvm/reset.c index b963fd975aac..0fae62a9eaef 100644 --- a/arch/arm64/kvm/reset.c +++ b/arch/arm64/kvm/reset.c @@ -92,7 +92,7 @@ static void kvm_vcpu_enable_sve(struct kvm_vcpu *vcpu) * Finalize vcpu's maximum SVE vector length, allocating * vcpu->arch.sve_state as necessary. */ -static int kvm_vcpu_finalize_sve(struct kvm_vcpu *vcpu) +static int kvm_vcpu_finalize_vec(struct kvm_vcpu *vcpu) { void *buf; unsigned int vl; @@ -122,21 +122,21 @@ static int kvm_vcpu_finalize_sve(struct kvm_vcpu *vcp= u) } =09 vcpu->arch.sve_state =3D buf; - vcpu_set_flag(vcpu, VCPU_SVE_FINALIZED); + vcpu_set_flag(vcpu, VCPU_VEC_FINALIZED); return 0; } =20 int kvm_arm_vcpu_finalize(struct kvm_vcpu *vcpu, int feature) { switch (feature) { - case KVM_ARM_VCPU_SVE: - if (!vcpu_has_sve(vcpu)) + case KVM_ARM_VCPU_VEC: + if (!vcpu_has_vec(vcpu)) return -EINVAL; =20 - if (kvm_arm_vcpu_sve_finalized(vcpu)) + if (kvm_arm_vcpu_vec_finalized(vcpu)) return -EPERM; =20 - return kvm_vcpu_finalize_sve(vcpu); + return kvm_vcpu_finalize_vec(vcpu); } =20 return -EINVAL; @@ -144,7 +144,7 @@ int kvm_arm_vcpu_finalize(struct kvm_vcpu *vcpu, int fe= ature) =20 bool kvm_arm_vcpu_is_finalized(struct kvm_vcpu *vcpu) { - if (vcpu_has_sve(vcpu) && !kvm_arm_vcpu_sve_finalized(vcpu)) + if (vcpu_has_vec(vcpu) && !kvm_arm_vcpu_vec_finalized(vcpu)) return false; =20 return true; @@ -163,7 +163,7 @@ void kvm_arm_vcpu_destroy(struct kvm_vcpu *vcpu) kfree(vcpu->arch.ccsidr); } =20 -static void kvm_vcpu_reset_sve(struct kvm_vcpu *vcpu) +static void kvm_vcpu_reset_vec(struct kvm_vcpu *vcpu) { if (vcpu_has_sve(vcpu)) memset(vcpu->arch.sve_state, 0, vcpu_sve_state_size(vcpu)); @@ -203,11 +203,11 @@ void kvm_reset_vcpu(struct kvm_vcpu *vcpu) if (loaded) kvm_arch_vcpu_put(vcpu); =20 - if (!kvm_arm_vcpu_sve_finalized(vcpu)) { + if (!kvm_arm_vcpu_vec_finalized(vcpu)) { if (vcpu_has_feature(vcpu, KVM_ARM_VCPU_SVE)) kvm_vcpu_enable_sve(vcpu); } else { - kvm_vcpu_reset_sve(vcpu); + kvm_vcpu_reset_vec(vcpu); } =20 if (vcpu_el1_is_32bit(vcpu)) --=20 2.47.3 From nobody Fri Jul 10 06:02:12 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0152343B4A7; Thu, 9 Jul 2026 18:40:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783622449; cv=none; b=djlGSZh/oWUruEJ5Io0VhLsUzyrH0d89YJoFAzyiideyhMMFpg+SffcHcpoNG6Yy1b1BfxkGS6X3J9K1cO3bZkgIAZtNHKzyvhlIsP7kcZD38HbDUoc4pe5Z8AFLsPns3P7+MFBOugkS0NgmYS3GodY1gwLadk9ygMTGjIXftCE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783622449; c=relaxed/simple; bh=sk5UV4D8nxCJMJ3xILivF4E7O/FkNOR/tMjqIGqB6Y0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=kLMbP2UICnId+r9x6fcvwJl55ya2Tcdn0M4OdzQJ9VIndvsJz8go2tgh34z275YPlqyWHuZ3Iv0JyHY4fdZ8uypEqVuHmlM/ydZDRFj1erkIMniX8UPIvqD0zuvRacqgfniETVRqUwmfNIoSmJPi9x6SRpLu09OOHM6YLgd0qOY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=mgKrxYgS; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="mgKrxYgS" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 007F41F00A3D; Thu, 9 Jul 2026 18:40:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1783622447; bh=/D7A+/K09S6yFl/i+7JwiO/DHtiAAbsIdjqdAGJ7jGk=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=mgKrxYgSIcBlpe4Bo27wDH0q+ZeuEC0ninInExr/W1Yqo3U1WVz6ydh4pge7oCiWt bILrQokD5f9APsTOc459WS424W1DvtacpBJ1sgsP+3yZakufGvxcwrVEky8ykFCKc5 Emc84V4sPzsXQHpBHA1DlNI0HtMkGmca5+dirLqM+HYjc4RXaw7xIApQ365KGTkclf 1Lx2VBIu5osET/0Z1MsQ7txX2JHUFt9TvT0Zi5UN1c+M/EJe87nQe3L4yQbrPWXVnt 7JQZ0dBFAb50PB+ASw5TmfZ0hZvtsuDpOXtN8aCLppZeWrO6G/1WHXkHRxV2E4n7Uo fH/8vGsAHgA3A== From: Mark Brown Date: Thu, 09 Jul 2026 19:27:30 +0100 Subject: [PATCH v12 09/29] KVM: arm64: Define internal features for SME Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260709-kvm-arm64-sme-v12-9-d0301d79ef58@kernel.org> References: <20260709-kvm-arm64-sme-v12-0-d0301d79ef58@kernel.org> In-Reply-To: <20260709-kvm-arm64-sme-v12-0-d0301d79ef58@kernel.org> To: Marc Zyngier , Joey Gouly , Catalin Marinas , Suzuki K Poulose , Will Deacon , Paolo Bonzini , Jonathan Corbet , Shuah Khan , Oliver Upton Cc: Dave Martin , Fuad Tabba , Mark Rutland , Ben Horgan , Jean-Philippe Brucker , linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Peter Maydell , Eric Auger , Mark Brown X-Mailer: b4 0.16-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=3307; i=broonie@kernel.org; h=from:subject:message-id; bh=sk5UV4D8nxCJMJ3xILivF4E7O/FkNOR/tMjqIGqB6Y0=; b=kA0DAAoBJNaLcl1Uh9AByyZiAGpP6vGixroq2Dqygirl/HNE1Gkjv+/lzgYvCL8/RgFecFYwQ YkBMwQAAQoAHRYhBK3maKpnVxi1n+Kf6iTWi3JdVIfQBQJqT+rxAAoJECTWi3JdVIfQo/UIAIHS s5yxPE+7oCWVKhITts7HuEm7l1olgpo6JbGKUqAgxynCfj8qAh7BEev4IH5210e223eBSgRlUKo /riXtJtMgYc8/hI/Nt3EQLhk37hhaZ1p3Bd07IM564c3ZYfixQRTzZuKBxnv5+QMePmFICCrnkx z/6hDvBsurCKVWxE8ZNZ+b9jF4LzX8PjEJj5hvr/zLzac96hjnA1wfMxWdyzsR8g+2SF4Qb9So7 09vohPckvwihA/If7RjRsialVdFDIWqSQZGL0nXq826A0nYrBxa9y3j/SLsnuqJ0nVLZY6QYQCb Bg7wXkjjfbzMjBAqmmjf6SfCxgobaPfCAPazBwU= X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB In order to simplify interdependencies in the rest of the series define the feature detection for SME and its subfeatures. Due to the need for vector length configuration we define a flag for SME like for SVE. We also have two subfeatures which add architectural state, FA64 and SME2, which are configured via the normal ID register scheme. Also provide helpers which check if the vCPU is in streaming mode or has ZA enabled. Reviewed-by: Fuad Tabba Signed-off-by: Mark Brown --- arch/arm64/include/asm/kvm_host.h | 35 ++++++++++++++++++++++++++++++++++- arch/arm64/kvm/sys_regs.c | 2 +- 2 files changed, 35 insertions(+), 2 deletions(-) diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm= _host.h index 8b746b1a1e53..8e185e43fbff 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -367,6 +367,8 @@ struct kvm_arch { #define KVM_ARCH_FLAG_WRITABLE_IMP_ID_REGS 10 /* Unhandled SEAs are taken to userspace */ #define KVM_ARCH_FLAG_EXIT_SEA 11 + /* SME exposed to guest */ +#define KVM_ARCH_FLAG_GUEST_HAS_SME 12 unsigned long flags; =20 /* VM-wide vCPU feature set */ @@ -1133,7 +1135,16 @@ struct kvm_vcpu_arch { #define vcpu_has_sve(vcpu) kvm_has_sve((vcpu)->kvm) #endif =20 -#define vcpu_has_vec(vcpu) vcpu_has_sve(vcpu) +#define kvm_has_sme(kvm) (system_supports_sme() && \ + test_bit(KVM_ARCH_FLAG_GUEST_HAS_SME, &(kvm)->arch.flags)) + +#ifdef __KVM_NVHE_HYPERVISOR__ +#define vcpu_has_sme(vcpu) kvm_has_sme(kern_hyp_va((vcpu)->kvm)) +#else +#define vcpu_has_sme(vcpu) kvm_has_sme((vcpu)->kvm) +#endif + +#define vcpu_has_vec(vcpu) (vcpu_has_sve(vcpu) || vcpu_has_sme(vcpu)) =20 #ifdef CONFIG_ARM64_PTR_AUTH #define vcpu_has_ptrauth(vcpu) \ @@ -1650,6 +1661,28 @@ void kvm_set_vm_id_reg(struct kvm *kvm, u32 reg, u64= val); #define kvm_has_sctlr2(k) \ (kvm_has_feat((k), ID_AA64MMFR3_EL1, SCTLRX, IMP)) =20 +#define kvm_has_fa64(k) \ + (system_supports_fa64() && \ + kvm_has_feat((k), ID_AA64SMFR0_EL1, FA64, IMP)) + +#define kvm_has_sme2(k) \ + (system_supports_sme2() && \ + kvm_has_feat((k), ID_AA64PFR1_EL1, SME, SME2)) + +#ifdef __KVM_NVHE_HYPERVISOR__ +#define vcpu_has_sme2(vcpu) kvm_has_sme2(kern_hyp_va((vcpu)->kvm)) +#define vcpu_has_fa64(vcpu) kvm_has_fa64(kern_hyp_va((vcpu)->kvm)) +#else +#define vcpu_has_sme2(vcpu) kvm_has_sme2((vcpu)->kvm) +#define vcpu_has_fa64(vcpu) kvm_has_fa64((vcpu)->kvm) +#endif + +#define vcpu_in_streaming_mode(vcpu) \ + (__vcpu_sys_reg(vcpu, SVCR) & SVCR_SM_MASK) + +#define vcpu_za_enabled(vcpu) \ + (__vcpu_sys_reg(vcpu, SVCR) & SVCR_ZA_MASK) + static inline bool kvm_arch_has_irq_bypass(void) { return true; diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index b352cd323e30..ba8a3ed8f5ff 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -2028,7 +2028,7 @@ static unsigned int sve_visibility(const struct kvm_v= cpu *vcpu, static unsigned int sme_visibility(const struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd) { - if (kvm_has_feat(vcpu->kvm, ID_AA64PFR1_EL1, SME, IMP)) + if (vcpu_has_sme(vcpu)) return 0; =20 return REG_HIDDEN; --=20 2.47.3 From nobody Fri Jul 10 06:02:12 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 037A743B4A7; Thu, 9 Jul 2026 18:40:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783622453; cv=none; b=R0m9Ue2APrKcCh3OcylSfm+vjSavD+W6NUb/F1kniDdv1G29uq7h6ny8j0IpwWM1DjAucoz8PnBpV7InRGQIuJvSRItl80tyDjClOpPFNeJDp59GkGlK2DsGJOaHx4jmDA2bqXtDSOg9QAwDMkenfQ2YY+ZQgX1cYBE1sgEmhq8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783622453; c=relaxed/simple; bh=LymwA3DqasGC4ZFs4/KMSvspNgOVO26BbyCDy7Uzk5Q=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=mzvF7iwCurJH/H9N1UqLIxtG+pJauUKNc47UL6NZZs6mdyDze63f3blo4iUbxqQwq+yRUNf3d12P0zIus1JSGx2beK2Uk6MZQ4rKbJ6FxdOw9cIJi2g+N3rwhcpX/dm4vqQr542srwacTG2QJBFXj9nY4E+0BJqJtXLKzLMyEZw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=dlPlxFTO; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="dlPlxFTO" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 83A951F00A3E; Thu, 9 Jul 2026 18:40:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1783622451; bh=H8WckkdslO+jqzhb243ic0W1zpfpgFKz9U8uw4dwQBU=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=dlPlxFTOihrtyHnEZV+H88T0XJoVHOEenO3yPnvf3RaMQ8boYA/0qV1wPonP0F87S QLsO7M/P+0Eoy+YtlhlMg4QMOEYa5Vb97vZ73rpD3q8RNehXzgR5EgaulQOEdBCLyz qyNoUE2uwAm70+opJk+XW/6Td4ooef+tZQHU/LHXYq+7jTYeFy26mfngWeofT3szIy PaXwey41iBRLFjKDlA/ZHVyBnhrWsVKqattai4MLOcPCdLBKgSffatPcrMRseXwplM oMpJKCy09TsN/42qiOmtGO7xkr2a52b4NClI03ZYSALAw4MMC7rF/XXZBeqdDBbTE2 aNiN5IRIo/7PA== From: Mark Brown Date: Thu, 09 Jul 2026 19:27:31 +0100 Subject: [PATCH v12 10/29] KVM: arm64: Rename sve_state_reg_region Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260709-kvm-arm64-sme-v12-10-d0301d79ef58@kernel.org> References: <20260709-kvm-arm64-sme-v12-0-d0301d79ef58@kernel.org> In-Reply-To: <20260709-kvm-arm64-sme-v12-0-d0301d79ef58@kernel.org> To: Marc Zyngier , Joey Gouly , Catalin Marinas , Suzuki K Poulose , Will Deacon , Paolo Bonzini , Jonathan Corbet , Shuah Khan , Oliver Upton Cc: Dave Martin , Fuad Tabba , Mark Rutland , Ben Horgan , Jean-Philippe Brucker , linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Peter Maydell , Eric Auger , Mark Brown X-Mailer: b4 0.16-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=2449; i=broonie@kernel.org; h=from:subject:message-id; bh=LymwA3DqasGC4ZFs4/KMSvspNgOVO26BbyCDy7Uzk5Q=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBqT+rxJEu7Sekl1584rUwiaayoFlVsCzxxoeDoa hKPxoF1eEiJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCak/q8QAKCRAk1otyXVSH 0BO2B/0THbdeuRzQNA7FHbTe5OzOQnS4lMTLibBq/lNyz0ieEu1Yvg9UagQb8JuQKDQny3UgTIt APBJQ4WCDX1fhXixyBC2AE/K966O1iTIMexQPxZUCihBgizLy80MHz5/T/smboVQkbTk8u1FeyA cydk1XYntnfjVYMpepAr9TqRL1eTvTYpTPXRa26lwYVH5MWNZ97VJJdH2JfG6AhVoz0HDDq/+4T VzOWCI5GntCxfMm4ZFsJEeTUcZ958m+jjwcAL/D4orUOLi+V34C0M7W2UQfKPvk6s3mWvPIJWCI CUkxQENtDBqYG05kBU8Nk4ZEsd2Qd2o7rk3J1SurCrLWaqfe X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB As for SVE we will need to pull parts of dynamically sized registers out of a block of memory for SME so we will use a similar code pattern for this. Rename the current struct sve_state_reg_region in preparation for this. No functional change. Reviewed-by: Fuad Tabba Reviewed-by: Jean-Philippe Brucker Signed-off-by: Mark Brown --- arch/arm64/kvm/guest.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/kvm/guest.c b/arch/arm64/kvm/guest.c index 0b789f73bf7c..3ae751e72c95 100644 --- a/arch/arm64/kvm/guest.c +++ b/arch/arm64/kvm/guest.c @@ -404,9 +404,9 @@ static int set_sve_vls(struct kvm_vcpu *vcpu, const str= uct kvm_one_reg *reg) */ #define vcpu_sve_slices(vcpu) 1 =20 -/* Bounds of a single SVE register slice within vcpu->arch.sve_state */ -struct sve_state_reg_region { - unsigned int koffset; /* offset into sve_state in kernel memory */ +/* Bounds of a single register slice within vcpu->arch.s[mv]e_state */ +struct vec_state_reg_region { + unsigned int koffset; /* offset into s[mv]e_state in kernel memory */ unsigned int klen; /* length in kernel memory */ unsigned int upad; /* extra trailing padding in user memory */ }; @@ -415,7 +415,7 @@ struct sve_state_reg_region { * Validate SVE register ID and get sanitised bounds for user/kernel SVE * register copy */ -static int sve_reg_to_region(struct sve_state_reg_region *region, +static int sve_reg_to_region(struct vec_state_reg_region *region, struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) { @@ -485,7 +485,7 @@ static int sve_reg_to_region(struct sve_state_reg_regio= n *region, static int get_sve_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *re= g) { int ret; - struct sve_state_reg_region region; + struct vec_state_reg_region region; char __user *uptr =3D (char __user *)reg->addr; =20 /* Handle the KVM_REG_ARM64_SVE_VLS pseudo-reg as a special case: */ @@ -511,7 +511,7 @@ static int get_sve_reg(struct kvm_vcpu *vcpu, const str= uct kvm_one_reg *reg) static int set_sve_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *re= g) { int ret; - struct sve_state_reg_region region; + struct vec_state_reg_region region; const char __user *uptr =3D (const char __user *)reg->addr; =20 /* Handle the KVM_REG_ARM64_SVE_VLS pseudo-reg as a special case: */ --=20 2.47.3 From nobody Fri Jul 10 06:02:12 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9596A43B4A7; Thu, 9 Jul 2026 18:40:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783622458; cv=none; b=qYj3CsvLCVG3gjyrNswgE/j+YUwiDCvzf26YuqyUqKvQByf3/EeJBuZ3MQEdbNq/4KFjm1MHEGxT1Q9XgA2WFZb9TReA+wtJ543IJ66t0Kpl2NnM4ymJ7TL0nodML5xBFSSMPmHW8VbdnnS2Jbh1rVjAPjAu8p9/T4wV1NlpaB0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783622458; c=relaxed/simple; bh=1sF/BYH85HO3kwSH/mqUWFa4CEl7bBw6DGcehely/x0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=fGCDcvjLB1J29Y+SCwaNEciguIxX6tlcdpNxQDo1yX9hhA38zkdkhTaMJGk3wCPqbru4O/KbOOOi8JZiRSvhCi2mqkyVhAL9O/VTR1SAV4Ujthm1iN2Dp958ZKw0U0C0B+zp5B+ResZhqMQUzO0JMTNmvtuMvNniDfsOJDaG2nE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Gi7hgy34; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Gi7hgy34" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 121221F000E9; Thu, 9 Jul 2026 18:40:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1783622456; bh=5Bp5YL6dNxVcJS8w+5AZKzMfxgUu6n6EByDBPkemuIM=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=Gi7hgy34UN7piQxujSDlZ61wFix+vURLvR4N73Ok52apqrPlhaPDhXMCshSqU95af zL7Z9j+fEbNkJHhmhGILmDcKvNpXDiz6hbLfrj5MoForEgmYsk+Cm4ZkaSRoairanx lysCoGBD8LVEtchOC1LtxCDtchg3Jl0vrEGAUkWUH+Vhfan6YawOZ5Uyx9wIdZSfsg HS7bxkyoJoKd8V7iqVISfh9dsy7GNcbow2btI1F04CiryucculRuckiLTpabswGFJQ kuCObQTOSLnXts88zWouYLs7HAExBhEXchiMnBKS5B9ojQa3fYulV32Y2eO2Q6RAMO Ks/Jge5js2sqw== From: Mark Brown Date: Thu, 09 Jul 2026 19:27:32 +0100 Subject: [PATCH v12 11/29] KVM: arm64: Store vector lengths in an array Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260709-kvm-arm64-sme-v12-11-d0301d79ef58@kernel.org> References: <20260709-kvm-arm64-sme-v12-0-d0301d79ef58@kernel.org> In-Reply-To: <20260709-kvm-arm64-sme-v12-0-d0301d79ef58@kernel.org> To: Marc Zyngier , Joey Gouly , Catalin Marinas , Suzuki K Poulose , Will Deacon , Paolo Bonzini , Jonathan Corbet , Shuah Khan , Oliver Upton Cc: Dave Martin , Fuad Tabba , Mark Rutland , Ben Horgan , Jean-Philippe Brucker , linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Peter Maydell , Eric Auger , Mark Brown X-Mailer: b4 0.16-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=10749; i=broonie@kernel.org; h=from:subject:message-id; bh=1sF/BYH85HO3kwSH/mqUWFa4CEl7bBw6DGcehely/x0=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBqT+ryLKZUbevZVByW/+TDGjxkoe5aYixB8PrzP 6z1f6nDVgeJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCak/q8gAKCRAk1otyXVSH 0GAgB/9TOkN1dsh/R+CieZuHihMToS5cIW96wH1qMU53t650cxOjX8lBxvmHE0TAG8uuEQNAhlh 1x+55HH6sseVFHA5ZVrXSJ4jaOJt3pUiTH6fxxepNX7ewI7orI6evBusDBqizdc3ol6YZqJGphF y+uW/ILYxDOLgklnk8WhKIQw3uU8LYBaihu1qGzNaNHR88i5+/dxl7PLfoHV7kMWe8Xgtj4g638 5vDJrsqsCbQ2EEb6/mPy52RvblOll+kQjZsDbdyDnVDghzTnv2ikDgceS8EZVC1ny7wZbWPNQfL a39RsMawCSII1rva8SxIuteF7+fVt0legs2If3a4aXNFx70h X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB SME adds a second vector length configured in a very similar way to the SVE vector length, in order to facilitate future code sharing for SME refactor our storage of vector lengths to use an array like the host does. We do not yet take much advantage of this so the intermediate code is not as clean as might be. No functional change. Signed-off-by: Mark Brown --- arch/arm64/include/asm/kvm_host.h | 11 ++++++----- arch/arm64/include/asm/kvm_hyp.h | 2 +- arch/arm64/include/asm/kvm_pkvm.h | 2 +- arch/arm64/kvm/guest.c | 6 +++--- arch/arm64/kvm/hyp/include/hyp/switch.h | 4 ++-- arch/arm64/kvm/hyp/nvhe/hyp-main.c | 4 ++-- arch/arm64/kvm/hyp/nvhe/pkvm.c | 7 ++++--- arch/arm64/kvm/reset.c | 22 +++++++++++----------- 8 files changed, 30 insertions(+), 28 deletions(-) diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm= _host.h index 8e185e43fbff..5e071381ae5b 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -77,8 +77,9 @@ enum kvm_mode kvm_get_mode(void); static inline enum kvm_mode kvm_get_mode(void) { return KVM_MODE_NONE; }; #endif =20 -extern unsigned int __ro_after_init kvm_sve_max_vl; -extern unsigned int __ro_after_init kvm_host_sve_max_vl; +extern unsigned int __ro_after_init kvm_max_vl[ARM64_VEC_MAX]; +extern unsigned int __ro_after_init kvm_host_max_vl[ARM64_VEC_MAX]; + int __init kvm_arm_init_sve(void); =20 u32 __attribute_const__ kvm_target_cpu(void); @@ -857,7 +858,7 @@ struct kvm_vcpu_arch { */ struct arm64_sve_state *sve_state; enum fp_type fp_type; - unsigned int sve_max_vl; + unsigned int max_vl[ARM64_VEC_MAX]; =20 /* Stage 2 paging state used by the hardware on next switch */ struct kvm_s2_mmu *hw_mmu; @@ -1100,7 +1101,7 @@ struct kvm_vcpu_arch { /* KVM is currently emulating an L2 to L1 exception */ #define IN_NESTED_EXCEPTION __vcpu_single_flag(sflags, BIT(9)) =20 -#define vcpu_sve_max_vq(vcpu) sve_vq_from_vl((vcpu)->arch.sve_max_vl) +#define vcpu_sve_max_vq(vcpu) sve_vq_from_vl((vcpu)->arch.max_vl[ARM64_VEC= _SVE]) =20 #define vcpu_sve_zcr_elx(vcpu) \ (unlikely(is_hyp_ctxt(vcpu)) ? ZCR_EL2 : ZCR_EL1) @@ -1119,7 +1120,7 @@ struct kvm_vcpu_arch { __size_ret; \ }) =20 -#define vcpu_sve_state_size(vcpu) sve_state_size_from_vl((vcpu)->arch.sve_= max_vl) +#define vcpu_sve_state_size(vcpu) sve_state_size_from_vl((vcpu)->arch.max_= vl[ARM64_VEC_SVE]) =20 #define KVM_GUESTDBG_VALID_MASK (KVM_GUESTDBG_ENABLE | \ KVM_GUESTDBG_USE_SW_BP | \ diff --git a/arch/arm64/include/asm/kvm_hyp.h b/arch/arm64/include/asm/kvm_= hyp.h index 4974492744cc..3d05533a0f67 100644 --- a/arch/arm64/include/asm/kvm_hyp.h +++ b/arch/arm64/include/asm/kvm_hyp.h @@ -150,7 +150,7 @@ extern u64 kvm_nvhe_sym(id_aa64smfr0_el1_sys_val); =20 extern unsigned long kvm_nvhe_sym(__icache_flags); extern unsigned int kvm_nvhe_sym(kvm_arm_vmid_bits); -extern unsigned int kvm_nvhe_sym(kvm_host_sve_max_vl); +extern unsigned int kvm_nvhe_sym(kvm_host_max_vl[ARM64_VEC_MAX]); extern unsigned long kvm_nvhe_sym(hyp_nr_cpus); extern unsigned int kvm_nvhe_sym(hyp_gicv3_nr_lr); =20 diff --git a/arch/arm64/include/asm/kvm_pkvm.h b/arch/arm64/include/asm/kvm= _pkvm.h index 74fedd9c5ff0..d4d22acf2fe7 100644 --- a/arch/arm64/include/asm/kvm_pkvm.h +++ b/arch/arm64/include/asm/kvm_pkvm.h @@ -188,7 +188,7 @@ static inline size_t pkvm_host_sve_state_size(void) if (!system_supports_sve()) return 0; =20 - return SVE_SIG_REGS_SIZE(sve_vq_from_vl(kvm_host_sve_max_vl)); + return SVE_SIG_REGS_SIZE(sve_vq_from_vl(kvm_host_max_vl[ARM64_VEC_SVE])); } =20 struct pkvm_mapping { diff --git a/arch/arm64/kvm/guest.c b/arch/arm64/kvm/guest.c index 3ae751e72c95..2370bb0ad94e 100644 --- a/arch/arm64/kvm/guest.c +++ b/arch/arm64/kvm/guest.c @@ -318,7 +318,7 @@ static int get_sve_vls(struct kvm_vcpu *vcpu, const str= uct kvm_one_reg *reg) if (!vcpu_has_sve(vcpu)) return -ENOENT; =20 - if (WARN_ON(!sve_vl_valid(vcpu->arch.sve_max_vl))) + if (WARN_ON(!sve_vl_valid(vcpu->arch.max_vl[ARM64_VEC_SVE]))) return -EINVAL; =20 memset(vqs, 0, sizeof(vqs)); @@ -356,7 +356,7 @@ static int set_sve_vls(struct kvm_vcpu *vcpu, const str= uct kvm_one_reg *reg) if (vq_present(vqs, vq)) max_vq =3D vq; =20 - if (max_vq > sve_vq_from_vl(kvm_sve_max_vl)) + if (max_vq > sve_vq_from_vl(kvm_max_vl[ARM64_VEC_SVE])) return -EINVAL; =20 /* @@ -375,7 +375,7 @@ static int set_sve_vls(struct kvm_vcpu *vcpu, const str= uct kvm_one_reg *reg) return -EINVAL; =20 /* vcpu->arch.sve_state will be alloc'd by kvm_vcpu_finalize_vec() */ - vcpu->arch.sve_max_vl =3D sve_vl_from_vq(max_vq); + vcpu->arch.max_vl[ARM64_VEC_SVE] =3D sve_vl_from_vq(max_vq); =20 return 0; } diff --git a/arch/arm64/kvm/hyp/include/hyp/switch.h b/arch/arm64/kvm/hyp/i= nclude/hyp/switch.h index 18131e395e24..33729e218c0a 100644 --- a/arch/arm64/kvm/hyp/include/hyp/switch.h +++ b/arch/arm64/kvm/hyp/include/hyp/switch.h @@ -493,7 +493,7 @@ static inline void __hyp_sve_save_host(void) struct arm64_sve_state *sve_regs =3D *host_data_ptr(sve_regs); =20 ctxt_sys_reg(hctxt, ZCR_EL1) =3D read_sysreg_el1(SYS_ZCR); - write_sysreg_s(sve_vq_from_vl(kvm_host_sve_max_vl) - 1, SYS_ZCR_EL2); + write_sysreg_s(sve_vq_from_vl(kvm_host_max_vl[ARM64_VEC_SVE]) - 1, SYS_ZC= R_EL2); sve_save_state(sve_regs, true); fpsimd_save_common(&hctxt->fp_regs); } @@ -548,7 +548,7 @@ static inline void fpsimd_lazy_switch_to_host(struct kv= m_vcpu *vcpu) zcr_el2 =3D vcpu_sve_max_vq(vcpu) - 1; write_sysreg_el2(zcr_el2, SYS_ZCR); } else { - zcr_el2 =3D sve_vq_from_vl(kvm_host_sve_max_vl) - 1; + zcr_el2 =3D sve_vq_from_vl(kvm_host_max_vl[ARM64_VEC_SVE]) - 1; write_sysreg_el2(zcr_el2, SYS_ZCR); =20 zcr_el1 =3D vcpu_sve_max_vq(vcpu) - 1; diff --git a/arch/arm64/kvm/hyp/nvhe/hyp-main.c b/arch/arm64/kvm/hyp/nvhe/h= yp-main.c index d3c69de698f4..14e24e257dcc 100644 --- a/arch/arm64/kvm/hyp/nvhe/hyp-main.c +++ b/arch/arm64/kvm/hyp/nvhe/hyp-main.c @@ -40,7 +40,7 @@ static void __hyp_sve_save_guest(struct kvm_vcpu *vcpu) sve_cond_update_zcr_vq(vcpu_sve_max_vq(vcpu) - 1, SYS_ZCR_EL2); sve_save_state(kern_hyp_va(vcpu->arch.sve_state), true); fpsimd_save_common(&vcpu->arch.ctxt.fp_regs); - write_sysreg_s(sve_vq_from_vl(kvm_host_sve_max_vl) - 1, SYS_ZCR_EL2); + write_sysreg_s(sve_vq_from_vl(kvm_host_max_vl[ARM64_VEC_SVE]) - 1, SYS_ZC= R_EL2); } =20 static void __hyp_sve_restore_host(void) @@ -57,7 +57,7 @@ static void __hyp_sve_restore_host(void) * that was discovered, if we wish to use larger VLs this will * need to be revisited. */ - write_sysreg_s(sve_vq_from_vl(kvm_host_sve_max_vl) - 1, SYS_ZCR_EL2); + write_sysreg_s(sve_vq_from_vl(kvm_host_max_vl[ARM64_VEC_SVE]) - 1, SYS_ZC= R_EL2); sve_load_state(sve_regs, true); fpsimd_load_common(&hctxt->fp_regs); write_sysreg_el1(ctxt_sys_reg(hctxt, ZCR_EL1), SYS_ZCR); diff --git a/arch/arm64/kvm/hyp/nvhe/pkvm.c b/arch/arm64/kvm/hyp/nvhe/pkvm.c index 9d7f632f01f8..d49f7f327adf 100644 --- a/arch/arm64/kvm/hyp/nvhe/pkvm.c +++ b/arch/arm64/kvm/hyp/nvhe/pkvm.c @@ -22,7 +22,7 @@ unsigned long __icache_flags; /* Used by kvm_get_vttbr(). */ unsigned int kvm_arm_vmid_bits; =20 -unsigned int kvm_host_sve_max_vl; +unsigned int kvm_host_max_vl[ARM64_VEC_MAX]; =20 /* * The currently loaded hyp vCPU for each physical CPU. Used in protected = mode @@ -459,7 +459,8 @@ static int pkvm_vcpu_init_sve(struct pkvm_hyp_vcpu *hyp= _vcpu, struct kvm_vcpu *h } =20 /* Limit guest vector length to the maximum supported by the host. */ - sve_max_vl =3D min(READ_ONCE(host_vcpu->arch.sve_max_vl), kvm_host_sve_ma= x_vl); + sve_max_vl =3D min(READ_ONCE(host_vcpu->arch.max_vl[ARM64_VEC_SVE]), + kvm_host_max_vl[ARM64_VEC_SVE]); sve_state_size =3D sve_state_size_from_vl(sve_max_vl); sve_state =3D kern_hyp_va(READ_ONCE(host_vcpu->arch.sve_state)); =20 @@ -473,7 +474,7 @@ static int pkvm_vcpu_init_sve(struct pkvm_hyp_vcpu *hyp= _vcpu, struct kvm_vcpu *h goto err; =20 vcpu->arch.sve_state =3D sve_state; - vcpu->arch.sve_max_vl =3D sve_max_vl; + vcpu->arch.max_vl[ARM64_VEC_SVE] =3D sve_max_vl; =20 return 0; err: diff --git a/arch/arm64/kvm/reset.c b/arch/arm64/kvm/reset.c index 0fae62a9eaef..fee01c38fa13 100644 --- a/arch/arm64/kvm/reset.c +++ b/arch/arm64/kvm/reset.c @@ -32,7 +32,7 @@ =20 /* Maximum phys_shift supported for any VM on this host */ static u32 __ro_after_init kvm_ipa_limit; -unsigned int __ro_after_init kvm_host_sve_max_vl; +unsigned int __ro_after_init kvm_host_max_vl[ARM64_VEC_MAX]; =20 /* * ARMv8 Reset Values @@ -46,14 +46,14 @@ unsigned int __ro_after_init kvm_host_sve_max_vl; #define VCPU_RESET_PSTATE_SVC (PSR_AA32_MODE_SVC | PSR_AA32_A_BIT | \ PSR_AA32_I_BIT | PSR_AA32_F_BIT) =20 -unsigned int __ro_after_init kvm_sve_max_vl; +unsigned int __ro_after_init kvm_max_vl[ARM64_VEC_MAX]; =20 int __init kvm_arm_init_sve(void) { if (system_supports_sve()) { - kvm_sve_max_vl =3D sve_max_virtualisable_vl(); - kvm_host_sve_max_vl =3D sve_max_vl(); - kvm_nvhe_sym(kvm_host_sve_max_vl) =3D kvm_host_sve_max_vl; + kvm_max_vl[ARM64_VEC_SVE] =3D sve_max_virtualisable_vl(); + kvm_host_max_vl[ARM64_VEC_SVE] =3D sve_max_vl(); + kvm_nvhe_sym(kvm_host_max_vl[ARM64_VEC_SVE]) =3D kvm_host_max_vl[ARM64_V= EC_SVE]; =20 /* * The get_sve_reg()/set_sve_reg() ioctl interface will need @@ -61,16 +61,16 @@ int __init kvm_arm_init_sve(void) * order to support vector lengths greater than * VL_ARCH_MAX: */ - if (WARN_ON(kvm_sve_max_vl > VL_ARCH_MAX)) - kvm_sve_max_vl =3D VL_ARCH_MAX; + if (WARN_ON(kvm_max_vl[ARM64_VEC_SVE] > VL_ARCH_MAX)) + kvm_max_vl[ARM64_VEC_SVE] =3D VL_ARCH_MAX; =20 /* * Don't even try to make use of vector lengths that * aren't available on all CPUs, for now: */ - if (kvm_sve_max_vl < sve_max_vl()) + if (kvm_max_vl[ARM64_VEC_SVE] < sve_max_vl()) pr_warn("KVM: SVE vector length for guests limited to %u bytes\n", - kvm_sve_max_vl); + kvm_max_vl[ARM64_VEC_SVE]); } =20 return 0; @@ -78,7 +78,7 @@ int __init kvm_arm_init_sve(void) =20 static void kvm_vcpu_enable_sve(struct kvm_vcpu *vcpu) { - vcpu->arch.sve_max_vl =3D kvm_sve_max_vl; + vcpu->arch.max_vl[ARM64_VEC_SVE] =3D kvm_max_vl[ARM64_VEC_SVE]; =20 /* * Userspace can still customize the vector lengths by writing @@ -99,7 +99,7 @@ static int kvm_vcpu_finalize_vec(struct kvm_vcpu *vcpu) size_t reg_sz; int ret; =20 - vl =3D vcpu->arch.sve_max_vl; + vl =3D vcpu->arch.max_vl[ARM64_VEC_SVE]; =20 /* * Responsibility for these properties is shared between --=20 2.47.3 From nobody Fri Jul 10 06:02:12 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2A22E441610; Thu, 9 Jul 2026 18:41:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783622462; cv=none; b=sR6KzHKYIgrDHohIiCDQqhMJhEcJjiUkP8XMTNAp8rB6/rOC2m4u5PAe1aQ5cNF2RAVUbEFKE3Zh0zC4zcpx3nlA3t+OtKGTdXEGBFOxKvmFXUilDJ8z57dvOpbcecqpRVqY0yWAvjSAa2DmORDMU9RAzpzpTyYa7BuqcxwcBUM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783622462; c=relaxed/simple; bh=zkAz4EpB+oD/CW01W7HnqzjEzUv3OlXONmLnbiTh4s0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=uMoqzVM5SUrCvoTtQsGqX6zZFCbLk7x5naP3oSlMhEOMYt2R4+qq8cCAwDt4aTCJMHHa19XBTzibceFAIsurOKS2qDI8eG7uRNwHQ1vqTJwDRyg6xb6wPr08TDLS5HbrPKir+vvdGjGS6SmTBkhthZJ0gGXrJp69FOhV9Nr2rEY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=L5rhxUX+; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="L5rhxUX+" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 97CE41F00A3A; Thu, 9 Jul 2026 18:40:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1783622460; bh=Hf3ZnwbaPwB7JWA6xLw/d7mljky+WZ0YaL8vLXxrCY0=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=L5rhxUX+nsrBajnjExeDBc2fTwO6wA7PYtjLR+rxXbgC4FNRZhXsenOevMrN6N0Yv PYxr4wbp4HghyqX0LCkSJ09OQrLiMVftug4jAbTG56/bV8bxbK0DR76J1ceoJfH9RD bAbNcUV98/JUN+dnEyQ1Rbyzl6T08DJqovnbjFNl8UhAvHyDCsa+eR5lcGsjv9Hbp/ ZklTydpEmNZqDF82uFA6YIHi9RHXt4jpvVHtT3e4aotJ2i3KbEoRAlD6TPx8PHp0Z+ gx/JWOyzryMiLqNieX+vARgfYp2bTHhSdnbgdRLJLxXsvr8RlsPAPPxscsTfQG8o5e XP4GopOyQu7cQ== From: Mark Brown Date: Thu, 09 Jul 2026 19:27:33 +0100 Subject: [PATCH v12 12/29] KVM: arm64: Factor SVE code out of fpsimd_lazy_switch_to_host() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260709-kvm-arm64-sme-v12-12-d0301d79ef58@kernel.org> References: <20260709-kvm-arm64-sme-v12-0-d0301d79ef58@kernel.org> In-Reply-To: <20260709-kvm-arm64-sme-v12-0-d0301d79ef58@kernel.org> To: Marc Zyngier , Joey Gouly , Catalin Marinas , Suzuki K Poulose , Will Deacon , Paolo Bonzini , Jonathan Corbet , Shuah Khan , Oliver Upton Cc: Dave Martin , Fuad Tabba , Mark Rutland , Ben Horgan , Jean-Philippe Brucker , linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Peter Maydell , Eric Auger , Mark Brown X-Mailer: b4 0.16-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=2931; i=broonie@kernel.org; h=from:subject:message-id; bh=zkAz4EpB+oD/CW01W7HnqzjEzUv3OlXONmLnbiTh4s0=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBqT+rzBz3N89BPQyzmP/17vU4/T3AWJcfrSuhZ/ JFYXNl0QY+JATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCak/q8wAKCRAk1otyXVSH 0LLAB/9PDxD2EnCQVkTX9BSFw4Z/rLLypJJ1H37bC7t2tQINmcPe1g+gvX2b31saVOqihuJIuZE d8HnWZ3cwTNGUASY96kURWvxgxQOo1tjSGxBBm+W8VlbbJFScB5K/bUu04HBWcqS9NMsvLz1Nol YfKgsEqeLAHRQt2ZUMNgd2t8kKlrWH01TU5VJlj4l/BFA02+MIsXJZZlUIA8m/j3YQ9PmyTOj67 tsd8/0Tc4yWpeFvO8y+zjExEr+Qc65X1crRItdsT37BxRGSuJtgHtttOyLZc3W+8yRMhYDgHK62 FjAug+GTVapgPtkQzZXNF9rmv3KYdxptrqw4v9Vc2pj2LrIo X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB Since the function will grow as a result of adding SME support move the SVE code out of fpsimd_lazy_switch_to_host(). No functional change, just code motion. Reviewed-by: Jean-Philippe Brucker Signed-off-by: Mark Brown --- arch/arm64/kvm/hyp/include/hyp/switch.h | 48 ++++++++++++++++++-----------= ---- 1 file changed, 27 insertions(+), 21 deletions(-) diff --git a/arch/arm64/kvm/hyp/include/hyp/switch.h b/arch/arm64/kvm/hyp/i= nclude/hyp/switch.h index 33729e218c0a..e444f0a94dcf 100644 --- a/arch/arm64/kvm/hyp/include/hyp/switch.h +++ b/arch/arm64/kvm/hyp/include/hyp/switch.h @@ -519,11 +519,11 @@ static inline void fpsimd_lazy_switch_to_guest(struct= kvm_vcpu *vcpu) } } =20 -static inline void fpsimd_lazy_switch_to_host(struct kvm_vcpu *vcpu) +static inline void sve_lazy_switch_to_host(struct kvm_vcpu *vcpu) { u64 zcr_el1, zcr_el2; =20 - if (!guest_owns_fp_regs()) + if (!vcpu_has_sve(vcpu)) return; =20 /* @@ -534,29 +534,35 @@ static inline void fpsimd_lazy_switch_to_host(struct = kvm_vcpu *vcpu) * synchronization event, we don't need an ISB here to avoid taking * traps for anything that was exposed to the guest. */ - if (vcpu_has_sve(vcpu)) { - zcr_el1 =3D read_sysreg_el1(SYS_ZCR); - __vcpu_assign_sys_reg(vcpu, vcpu_sve_zcr_elx(vcpu), zcr_el1); + zcr_el1 =3D read_sysreg_el1(SYS_ZCR); + __vcpu_assign_sys_reg(vcpu, vcpu_sve_zcr_elx(vcpu), zcr_el1); =20 - /* - * The guest's state is always saved using the guest's max VL. - * Ensure that the host has the guest's max VL active such that - * the host can save the guest's state lazily, but don't - * artificially restrict the host to the guest's max VL. - */ - if (has_vhe()) { - zcr_el2 =3D vcpu_sve_max_vq(vcpu) - 1; - write_sysreg_el2(zcr_el2, SYS_ZCR); - } else { - zcr_el2 =3D sve_vq_from_vl(kvm_host_max_vl[ARM64_VEC_SVE]) - 1; - write_sysreg_el2(zcr_el2, SYS_ZCR); - - zcr_el1 =3D vcpu_sve_max_vq(vcpu) - 1; - write_sysreg_el1(zcr_el1, SYS_ZCR); - } + /* + * The guest's state is always saved using the guest's max VL. + * Ensure that the host has the guest's max VL active such + * that the host can save the guest's state lazily, but don't + * artificially restrict the host to the guest's max VL. + */ + if (has_vhe()) { + zcr_el2 =3D vcpu_sve_max_vq(vcpu) - 1; + write_sysreg_el2(zcr_el2, SYS_ZCR); + } else { + zcr_el2 =3D sve_vq_from_vl(kvm_host_max_vl[ARM64_VEC_SVE]) - 1; + write_sysreg_el2(zcr_el2, SYS_ZCR); + + zcr_el1 =3D vcpu_sve_max_vq(vcpu) - 1; + write_sysreg_el1(zcr_el1, SYS_ZCR); } } =20 +static inline void fpsimd_lazy_switch_to_host(struct kvm_vcpu *vcpu) +{ + if (!guest_owns_fp_regs()) + return; + + sve_lazy_switch_to_host(vcpu); +} + static void kvm_hyp_save_fpsimd_host(struct kvm_vcpu *vcpu) { struct kvm_cpu_context *hctxt =3D host_data_ptr(host_ctxt); --=20 2.47.3 From nobody Fri Jul 10 06:02:12 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A118A441605; Thu, 9 Jul 2026 18:41:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783622467; cv=none; b=sZmOM96fS9u+NQF1J3vTYumwkbbwiaw09ogyohNzxImSmQ3LTml/EfqS+4PUGfOZG8/04L3O+/qGzNdHaU+fa9bCXBmlEcQ8+PrR9CCunJUCq7sYU2YUzI0C4nJNe0IcDTmj5sQSa0ohQs/Hminv2M2fu0kRVgnY5SlCpb1sCvQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783622467; c=relaxed/simple; bh=ehgZkteamEO7lsn/YovoqQS1aFysUSpw5kKyZXzrBKw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=EJ3flK8rLbHm3bXaZrzv8MKodWAgboYUb31GgE0Ukd66RGTKz+VC2UhquIZ/byzMoRpzTP2fYMylgnHT79Azc3nL45+ugoqKgMjU/Tzr1wOxr9U0En5KUtSAfVMnFDIvXcORw0VaXV6N9auIXWfm7klLiq2WiuN6jjRQ6Hb/ZoA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=nD0yT94m; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="nD0yT94m" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 2A8551F000E9; Thu, 9 Jul 2026 18:41:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1783622465; bh=qVJP9IC6O5+JtqSVBZPIwZ7OSRal3lx5jLwdPPRuuXw=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=nD0yT94meAmj9kLxNwC9CqfO3AvwFzBNHJKmRIXbeAR66+FfKKPzI1GfwTOMOFLlC f0tMI08TCW6l4W4eUuQAQiu0jcFCwmb518B4NsEsAkijfAg+DdyRf1hwCD3cM+Cgo9 xialvWbkk8BWTUeCtxiMPg9H+ooQqwbqxU8IR63tcbLwLuaWSMk7nHfHo3RCoIdxjb IMwShNdJ11bMmh5mViCHOxjb8jCQLtU7tU6oI8aRPbdW0UC9PITHSGLmoR6vTsmGaj 4O9rf2ErGsJS5gMuwTgmSnAiT62mKrQmYuEwrLl95E5f1lUMm/RvGazNExBUwNtmcM VGJd7jvoa6Ovg== From: Mark Brown Date: Thu, 09 Jul 2026 19:27:34 +0100 Subject: [PATCH v12 13/29] KVM: arm64: Document the KVM ABI for SME Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260709-kvm-arm64-sme-v12-13-d0301d79ef58@kernel.org> References: <20260709-kvm-arm64-sme-v12-0-d0301d79ef58@kernel.org> In-Reply-To: <20260709-kvm-arm64-sme-v12-0-d0301d79ef58@kernel.org> To: Marc Zyngier , Joey Gouly , Catalin Marinas , Suzuki K Poulose , Will Deacon , Paolo Bonzini , Jonathan Corbet , Shuah Khan , Oliver Upton Cc: Dave Martin , Fuad Tabba , Mark Rutland , Ben Horgan , Jean-Philippe Brucker , linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Peter Maydell , Eric Auger , Mark Brown X-Mailer: b4 0.16-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=12406; i=broonie@kernel.org; h=from:subject:message-id; bh=ehgZkteamEO7lsn/YovoqQS1aFysUSpw5kKyZXzrBKw=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBqT+r0aq1pwuJwDQiXYG3b0+/RffA9zTW8K7yZl kQPi9vUdvOJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCak/q9AAKCRAk1otyXVSH 0GrLB/0UpXHunsCDJ4F950OS1RXp6d4ShOPDBpK7uNGdYEfpr/bkA5yOqByyu5kGZufkXFj0uqk Jogo3ylvff9EPX7eQHUFag1pvGCU6lFQfz00Ebp/dMsBgZ3mO+XwQZl9inSmWzXBqrDVDhMf/B2 0W6boURUJy0FsS6j/csm3GsucgexMMHxhn6uodJ9fpAS2uoeKB3f8bCyK8NuxU+M7gUE2UToFYm QU4lnofAmbI9hrGrmw33MrTtvDFVU8Z52XqTLMsw3Ku58+d+lmJcQlgl/olJmDbTg9YaWM2ChXb C4mt+OBzqwIDxqbWWq8v6SW5BIiJlakuz2NLHu7FPh7yS8Yl X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB SME, the Scalable Matrix Extension, is an arm64 extension which adds support for matrix operations, with core concepts patterned after SVE. SVE introduced some complication in the ABI since it adds new vector floating point registers with runtime configurable size, the size being controlled by a parameter called the vector length (VL). To provide control of this to VMMs we offer two phase configuration of SVE, SVE must first be enabled for the vCPU with KVM_ARM_VCPU_INIT(KVM_ARM_VCPU_SVE), after which vector length may then be configured but the configurably sized floating point registers are inaccessible until finalized with a call to KVM_ARM_VCPU_FINALIZE(KVM_ARM_VCPU_SVE) after which the configurably sized registers can be accessed. SME introduces an additional independent configurable vector length which as well as controlling the size of the new ZA register also provides an alternative view of the configurably sized SVE registers (known as streaming mode) with the guest able to switch between the two modes as it pleases. There is also a fixed sized register ZT0 introduced in SME2. As well as streaming mode the guest may enable and disable ZA and (where SME2 is available) ZT0 dynamically independently of streaming mode. These modes are controlled via the system register SVCR. We handle the configuration of the vector length for SME in a similar manner to SVE, requiring initialization and finalization of the feature with a pseudo register controlling the available SME vector lengths as for SVE. Further, if the guest has both SVE and SME then finalizing one prevents further configuration of the vector length for the other. Where both SVE and SME are configured for the guest we present the SVE registers to userspace as having the maximum vector length of the currently active vector type as configured via SVCR.SM, imposing an ordering requirement on userspace. Userspace access to ZA and (if configured) ZT0 is only available when SVCR.ZA is 1. Reviewed-by: Fuad Tabba Signed-off-by: Mark Brown --- Documentation/virt/kvm/api.rst | 124 +++++++++++++++++++++++++++++--------= ---- 1 file changed, 88 insertions(+), 36 deletions(-) diff --git a/Documentation/virt/kvm/api.rst b/Documentation/virt/kvm/api.rst index a5f9ee92f43e..64f482c9f6a9 100644 --- a/Documentation/virt/kvm/api.rst +++ b/Documentation/virt/kvm/api.rst @@ -406,7 +406,7 @@ Errors: instructions from device memory (arm64) ENOSYS data abort outside memslots with no syndrome info and KVM_CAP_ARM_NISV_TO_USER not enabled (arm64) - EPERM SVE feature set but not finalized (arm64) + EPERM SVE or SME feature set but not finalized (arm64) =3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =20 This ioctl is used to run a guest virtual cpu. While there are no @@ -2607,11 +2607,11 @@ Specifically: =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D= =3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D =20 .. [1] These encodings are not accepted for SVE-enabled vcpus. See - :ref:`KVM_ARM_VCPU_INIT`. + :ref:`KVM_ARM_VCPU_INIT`. They are also not accepted when SME is + enabled without SVE and the vcpu is in streaming mode. =20 The equivalent register content can be accessed via bits [127:0] of - the corresponding SVE Zn registers instead for vcpus that have SVE - enabled (see below). + the corresponding SVE Zn registers in these cases (see below). =20 arm64 CCSIDR registers are demultiplexed by CSSELR value:: =20 @@ -2642,24 +2642,38 @@ arm64 SVE registers have the following bit patterns= :: 0x6050 0000 0015 060 FFR bits[256*slice + 255 : 256*sli= ce] 0x6060 0000 0015 ffff KVM_REG_ARM64_SVE_VLS pseudo-regis= ter =20 -Access to register IDs where 2048 * slice >=3D 128 * max_vq will fail with -ENOENT. max_vq is the vcpu's maximum supported vector length in 128-bit -quadwords: see [2]_ below. +arm64 SME registers have the following bit patterns:: =20 -These registers are only accessible on vcpus for which SVE is enabled. -See KVM_ARM_VCPU_INIT for details. + 0x6080 0000 0017 ZA[n] bits[2048*slice + 2047 : 204= 8*slice] + 0x6060 0000 0017 0600 ZT0 + 0x6060 0000 0017 fffe KVM_REG_ARM64_SME_VLS pseudo-regis= ter =20 -In addition, except for KVM_REG_ARM64_SVE_VLS, these registers are not -accessible until the vcpu's SVE configuration has been finalized -using KVM_ARM_VCPU_FINALIZE(KVM_ARM_VCPU_SVE). See KVM_ARM_VCPU_INIT -and KVM_ARM_VCPU_FINALIZE for more information about this procedure. +Access to Z, P, FFR or ZA register IDs where 2048 * slice >=3D 128 * +max_vq will fail with ENOENT. max_vq is the vcpu's current maximum +supported vector length in 128-bit quadwords: see [2]_ below. =20 -KVM_REG_ARM64_SVE_VLS is a pseudo-register that allows the set of vector -lengths supported by the vcpu to be discovered and configured by -userspace. When transferred to or from user memory via KVM_GET_ONE_REG -or KVM_SET_ONE_REG, the value of this register is of type -__u64[KVM_ARM64_SVE_VLS_WORDS], and encodes the set of vector lengths as -follows:: +Changing the value of SVCR.SM will result in the contents of registers +that are architecturally reset by entering or exiting streaming mode +being reset. When restoring the values of these registers for a VM +with SME support it is important that SVCR.SM be configured first. + +Access to the ZA and ZT0 registers is only available if SVCR.ZA is set +to 1. These registers are only accessible on vcpus for which SME is +enabled. See KVM_ARM_VCPU_INIT for details. + +In addition, except for KVM_REG_ARM64_SVE_VLS and +KVM_REG_ARM64_SME_VLS, these registers are not accessible until the +vcpu's SVE and SME configuration has been finalized using +KVM_ARM_VCPU_FINALIZE(KVM_ARM_VCPU_VEC). See KVM_ARM_VCPU_INIT and +KVM_ARM_VCPU_FINALIZE for more information about this procedure. + +KVM_REG_ARM64_SVE_VLS and KVM_REG_ARM64_SME_VLS are +pseudo-registers that allows the set of vector lengths supported by +the vcpu to be discovered and configured by userspace. When +transferred to or from user memory via KVM_GET_ONE_REG or +KVM_SET_ONE_REG, the value of this register is of type +__u64[KVM_ARM64_SVE_VLS_WORDS], and encodes the set of vector lengths +as follows:: =20 __u64 vector_lengths[KVM_ARM64_SVE_VLS_WORDS]; =20 @@ -2671,19 +2685,25 @@ follows:: /* Vector length vq * 16 bytes not supported */ =20 .. [2] The maximum value vq for which the above condition is true is - max_vq. This is the maximum vector length available to the guest on - this vcpu, and determines which register slices are visible through - this ioctl interface. + max_vq. This is the maximum vector length currently available to + the guest on this vcpu, and determines which register slices are + visible through this ioctl interface. Note that these slices + should not be confused with the architectural "ZA tile slice". + + If SME is supported and SVCR.SM is 1, then the max_vq used for the + Z and P registers is the maximum SME vector length. Otherwise + it is the maximum SVE vector length. =20 (See Documentation/arch/arm64/sve.rst for an explanation of the "vq" nomenclature.) =20 -KVM_REG_ARM64_SVE_VLS is only accessible after KVM_ARM_VCPU_INIT. -KVM_ARM_VCPU_INIT initialises it to the best set of vector lengths that -the host supports. +KVM_REG_ARM64_SVE_VLS and KVM_REG_ARM64_SME_VLS are only accessible +after KVM_ARM_VCPU_INIT. KVM_ARM_VCPU_INIT initialises them to the +best set of vector lengths that the host supports. =20 -Userspace may subsequently modify it if desired until the vcpu's SVE -configuration is finalized using KVM_ARM_VCPU_FINALIZE(KVM_ARM_VCPU_SVE). +Userspace may subsequently modify these registers if desired until the +vcpu's SVE and SME configuration is finalized using +KVM_ARM_VCPU_FINALIZE(KVM_ARM_VCPU_VEC). =20 Apart from simply removing all vector lengths from the host set that exceed some value, support for arbitrarily chosen sets of vector lengths @@ -2691,8 +2711,8 @@ is hardware-dependent and may not be available. Atte= mpting to configure an invalid set of vector lengths via KVM_SET_ONE_REG will fail with EINVAL. =20 -After the vcpu's SVE configuration is finalized, further attempts to -write this register will fail with EPERM. +After the vcpu's SVE or SME configuration is finalized, further +attempts to write these registers will fail with EPERM. =20 arm64 bitmap feature firmware pseudo-registers have the following bit patt= ern:: =20 @@ -3491,6 +3511,7 @@ The initial values are defined as: - General Purpose registers, including PC and SP: set to 0 - FPSIMD/NEON registers: set to 0 - SVE registers: set to 0 + - SME registers: set to 0 - System registers: Reset to their architecturally defined values as for a warm reset to EL1 (resp. SVC) or EL2 (in the case of EL2 being enabled). @@ -3534,7 +3555,7 @@ Possible features: =20 - KVM_ARM_VCPU_SVE: Enables SVE for the CPU (arm64 only). Depends on KVM_CAP_ARM_SVE. - Requires KVM_ARM_VCPU_FINALIZE(KVM_ARM_VCPU_SVE): + Requires KVM_ARM_VCPU_FINALIZE(KVM_ARM_VCPU_VEC): =20 * After KVM_ARM_VCPU_INIT: =20 @@ -3542,7 +3563,7 @@ Possible features: initial value of this pseudo-register indicates the best set of vector lengths possible for a vcpu on this host. =20 - * Before KVM_ARM_VCPU_FINALIZE(KVM_ARM_VCPU_SVE): + * Before KVM_ARM_VCPU_FINALIZE(KVM_ARM_VCPU_VEC): =20 - KVM_RUN and KVM_GET_REG_LIST are not available; =20 @@ -3555,11 +3576,41 @@ Possible features: KVM_SET_ONE_REG, to modify the set of vector lengths available for the vcpu. =20 - * After KVM_ARM_VCPU_FINALIZE(KVM_ARM_VCPU_SVE): + * After KVM_ARM_VCPU_FINALIZE(KVM_ARM_VCPU_VEC): =20 - the KVM_REG_ARM64_SVE_VLS pseudo-register is immutable, and can no longer be written using KVM_SET_ONE_REG. =20 + - KVM_ARM_VCPU_SME: Enables SME for the CPU (arm64 only). + Depends on KVM_CAP_ARM_SME. + Requires KVM_ARM_VCPU_FINALIZE(KVM_ARM_VCPU_VEC): + + * After KVM_ARM_VCPU_INIT: + + - KVM_REG_ARM64_SME_VLS may be read using KVM_GET_ONE_REG: the + initial value of this pseudo-register indicates the best set of + vector lengths possible for a vcpu on this host. + + * Before KVM_ARM_VCPU_FINALIZE(KVM_ARM_VCPU_VEC): + + - KVM_RUN and KVM_GET_REG_LIST are not available; + + - KVM_GET_ONE_REG and KVM_SET_ONE_REG cannot be used to access + the scalable architectural SVE registers + KVM_REG_ARM64_SVE_ZREG(), KVM_REG_ARM64_SVE_PREG() or + KVM_REG_ARM64_SVE_FFR, the matrix register + KVM_REG_ARM64_SME_ZAHREG() or the LUT register + KVM_REG_ARM64_SME_ZTREG(); + + - KVM_REG_ARM64_SME_VLS may optionally be written using + KVM_SET_ONE_REG, to modify the set of vector lengths available + for the vcpu. + + * After KVM_ARM_VCPU_FINALIZE(KVM_ARM_VCPU_VEC): + + - the KVM_REG_ARM64_SME_VLS pseudo-register is immutable, and can + no longer be written using KVM_SET_ONE_REG. + - KVM_ARM_VCPU_HAS_EL2: Enable Nested Virtualisation support, booting the guest from EL2 instead of EL1. Depends on KVM_CAP_ARM_EL2. @@ -5156,11 +5207,12 @@ Errors: =20 Recognised values for feature: =20 - =3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D - arm64 KVM_ARM_VCPU_SVE (requires KVM_CAP_ARM_SVE) - =3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D + =3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + arm64 KVM_ARM_VCPU_VEC (requires KVM_CAP_ARM_SVE or KVM_CAP_ARM_SME) + arm64 KVM_ARM_VCPU_SVE (alias for KVM_ARM_VCPU_VEC) + =3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =20 -Finalizes the configuration of the specified vcpu feature. +Finalizes the configuration of the specified vcpu features. =20 The vcpu must already have been initialised, enabling the affected feature= , by means of a successful :ref:`KVM_ARM_VCPU_INIT ` call wi= th the --=20 2.47.3 From nobody Fri Jul 10 06:02:12 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0CB224446F5; Thu, 9 Jul 2026 18:41:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783622473; cv=none; b=byCFWGtpGJA63KsrUfV0u2NUKwGF+VMzzXiAiP+AfZEvEPCMkk3AdkE4ZJ/Zd3xI6knDHx1bWoWCXQhux9tqX2VGTZMC5I7u+cFrs75i2vI8INsYKKqvPTm7Ce3a/yHA4yfZ+BfYlgr62QHxPknnu5MWnF7hhXStYqZZkCLf+1M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783622473; c=relaxed/simple; bh=ZaSkLrGVVhyGTgWWCPCFYM3SkrZ1IhJvGyclXLH2+Gk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ToEfIHnGOCnJ+YYwSSjnmX2XzcRDq4pRyQJ7nM8UrHZzodKHZ7q0bSosh0dDEXfiOFSd7C/pGQYHrgiimP2XgqjZs43lq59hpzZTurQsDfjoRDD0J7kZmr94xWl0LxXw47QIeHAfODYVBoHMmegp1quCR6dbb5/a/JKlyOb1Cpg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=muKt2TjL; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="muKt2TjL" Received: by smtp.kernel.org (Postfix) with ESMTPSA id AFFAC1F00A3D; Thu, 9 Jul 2026 18:41:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1783622469; bh=lzhFuYQxcZJAxYenXQo/+7l7I2GvDTvsQr8LtVTrZj8=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=muKt2TjL5F7NLrf5fE+Byxp4o4H5Y4QVgD5wAqCuGyPkfJI25zPD3PWemp750dcAG D9sCDwiqupXpabwhmA8NVP21NeZfPRLRYYGD1QKLVSMXtKSB94OfrlPG5mbUmiCdJx YC69hNQWlw5sNQHLjw6Z8JA1WS4jnsM2JETCD7VYl8hwY0edugflRQChatD3RlCJGY b8hgDPWlYgLLuWx+iYP0cONX0Y+lGACZ4eTS7ka52niGt0jvEtgbtH6onXuPwQt2EC GLJbwBN3Jth9h2VwpdFRrIJpQ/BlmA45nCUpfe6UaWhppKj6nDcM9+DyMJxI0/80dY CLzp9grU51WTQ== From: Mark Brown Date: Thu, 09 Jul 2026 19:27:35 +0100 Subject: [PATCH v12 14/29] KVM: arm64: Implement SME vector length configuration Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260709-kvm-arm64-sme-v12-14-d0301d79ef58@kernel.org> References: <20260709-kvm-arm64-sme-v12-0-d0301d79ef58@kernel.org> In-Reply-To: <20260709-kvm-arm64-sme-v12-0-d0301d79ef58@kernel.org> To: Marc Zyngier , Joey Gouly , Catalin Marinas , Suzuki K Poulose , Will Deacon , Paolo Bonzini , Jonathan Corbet , Shuah Khan , Oliver Upton Cc: Dave Martin , Fuad Tabba , Mark Rutland , Ben Horgan , Jean-Philippe Brucker , linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Peter Maydell , Eric Auger , Mark Brown X-Mailer: b4 0.16-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=9943; i=broonie@kernel.org; h=from:subject:message-id; bh=ZaSkLrGVVhyGTgWWCPCFYM3SkrZ1IhJvGyclXLH2+Gk=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBqT+r1A3kP0rV28MJAQYyKg/tnLz9XTE6wQjE5u JrJALX9iO+JATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCak/q9QAKCRAk1otyXVSH 0BWJB/91oDGduFQsOrJF58cW0d/jKRZVGgp/CX+r2QysiBXzh7I4JzKGzZosqY4krmOVxJIo7nn bC80gjkSqG0iWyf8FP3SUZcf1bOIs04j8NXuSCgvCzyuKFVMUvzHq17Htb2xKDK8JBxsVSIxW5p iS5uuj6KIlzb6qwn5USwBMyx/snvOMJtEwT9ahywcL4pOj42b53xu0K1O0zoC7WerEwfCpbvm3p wb2Mlo0RGvi2Szifd0Oml9IqSKHHdz8fOszHv7FJX+0Du6IZaX5g0IM2PkV496lYl6kIxZIRojQ w/G/mDFZBqxOTZSZ/UJFhUU57xL+FnSTZ0z1GVs5Iy0dklno X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB SME implements a vector length which architecturally looks very similar to that for SVE, configured in a very similar manner. This controls the vector length used for the ZA matrix register, and for the SVE vector and predicate registers when in streaming mode. The only substantial difference is that unlike SVE the architecture does not guarantee that any particular vector length will be implemented. Configuration for SME vector lengths is done using a virtual register as for SVE, hook up the implementation for the virtual register. Since we do not yet have support for any of the new SME registers stub register access functions are provided that only allow VL configuration. These will be extended as the SME specific registers, as for SVE. Since vq_available() is currently only defined for CONFIG_SVE add a stub for builds where that is disabled. Signed-off-by: Mark Brown --- arch/arm64/include/asm/fpsimd.h | 1 + arch/arm64/include/asm/kvm_host.h | 19 +++++++++- arch/arm64/include/uapi/asm/kvm.h | 7 ++++ arch/arm64/kvm/guest.c | 80 +++++++++++++++++++++++++++++++----= ---- 4 files changed, 89 insertions(+), 18 deletions(-) diff --git a/arch/arm64/include/asm/fpsimd.h b/arch/arm64/include/asm/fpsim= d.h index 0a3299142683..c3da16fdb158 100644 --- a/arch/arm64/include/asm/fpsimd.h +++ b/arch/arm64/include/asm/fpsimd.h @@ -542,6 +542,7 @@ static inline int sve_max_vl(void) return -EINVAL; } =20 +static inline bool vq_available(enum vec_type type, unsigned int vq) { ret= urn false; } static inline bool sve_vq_available(unsigned int vq) { return false; } =20 static inline void sve_user_disable(void) { BUILD_BUG(); } diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm= _host.h index 5e071381ae5b..858341eb1e8f 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -855,8 +855,15 @@ struct kvm_vcpu_arch { * low 128 bits of the SVE Z registers. When the core * floating point code saves the register state of a task it * records which view it saved in fp_type. + * + * If SME support is also present then it provides an + * alternative view of the SVE registers accessed as for the Z + * registers when PSTATE.SM is 1, plus an additional set of + * SME specific state in the matrix register ZA and LUT + * register ZT0. */ struct arm64_sve_state *sve_state; + struct arm64_sme_state *sme_state; enum fp_type fp_type; unsigned int max_vl[ARM64_VEC_MAX]; =20 @@ -1101,7 +1108,15 @@ struct kvm_vcpu_arch { /* KVM is currently emulating an L2 to L1 exception */ #define IN_NESTED_EXCEPTION __vcpu_single_flag(sflags, BIT(9)) =20 -#define vcpu_sve_max_vq(vcpu) sve_vq_from_vl((vcpu)->arch.max_vl[ARM64_VEC= _SVE]) +#define vcpu_vec_max_vq(vcpu, type) sve_vq_from_vl((vcpu)->arch.max_vl[typ= e]) + +#define vcpu_sve_max_vq(vcpu) vcpu_vec_max_vq(vcpu, ARM64_VEC_SVE) +#define vcpu_sme_max_vq(vcpu) vcpu_vec_max_vq(vcpu, ARM64_VEC_SME) + +#define vcpu_sve_max_vl(vcpu) ((vcpu)->arch.max_vl[ARM64_VEC_SVE]) +#define vcpu_sme_max_vl(vcpu) ((vcpu)->arch.max_vl[ARM64_VEC_SME]) + +#define vcpu_max_vl(vcpu) max(vcpu_sve_max_vl(vcpu), vcpu_sme_max_vl(vcpu)) =20 #define vcpu_sve_zcr_elx(vcpu) \ (unlikely(is_hyp_ctxt(vcpu)) ? ZCR_EL2 : ZCR_EL1) @@ -1120,7 +1135,7 @@ struct kvm_vcpu_arch { __size_ret; \ }) =20 -#define vcpu_sve_state_size(vcpu) sve_state_size_from_vl((vcpu)->arch.max_= vl[ARM64_VEC_SVE]) +#define vcpu_sve_state_size(vcpu) sve_state_size_from_vl(vcpu_sve_max_vl(v= cpu)) =20 #define KVM_GUESTDBG_VALID_MASK (KVM_GUESTDBG_ENABLE | \ KVM_GUESTDBG_USE_SW_BP | \ diff --git a/arch/arm64/include/uapi/asm/kvm.h b/arch/arm64/include/uapi/as= m/kvm.h index 83af99ca4e1b..15d53300914b 100644 --- a/arch/arm64/include/uapi/asm/kvm.h +++ b/arch/arm64/include/uapi/asm/kvm.h @@ -354,6 +354,13 @@ struct kvm_arm_counter_offset { #define KVM_ARM64_SVE_VLS_WORDS \ ((KVM_ARM64_SVE_VQ_MAX - KVM_ARM64_SVE_VQ_MIN) / 64 + 1) =20 +/* SME registers */ +#define KVM_REG_ARM64_SME (0x17 << KVM_REG_ARM_COPROC_SHIFT) + +/* Vector lengths pseudo-register: */ +#define KVM_REG_ARM64_SME_VLS (KVM_REG_ARM64 | KVM_REG_ARM64_SME | \ + KVM_REG_SIZE_U512 | 0xfffe) + /* Bitmap feature firmware registers */ #define KVM_REG_ARM_FW_FEAT_BMAP (0x0016 << KVM_REG_ARM_COPROC_SHIFT) #define KVM_REG_ARM_FW_FEAT_BMAP_REG(r) (KVM_REG_ARM64 | KVM_REG_SIZE_U64= | \ diff --git a/arch/arm64/kvm/guest.c b/arch/arm64/kvm/guest.c index 2370bb0ad94e..48e6b500f531 100644 --- a/arch/arm64/kvm/guest.c +++ b/arch/arm64/kvm/guest.c @@ -310,22 +310,20 @@ static int set_core_reg(struct kvm_vcpu *vcpu, const = struct kvm_one_reg *reg) #define vq_mask(vq) ((u64)1 << ((vq) - SVE_VQ_MIN) % 64) #define vq_present(vqs, vq) (!!((vqs)[vq_word(vq)] & vq_mask(vq))) =20 -static int get_sve_vls(struct kvm_vcpu *vcpu, const struct kvm_one_reg *re= g) +static int get_vec_vls(enum vec_type vec_type, struct kvm_vcpu *vcpu, + const struct kvm_one_reg *reg) { unsigned int max_vq, vq; u64 vqs[KVM_ARM64_SVE_VLS_WORDS]; =20 - if (!vcpu_has_sve(vcpu)) - return -ENOENT; - - if (WARN_ON(!sve_vl_valid(vcpu->arch.max_vl[ARM64_VEC_SVE]))) + if (WARN_ON(!sve_vl_valid(vcpu->arch.max_vl[vec_type]))) return -EINVAL; =20 memset(vqs, 0, sizeof(vqs)); =20 - max_vq =3D vcpu_sve_max_vq(vcpu); + max_vq =3D vcpu_vec_max_vq(vcpu, vec_type); for (vq =3D SVE_VQ_MIN; vq <=3D max_vq; ++vq) - if (sve_vq_available(vq)) + if (vq_available(vec_type, vq)) vqs[vq_word(vq)] |=3D vq_mask(vq); =20 if (copy_to_user((void __user *)reg->addr, vqs, sizeof(vqs))) @@ -334,18 +332,16 @@ static int get_sve_vls(struct kvm_vcpu *vcpu, const s= truct kvm_one_reg *reg) return 0; } =20 -static int set_sve_vls(struct kvm_vcpu *vcpu, const struct kvm_one_reg *re= g) +static int set_vec_vls(enum vec_type vec_type, struct kvm_vcpu *vcpu, + const struct kvm_one_reg *reg) { unsigned int max_vq, vq; u64 vqs[KVM_ARM64_SVE_VLS_WORDS]; =20 - if (!vcpu_has_sve(vcpu)) - return -ENOENT; - if (kvm_arm_vcpu_vec_finalized(vcpu)) return -EPERM; /* too late! */ =20 - if (WARN_ON(vcpu->arch.sve_state)) + if (WARN_ON(!sve_vl_valid(vcpu->arch.max_vl[vec_type]))) return -EINVAL; =20 if (copy_from_user(vqs, (const void __user *)reg->addr, sizeof(vqs))) @@ -356,18 +352,18 @@ static int set_sve_vls(struct kvm_vcpu *vcpu, const s= truct kvm_one_reg *reg) if (vq_present(vqs, vq)) max_vq =3D vq; =20 - if (max_vq > sve_vq_from_vl(kvm_max_vl[ARM64_VEC_SVE])) + if (max_vq > sve_vq_from_vl(kvm_max_vl[vec_type])) return -EINVAL; =20 /* * Vector lengths supported by the host can't currently be * hidden from the guest individually: instead we can only set a - * maximum via ZCR_EL2.LEN. So, make sure the available vector + * maximum via xCR_EL2.LEN. So, make sure the available vector * lengths match the set requested exactly up to the requested * maximum: */ for (vq =3D SVE_VQ_MIN; vq <=3D max_vq; ++vq) - if (vq_present(vqs, vq) !=3D sve_vq_available(vq)) + if (vq_present(vqs, vq) !=3D vq_available(vec_type, vq)) return -EINVAL; =20 /* Can't run with no vector lengths at all: */ @@ -375,11 +371,27 @@ static int set_sve_vls(struct kvm_vcpu *vcpu, const s= truct kvm_one_reg *reg) return -EINVAL; =20 /* vcpu->arch.sve_state will be alloc'd by kvm_vcpu_finalize_vec() */ - vcpu->arch.max_vl[ARM64_VEC_SVE] =3D sve_vl_from_vq(max_vq); + vcpu->arch.max_vl[vec_type] =3D sve_vl_from_vq(max_vq); =20 return 0; } =20 +static int get_sve_vls(struct kvm_vcpu *vcpu, const struct kvm_one_reg *re= g) +{ + if (!vcpu_has_sve(vcpu)) + return -ENOENT; + + return get_vec_vls(ARM64_VEC_SVE, vcpu, reg); +} + +static int set_sve_vls(struct kvm_vcpu *vcpu, const struct kvm_one_reg *re= g) +{ + if (!vcpu_has_sve(vcpu)) + return -ENOENT; + + return set_vec_vls(ARM64_VEC_SVE, vcpu, reg); +} + #define SVE_REG_SLICE_SHIFT 0 #define SVE_REG_SLICE_BITS 5 #define SVE_REG_ID_SHIFT (SVE_REG_SLICE_SHIFT + SVE_REG_SLICE_BITS) @@ -533,6 +545,40 @@ static int set_sve_reg(struct kvm_vcpu *vcpu, const st= ruct kvm_one_reg *reg) return 0; } =20 +static int get_sme_vls(struct kvm_vcpu *vcpu, const struct kvm_one_reg *re= g) +{ + if (!vcpu_has_sme(vcpu)) + return -ENOENT; + + return get_vec_vls(ARM64_VEC_SME, vcpu, reg); +} + +static int set_sme_vls(struct kvm_vcpu *vcpu, const struct kvm_one_reg *re= g) +{ + if (!vcpu_has_sme(vcpu)) + return -ENOENT; + + return set_vec_vls(ARM64_VEC_SME, vcpu, reg); +} + +static int get_sme_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *re= g) +{ + /* Handle the KVM_REG_ARM64_SME_VLS pseudo-reg as a special case: */ + if (reg->id =3D=3D KVM_REG_ARM64_SME_VLS) + return get_sme_vls(vcpu, reg); + + return -EINVAL; +} + +static int set_sme_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *re= g) +{ + /* Handle the KVM_REG_ARM64_SME_VLS pseudo-reg as a special case: */ + if (reg->id =3D=3D KVM_REG_ARM64_SME_VLS) + return set_sme_vls(vcpu, reg); + + return -EINVAL; +} + int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *r= egs) { return -EINVAL; @@ -711,6 +757,7 @@ int kvm_arm_get_reg(struct kvm_vcpu *vcpu, const struct= kvm_one_reg *reg) case KVM_REG_ARM_FW_FEAT_BMAP: return kvm_arm_get_fw_reg(vcpu, reg); case KVM_REG_ARM64_SVE: return get_sve_reg(vcpu, reg); + case KVM_REG_ARM64_SME: return get_sme_reg(vcpu, reg); } =20 return kvm_arm_sys_reg_get_reg(vcpu, reg); @@ -728,6 +775,7 @@ int kvm_arm_set_reg(struct kvm_vcpu *vcpu, const struct= kvm_one_reg *reg) case KVM_REG_ARM_FW_FEAT_BMAP: return kvm_arm_set_fw_reg(vcpu, reg); case KVM_REG_ARM64_SVE: return set_sve_reg(vcpu, reg); + case KVM_REG_ARM64_SME: return set_sme_reg(vcpu, reg); } =20 return kvm_arm_sys_reg_set_reg(vcpu, reg); --=20 2.47.3 From nobody Fri Jul 10 06:02:12 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AF344444715; Thu, 9 Jul 2026 18:41:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783622476; cv=none; b=R9yZqAN+Wn2QZ11y2bdfASl9N/Mkl67SO+7uCvIfJKi1vs7g3PUnWODF/HBDGr+yTa5AptPCapbEWomFF8kuqEY+eE/hbp93Hne5BowCPIXQIWgMUrxlHDqTMB/ppSS77Mc5+svUzQa6yat1xA1V/6+XLu6k6kIGmOLfQKoaCKA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783622476; c=relaxed/simple; bh=H+o/3748vgny3lGilz48bxpWfmNuNNC3E7l3zKXni58=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=V3VDUD/i9uqbNVt59CsJVarApunjCimaYr4De283Kt2CjpRLj5X+gdSZvjLNzCD9M3tcj8mX3cFAg80P5iWNyWPF+C9HcgyIFzKTl1mcSKQwoDnjrbn7LFpPC0CqcR0FVgQXU6OvGpkVBL+x779zN5hwEUrEzepCN0GhZTZslNk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=YUhHySC5; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="YUhHySC5" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 44D181F000E9; Thu, 9 Jul 2026 18:41:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1783622474; bh=J1zy4AKaHiqNQMXG5h+LXU01eSdMuOzbdR0P6vsnTdA=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=YUhHySC5ldJ9PzM+dEsvIupD2s4maZWvpTCWI1UMUQexsLzv5x8TP2rP2CaP9XJCL Qx6Q/HI/MWEkSi4Tq2zaap1HFZcx9pLGQl/T6y/D7h8rOCly72mhF5TRG4HERYnbWP 24Re/R0xAE6qb+bkMSeGzhi5ZmtjqLEzu+/eMeyL6YScbGswcdNrR5EVEq0XXtZfmX S6qKRAW/VmHeKI2JquWu3njRoILzW9v1xzvU72D1rOiVggYpj9jUfgsmP4ynJCsuKk 7jJhCA764xMDrXjMyqEZpmE+iAsFKHX1W9wvlcLUDaUHb8zHejba+BuFDCRLbhjYkp kJoxWtj4eeLsg== From: Mark Brown Date: Thu, 09 Jul 2026 19:27:36 +0100 Subject: [PATCH v12 15/29] KVM: arm64: Support SME control registers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260709-kvm-arm64-sme-v12-15-d0301d79ef58@kernel.org> References: <20260709-kvm-arm64-sme-v12-0-d0301d79ef58@kernel.org> In-Reply-To: <20260709-kvm-arm64-sme-v12-0-d0301d79ef58@kernel.org> To: Marc Zyngier , Joey Gouly , Catalin Marinas , Suzuki K Poulose , Will Deacon , Paolo Bonzini , Jonathan Corbet , Shuah Khan , Oliver Upton Cc: Dave Martin , Fuad Tabba , Mark Rutland , Ben Horgan , Jean-Philippe Brucker , linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Peter Maydell , Eric Auger , Mark Brown X-Mailer: b4 0.16-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=7447; i=broonie@kernel.org; h=from:subject:message-id; bh=H+o/3748vgny3lGilz48bxpWfmNuNNC3E7l3zKXni58=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBqT+r15HXbQAr5sSxD3/cE7n/6Cxgqwt33CFRqy RwZCrlpSN2JATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCak/q9QAKCRAk1otyXVSH 0EVTB/0bMXu3zQH8xEUX43SPjfSfn//HtgI9O+hBCXcrYAsokFH2mf4/raz44k2Pbyu+KJUl/BM 8lNWqaaks6Pz79NxvyjNI4KK4tEsNGs6IYquMAwggmpE4RddUKxqP9az5L74qqSmZVjOwHmMz4e GO/a0eG4bWVTCVLMPHq8zmDqlR4rudyLHzD6RlzErZQAsDXSXGO0Ddv5iddaUfAuEyVjjmxXFxf cFAem8xXKiG8yZllU8i+MNdYdhzBLZjt5v0ViGVCO2GNZNFJ1FslJi3xm/rCVJWhavugVMzKcE/ 0WH29PuGrOi6hC3mZsQ/44xl9cwfRni3H1Qbtnoz8fH/D5MQ X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB SME is configured by the system registers SMCR_EL1 and SMCR_EL2, add definitions and userspace access for them. These control the SME vector length in a manner similar to that for SVE and also have feature enable bits for SME2 and FA64. A subsequent patch will add management of them for guests as part of the general floating point context switch, as is done for the equivalent SVE registers. Signed-off-by: Mark Brown --- arch/arm64/include/asm/kvm_emulate.h | 15 +++++++++++++++ arch/arm64/include/asm/kvm_host.h | 2 ++ arch/arm64/include/asm/vncr_mapping.h | 1 + arch/arm64/kvm/nested.c | 5 +++++ arch/arm64/kvm/sys_regs.c | 31 ++++++++++++++++++++++++++++++- 5 files changed, 53 insertions(+), 1 deletion(-) diff --git a/arch/arm64/include/asm/kvm_emulate.h b/arch/arm64/include/asm/= kvm_emulate.h index 994afbf479fc..b5dc8a4c320a 100644 --- a/arch/arm64/include/asm/kvm_emulate.h +++ b/arch/arm64/include/asm/kvm_emulate.h @@ -90,6 +90,15 @@ static inline void kvm_inject_nested_sve_trap(struct kvm= _vcpu *vcpu) kvm_inject_nested_sync(vcpu, esr); } =20 +static inline void kvm_inject_nested_sme_trap(struct kvm_vcpu *vcpu, + u64 smtc) +{ + u64 esr =3D FIELD_PREP(ESR_ELx_EC_MASK, ESR_ELx_EC_SME) | + ESR_ELx_IL | smtc; + + kvm_inject_nested_sync(vcpu, esr); +} + #if defined(__KVM_VHE_HYPERVISOR__) || defined(__KVM_NVHE_HYPERVISOR__) static __always_inline bool vcpu_el1_is_32bit(struct kvm_vcpu *vcpu) { @@ -689,4 +698,10 @@ static inline void vcpu_set_hcrx(struct kvm_vcpu *vcpu) vcpu->arch.hcrx_el2 |=3D HCRX_EL2_EnASR; } } + +static inline bool guest_hyp_sme_traps_enabled(const struct kvm_vcpu *vcpu) +{ + return __guest_hyp_cptr_xen_trap_enabled(vcpu, SMEN); +} + #endif /* __ARM64_KVM_EMULATE_H__ */ diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm= _host.h index 858341eb1e8f..796b6e3a50f7 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -546,6 +546,7 @@ enum vcpu_sysreg { MDCR_EL2, /* Monitor Debug Configuration Register (EL2) */ CNTHCTL_EL2, /* Counter-timer Hypervisor Control register */ ZCR_EL2, /* SVE Control Register (EL2) */ + SMCR_EL2, /* SME Control Register (EL2) */ =20 /* Any VNCR-capable reg goes after this point */ MARKER(__VNCR_START__), @@ -554,6 +555,7 @@ enum vcpu_sysreg { VNCR(ACTLR_EL1),/* Auxiliary Control Register */ VNCR(CPACR_EL1),/* Coprocessor Access Control */ VNCR(ZCR_EL1), /* SVE Control */ + VNCR(SMCR_EL1), /* SME Control */ VNCR(TTBR0_EL1),/* Translation Table Base Register 0 */ VNCR(TTBR1_EL1),/* Translation Table Base Register 1 */ VNCR(TCR_EL1), /* Translation Control Register */ diff --git a/arch/arm64/include/asm/vncr_mapping.h b/arch/arm64/include/asm= /vncr_mapping.h index 14366d35ce82..c3bf92ac52d4 100644 --- a/arch/arm64/include/asm/vncr_mapping.h +++ b/arch/arm64/include/asm/vncr_mapping.h @@ -44,6 +44,7 @@ #define VNCR_HDFGWTR_EL2 0x1D8 #define VNCR_ZCR_EL1 0x1E0 #define VNCR_HAFGRTR_EL2 0x1E8 +#define VNCR_SMCR_EL1 0x1F0 #define VNCR_TTBR0_EL1 0x200 #define VNCR_TTBR1_EL1 0x210 #define VNCR_FAR_EL1 0x220 diff --git a/arch/arm64/kvm/nested.c b/arch/arm64/kvm/nested.c index fb54f6dad995..50e25ab9b604 100644 --- a/arch/arm64/kvm/nested.c +++ b/arch/arm64/kvm/nested.c @@ -1920,6 +1920,11 @@ int kvm_init_nv_sysregs(struct kvm_vcpu *vcpu) resx.res1 =3D ZCR_ELx_RES1; set_sysreg_masks(kvm, ZCR_EL2, resx); =20 + /* SMCR_EL2 - bits 8:4 are RAZ/WI so treat them as RES0 */ + resx.res0 =3D SMCR_ELx_RES0 | GENMASK_ULL(8, 4); + resx.res1 =3D SMCR_ELx_RES1; + set_sysreg_masks(kvm, SMCR_EL2, resx); + out: for (enum vcpu_sysreg sr =3D __SANITISED_REG_START__; sr < NR_SYS_REGS; s= r++) __vcpu_rmw_sys_reg(vcpu, sr, |=3D, 0); diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index ba8a3ed8f5ff..24bbe30c075a 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -121,6 +121,7 @@ static enum sr_loc_attr locate_direct_register(const st= ruct kvm_vcpu *vcpu, case ELR_EL1: case SPSR_EL1: case ZCR_EL1: + case SMCR_EL1: case SCTLR2_EL1: /* * EL1 registers which have an ELx2 mapping are loaded if @@ -241,6 +242,7 @@ static u64 read_sr_from_cpu(enum vcpu_sysreg reg) case ELR_EL1: val =3D read_sysreg_s(SYS_ELR_EL12); break; case SPSR_EL1: val =3D read_sysreg_s(SYS_SPSR_EL12); break; case ZCR_EL1: val =3D read_sysreg_s(SYS_ZCR_EL12); break; + case SMCR_EL1: val =3D read_sysreg_s(SYS_SMCR_EL12); break; case SCTLR2_EL1: val =3D read_sysreg_s(SYS_SCTLR2_EL12); break; case TPIDR_EL0: val =3D read_sysreg_s(SYS_TPIDR_EL0); break; case TPIDRRO_EL0: val =3D read_sysreg_s(SYS_TPIDRRO_EL0); break; @@ -279,6 +281,7 @@ static void write_sr_to_cpu(enum vcpu_sysreg reg, u64 v= al) case ELR_EL1: write_sysreg_s(val, SYS_ELR_EL12); break; case SPSR_EL1: write_sysreg_s(val, SYS_SPSR_EL12); break; case ZCR_EL1: write_sysreg_s(val, SYS_ZCR_EL12); break; + case SMCR_EL1: write_sysreg_s(val, SYS_SMCR_EL12); break; case SCTLR2_EL1: write_sysreg_s(val, SYS_SCTLR2_EL12); break; case TPIDR_EL0: write_sysreg_s(val, SYS_TPIDR_EL0); break; case TPIDRRO_EL0: write_sysreg_s(val, SYS_TPIDRRO_EL0); break; @@ -2830,6 +2833,12 @@ static unsigned int sve_el2_visibility(const struct = kvm_vcpu *vcpu, return __el2_visibility(vcpu, rd, sve_visibility); } =20 +static unsigned int sme_el2_visibility(const struct kvm_vcpu *vcpu, + const struct sys_reg_desc *rd) +{ + return __el2_visibility(vcpu, rd, sme_visibility); +} + static unsigned int vncr_el2_visibility(const struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd) { @@ -2872,6 +2881,23 @@ static bool access_zcr_el2(struct kvm_vcpu *vcpu, return true; } =20 +static bool access_smcr_el2(struct kvm_vcpu *vcpu, + struct sys_reg_params *p, + const struct sys_reg_desc *r) +{ + if (guest_hyp_sme_traps_enabled(vcpu)) { + kvm_inject_nested_sme_trap(vcpu, ESR_ELx_SME_ISS_SMTC_SME_DISABLED); + return false; + } + + if (!p->is_write) + p->regval =3D __vcpu_sys_reg(vcpu, SMCR_EL2); + else + __vcpu_assign_sys_reg(vcpu, SMCR_EL2, p->regval); + + return true; +} + static bool access_gic_vtr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, const struct sys_reg_desc *r) @@ -3386,7 +3412,7 @@ static const struct sys_reg_desc sys_reg_descs[] =3D { { SYS_DESC(SYS_ZCR_EL1), NULL, reset_val, ZCR_EL1, 0, .visibility =3D sve= _visibility }, { SYS_DESC(SYS_TRFCR_EL1), undef_access }, { SYS_DESC(SYS_SMPRI_EL1), undef_access }, - { SYS_DESC(SYS_SMCR_EL1), undef_access }, + { SYS_DESC(SYS_SMCR_EL1), NULL, reset_val, SMCR_EL1, 0, .visibility =3D s= me_visibility }, { SYS_DESC(SYS_TTBR0_EL1), access_vm_reg, reset_unknown, TTBR0_EL1 }, { SYS_DESC(SYS_TTBR1_EL1), access_vm_reg, reset_unknown, TTBR1_EL1 }, { SYS_DESC(SYS_TCR_EL1), access_vm_reg, reset_val, TCR_EL1, 0 }, @@ -3754,6 +3780,9 @@ static const struct sys_reg_desc sys_reg_descs[] =3D { =20 EL2_REG_VNCR(HCRX_EL2, reset_val, 0), =20 + EL2_REG_FILTERED(SMCR_EL2, access_smcr_el2, reset_val, 0, + sme_el2_visibility), + EL2_REG(TTBR0_EL2, access_rw, reset_val, 0), EL2_REG(TTBR1_EL2, access_rw, reset_val, 0), EL2_REG(TCR_EL2, access_rw, reset_val, TCR_EL2_RES1), --=20 2.47.3 From nobody Fri Jul 10 06:02:12 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 12FF543B3C0; Thu, 9 Jul 2026 18:41:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783622480; cv=none; b=lmUjIWzbcUbqmla+0xtRRE4825kz6DNTeFBcVz3nlH8ChNs0D4DqF2PKWozefIy3aS97p0K8bSiPczAT4DpkEDSLbPLA4gqyt0kVjp5syNBg1Na/eBKjjU6hG1GiEDLiyetuZRKZeoDeTG40PBoP1poNIjROedaHOCuLSCvIIz0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783622480; c=relaxed/simple; bh=OLmfKw1OWtsaEUazoIIIWYByRIJqe5QP2QutP6yHROg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=jagIjV/OnmpvybARDjqEjpRnclvLUAmrO+kPm/RKBa5eqEthxU/OIGb/VE6t4Ws/eJFOcYhlqqLuLDq7FVLBCfN7gzdjsegDPARS0ugDVSirVJ8Nb/tnS2C3Ne7HQXtjsreKz80x8jseqWvdQ7r3cHFjDlNyzBN42t4ug6VR+T0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Hb6aJg1W; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Hb6aJg1W" Received: by smtp.kernel.org (Postfix) with ESMTPSA id D07301F00A3E; Thu, 9 Jul 2026 18:41:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1783622479; bh=8QKfeY6MF9dpRy4jWvo6mGVT4QR36ThS7v75EfE7dSs=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=Hb6aJg1Wjqo/SEoWUmFvb+zcUcQnZhXZEFej5E0iomb43yaaxRuf3tAAEjZqnm/0a ZKlfz1IFf8UJske23+xBUmbH/PIR/4QM2Aa0cNnXd2ApBtmpxt4AbRyho2Gug92dgv Ecqs8NqccQl5D7g1G8pfhE3UgbIZiBq62PPdOn35aUwoDjVp6KuEuKD1zNgxhG8YEs QGJRYjRLAoOzpqXXRjbmVbe7jI46Uyxb3D8ecevg5Swtwn+Iq7uB6VAjGTV7A/W5BF BqYK0fB8yduC2HY3V/Uez4bu77RWewBkGLHfGuIsXOdjFj+EvLvCqB3WX0JHv4vEMf nQVeTkb/YKK7Q== From: Mark Brown Date: Thu, 09 Jul 2026 19:27:37 +0100 Subject: [PATCH v12 16/29] KVM: arm64: Support TPIDR2_EL0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260709-kvm-arm64-sme-v12-16-d0301d79ef58@kernel.org> References: <20260709-kvm-arm64-sme-v12-0-d0301d79ef58@kernel.org> In-Reply-To: <20260709-kvm-arm64-sme-v12-0-d0301d79ef58@kernel.org> To: Marc Zyngier , Joey Gouly , Catalin Marinas , Suzuki K Poulose , Will Deacon , Paolo Bonzini , Jonathan Corbet , Shuah Khan , Oliver Upton Cc: Dave Martin , Fuad Tabba , Mark Rutland , Ben Horgan , Jean-Philippe Brucker , linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Peter Maydell , Eric Auger , Mark Brown X-Mailer: b4 0.16-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=4705; i=broonie@kernel.org; h=from:subject:message-id; bh=OLmfKw1OWtsaEUazoIIIWYByRIJqe5QP2QutP6yHROg=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBqT+r2eWYjFk8bdfaH/Pjp6UDY1wM7lmpXxg5nA xo4v1+XpVuJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCak/q9gAKCRAk1otyXVSH 0EBXB/9hZPH5pwvkWLxxYoLVFduATHzoN308+D/49F+SfOsHgHbM/Elxs8TuotNKs2PYckT7Gqd Y0Qz9UM/InYx+IGM+1hXRML4fiqlUBLjTWZElEXjvSt+dl2IeS1943h46NQXq9C3/jqy2h6wTtK IR7KTmVhqExxUcFrcFaYPjEyV7HMsosEW7fa+KfWWKVf9yCI7D7n6qkxupcTgXHxPqgyXxF6pHD 5zmvbXwmeop2ymCrWSgpJFzwQXDJVwFkL7jJ3sk+pFsevfd4lGoo07t3vBu0f1q1IPACEy0B3I8 UhjNI+f8yvglhms0QJu5ZQ7SwP9JYDF3TUEN8gmewqymbk5z X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB SME adds a new thread ID register, TPIDR2_EL0. This is used in userspace for delayed saving of the ZA state but in terms of the architecture is not really connected to SME other than being part of FEAT_SME. It has an independent fine grained trap and the runtime connection with the rest of SME is purely software defined. Expose the register as a system register if the guest supports SME, context switching it along with the other EL0 TPIDRs. Reviewed-by: Fuad Tabba Signed-off-by: Mark Brown --- arch/arm64/include/asm/kvm_host.h | 1 + arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h | 12 ++++++++++++ arch/arm64/kvm/sys_regs.c | 6 +++++- 3 files changed, 18 insertions(+), 1 deletion(-) diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm= _host.h index 796b6e3a50f7..da7e572822a1 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -460,6 +460,7 @@ enum vcpu_sysreg { CSSELR_EL1, /* Cache Size Selection Register */ TPIDR_EL0, /* Thread ID, User R/W */ TPIDRRO_EL0, /* Thread ID, User R/O */ + TPIDR2_EL0, /* Thread ID, Register 2 */ TPIDR_EL1, /* Thread ID, Privileged */ CNTKCTL_EL1, /* Timer Control Register (EL1) */ PAR_EL1, /* Physical Address Register */ diff --git a/arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h b/arch/arm64/kvm/hy= p/include/hyp/sysreg-sr.h index 5624fd705ae3..0fd4092e4f25 100644 --- a/arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h +++ b/arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h @@ -88,6 +88,14 @@ static inline bool ctxt_has_sctlr2(struct kvm_cpu_contex= t *ctxt) return kvm_has_sctlr2(kern_hyp_va(vcpu->kvm)); } =20 +static inline bool ctxt_has_sme(struct kvm_cpu_context *ctxt) +{ + struct kvm_vcpu *vcpu; + + vcpu =3D ctxt_to_vcpu(ctxt); + return kvm_has_sme(kern_hyp_va(vcpu->kvm)); +} + static inline bool ctxt_is_guest(struct kvm_cpu_context *ctxt) { return host_data_ptr(host_ctxt) !=3D ctxt; @@ -127,6 +135,8 @@ static inline void __sysreg_save_user_state(struct kvm_= cpu_context *ctxt) { ctxt_sys_reg(ctxt, TPIDR_EL0) =3D read_sysreg(tpidr_el0); ctxt_sys_reg(ctxt, TPIDRRO_EL0) =3D read_sysreg(tpidrro_el0); + if (ctxt_has_sme(ctxt)) + ctxt_sys_reg(ctxt, TPIDR2_EL0) =3D read_sysreg_s(SYS_TPIDR2_EL0); } =20 static inline void __sysreg_save_el1_state(struct kvm_cpu_context *ctxt) @@ -204,6 +214,8 @@ static inline void __sysreg_restore_user_state(struct k= vm_cpu_context *ctxt) { write_sysreg(ctxt_sys_reg(ctxt, TPIDR_EL0), tpidr_el0); write_sysreg(ctxt_sys_reg(ctxt, TPIDRRO_EL0), tpidrro_el0); + if (ctxt_has_sme(ctxt)) + write_sysreg_s(ctxt_sys_reg(ctxt, TPIDR2_EL0), SYS_TPIDR2_EL0); } =20 static inline void __sysreg_restore_el1_state(struct kvm_cpu_context *ctxt, diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 24bbe30c075a..8f19caac6008 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -131,6 +131,7 @@ static enum sr_loc_attr locate_direct_register(const st= ruct kvm_vcpu *vcpu, =20 case TPIDR_EL0: case TPIDRRO_EL0: + case TPIDR2_EL0: case TPIDR_EL1: case PAR_EL1: case DACR32_EL2: @@ -246,6 +247,7 @@ static u64 read_sr_from_cpu(enum vcpu_sysreg reg) case SCTLR2_EL1: val =3D read_sysreg_s(SYS_SCTLR2_EL12); break; case TPIDR_EL0: val =3D read_sysreg_s(SYS_TPIDR_EL0); break; case TPIDRRO_EL0: val =3D read_sysreg_s(SYS_TPIDRRO_EL0); break; + case TPIDR2_EL0: val =3D read_sysreg_s(SYS_TPIDR2_EL0); break; case TPIDR_EL1: val =3D read_sysreg_s(SYS_TPIDR_EL1); break; case PAR_EL1: val =3D read_sysreg_par(); break; case DACR32_EL2: val =3D read_sysreg_s(SYS_DACR32_EL2); break; @@ -285,6 +287,7 @@ static void write_sr_to_cpu(enum vcpu_sysreg reg, u64 v= al) case SCTLR2_EL1: write_sysreg_s(val, SYS_SCTLR2_EL12); break; case TPIDR_EL0: write_sysreg_s(val, SYS_TPIDR_EL0); break; case TPIDRRO_EL0: write_sysreg_s(val, SYS_TPIDRRO_EL0); break; + case TPIDR2_EL0: write_sysreg_s(val, SYS_TPIDR2_EL0); break; case TPIDR_EL1: write_sysreg_s(val, SYS_TPIDR_EL1); break; case PAR_EL1: write_sysreg_s(val, SYS_PAR_EL1); break; case DACR32_EL2: write_sysreg_s(val, SYS_DACR32_EL2); break; @@ -3598,7 +3601,8 @@ static const struct sys_reg_desc sys_reg_descs[] =3D { .visibility =3D s1poe_visibility }, { SYS_DESC(SYS_TPIDR_EL0), NULL, reset_unknown, TPIDR_EL0 }, { SYS_DESC(SYS_TPIDRRO_EL0), NULL, reset_unknown, TPIDRRO_EL0 }, - { SYS_DESC(SYS_TPIDR2_EL0), undef_access }, + { SYS_DESC(SYS_TPIDR2_EL0), NULL, reset_unknown, TPIDR2_EL0, + .visibility =3D sme_visibility }, =20 { SYS_DESC(SYS_SCXTNUM_EL0), undef_access }, =20 --=20 2.47.3 From nobody Fri Jul 10 06:02:12 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9A99843B3E7; Thu, 9 Jul 2026 18:41:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783622485; cv=none; b=SqGkqArL+QHMeHwyhuqS2I4sQobzvmaoK6Apa2T0maPyqVYO/nPgicDvZi4ElVS6ZkVaVnEVcN1z2yIB5dg9B+GYl1oH+URYkfGhNhaBWbcpiRyg40Yxis9CyS9eGeOJjOHv9ktbkEVFOUNQw7pC7EuUWk7pe3TUDeUjCaZZIqs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783622485; c=relaxed/simple; bh=birBR4wQDbv7Ccj0Fs97aBFsK/r1maIYM5BCTRl4oyM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=upND2fTc7RcPiQGS7pGss/bXtrQIOTQIz8V66gSL6mxboB4+5rOhRkutIVr1jRUnYeGSSejA0ZHTFgYGrXsCLF5cVhCmgK1lzKa0dFVQpCBLgklH5jk6nnGfhMOSu3itnvvDxIPMgOUI3YDGlsmGp+ZKAnJfSTCbitMEtJ9Rp34= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=GKOx0Wzu; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="GKOx0Wzu" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 63A061F00A3F; Thu, 9 Jul 2026 18:41:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1783622483; bh=J3568gSpivrJn0HnRbt2bCdowItVzvgVATPFHXMn/go=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=GKOx0WzucUJsYO8tE81KCydUBnyv4WBYjTy1bzv9wusfx9FVeY9rElEaHc0bJFqpT Te13e5Afh30fbIHI0LoQeKNSA+pp+vl5zqaHSV9TqjjZeIUq31XlZJ+441OI2RKJKh xHZORthsp0DsuJGRBEujUFSbEK5+2H6p/LF/SvVcdFI79B+e0EIWXzTzqfE2gp/7PU qsA+EezsG+MElYdSldexgqKA10OmqO3/2cK0INfy91C7vDRpXaXoU7UiXM+lq58YQb umTSgroP4ndXwCwH/Idd7uETyQc+AI+/K9i7dkuw7B3oriFF78s89+llFaJpFY0Xqy 0RL5tOCoC7ZSw== From: Mark Brown Date: Thu, 09 Jul 2026 19:27:38 +0100 Subject: [PATCH v12 17/29] KVM: arm64: Support SME identification registers for guests Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260709-kvm-arm64-sme-v12-17-d0301d79ef58@kernel.org> References: <20260709-kvm-arm64-sme-v12-0-d0301d79ef58@kernel.org> In-Reply-To: <20260709-kvm-arm64-sme-v12-0-d0301d79ef58@kernel.org> To: Marc Zyngier , Joey Gouly , Catalin Marinas , Suzuki K Poulose , Will Deacon , Paolo Bonzini , Jonathan Corbet , Shuah Khan , Oliver Upton Cc: Dave Martin , Fuad Tabba , Mark Rutland , Ben Horgan , Jean-Philippe Brucker , linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Peter Maydell , Eric Auger , Mark Brown X-Mailer: b4 0.16-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=8793; i=broonie@kernel.org; h=from:subject:message-id; bh=birBR4wQDbv7Ccj0Fs97aBFsK/r1maIYM5BCTRl4oyM=; b=kA0DAAoBJNaLcl1Uh9AByyZiAGpP6vej0KoDmFc7WrcgrL/BOsPE4eAteO9JmQrEdR1HGfYU1 4kBMwQAAQoAHRYhBK3maKpnVxi1n+Kf6iTWi3JdVIfQBQJqT+r3AAoJECTWi3JdVIfQhyIH/3g5 ACq/9Qr9TZayorQgYaE++8jCzUAhogQ+oHFsgofv/Hss8G8qPmotlpb3JkkIMnIF5Qtd8hl7FX0 JGq9mJPXxeKK8/yuFWikeRjAmdNdtW3L0zfan6JJt4JKJXaepXJfk16Par8Zs02MAwW9pzgzLvV oA05gf70LJL2FNNhp/TybSFsTgtVFw5gFWOo4qnDogBfKI4jjR80YY0yCdvjczIChSkY21b8Z6g +f8jU04iCBcoc48GQMRFOgsMeiKKNScxD4DzlZM7D9hxrtXXqMei+z2XqJQRPxhhMqfXbxyjEud CZ5fm9SUz7it64X1EW/iz838wDfJBlaa+V63Ozw= X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB The primary register for identifying SME is ID_AA64PFR1_EL1.SME. This is hidden from guests unless SME is enabled by the VMM. When it is visible it is writable and can be used to control the availability of SME2. There is also a new register ID_AA64SMFR0_EL1 which we make writable, forcing it to all bits 0 if SME is disabled. This includes the field SMEver giving the SME version, userspace is responsible for ensuring the value is consistent with ID_AA64PFR1_EL1.SME. It also includes FA64, a separately enableable extension which provides the full FPSIMD and SVE instruction set including FFR in streaming mode. Userspace can control the availability of FA64 by writing to this field. The other features enumerated there only add new instructions, there are no architectural controls for these. There is a further identification register SMIDR_EL1 which provides a basic description of the SME microarchitecture, in a manner similar to MIDR_EL1 for the PE. It also describes support for priority management and a basic affinity description for shared SME units, plus some RES0 space. We do not support priority management for guests so this is hidden from guests, along with any fields defined in future. As for MIDR_EL1 and REVIDR_EL1 we expose the implementer and revision information to guests with the raw value from the CPU we are running on, this may present issues for asymmetric systems or for migration as it does for the existing registers. Signed-off-by: Mark Brown --- arch/arm64/include/asm/kvm_host.h | 3 +++ arch/arm64/kvm/config.c | 8 +------ arch/arm64/kvm/hyp/nvhe/pkvm.c | 4 +++- arch/arm64/kvm/sys_regs.c | 46 ++++++++++++++++++++++++++++++++++-= ---- 4 files changed, 47 insertions(+), 14 deletions(-) diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm= _host.h index da7e572822a1..e8c2907aacd2 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -410,6 +410,7 @@ struct kvm_arch { u64 revidr_el1; u64 aidr_el1; u64 ctr_el0; + u64 smidr_el1; =20 /* Masks for VNCR-backed and general EL2 sysregs */ struct kvm_sysreg_masks *sysreg_masks; @@ -1585,6 +1586,8 @@ static inline u64 *__vm_id_reg(struct kvm_arch *ka, u= 32 reg) return &ka->revidr_el1; case SYS_AIDR_EL1: return &ka->aidr_el1; + case SYS_SMIDR_EL1: + return &ka->smidr_el1; default: WARN_ON_ONCE(1); return NULL; diff --git a/arch/arm64/kvm/config.c b/arch/arm64/kvm/config.c index 0622162b089e..cb6f3ea556c2 100644 --- a/arch/arm64/kvm/config.c +++ b/arch/arm64/kvm/config.c @@ -281,14 +281,8 @@ static bool feat_anerr(struct kvm *kvm) =20 static bool feat_sme_smps(struct kvm *kvm) { - /* - * Revisit this if KVM ever supports SME -- this really should - * look at the guest's view of SMIDR_EL1. Funnily enough, this - * is not captured in the JSON file, but only as a note in the - * ARM ARM. - */ return (kvm_has_feat(kvm, FEAT_SME) && - (read_sysreg_s(SYS_SMIDR_EL1) & SMIDR_EL1_SMPS)); + (kvm_read_vm_id_reg(kvm, SYS_SMIDR_EL1) & SMIDR_EL1_SMPS)); } =20 static bool feat_spe_fds(struct kvm *kvm) diff --git a/arch/arm64/kvm/hyp/nvhe/pkvm.c b/arch/arm64/kvm/hyp/nvhe/pkvm.c index d49f7f327adf..620f3395ea4e 100644 --- a/arch/arm64/kvm/hyp/nvhe/pkvm.c +++ b/arch/arm64/kvm/hyp/nvhe/pkvm.c @@ -357,8 +357,10 @@ static void pkvm_init_features_from_host(struct pkvm_h= yp_vm *hyp_vm, const struc host_kvm->arch.vcpu_features, KVM_VCPU_MAX_FEATURES); =20 - if (test_bit(KVM_ARCH_FLAG_WRITABLE_IMP_ID_REGS, &host_arch_flags)) + if (test_bit(KVM_ARCH_FLAG_WRITABLE_IMP_ID_REGS, &host_arch_flags)) { hyp_vm->kvm.arch.midr_el1 =3D host_kvm->arch.midr_el1; + hyp_vm->kvm.arch.smidr_el1 =3D host_kvm->arch.smidr_el1; + } =20 return; } diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 8f19caac6008..91ef82dd6b1a 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1951,6 +1951,7 @@ static inline bool is_vm_ftr_id_reg(u32 id) case SYS_MIDR_EL1: case SYS_REVIDR_EL1: case SYS_AIDR_EL1: + case SYS_SMIDR_EL1: return true; default: return (sys_reg_Op0(id) =3D=3D 3 && sys_reg_Op1(id) =3D=3D 0 && @@ -1979,7 +1980,11 @@ static unsigned int id_visibility(const struct kvm_v= cpu *vcpu, =20 switch (id) { case SYS_ID_AA64ZFR0_EL1: - if (!vcpu_has_sve(vcpu)) + if (!vcpu_has_sve(vcpu) && !vcpu_has_sme(vcpu)) + return REG_RAZ; + break; + case SYS_ID_AA64SMFR0_EL1: + if (!vcpu_has_sme(vcpu)) return REG_RAZ; break; } @@ -2101,7 +2106,9 @@ static u64 sanitise_id_aa64pfr1_el1(const struct kvm_= vcpu *vcpu, u64 val) SYS_FIELD_GET(ID_AA64PFR0_EL1, RAS, pfr0) =3D=3D ID_AA64PFR0_EL1_RA= S_IMP)) val &=3D ~ID_AA64PFR1_EL1_RAS_frac; =20 - val &=3D ~ID_AA64PFR1_EL1_SME; + if (!kvm_has_sme(vcpu->kvm)) + val &=3D ~ID_AA64PFR1_EL1_SME; + val &=3D ~ID_AA64PFR1_EL1_RNDR_trap; val &=3D ~ID_AA64PFR1_EL1_NMI; val &=3D ~ID_AA64PFR1_EL1_GCS; @@ -3119,8 +3126,11 @@ static bool access_imp_id_reg(struct kvm_vcpu *vcpu, return access_id_reg(vcpu, p, r); =20 /* - * Otherwise, fall back to the old behavior of returning the value of - * the current CPU. + * Otherwise, fall back to the old behavior of returning the + * value of the current CPU for REVIDR_EL1 and AIDR_EL1, or + * use whatever the sanitised reset value we have is for other + * registers not exposed prior to writability support for + * these registers. */ switch (reg_to_encoding(r)) { case SYS_REVIDR_EL1: @@ -3129,6 +3139,9 @@ static bool access_imp_id_reg(struct kvm_vcpu *vcpu, case SYS_AIDR_EL1: p->regval =3D read_sysreg(aidr_el1); break; + case SYS_SMIDR_EL1: + p->regval =3D read_id_reg(vcpu, r); + break; default: WARN_ON_ONCE(1); } @@ -3139,12 +3152,15 @@ static bool access_imp_id_reg(struct kvm_vcpu *vcpu, static u64 __ro_after_init boot_cpu_midr_val; static u64 __ro_after_init boot_cpu_revidr_val; static u64 __ro_after_init boot_cpu_aidr_val; +static u64 __ro_after_init boot_cpu_smidr_val; =20 static void init_imp_id_regs(void) { boot_cpu_midr_val =3D read_sysreg(midr_el1); boot_cpu_revidr_val =3D read_sysreg(revidr_el1); boot_cpu_aidr_val =3D read_sysreg(aidr_el1); + if (system_supports_sme()) + boot_cpu_smidr_val =3D read_sysreg_s(SYS_SMIDR_EL1); } =20 static u64 reset_imp_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_de= sc *r) @@ -3156,6 +3172,8 @@ static u64 reset_imp_id_reg(struct kvm_vcpu *vcpu, co= nst struct sys_reg_desc *r) return boot_cpu_revidr_val; case SYS_AIDR_EL1: return boot_cpu_aidr_val; + case SYS_SMIDR_EL1: + return boot_cpu_smidr_val & r->val; default: KVM_BUG_ON(1, vcpu->kvm); return 0; @@ -3204,6 +3222,16 @@ static int set_imp_id_reg(struct kvm_vcpu *vcpu, con= st struct sys_reg_desc *r, .val =3D mask, \ } =20 +#define IMPLEMENTATION_ID_FILTERED(reg, mask, reg_visibility) { \ + SYS_DESC(SYS_##reg), \ + .access =3D access_imp_id_reg, \ + .get_user =3D get_id_reg, \ + .set_user =3D set_imp_id_reg, \ + .reset =3D reset_imp_id_reg, \ + .visibility =3D reg_visibility, \ + .val =3D mask, \ + } + static u64 reset_mdcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) { __vcpu_assign_sys_reg(vcpu, r->reg, vcpu->kvm->arch.nr_pmu_counters); @@ -3320,7 +3348,6 @@ static const struct sys_reg_desc sys_reg_descs[] =3D { ID_AA64PFR1_EL1_MTE_frac | ID_AA64PFR1_EL1_NMI | ID_AA64PFR1_EL1_RNDR_trap | - ID_AA64PFR1_EL1_SME | ID_AA64PFR1_EL1_RES0 | ID_AA64PFR1_EL1_MPAM_frac | ID_AA64PFR1_EL1_MTE)), @@ -3331,7 +3358,7 @@ static const struct sys_reg_desc sys_reg_descs[] =3D { ID_AA64PFR2_EL1_GCIE)), ID_UNALLOCATED(4,3), ID_WRITABLE(ID_AA64ZFR0_EL1, ~ID_AA64ZFR0_EL1_RES0), - ID_HIDDEN(ID_AA64SMFR0_EL1), + ID_WRITABLE(ID_AA64SMFR0_EL1, ~ID_AA64SMFR0_EL1_RES0), ID_UNALLOCATED(4,6), ID_WRITABLE(ID_AA64FPFR0_EL1, ~ID_AA64FPFR0_EL1_RES0), =20 @@ -3544,6 +3571,13 @@ static const struct sys_reg_desc sys_reg_descs[] =3D= { { SYS_DESC(SYS_CCSIDR_EL1), access_ccsidr }, { SYS_DESC(SYS_CLIDR_EL1), access_clidr, reset_clidr, CLIDR_EL1, .set_user =3D set_clidr, .val =3D ~CLIDR_EL1_RES0 }, + IMPLEMENTATION_ID_FILTERED(SMIDR_EL1, + (SMIDR_EL1_NSMC | SMIDR_EL1_HIP | + SMIDR_EL1_AFFINITY2 | + SMIDR_EL1_IMPLEMENTER | + SMIDR_EL1_REVISION | SMIDR_EL1_SH | + SMIDR_EL1_AFFINITY), + sme_visibility), IMPLEMENTATION_ID(AIDR_EL1, GENMASK_ULL(63, 0)), { SYS_DESC(SYS_CSSELR_EL1), access_csselr, reset_unknown, CSSELR_EL1 }, ID_FILTERED(CTR_EL0, ctr_el0, --=20 2.47.3 From nobody Fri Jul 10 06:02:12 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 514C54F7997; Thu, 9 Jul 2026 18:41:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783622490; cv=none; b=fQXNqkhpI/h6P+zFas4+Y1YSuWzZqwVrIrX0SSix+gqj5YeXfugxTpJQhel+fXzZPXZBCv3U1E0BOv5gdT9f4QSSapHR2Wdp0Y/f4KQ0Y1wRaISb20AtFACv+dOdkSfafw9lERMCrpww+XTqqGmzMbSLctpRQTDJOVuuu3SRbfc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783622490; c=relaxed/simple; bh=cQOTqwdunjLIZgL4rF+SwwGCqO26Oh5PN9HCvtmvnxc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Bj5j2X3PS3oAmDWTfhV/7br+opTM04rwg5XpY6At+TJVqUGC09FUZ5q/pFCVKtLd4oLh28c1vU9vpsxmqhhNlxDmKY941rUAOU04neEEcCFsjVz6vcU7BZV7V3ZrPMhuqqvE5ntGz5D/ZflqObZsJ6Uz1WifNq30QLbqI8mdBQQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=P6igcleB; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="P6igcleB" Received: by smtp.kernel.org (Postfix) with ESMTPSA id ED5CC1F00A3A; Thu, 9 Jul 2026 18:41:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1783622488; bh=+zsbnn3YS/GuNqXb5/oAI/TG0iEFK1kmPP5/xMQf7S0=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=P6igcleB1FnD31LovBqf5Z4AMefvMz8yE0Q+kXx6GkLAAtSiN1pbCuGoCozQHHIZB U1bi4keeVTHOYXmXdCm4zKgCzGR7DfuWBtiYuhSxETOdaGIySGJfsfwcZo+3U8BV89 5+oc0bfpTieJUcDVESTjbtGXssr42CEnHicKoagXO+r4vv+WEzWWzEQKKwGCezPQaN Ood0wR19aZbYM8DZgAsAYeU4PYoiT/qXjyMXdtf9KeX06s1E0v4D9rNmDzqphYIqs8 BzZsQIB9tkqRI5gKTyxYnYjq/9HCj3PKUgPZUhKTvupI6LfFv3h1aPeAIJp/Qn1OdX V3/4Y98Dz3wAA== From: Mark Brown Date: Thu, 09 Jul 2026 19:27:39 +0100 Subject: [PATCH v12 18/29] KVM: arm64: Support SME priority registers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260709-kvm-arm64-sme-v12-18-d0301d79ef58@kernel.org> References: <20260709-kvm-arm64-sme-v12-0-d0301d79ef58@kernel.org> In-Reply-To: <20260709-kvm-arm64-sme-v12-0-d0301d79ef58@kernel.org> To: Marc Zyngier , Joey Gouly , Catalin Marinas , Suzuki K Poulose , Will Deacon , Paolo Bonzini , Jonathan Corbet , Shuah Khan , Oliver Upton Cc: Dave Martin , Fuad Tabba , Mark Rutland , Ben Horgan , Jean-Philippe Brucker , linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Peter Maydell , Eric Auger , Mark Brown X-Mailer: b4 0.16-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=6235; i=broonie@kernel.org; h=from:subject:message-id; bh=cQOTqwdunjLIZgL4rF+SwwGCqO26Oh5PN9HCvtmvnxc=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBqT+r4MjZuB7zMChKgyrzW6IU5hQAp04ROuoCBt 41AaprhheyJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCak/q+AAKCRAk1otyXVSH 0IFEB/9yQ5ZSe/X7bAP1zbd03UqzI3xw/lXAnBAIDTqcgPmvKGeQNJhWQjNEu3sDnUMAKexCLT+ U09NOqg2XrfX4N3HBinvi/XOK6lZq2VHXBFrXw3srsbcQNcyX8Pz0TqKvkBw4R9lw40yO/CPIoN ivgdyu8t2OwhChCQ9KCtaRzZR2ZPkvrOtfVSYkgz9vbdOmYekS6bJMB4Lc64ODUF4Bwo3Pfuhyb QisSw9H6AeTQOlGYWuja3PmB8c7ZfUAykBWWPxb8X2axQVyqcnIDhUmy6Ia0u5l+H/XLh7pogcA uLCPCt/aXf6Vk4Xz+pR0YenQToFk4jOLaf6wljlCUi4q8aFl X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB SME has optional support for configuring the relative priorities of PEs in systems where they share a single SME hardware block, known as a SMCU. Currently we do not have any support for this in Linux and will also hide it from KVM guests, pending experience with practical implementations. The interface for configuring priority support is via two new system registers, these registers are always defined when SME is available. The register SMPRI_EL1 allows control of SME execution priorities. Since we disable SME priority support for guests this register is RES0, define it as such and enable fine grained traps for SMPRI_EL1 to ensure that guests can't write to it even if the hardware supports priorities. Since the register should be readable with fixed contents we only trap writes, not reads. Since there is no host support for using priorities the register currently left with a value of 0 by the host so we do not need to update the value for guests. There is also an EL2 register SMPRIMAP_EL2 for virtualisation of priorities, this is RES0 when priority configuration is not supported but has no specific traps available. When saving state from a nested guest we overwrite any value the guest stored. Signed-off-by: Mark Brown --- arch/arm64/include/asm/kvm_host.h | 1 + arch/arm64/include/asm/vncr_mapping.h | 1 + arch/arm64/kvm/config.c | 4 ++++ arch/arm64/kvm/hyp/vhe/sysreg-sr.c | 7 +++++++ arch/arm64/kvm/sys_regs.c | 31 ++++++++++++++++++++++++++++++- 5 files changed, 43 insertions(+), 1 deletion(-) diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm= _host.h index e8c2907aacd2..35339cbf23f9 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -558,6 +558,7 @@ enum vcpu_sysreg { VNCR(CPACR_EL1),/* Coprocessor Access Control */ VNCR(ZCR_EL1), /* SVE Control */ VNCR(SMCR_EL1), /* SME Control */ + VNCR(SMPRIMAP_EL2), /* Streaming Mode Priority Mapping Register */ VNCR(TTBR0_EL1),/* Translation Table Base Register 0 */ VNCR(TTBR1_EL1),/* Translation Table Base Register 1 */ VNCR(TCR_EL1), /* Translation Control Register */ diff --git a/arch/arm64/include/asm/vncr_mapping.h b/arch/arm64/include/asm= /vncr_mapping.h index c3bf92ac52d4..f6152fbbfe03 100644 --- a/arch/arm64/include/asm/vncr_mapping.h +++ b/arch/arm64/include/asm/vncr_mapping.h @@ -45,6 +45,7 @@ #define VNCR_ZCR_EL1 0x1E0 #define VNCR_HAFGRTR_EL2 0x1E8 #define VNCR_SMCR_EL1 0x1F0 +#define VNCR_SMPRIMAP_EL2 0x1F8 #define VNCR_TTBR0_EL1 0x200 #define VNCR_TTBR1_EL1 0x210 #define VNCR_FAR_EL1 0x220 diff --git a/arch/arm64/kvm/config.c b/arch/arm64/kvm/config.c index cb6f3ea556c2..f71edb59106b 100644 --- a/arch/arm64/kvm/config.c +++ b/arch/arm64/kvm/config.c @@ -1677,6 +1677,10 @@ static void __compute_hfgwtr(struct kvm_vcpu *vcpu) =20 if (cpus_have_final_cap(ARM64_WORKAROUND_AMPERE_AC03_CPU_38)) *vcpu_fgt(vcpu, HFGWTR_EL2) |=3D HFGWTR_EL2_TCR_EL1; + + /* Emulate RES0 for SMPRI_EL1 until we support priorities */ + if (cpus_have_final_cap(ARM64_SME)) + *vcpu_fgt(vcpu, HFGWTR_EL2) &=3D ~HFGWTR_EL2_nSMPRI_EL1; } =20 static void __compute_hdfgwtr(struct kvm_vcpu *vcpu) diff --git a/arch/arm64/kvm/hyp/vhe/sysreg-sr.c b/arch/arm64/kvm/hyp/vhe/sy= sreg-sr.c index be685b63e8cf..0fe7153eab08 100644 --- a/arch/arm64/kvm/hyp/vhe/sysreg-sr.c +++ b/arch/arm64/kvm/hyp/vhe/sysreg-sr.c @@ -80,6 +80,13 @@ static void __sysreg_save_vel2_state(struct kvm_vcpu *vc= pu) =20 if (ctxt_has_sctlr2(&vcpu->arch.ctxt)) __vcpu_assign_sys_reg(vcpu, SCTLR2_EL2, read_sysreg_el1(SYS_SCTLR2)); + + /* + * We block SME priorities so SMPRIMAP_EL2 is RES0, however we + * do not have traps to block access so the guest might have + * updated the state, overwrite anything there. + */ + __vcpu_assign_sys_reg(vcpu, SMPRIMAP_EL2, 0); } =20 static void __sysreg_restore_vel2_state(struct kvm_vcpu *vcpu) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 91ef82dd6b1a..c43cb1b8fb68 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -779,6 +779,15 @@ static bool trap_raz_wi(struct kvm_vcpu *vcpu, return read_zero(vcpu, p); } =20 +static int set_res0(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, + u64 val) +{ + if (val) + return -EINVAL; + + return 0; +} + /* * ARMv8.1 mandates at least a trivial LORegion implementation, where all = the * RW registers are RES0 (which we can implement as RAZ/WI). On an ARMv8.0 @@ -2054,6 +2063,15 @@ static unsigned int fp8_visibility(const struct kvm_= vcpu *vcpu, return REG_HIDDEN; } =20 +static unsigned int sme_raz_visibility(const struct kvm_vcpu *vcpu, + const struct sys_reg_desc *rd) +{ + if (vcpu_has_sme(vcpu)) + return REG_RAZ; + + return REG_HIDDEN; +} + static u64 sanitise_id_aa64pfr0_el1(const struct kvm_vcpu *vcpu, u64 val) { if (!vcpu_has_sve(vcpu)) @@ -3441,7 +3459,15 @@ static const struct sys_reg_desc sys_reg_descs[] =3D= { =20 { SYS_DESC(SYS_ZCR_EL1), NULL, reset_val, ZCR_EL1, 0, .visibility =3D sve= _visibility }, { SYS_DESC(SYS_TRFCR_EL1), undef_access }, - { SYS_DESC(SYS_SMPRI_EL1), undef_access }, + + /* + * SMPRI_EL1 is UNDEF when SME is disabled, the UNDEF is + * handled via FGU which is handled without consulting this + * table. + */ + { SYS_DESC(SYS_SMPRI_EL1), trap_raz_wi, .set_user =3D set_res0, + .visibility =3D sme_raz_visibility }, + { SYS_DESC(SYS_SMCR_EL1), NULL, reset_val, SMCR_EL1, 0, .visibility =3D s= me_visibility }, { SYS_DESC(SYS_TTBR0_EL1), access_vm_reg, reset_unknown, TTBR0_EL1 }, { SYS_DESC(SYS_TTBR1_EL1), access_vm_reg, reset_unknown, TTBR1_EL1 }, @@ -3818,6 +3844,9 @@ static const struct sys_reg_desc sys_reg_descs[] =3D { =20 EL2_REG_VNCR(HCRX_EL2, reset_val, 0), =20 + { SYS_DESC(SYS_SMPRIMAP_EL2), .reg =3D SMPRIMAP_EL2, + .access =3D trap_raz_wi, .set_user =3D set_res0, .reset =3D reset_val, + .val =3D 0, .visibility =3D sme_el2_visibility }, EL2_REG_FILTERED(SMCR_EL2, access_smcr_el2, reset_val, 0, sme_el2_visibility), =20 --=20 2.47.3 From nobody Fri Jul 10 06:02:12 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 199B143B495; Thu, 9 Jul 2026 18:41:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783622494; cv=none; b=Dajg4sjSsAC/BWp9/IPyE1p0aytZuGmdFMxMEsTyVm+T5g6KJQt0pJ+WZe7YNCJgwFP/vfwVcAcbodkBDDsp3szTZykZruUoTG+q7ECGZpG9JQLaU9TLj/dFIHFRfaOGpW9cKvAolCO9BLEgYRPOn6BjblmgoknGYcdmBGRTWwQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783622494; c=relaxed/simple; bh=eYifdoGL1bXvWRmzpU9jq6qwsx2hr1vVYHaneD9gHQ4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=jqDzUYCbZW2/8RHQl4OwtIAS9OKNzk5Jrth+ItTLYkhxc+6tcZIEIpQwUhjxdXdQF8/v9LDktx/sodenwrtjM4AxbC6i2uPEkSygfJwrkvneSgr3O6GFleXWJNpvfzzoSIa9dQ0Yl96hj5zwKsLjYtF88OTMER4+wpKJPIic9DA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=gb86JdKe; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="gb86JdKe" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 8AB401F00ADB; Thu, 9 Jul 2026 18:41:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1783622492; bh=P3S9ahELkZZIZ12rSRHflO3V7CBzUhWm1iIfAQIars4=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=gb86JdKe3J6irrUpJMsO+Xhu7CUxlQJ1QwxCoIF3tRoZ3H2KYzLLl5FM6nFb32V4a pnhXGpqt8S+yYE/oGsY2Q6k9ITqGXVEhX2ktD7uPRsDCctIrc9+oFkejUb7fr2m5HZ eh12s54+KJlfxE1F5Wdd4uYRA6HcITV5UPKwwJsBcSWHzciVL8YfKkrX1hjRc234mc IrIDwT2s1zlADcU1e4/31mOARYkniQhZN5IIpGt1/+yaUlyQ399aq1mEPGnwpKgXIP FSng2F+VZCGgY47+1fbKMElQR5wwogRezv4Cjl34uBUSde7v7OeQ6xhrbR3v2CKZlt oSU9cxNXIWfow== From: Mark Brown Date: Thu, 09 Jul 2026 19:27:40 +0100 Subject: [PATCH v12 19/29] KVM: arm64: Support userspace access to streaming mode Z and P registers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260709-kvm-arm64-sme-v12-19-d0301d79ef58@kernel.org> References: <20260709-kvm-arm64-sme-v12-0-d0301d79ef58@kernel.org> In-Reply-To: <20260709-kvm-arm64-sme-v12-0-d0301d79ef58@kernel.org> To: Marc Zyngier , Joey Gouly , Catalin Marinas , Suzuki K Poulose , Will Deacon , Paolo Bonzini , Jonathan Corbet , Shuah Khan , Oliver Upton Cc: Dave Martin , Fuad Tabba , Mark Rutland , Ben Horgan , Jean-Philippe Brucker , linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Peter Maydell , Eric Auger , Mark Brown X-Mailer: b4 0.16-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=6007; i=broonie@kernel.org; h=from:subject:message-id; bh=eYifdoGL1bXvWRmzpU9jq6qwsx2hr1vVYHaneD9gHQ4=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBqT+r5lwnwta7n/Zrr7qqlakkaGaTr8EuIQa3RN 286aH7nnl6JATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCak/q+QAKCRAk1otyXVSH 0AzdB/9j6CIkb2ghzAEIyR2aDw/2xVUe2ijE8yHfieWBN0gTYIl5yB4zp4PuM3fl/EQXX22Av+h FcBNNv3DyuuYCf8v4fByEYOLJ8RpWA/KMRqqoyQ6bK2geprtJ9mvbHwgopqACOk3huf1kvD9d9Z ySFs5Z9H36vdJTPxGK7tTuAm+z5U9vW8weRgbeziwqDzCDeqZqmai+5lP1XqJTxU5By3M7zAVLN 7D7k5C+59P4P82fbgCeR2fis0JWRLEZNCi2a64DFUenWp1pltxxsB8QwHMfMB+fefs32+/sw8AM aWSBnnEy/r8LvDxYCuGc+DNkM0CAJ3fYazuacS2/4EEK9tpn X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB SME introduces a mode called streaming mode where the Z, P and optionally FFR registers can be accessed using the SVE instructions but with the SME vector length. Reflect this in the ABI for accessing the guest registers by making the vector length for the vcpu reflect the vector length that would be seen by the guest were it running, using the SME vector length when the guest is configured for streaming mode. Since SME may be present without SVE we also update the existing checks for access to the Z, P and V registers to check for either SVE or streaming mode. When not in streaming mode the guest floating point state may be accessed via the V registers. Any VMM that supports SME must be aware of the need to configure streaming mode prior to writing the floating point registers that this creates. Signed-off-by: Mark Brown --- arch/arm64/kvm/guest.c | 83 +++++++++++++++++++++++++++++++++++++++-------= ---- 1 file changed, 65 insertions(+), 18 deletions(-) diff --git a/arch/arm64/kvm/guest.c b/arch/arm64/kvm/guest.c index 48e6b500f531..110cc7f7527a 100644 --- a/arch/arm64/kvm/guest.c +++ b/arch/arm64/kvm/guest.c @@ -73,6 +73,19 @@ static u64 core_reg_offset_from_id(u64 id) return id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK | KVM_REG_ARM_CORE); } =20 +static bool vcpu_has_sve_regs(const struct kvm_vcpu *vcpu) +{ + return vcpu_has_sve(vcpu) || vcpu_in_streaming_mode(vcpu); +} + +static bool vcpu_ffr_enabled(const struct kvm_vcpu *vcpu) +{ + if (vcpu_in_streaming_mode(vcpu)) + return vcpu_has_fa64(vcpu); + else + return vcpu_has_sve(vcpu); +} + static int core_reg_size_from_offset(const struct kvm_vcpu *vcpu, u64 off) { int size; @@ -110,9 +123,10 @@ static int core_reg_size_from_offset(const struct kvm_= vcpu *vcpu, u64 off) /* * The KVM_REG_ARM64_SVE regs must be used instead of * KVM_REG_ARM_CORE for accessing the FPSIMD V-registers on - * SVE-enabled vcpus: + * SVE-enabled vcpus or when a SME enabled vcpu is in + * streaming mode: */ - if (vcpu_has_sve(vcpu) && core_reg_offset_is_vreg(off)) + if (vcpu_has_sve_regs(vcpu) && core_reg_offset_is_vreg(off)) return -EINVAL; =20 return size; @@ -423,6 +437,24 @@ struct vec_state_reg_region { unsigned int upad; /* extra trailing padding in user memory */ }; =20 +/* + * We represent the Z and P registers to userspace using either the + * SVE or SME vector length, depending on which features the guest has + * and if the guest is in streaming mode. + */ +static unsigned int vcpu_sve_cur_vq(struct kvm_vcpu *vcpu) +{ + unsigned int vq =3D 0; + + if (vcpu_has_sve(vcpu)) + vq =3D vcpu_sve_max_vq(vcpu); + + if (vcpu_in_streaming_mode(vcpu)) + vq =3D vcpu_sme_max_vq(vcpu); + + return vq; +} + /* * Validate SVE register ID and get sanitised bounds for user/kernel SVE * register copy @@ -460,20 +492,25 @@ static int sve_reg_to_region(struct vec_state_reg_reg= ion *region, reg_num =3D (reg->id & SVE_REG_ID_MASK) >> SVE_REG_ID_SHIFT; =20 if (reg->id >=3D zreg_id_min && reg->id <=3D zreg_id_max) { - if (!vcpu_has_sve(vcpu) || (reg->id & SVE_REG_SLICE_MASK) > 0) + if (!vcpu_has_sve_regs(vcpu) || (reg->id & SVE_REG_SLICE_MASK) > 0) return -ENOENT; =20 - vq =3D vcpu_sve_max_vq(vcpu); + vq =3D vcpu_sve_cur_vq(vcpu); =20 reqoffset =3D SVE_SIG_ZREG_OFFSET(vq, reg_num) - SVE_SIG_REGS_OFFSET; reqlen =3D KVM_SVE_ZREG_SIZE; maxlen =3D SVE_SIG_ZREG_SIZE(vq); } else if (reg->id >=3D preg_id_min && reg->id <=3D preg_id_max) { - if (!vcpu_has_sve(vcpu) || (reg->id & SVE_REG_SLICE_MASK) > 0) + if (!vcpu_has_sve_regs(vcpu) || (reg->id & SVE_REG_SLICE_MASK) > 0) return -ENOENT; =20 - vq =3D vcpu_sve_max_vq(vcpu); + if (!vcpu_ffr_enabled(vcpu) && + (reg->id >=3D KVM_REG_ARM64_SVE_FFR(0)) && + (reg->id <=3D KVM_REG_ARM64_SVE_FFR(SVE_NUM_SLICES - 1))) + return -ENOENT; + + vq =3D vcpu_sve_cur_vq(vcpu); =20 reqoffset =3D SVE_SIG_PREG_OFFSET(vq, reg_num) - SVE_SIG_REGS_OFFSET; @@ -640,15 +677,21 @@ static unsigned long num_core_regs(const struct kvm_v= cpu *vcpu) static unsigned long num_sve_regs(const struct kvm_vcpu *vcpu) { const unsigned int slices =3D vcpu_sve_slices(vcpu); + int regs, ret; =20 - if (!vcpu_has_sve(vcpu)) + if (!vcpu_has_sve(vcpu) && !vcpu_in_streaming_mode(vcpu)) return 0; =20 /* Policed by KVM_GET_REG_LIST: */ WARN_ON(!kvm_arm_vcpu_vec_finalized(vcpu)); =20 - return slices * (SVE_NUM_PREGS + SVE_NUM_ZREGS + 1 /* FFR */) - + 1; /* KVM_REG_ARM64_SVE_VLS */ + regs =3D SVE_NUM_PREGS + SVE_NUM_ZREGS; + if (vcpu_ffr_enabled(vcpu)) + regs++; /* FFR */ + ret =3D regs * slices; + if (vcpu_has_sve(vcpu)) + ret++; /* KVM_REG_ARM64_SVE_VLS */ + return ret; } =20 static int copy_sve_reg_indices(const struct kvm_vcpu *vcpu, @@ -659,7 +702,7 @@ static int copy_sve_reg_indices(const struct kvm_vcpu *= vcpu, unsigned int i, n; int num_regs =3D 0; =20 - if (!vcpu_has_sve(vcpu)) + if (!vcpu_has_sve_regs(vcpu)) return 0; =20 /* Policed by KVM_GET_REG_LIST: */ @@ -669,10 +712,12 @@ static int copy_sve_reg_indices(const struct kvm_vcpu= *vcpu, * Enumerate this first, so that userspace can save/restore in * the order reported by KVM_GET_REG_LIST: */ - reg =3D KVM_REG_ARM64_SVE_VLS; - if (put_user(reg, uindices++)) - return -EFAULT; - ++num_regs; + if (vcpu_has_sve(vcpu)) { + reg =3D KVM_REG_ARM64_SVE_VLS; + if (put_user(reg, uindices++)) + return -EFAULT; + ++num_regs; + } =20 for (i =3D 0; i < slices; i++) { for (n =3D 0; n < SVE_NUM_ZREGS; n++) { @@ -689,10 +734,12 @@ static int copy_sve_reg_indices(const struct kvm_vcpu= *vcpu, num_regs++; } =20 - reg =3D KVM_REG_ARM64_SVE_FFR(i); - if (put_user(reg, uindices++)) - return -EFAULT; - num_regs++; + if (vcpu_ffr_enabled(vcpu)) { + reg =3D KVM_REG_ARM64_SVE_FFR(i); + if (put_user(reg, uindices++)) + return -EFAULT; + num_regs++; + } } =20 return num_regs; --=20 2.47.3 From nobody Fri Jul 10 06:02:12 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8FE87437478; Thu, 9 Jul 2026 18:41:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783622498; cv=none; b=VHX3/UOuUH7Vv/0nCOI/QirmZ4pf4rZ4he6Pv7xOZgLoRjG0OVgPWweiVZRrrAfEJW5vqXZGljVNfFpnGTJzEBwoTsDgNzYbIqHFgZVNmzn7sGZV0h61ZtFQ6sSPLigJW5T2SSuMVFwTsiCmG+kUUbTL9NmzhTuJbJtu42ZmOXE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783622498; c=relaxed/simple; bh=xLxlJPLqDSuT3BzgbokMn0PxDYZwCK7AxD2XRKqXdeI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Is0l2ExgKKhOcaZ0yZEbTMj9kL8ri8D+SQh5TsNu1FngHxoAJAZNlBbXbAXc3C+W4A+OruGNIcZP4658nNcNrVsb6/OFM6iAzQz7fNqdK7Xm0pWOdGjgExGouKbJTU/2+4RTBmxDcDPX3ty6XvycCzDpwB0nFH3TUeovuRvy4k0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Zda6x0mJ; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Zda6x0mJ" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1C9FE1F000E9; Thu, 9 Jul 2026 18:41:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1783622497; bh=uWFRDM+Io32xW+VhypJpKi1NlK0gVsSgLCMgEKdC5HI=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=Zda6x0mJsPBLFasezouRcdvrKMHgutAyMXmesY7G3JWWfhrVnNiB/Ao/y0OC8d1JJ PQoNkXGZlPFxheKISW4JnlHU4OU9ubF0cac3Q4iqO05RepuZH669mMtM0FOSdhqz2L jBBUWwq0uxItW07baKK5UuicvXZpS64YoYJzmuVOSRGZ+z5lwzs4kRR6Rf9IVye+eY LFdJL4rlGGptGa9hX8LrR+p6tl94B/Pi4FEw8A/BgeekmBrLSs/RRxdG9bJTDyLBxo dlCN238lYZTUAX/tpO5kOXDMglgREoFj/onmTvWh0TJEBRR0A/7sZLzvmJbdCjIgki pjttZk+o/ZK2w== From: Mark Brown Date: Thu, 09 Jul 2026 19:27:41 +0100 Subject: [PATCH v12 20/29] KVM: arm64: Flush register state on writes to SVCR.SM and SVCR.ZA Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260709-kvm-arm64-sme-v12-20-d0301d79ef58@kernel.org> References: <20260709-kvm-arm64-sme-v12-0-d0301d79ef58@kernel.org> In-Reply-To: <20260709-kvm-arm64-sme-v12-0-d0301d79ef58@kernel.org> To: Marc Zyngier , Joey Gouly , Catalin Marinas , Suzuki K Poulose , Will Deacon , Paolo Bonzini , Jonathan Corbet , Shuah Khan , Oliver Upton Cc: Dave Martin , Fuad Tabba , Mark Rutland , Ben Horgan , Jean-Philippe Brucker , linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Peter Maydell , Eric Auger , Mark Brown X-Mailer: b4 0.16-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=5358; i=broonie@kernel.org; h=from:subject:message-id; bh=xLxlJPLqDSuT3BzgbokMn0PxDYZwCK7AxD2XRKqXdeI=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBqT+r5F8QipAIMBO6Q09sPsqE2U7PJLdF3m/V0T LibAnM2wEWJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCak/q+QAKCRAk1otyXVSH 0OQSB/0XoS5Y2E+udp8ouzf4dEN0zfUsqxind+iDfMKL78nZKhP9Ee/HpIUI3ya+0cM1+Q/KmQB Xtpd9j5A+LjVyAixjZLzcgpXDGRI/B3HHdGVUIhJIzLuzfL4JzzYwZO1DTdhi9jIVQ4eTsFAHB3 /Ks5h7d3feiDUoRJD9j/K5lo50oDpFCrZaUPSkfRM1r5J9Zwq5828p0BNClc+zM2Dya5ZXgJbL9 kWCSQvJySzBbUI7mLCcw1baVMfHISLMaWXsGDTSuohcNoj+jSh0qI3IdHVnaaJ9J7RpMdCeCljQ 1x7YBFiCnv3nnlrTTrx0hWT3xOUFHkqdF05poMD4zyJdJCQQ X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB Writes to the physical SVCR.SM and SVCR.ZA change the state of PSTATE.SM and PSTATE.ZA, causing other floating point state to reset. Emulate this behaviour for writes done via the KVM userspace ABI. Setting PSTATE.ZA to 1 causes ZA and ZT0 to be reset to 0, these are stored in sme_state. Setting PSTATE.ZA to 0 causes ZA and ZT0 to become inaccessib= le so no reset is needed. Any change in PSTATE.SM causes the V, Z, P, FFR and FPMR registers to be reset to 0 and FPSR to be reset to 0x800009f. Rather than introduce a requirement that the vector configuration be finalised before writing to SVCR we check for this before updating the SVE and SME specific state, when finalisation happens they will be allocated with an initial state of 0. Similarly in order to avoid ordering requirements between finalisation and writes to the ID registers we always allocate space for ZT0 if the hardware supports it, this is 512 bytes per vCPU. The overwhelming majority of practical systems with SME are expected to want use SME2, there is very little practical reason to disable it other than for feature testing, and the additional complexity seems more likely to lead to bugs than deliver practical benefits. Signed-off-by: Mark Brown --- arch/arm64/include/asm/kvm_host.h | 28 ++++++++++++++++++++++++++++ arch/arm64/include/asm/sysreg.h | 2 ++ arch/arm64/kvm/sys_regs.c | 30 +++++++++++++++++++++++++++++- 3 files changed, 59 insertions(+), 1 deletion(-) diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm= _host.h index 35339cbf23f9..b78c039cb5ec 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -1142,6 +1142,34 @@ struct kvm_vcpu_arch { =20 #define vcpu_sve_state_size(vcpu) sve_state_size_from_vl(vcpu_sve_max_vl(v= cpu)) =20 +#define vcpu_sme_state(vcpu) (kern_hyp_va((vcpu)->arch.sme_state)) + +#define sme_state_size_from_vl(vl, sme2) ({ \ + size_t __size_ret; \ + unsigned int __vq; \ + \ + if (WARN_ON(!sve_vl_valid(vl))) { \ + __size_ret =3D 0; \ + } else { \ + __vq =3D sve_vq_from_vl(vl); \ + __size_ret =3D ZA_SIG_REGS_SIZE(__vq); \ + if (sme2) \ + __size_ret +=3D ZT_SIG_REG_BYTES; \ + } \ + \ + __size_ret; \ +}) + +/* + * Always provide space for ZT0 to avoid ordering requirements with ID + * register writes and vector finalization. + */ +#define vcpu_sme_state_size(vcpu) ({ \ + unsigned long __vl; \ + __vl =3D (vcpu)->arch.max_vl[ARM64_VEC_SME]; \ + sme_state_size_from_vl(__vl, system_supports_sme2()); \ +}) + #define KVM_GUESTDBG_VALID_MASK (KVM_GUESTDBG_ENABLE | \ KVM_GUESTDBG_USE_SW_BP | \ KVM_GUESTDBG_USE_HW | \ diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysre= g.h index 4b96449e0ffa..b434320de1a7 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -1108,6 +1108,8 @@ #define gicr_insn(insn) read_sysreg_s(GICV5_OP_GICR_##insn) #define gic_insn(v, insn) write_sysreg_s(v, GICV5_OP_GIC_##insn) =20 +#define FPSR_RESET_VALUE 0x800009f + #ifdef __ASSEMBLER__ =20 .macro mrs_s, rt, sreg diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index c43cb1b8fb68..e8d3eceb0124 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1015,6 +1015,34 @@ static unsigned int hidden_visibility(const struct k= vm_vcpu *vcpu, return REG_HIDDEN; } =20 +static int set_svcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, + u64 val) +{ + u64 old =3D __vcpu_sys_reg(vcpu, rd->reg); + + if (val & SVCR_RES0) + return -EINVAL; + + if ((val & SVCR_ZA) && !(old & SVCR_ZA) && + kvm_arm_vcpu_vec_finalized(vcpu)) + memset(vcpu->arch.sme_state, 0, vcpu_sme_state_size(vcpu)); + + if ((val & SVCR_SM) !=3D (old & SVCR_SM)) { + memset(vcpu->arch.ctxt.fp_regs.vregs, 0, + sizeof(vcpu->arch.ctxt.fp_regs.vregs)); + + if (kvm_arm_vcpu_vec_finalized(vcpu)) + memset(vcpu->arch.sve_state, 0, + vcpu_sve_state_size(vcpu)); + + __vcpu_assign_sys_reg(vcpu, FPMR, 0); + vcpu->arch.ctxt.fp_regs.fpsr =3D FPSR_RESET_VALUE; + } + + __vcpu_assign_sys_reg(vcpu, rd->reg, val); + return 0; +} + static unsigned int pmu_visibility(const struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) { @@ -3612,7 +3640,7 @@ static const struct sys_reg_desc sys_reg_descs[] =3D { CTR_EL0_DminLine_MASK | CTR_EL0_L1Ip_MASK | CTR_EL0_IminLine_MASK), - { SYS_DESC(SYS_SVCR), undef_access, reset_val, SVCR, 0, .visibility =3D s= me_visibility }, + { SYS_DESC(SYS_SVCR), undef_access, reset_val, SVCR, 0, .visibility =3D s= me_visibility, .set_user =3D set_svcr }, { SYS_DESC(SYS_FPMR), undef_access, reset_val, FPMR, 0, .visibility =3D f= p8_visibility }, =20 { PMU_SYS_REG(PMCR_EL0), .access =3D access_pmcr, .reset =3D reset_pmcr, --=20 2.47.3 From nobody Fri Jul 10 06:02:12 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DC8D9446833; Thu, 9 Jul 2026 18:41:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783622503; cv=none; b=kAo+TWn8bNFUSBBBAxfHFqG5MomY8oxnBsqMWgKlc9+yJ1zjI9bxwtE1HskUlPxYNdvxxLls/mmFY25Y8PLIO/rFlD0N5dvYnekHZOBexQD4KjJQc0cC8Ytc2Ak691+Nb2pF6Uc47crbjpAQOJ2wJIVSVOmqm5fuo9f2c9qVKSc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783622503; c=relaxed/simple; bh=OWLQ+fStXa0u76ZwF0nDRlLR1/mZJ3iEmSPjs0EDopk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=C4gbfnywQ1+1eLqYVq4syCl5mL/SrlgAtwPN1+oQQzDhVnk+7pJB/ToI5SeYChObnmsh1Qv/JJRdT1iz+J2L8MrXX5cdBZur7ES8fCLWUK89KOu2oPxE44n1vJ55zUaVaWoRtnD/U9UhFvP8p1+Grl9JJmAJi5MvVTA8xyxmIMs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=oW4tUVBd; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="oW4tUVBd" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 9FB721F00A3A; Thu, 9 Jul 2026 18:41:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1783622501; bh=cQTVOv3doodlzyRyF79rD7oVUshuooj7eTaIdQCTKvI=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=oW4tUVBdsGDpzVTxMxCpwOVjH9J/BzhM4mX62kQ3A9aaAmEg2hZHw9w3Ma1KHujj2 cxfMOFChDDGD+8ttgI8ZFQP5EPP70LyNRL7bMKimMZ1W0wr9MPMhTkhrNn9gTUXyIC uDiitFqrh9IPtcipW9Hqj/2Y/KbFIShaEc720Uoq3oUXbXZoiy7SYS6wJf6XSDkgKm iJGOSbWKF2BwE2Myj4NGLU9d4XEERGOen4hnY/e9iHIjWaPUwwpIFWdnDHYI29IT2P wCAgJaB+SN7+owVCEwhHG4t6ogXhKRW+MwStmSKe0/k3QhwQNRFfZk03fEY+RfFoFj FpM/74AMaoWSQ== From: Mark Brown Date: Thu, 09 Jul 2026 19:27:42 +0100 Subject: [PATCH v12 21/29] KVM: arm64: Expose SME specific state to userspace Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260709-kvm-arm64-sme-v12-21-d0301d79ef58@kernel.org> References: <20260709-kvm-arm64-sme-v12-0-d0301d79ef58@kernel.org> In-Reply-To: <20260709-kvm-arm64-sme-v12-0-d0301d79ef58@kernel.org> To: Marc Zyngier , Joey Gouly , Catalin Marinas , Suzuki K Poulose , Will Deacon , Paolo Bonzini , Jonathan Corbet , Shuah Khan , Oliver Upton Cc: Dave Martin , Fuad Tabba , Mark Rutland , Ben Horgan , Jean-Philippe Brucker , linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Peter Maydell , Eric Auger , Mark Brown X-Mailer: b4 0.16-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=9460; i=broonie@kernel.org; h=from:subject:message-id; bh=OWLQ+fStXa0u76ZwF0nDRlLR1/mZJ3iEmSPjs0EDopk=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBqT+r6h491T9bGd1eUvEib9Cp2kpfmugE+g+FtI /aJymEC1KyJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCak/q+gAKCRAk1otyXVSH 0MVqB/0TIYafOM8No1bOAQRuHKFvO4QgwYq4/4jO7qfQ5CzOpkbZVLFqj+fkuHviFyx4kaZCgdu Pk9MTQR6hzIGm/unbHtXaZtED0VIMbJYDnDLDYJA/ONERXDjuF44SoSQbgaq1YhzD/IGBiV1eCf n1w347uK3csNdG4WZ8n26OghSpUh0RkgVhYm8HSIVsX5XcNVPW8f6d0Ia5x2DVosp9HIp+5nZAd wqvm2LlnDriwJY764KQkR/gUM5oSJBkvQ+WEvhQbSu1R1GqZyKJQptJb4n5dTigbpjYmmK55mF3 2YRdGaITeBCyGd8Fzc4RCq3n+UCRsrAaXygleAfUtbI/zQd0 X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB SME introduces two new registers, the ZA matrix register and the ZT0 LUT register. Both of these registers are only accessible when PSTATE.ZA is set and ZT0 is only present if SME2 is enabled for the guest. Provide support for configuring these from VMMs. The ZA matrix is a single SVL*SVL register which is available when PSTATE.ZA is set. We follow the pattern established by the architecture itself and expose this to userspace as a series of horizontal SVE vectors with the streaming mode vector length, using the format already established for the SVE vectors themselves. ZT0 is a single register with a refreshingly fixed size 512 bit register which is like ZA accessible only when PSTATE.ZA is set. Add support for it to the userspace API. As is done in the architecture for both ZA and ZT0 the value will be reset to 0 whenever PSTATE.ZA changes from 0 to 1 and the registers are inaccessible when PSTATE.ZA is 0. While there is currently only one ZT register the naming as ZT0 and the instruction encoding clearly leave room for future extensions adding more ZT registers. This encoding can readily support such an extension if one is introduced. Signed-off-by: Mark Brown --- arch/arm64/include/uapi/asm/kvm.h | 20 ++++ arch/arm64/kvm/guest.c | 186 ++++++++++++++++++++++++++++++++++= +++- 2 files changed, 204 insertions(+), 2 deletions(-) diff --git a/arch/arm64/include/uapi/asm/kvm.h b/arch/arm64/include/uapi/as= m/kvm.h index 15d53300914b..deccb034fce3 100644 --- a/arch/arm64/include/uapi/asm/kvm.h +++ b/arch/arm64/include/uapi/asm/kvm.h @@ -357,6 +357,26 @@ struct kvm_arm_counter_offset { /* SME registers */ #define KVM_REG_ARM64_SME (0x17 << KVM_REG_ARM_COPROC_SHIFT) =20 +#define KVM_ARM64_SME_VQ_MIN __SVE_VQ_MIN +#define KVM_ARM64_SME_VQ_MAX 16 + +/* ZA and ZTn occupy blocks at the following offsets within this range: */ +#define KVM_REG_ARM64_SME_ZA_BASE 0 +#define KVM_REG_ARM64_SME_ZT_BASE 0x600 + +#define KVM_ARM64_SME_MAX_ZAHREG (__SVE_VQ_BYTES * KVM_ARM64_SME_VQ_MAX) + +#define KVM_REG_ARM64_SME_ZAHREG(n, i) \ + (KVM_REG_ARM64 | KVM_REG_ARM64_SME | KVM_REG_ARM64_SME_ZA_BASE | \ + KVM_REG_SIZE_U2048 | \ + (((n) & (KVM_ARM64_SME_MAX_ZAHREG - 1)) << 5) | \ + ((i) & (KVM_ARM64_SVE_MAX_SLICES - 1))) + +#define KVM_REG_ARM64_SME_ZTREG_SIZE (512 / 8) +#define KVM_REG_ARM64_SME_ZTREG(n) \ + (KVM_REG_ARM64 | KVM_REG_ARM64_SME | KVM_REG_ARM64_SME_ZT_BASE | \ + KVM_REG_SIZE_U512 | (n)) + /* Vector lengths pseudo-register: */ #define KVM_REG_ARM64_SME_VLS (KVM_REG_ARM64 | KVM_REG_ARM64_SME | \ KVM_REG_SIZE_U512 | 0xfffe) diff --git a/arch/arm64/kvm/guest.c b/arch/arm64/kvm/guest.c index 110cc7f7527a..1b85f0383628 100644 --- a/arch/arm64/kvm/guest.c +++ b/arch/arm64/kvm/guest.c @@ -598,22 +598,133 @@ static int set_sme_vls(struct kvm_vcpu *vcpu, const = struct kvm_one_reg *reg) return set_vec_vls(ARM64_VEC_SME, vcpu, reg); } =20 +#define ZAH_REG_SLICE_SHIFT 0 +#define ZAH_REG_SLICE_BITS 5 +#define ZAH_REG_ID_SHIFT (ZAH_REG_SLICE_SHIFT + ZAH_REG_SLICE_BITS) +#define ZAH_REG_ID_BITS 8 + +#define ZAH_REG_SLICE_MASK \ + GENMASK(ZAH_REG_SLICE_SHIFT + ZAH_REG_SLICE_BITS - 1, \ + ZAH_REG_SLICE_SHIFT) +#define ZAH_REG_ID_MASK \ + GENMASK(ZAH_REG_ID_SHIFT + ZAH_REG_ID_BITS - 1, ZAH_REG_ID_SHIFT) + +/* + * Validate SME register ID and get sanitised bounds for user/kernel SME + * register copy + */ +static int sme_reg_to_region(struct vec_state_reg_region *region, + struct kvm_vcpu *vcpu, + const struct kvm_one_reg *reg) +{ + /* reg ID ranges for ZA.H[n] registers */ + unsigned int vq =3D vcpu_sme_max_vq(vcpu); + const u64 za_h_max =3D vq * __SVE_VQ_BYTES; + const u64 zah_id_min =3D KVM_REG_ARM64_SME_ZAHREG(0, 0); + const u64 zah_id_max =3D KVM_REG_ARM64_SME_ZAHREG(za_h_max - 1, + SVE_NUM_SLICES - 1); + unsigned int reg_num; + + unsigned int reqoffset, reqlen; /* User-requested offset and length */ + unsigned int maxlen; /* Maximum permitted length */ + + size_t sme_state_size; + + reg_num =3D (reg->id & ZAH_REG_ID_MASK) >> ZAH_REG_ID_SHIFT; + + if (reg->id >=3D zah_id_min && reg->id <=3D zah_id_max) { + if (!vcpu_has_sme(vcpu) || (reg->id & ZAH_REG_SLICE_MASK) > 0) + return -ENOENT; + + if (!vcpu_za_enabled(vcpu)) + return -EBUSY; + + /* ZA is exposed as SVE vectors ZA.H[n] */ + reqoffset =3D ZA_SIG_ZAV_OFFSET(vq, reg_num) - + ZA_SIG_REGS_OFFSET; + reqlen =3D KVM_SVE_ZREG_SIZE; + maxlen =3D SVE_SIG_ZREG_SIZE(vq); + } else if (reg->id =3D=3D KVM_REG_ARM64_SME_ZTREG(0)) { + if (!kvm_has_feat(vcpu->kvm, ID_AA64PFR1_EL1, SME, SME2)) + return -ENOENT; + + if (!vcpu_za_enabled(vcpu)) + return -EBUSY; + + /* ZT0 is stored after ZA */ + reqoffset =3D ZA_SIG_REGS_SIZE(vq); + reqlen =3D KVM_REG_ARM64_SME_ZTREG_SIZE; + maxlen =3D KVM_REG_ARM64_SME_ZTREG_SIZE; + } else { + return -EINVAL; + } + + sme_state_size =3D vcpu_sme_state_size(vcpu); + if (WARN_ON(!sme_state_size)) + return -EINVAL; + + region->koffset =3D array_index_nospec(reqoffset, sme_state_size); + region->klen =3D min(maxlen, reqlen); + region->upad =3D reqlen - region->klen; + + return 0; +} + +/* + * ZA is exposed as an array of horizontal vectors with the same + * format as SVE, mirroring the architecture's LDR ZA[Wv, offs], [Xn] + * instruction. + */ + static int get_sme_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *re= g) { + int ret; + struct vec_state_reg_region region; + char __user *uptr =3D (char __user *)reg->addr; + /* Handle the KVM_REG_ARM64_SME_VLS pseudo-reg as a special case: */ if (reg->id =3D=3D KVM_REG_ARM64_SME_VLS) return get_sme_vls(vcpu, reg); =20 - return -EINVAL; + /* Try to interpret reg ID as an architectural SME register... */ + ret =3D sme_reg_to_region(®ion, vcpu, reg); + if (ret) + return ret; + + if (!kvm_arm_vcpu_vec_finalized(vcpu)) + return -EPERM; + + if (copy_to_user(uptr, (void *)vcpu->arch.sme_state + region.koffset, + region.klen) || + clear_user(uptr + region.klen, region.upad)) + return -EFAULT; + + return 0; } =20 static int set_sme_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *re= g) { + int ret; + struct vec_state_reg_region region; + char __user *uptr =3D (char __user *)reg->addr; + /* Handle the KVM_REG_ARM64_SME_VLS pseudo-reg as a special case: */ if (reg->id =3D=3D KVM_REG_ARM64_SME_VLS) return set_sme_vls(vcpu, reg); =20 - return -EINVAL; + /* Try to interpret reg ID as an architectural SME register... */ + ret =3D sme_reg_to_region(®ion, vcpu, reg); + if (ret) + return ret; + + if (!kvm_arm_vcpu_vec_finalized(vcpu)) + return -EPERM; + + if (copy_from_user((void *)vcpu->arch.sme_state + region.koffset, uptr, + region.klen)) + return -EFAULT; + + return 0; } =20 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *r= egs) @@ -694,6 +805,27 @@ static unsigned long num_sve_regs(const struct kvm_vcp= u *vcpu) return ret; } =20 +static unsigned long num_sme_regs(const struct kvm_vcpu *vcpu) +{ + const unsigned int slices =3D vcpu_sve_slices(vcpu); + int regs; + + if (!vcpu_has_sme(vcpu)) + return 0; + + /* Policed by KVM_GET_REG_LIST: */ + WARN_ON(!kvm_arm_vcpu_vec_finalized(vcpu)); + + /* KVM_REG_ARM64_SME_VLS */ + regs =3D 1; + + /* ZA, and ZT0 if SME2 */ + if (vcpu_za_enabled(vcpu)) + regs +=3D (slices * vcpu_sme_max_vl(vcpu)) + vcpu_has_sme2(vcpu); + + return regs; +} + static int copy_sve_reg_indices(const struct kvm_vcpu *vcpu, u64 __user *uindices) { @@ -745,6 +877,50 @@ static int copy_sve_reg_indices(const struct kvm_vcpu = *vcpu, return num_regs; } =20 +static int copy_sme_reg_indices(const struct kvm_vcpu *vcpu, + u64 __user *uindices) +{ + const unsigned int slices =3D vcpu_sve_slices(vcpu); + u64 reg; + unsigned int i, n; + int num_regs =3D 0; + + if (!vcpu_has_sme(vcpu)) + return 0; + + /* Policed by KVM_GET_REG_LIST: */ + WARN_ON(!kvm_arm_vcpu_vec_finalized(vcpu)); + + /* + * Enumerate this first, so that userspace can save/restore in + * the order reported by KVM_GET_REG_LIST: + */ + reg =3D KVM_REG_ARM64_SME_VLS; + if (put_user(reg, uindices++)) + return -EFAULT; + ++num_regs; + + if (vcpu_za_enabled(vcpu)) { + for (i =3D 0; i < slices; i++) { + for (n =3D 0; n < vcpu_sme_max_vl(vcpu); n++) { + reg =3D KVM_REG_ARM64_SME_ZAHREG(n, i); + if (put_user(reg, uindices++)) + return -EFAULT; + num_regs++; + } + } + + if (vcpu_has_sme2(vcpu)) { + reg =3D KVM_REG_ARM64_SME_ZTREG(0); + if (put_user(reg, uindices++)) + return -EFAULT; + num_regs++; + } + } + + return num_regs; +} + /** * kvm_arm_num_regs - how many registers do we present via KVM_GET_ONE_REG * @vcpu: the vCPU pointer @@ -757,6 +933,7 @@ unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu) =20 res +=3D num_core_regs(vcpu); res +=3D num_sve_regs(vcpu); + res +=3D num_sme_regs(vcpu); res +=3D kvm_arm_num_sys_reg_descs(vcpu); res +=3D kvm_arm_get_fw_num_regs(vcpu); =20 @@ -784,6 +961,11 @@ int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u6= 4 __user *uindices) return ret; uindices +=3D ret; =20 + ret =3D copy_sme_reg_indices(vcpu, uindices); + if (ret < 0) + return ret; + uindices +=3D ret; + ret =3D kvm_arm_copy_fw_reg_indices(vcpu, uindices); if (ret < 0) return ret; --=20 2.47.3 From nobody Fri Jul 10 06:02:12 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 83D6B446857; Thu, 9 Jul 2026 18:41:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783622508; cv=none; b=BfQn5sA4171A5PlN0pf9cTmVFeqiPwr4vL+OgRTSK/clniPUDynhRABUfpk3xpCeHIomhcqcH7yxF6/3SXU+YsFWDm5wcZ7Bmnfb0DrcIAX5hEXJbmx6pQ76qNUUQI/WJVbhqTbF9/C1US3NQZ8PrjXXUdVCEeLNyBYNx5CqU9A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783622508; c=relaxed/simple; bh=ewc6MxdTFQrnYvQ4pRkzTspYwGUj+K2NicxNwR5qZIA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ISxRr6Ia1NyNv1aIlV30UQvaHt88T+woLuQHw49R+xJ5lOnotBVhsmC7Rl6RkP+8YhqDZNL1vbE9u+pBQ58l58X5qpB1/2eua++8M5cy1u3DZGDKCpt4BBZwh1Q0oFICgLnuZa2b2tnwAwwo0e66mG/2jXvd+AOf9147QJv0jNg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Gb3QgRs2; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Gb3QgRs2" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 3637D1F00A3D; Thu, 9 Jul 2026 18:41:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1783622506; bh=MLStMQQAVDWe3AzNbiGQdQWZObxUA+fH6UwR9OaGb6w=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=Gb3QgRs2bpqbMGAc/VteumEH1TcGWaKbEcgOspzXngK2s9QluCXltO9iUEG892+QH zqvSvjMmRLCyvi36gMU1d4wxOKhLpTtGAtdZ/VXgSew0yNH8gAsz0dcD5NtnvVjf7E 0kHSBWxTklU/GwTaJssY7ll+TVgXbF6a1ANMalt+co2n0h29BEGieZdJ09I1wvfjhH 3twuzcy8Fc7tNCVEBb+fFoH8a8n3oLNKkMZg25U/fu34ejTYUkhDc49UJkzW1WxlJN sy6mq7KhLFWV1zpV1DQje3zA62iCrGKkGimbRhBWio5Pl44uiBC4SWN9u3qqyw+v2u DAyXz9pMZPLJg== From: Mark Brown Date: Thu, 09 Jul 2026 19:27:43 +0100 Subject: [PATCH v12 22/29] KVM: arm64: Context switch SME state for guests Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260709-kvm-arm64-sme-v12-22-d0301d79ef58@kernel.org> References: <20260709-kvm-arm64-sme-v12-0-d0301d79ef58@kernel.org> In-Reply-To: <20260709-kvm-arm64-sme-v12-0-d0301d79ef58@kernel.org> To: Marc Zyngier , Joey Gouly , Catalin Marinas , Suzuki K Poulose , Will Deacon , Paolo Bonzini , Jonathan Corbet , Shuah Khan , Oliver Upton Cc: Dave Martin , Fuad Tabba , Mark Rutland , Ben Horgan , Jean-Philippe Brucker , linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Peter Maydell , Eric Auger , Mark Brown X-Mailer: b4 0.16-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=21691; i=broonie@kernel.org; h=from:subject:message-id; bh=ewc6MxdTFQrnYvQ4pRkzTspYwGUj+K2NicxNwR5qZIA=; b=kA0DAAoBJNaLcl1Uh9AByyZiAGpP6vujParhCnB47uVQkXLWRScPSPF7T1u3ikbwrphnVA+mS IkBMwQAAQoAHRYhBK3maKpnVxi1n+Kf6iTWi3JdVIfQBQJqT+r7AAoJECTWi3JdVIfQofwIAIYz R75xVSJJmPP4T77z8miDmvLeA1Ue7q2Zpw+riQ58PyBwMVfpDBUD4JmwXChH00jnXNUSBVs3Zc7 SajLYNotdXhSZrmOn6bIrQ9wJ8McYb1zTtUq24rcVwZagOKsdm8zUEOZlojGsdO90ndLqP0GAuX rqfDYGE5lspG6mIoOvFSakm/dqIqQtaG5IQz8Xdh7LUyzD7rwxILsJ+sMReSMhV/EInXblze41B 2iQ/f2Mi0A/7LehSCTea1KqoU3g8VSNIP+iWhNt5ThRTh2XOxQVU3pQvyqb3mQD/5Hdcz3lsi2k DqrfK4dqrIdUPhlz3m2Z0KomoEqiNjg0axydDzg= X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB If the guest has SME state we need to context switch that state, provide support for that for normal guests. SME has three sets of registers, ZA, ZT (only present for SME2) and also streaming SVE which replaces the standard floating point registers when active. The first two are fairly straightforward, they are accessible only when PSTATE.ZA is set and we can reuse the assembly from the host to save and load them from a single contiguous buffer. When PSTATE.ZA is not set then these registers are inaccessible, when the guest enables PSTATE.ZA all bits will be set to 0 by that and nothing is required on restore. Streaming mode is slightly more complicated, when enabled via PSTATE.SM it provides a version of the SVE registers using the SME vector length and may optionally omit the FFR register. SME may also be present without SVE. The register state is stored in sve_state as for non-streaming SVE mode, we make an initial selection of registers to update based on the guest SVE support and then override this when loading SVCR if streaming mode is enabled. A further complication is that when the hardware is in streaming mode guest operations that are invalid in in streaming mode will generate SME exceptions. There are also subfeature exceptions for SME2 controlled via SMCR which generate distinct exception codes. In many situations these exceptions are routed directly to the lower ELs with no opportunity for the hypervisor to intercept. So that guests do not see unexpected exception types due to the actual hardware configuration not being what the guest configured we update the SMCRs and SVCR even if the guest does not own the registers. Since in order to avoid duplication with SME we now restore the register state outside of the SVE specific restore function we need to move the restore of the effective VL for nested guests to a separate restore function run after loading the floating point register state, along with the similar handling required for SME. Signed-off-by: Mark Brown --- arch/arm64/include/asm/fpsimd.h | 10 ++ arch/arm64/include/asm/kvm_host.h | 25 +++-- arch/arm64/kvm/fpsimd.c | 26 +++-- arch/arm64/kvm/hyp/include/hyp/switch.h | 173 ++++++++++++++++++++++++++++= ++-- arch/arm64/kvm/hyp/nvhe/hyp-main.c | 127 +++++++++++++++++++---- 5 files changed, 319 insertions(+), 42 deletions(-) diff --git a/arch/arm64/include/asm/fpsimd.h b/arch/arm64/include/asm/fpsim= d.h index c3da16fdb158..9806b75e5e4c 100644 --- a/arch/arm64/include/asm/fpsimd.h +++ b/arch/arm64/include/asm/fpsimd.h @@ -431,6 +431,15 @@ static inline void sve_user_enable(void) write_sysreg_s(__new, (reg)); \ } while (0) =20 +#define sme_cond_update_smcr_vq(val, reg) \ + do { \ + u64 __smcr =3D read_sysreg_s((reg)); \ + u64 __new =3D __smcr & ~SMCR_ELx_LEN_MASK; \ + __new |=3D (val) & SMCR_ELx_LEN_MASK; \ + if (__smcr !=3D __new) \ + write_sysreg_s(__new, (reg)); \ + } while (0) + /* * Probing and setup functions. * Calls to these functions must be serialised with one another. @@ -549,6 +558,7 @@ static inline void sve_user_disable(void) { BUILD_BUG()= ; } static inline void sve_user_enable(void) { BUILD_BUG(); } =20 #define sve_cond_update_zcr_vq(val, reg) do { } while (0) +#define sme_cond_update_smcr_vq(val, reg) do { } while (0) =20 static inline void vec_init_vq_map(enum vec_type t) { } static inline void vec_update_vq_map(enum vec_type t) { } diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm= _host.h index b78c039cb5ec..26ad8962b65d 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -1126,6 +1126,9 @@ struct kvm_vcpu_arch { #define vcpu_sve_zcr_elx(vcpu) \ (unlikely(is_hyp_ctxt(vcpu)) ? ZCR_EL2 : ZCR_EL1) =20 +#define vcpu_sme_smcr_elx(vcpu) \ + (unlikely(is_hyp_ctxt(vcpu)) ? SMCR_EL2 : SMCR_EL1) + #define sve_state_size_from_vl(sve_max_vl) ({ \ size_t __size_ret; \ unsigned int __vq; \ @@ -1140,10 +1143,20 @@ struct kvm_vcpu_arch { __size_ret; \ }) =20 -#define vcpu_sve_state_size(vcpu) sve_state_size_from_vl(vcpu_sve_max_vl(v= cpu)) +#define vcpu_sve_state_size(vcpu) sve_state_size_from_vl(vcpu_max_vl(vcpu)) =20 #define vcpu_sme_state(vcpu) (kern_hyp_va((vcpu)->arch.sme_state)) =20 +/* + * Always provide space for ZT0 to avoid ordering requirements with ID + * register writes and vector finalization. + */ +#define vcpu_sme_state_size(vcpu) ({ \ + unsigned long __vl; \ + __vl =3D (vcpu)->arch.max_vl[ARM64_VEC_SME]; \ + sme_state_size_from_vl(__vl, system_supports_sme2()); \ +}) + #define sme_state_size_from_vl(vl, sme2) ({ \ size_t __size_ret; \ unsigned int __vq; \ @@ -1160,16 +1173,6 @@ struct kvm_vcpu_arch { __size_ret; \ }) =20 -/* - * Always provide space for ZT0 to avoid ordering requirements with ID - * register writes and vector finalization. - */ -#define vcpu_sme_state_size(vcpu) ({ \ - unsigned long __vl; \ - __vl =3D (vcpu)->arch.max_vl[ARM64_VEC_SME]; \ - sme_state_size_from_vl(__vl, system_supports_sme2()); \ -}) - #define KVM_GUESTDBG_VALID_MASK (KVM_GUESTDBG_ENABLE | \ KVM_GUESTDBG_USE_SW_BP | \ KVM_GUESTDBG_USE_HW | \ diff --git a/arch/arm64/kvm/fpsimd.c b/arch/arm64/kvm/fpsimd.c index 567dd43970c5..bb0bf8d81522 100644 --- a/arch/arm64/kvm/fpsimd.c +++ b/arch/arm64/kvm/fpsimd.c @@ -83,19 +83,24 @@ void kvm_arch_vcpu_ctxsync_fp(struct kvm_vcpu *vcpu) WARN_ON_ONCE(!irqs_disabled()); =20 if (guest_owns_fp_regs()) { - /* - * Currently we do not support SME guests so SVCR is - * always 0 and we just need a variable to point to. - */ fp_state.st =3D &vcpu->arch.ctxt.fp_regs; fp_state.sve_state =3D vcpu->arch.sve_state; fp_state.zcr =3D vcpu_sve_max_vq(vcpu) - 1; - fp_state.smcr =3D 0; - fp_state.sme_state =3D NULL; + fp_state.smcr =3D vcpu_sme_max_vq(vcpu) - 1; + fp_state.sme_state =3D vcpu->arch.sme_state; fp_state.svcr =3D __ctxt_sys_reg(&vcpu->arch.ctxt, SVCR); fp_state.fpmr =3D __ctxt_sys_reg(&vcpu->arch.ctxt, FPMR); fp_state.fp_type =3D &vcpu->arch.fp_type; =20 + if (kvm_has_fa64(vcpu->kvm)) + fp_state.smcr |=3D SMCR_ELx_FA64; + if (kvm_has_sme2(vcpu->kvm)) + fp_state.smcr |=3D SMCR_ELx_EZT0; + + /* + * For SME only guests fpsimd_save() will override the + * state selection if we are in streaming mode. + */ if (vcpu_has_sve(vcpu)) fp_state.to_save =3D FP_STATE_SVE; else @@ -104,6 +109,15 @@ void kvm_arch_vcpu_ctxsync_fp(struct kvm_vcpu *vcpu) fpsimd_bind_state_to_cpu(&fp_state); =20 clear_thread_flag(TIF_FOREIGN_FPSTATE); + } else { + /* + * We might have enabled SME to configure traps but + * insist the host doesn't run the hypervisor with SME + * enabled, ensure it's disabled again. + */ + if (system_supports_sme()) { + sme_smstop(); + } } } =20 diff --git a/arch/arm64/kvm/hyp/include/hyp/switch.h b/arch/arm64/kvm/hyp/i= nclude/hyp/switch.h index e444f0a94dcf..7c913da9babb 100644 --- a/arch/arm64/kvm/hyp/include/hyp/switch.h +++ b/arch/arm64/kvm/hyp/include/hyp/switch.h @@ -462,6 +462,28 @@ static inline bool kvm_hyp_handle_mops(struct kvm_vcpu= *vcpu, u64 *exit_code) return true; } =20 +static inline void __hyp_sme_restore_guest(struct kvm_vcpu *vcpu, + bool *restore_sve, + bool *restore_ffr) +{ + /* + * The vCPU's saved SVE state layout always matches the max VL of the + * vCPU. Start off with the max VL so we can load the SVE state. + */ + sme_cond_update_smcr_vq(vcpu_sme_max_vq(vcpu) - 1, SYS_SMCR_EL2); + + if (vcpu_in_streaming_mode(vcpu)) { + *restore_sve =3D true; + *restore_ffr =3D vcpu_has_fa64(vcpu); + } + + if (vcpu_za_enabled(vcpu)) + sme_load_state(kern_hyp_va(vcpu->arch.sme_state), + vcpu_has_sme2(vcpu)); + + write_sysreg_el1(__vcpu_sys_reg(vcpu, vcpu_sme_smcr_elx(vcpu)), SYS_SMCR); +} + static inline void __hyp_sve_restore_guest(struct kvm_vcpu *vcpu) { u64 zcr_el2 =3D vcpu_sve_max_vq(vcpu) - 1; @@ -471,20 +493,34 @@ static inline void __hyp_sve_restore_guest(struct kvm= _vcpu *vcpu) * vCPU. Start off with the max VL so we can load the SVE state. */ sve_cond_update_zcr_vq(zcr_el2, SYS_ZCR_EL2); - sve_load_state(kern_hyp_va(vcpu->arch.sve_state), true); - fpsimd_load_common(&vcpu->arch.ctxt.fp_regs); + write_sysreg_el1(__vcpu_sys_reg(vcpu, vcpu_sve_zcr_elx(vcpu)), SYS_ZCR); +} + +static inline void __hyp_nv_restore_guest_vls(struct kvm_vcpu *vcpu) +{ + if (!is_nested_ctxt(vcpu)) + return; =20 /* * The effective VL for a VM could differ from the max VL when running a * nested guest, as the guest hypervisor could select a smaller VL. Slap * that into hardware before wrapping up. */ - if (is_nested_ctxt(vcpu)) { + + if (vcpu_has_sve(vcpu)) { + u64 zcr_el2 =3D vcpu_sve_max_vq(vcpu) - 1; + zcr_el2 =3D min(zcr_el2, __vcpu_sys_reg(vcpu, ZCR_EL2)); sve_cond_update_zcr_vq(zcr_el2, SYS_ZCR_EL2); } =20 - write_sysreg_el1(__vcpu_sys_reg(vcpu, vcpu_sve_zcr_elx(vcpu)), SYS_ZCR); + if (vcpu_has_sme(vcpu)) { + u64 max_len =3D vcpu_sme_max_vq(vcpu) - 1; + u64 smcr_len =3D SYS_FIELD_GET(SMCR_ELx, LEN, + __vcpu_sys_reg(vcpu, SMCR_EL2)); + + sme_cond_update_smcr_vq(min(smcr_len, max_len), SYS_SMCR_EL2); + } } =20 static inline void __hyp_sve_save_host(void) @@ -498,10 +534,48 @@ static inline void __hyp_sve_save_host(void) fpsimd_save_common(&hctxt->fp_regs); } =20 +static inline void kvm_sme_configure_traps(struct kvm_vcpu *vcpu) +{ + u64 smcr_el1, smcr_el2, guest_el2_len, svcr; + + if (!vcpu_has_sme(vcpu)) + return; + + smcr_el2 =3D vcpu_sme_max_vq(vcpu) - 1; + + /* A guest hypervisor may restrict the effective max VL. */ + if (is_nested_ctxt(vcpu)) { + guest_el2_len =3D SYS_FIELD_GET(SMCR_ELx, LEN, + __vcpu_sys_reg(vcpu, SMCR_EL2)); + smcr_el2 =3D min(smcr_el2, guest_el2_len); + } + + if (vcpu_has_fa64(vcpu)) + smcr_el2 |=3D SMCR_ELx_FA64; + if (vcpu_has_sme2(vcpu)) + smcr_el2 |=3D SMCR_ELx_EZT0; + + write_sysreg_el2(smcr_el2, SYS_SMCR); + + smcr_el1 =3D __vcpu_sys_reg(vcpu, vcpu_sme_smcr_elx(vcpu)); + write_sysreg_el1(smcr_el1, SYS_SMCR); + + svcr =3D __vcpu_sys_reg(vcpu, SVCR); + write_sysreg_s(svcr, SYS_SVCR); +} + static inline void fpsimd_lazy_switch_to_guest(struct kvm_vcpu *vcpu) { u64 zcr_el1, zcr_el2; =20 + /* + * We always load the SME control registers that affect traps + * since if they are not configured as expected by the guest + * then it may have exceptions that it does not expect + * directly delivered. + */ + kvm_sme_configure_traps(vcpu); + if (!guest_owns_fp_regs()) return; =20 @@ -555,8 +629,57 @@ static inline void sve_lazy_switch_to_host(struct kvm_= vcpu *vcpu) } } =20 +static inline void sme_lazy_switch_to_host(struct kvm_vcpu *vcpu) +{ + u64 smcr_el1, smcr_el2; + + if (!vcpu_has_sme(vcpu)) + return; + + /* + * __deactivate_cptr_traps() disabled traps, but there hasn't + * necessarily been a context synchronization event yet. + */ + isb(); + + smcr_el1 =3D read_sysreg_el1(SYS_SMCR); + __vcpu_assign_sys_reg(vcpu, vcpu_sme_smcr_elx(vcpu), smcr_el1); + + smcr_el2 =3D 0; + if (system_supports_fa64()) + smcr_el2 |=3D SMCR_ELx_FA64; + if (system_supports_sme2()) + smcr_el2 |=3D SMCR_ELx_EZT0; + + /* + * The guest's state is always saved using the guest's max VL. + * Ensure that the host has the guest's max VL active such + * that the host can save the guest's state lazily, but don't + * artificially restrict the host to the guest's max VL. + */ + if (has_vhe()) { + smcr_el2 |=3D vcpu_sme_max_vq(vcpu) - 1; + write_sysreg_el2(smcr_el2, SYS_SMCR); + } else { + smcr_el1 =3D smcr_el2; + smcr_el2 |=3D sve_vq_from_vl(kvm_host_max_vl[ARM64_VEC_SME]) - 1; + write_sysreg_el2(smcr_el2, SYS_SMCR); + + smcr_el1 |=3D vcpu_sme_max_vq(vcpu) - 1; + write_sysreg_el1(smcr_el1, SYS_SMCR); + } + + __vcpu_assign_sys_reg(vcpu, SVCR, read_sysreg_s(SYS_SVCR)); +} + static inline void fpsimd_lazy_switch_to_host(struct kvm_vcpu *vcpu) { + /* + * We always load the control registers for the guest so we + * always restore state for the host. + */ + sme_lazy_switch_to_host(vcpu); + if (!guest_owns_fp_regs()) return; =20 @@ -567,6 +690,16 @@ static void kvm_hyp_save_fpsimd_host(struct kvm_vcpu *= vcpu) { struct kvm_cpu_context *hctxt =3D host_data_ptr(host_ctxt); =20 + /* + * The hypervisor refuses to run if streaming mode or ZA is + * enabled, we only need to save SMCR_EL1 for SME. For pKVM + * we will restore this, reset SMCR_EL2 to a fixed value and + * disable streaming mode and ZA to avoid any state being + * leaked. + */ + if (system_supports_sme()) + ctxt_sys_reg(hctxt, SMCR_EL1) =3D read_sysreg_el1(SYS_SMCR); + /* * Non-protected kvm relies on the host restoring its sve state. * Protected kvm restores the host's sve state as not to reveal that @@ -591,14 +724,17 @@ static void kvm_hyp_save_fpsimd_host(struct kvm_vcpu = *vcpu) */ static inline bool kvm_hyp_handle_fpsimd(struct kvm_vcpu *vcpu, u64 *exit_= code) { - bool sve_guest; - u8 esr_ec; + bool restore_sve, restore_ffr; + bool sve_guest, sme_guest; + u8 esr_ec, esr_iss_smtc; =20 if (!system_supports_fpsimd()) return false; =20 sve_guest =3D vcpu_has_sve(vcpu); + sme_guest =3D vcpu_has_sme(vcpu); esr_ec =3D kvm_vcpu_trap_get_class(vcpu); + esr_iss_smtc =3D ESR_ELx_SME_ISS_SMTC((kvm_vcpu_get_esr(vcpu))); =20 /* Only handle traps the vCPU can support here: */ switch (esr_ec) { @@ -617,6 +753,15 @@ static inline bool kvm_hyp_handle_fpsimd(struct kvm_vc= pu *vcpu, u64 *exit_code) if (guest_hyp_sve_traps_enabled(vcpu)) return false; break; + case ESR_ELx_EC_SME: + if (!sme_guest) + return false; + if (guest_hyp_sme_traps_enabled(vcpu)) + return false; + if (!kvm_has_sme2(kern_hyp_va(vcpu->kvm)) && + (esr_iss_smtc =3D=3D ESR_ELx_SME_ISS_SMTC_ZT_DISABLED)) + return false; + break; default: return false; } @@ -632,10 +777,22 @@ static inline bool kvm_hyp_handle_fpsimd(struct kvm_v= cpu *vcpu, u64 *exit_code) kvm_hyp_save_fpsimd_host(vcpu); =20 /* Restore the guest state */ + + /* These may be overridden for a SME guest */ + restore_sve =3D sve_guest; + restore_ffr =3D sve_guest; + if (sve_guest) __hyp_sve_restore_guest(vcpu); - else + if (sme_guest) + __hyp_sme_restore_guest(vcpu, &restore_sve, &restore_ffr); + + if (restore_sve) { + sve_load_state(kern_hyp_va(vcpu->arch.sve_state), restore_ffr); + fpsimd_load_common(&vcpu->arch.ctxt.fp_regs); + } else { fpsimd_load_state(&vcpu->arch.ctxt.fp_regs); + } =20 if (kvm_has_fpmr(kern_hyp_va(vcpu->kvm))) write_sysreg_s(__vcpu_sys_reg(vcpu, FPMR), SYS_FPMR); @@ -644,6 +801,8 @@ static inline bool kvm_hyp_handle_fpsimd(struct kvm_vcp= u *vcpu, u64 *exit_code) if (!(read_sysreg(hcr_el2) & HCR_RW)) write_sysreg(__vcpu_sys_reg(vcpu, FPEXC32_EL2), fpexc32_el2); =20 + __hyp_nv_restore_guest_vls(vcpu); + *host_data_ptr(fp_owner) =3D FP_STATE_GUEST_OWNED; =20 /* diff --git a/arch/arm64/kvm/hyp/nvhe/hyp-main.c b/arch/arm64/kvm/hyp/nvhe/h= yp-main.c index 14e24e257dcc..0f6e3479a7e4 100644 --- a/arch/arm64/kvm/hyp/nvhe/hyp-main.c +++ b/arch/arm64/kvm/hyp/nvhe/hyp-main.c @@ -31,16 +31,28 @@ void __kvm_hyp_host_forward_smc(struct kvm_cpu_context = *host_ctxt); =20 static void __hyp_sve_save_guest(struct kvm_vcpu *vcpu) { - __vcpu_assign_sys_reg(vcpu, ZCR_EL1, read_sysreg_el1(SYS_ZCR)); - /* - * On saving/restoring guest sve state, always use the maximum VL for - * the guest. The layout of the data when saving the sve state depends - * on the VL, so use a consistent (i.e., the maximum) guest VL. - */ - sve_cond_update_zcr_vq(vcpu_sve_max_vq(vcpu) - 1, SYS_ZCR_EL2); - sve_save_state(kern_hyp_va(vcpu->arch.sve_state), true); + bool save_ffr =3D !vcpu_in_streaming_mode(vcpu) || vcpu_has_fa64(vcpu); + + if (vcpu_has_sve(vcpu)) { + __vcpu_assign_sys_reg(vcpu, ZCR_EL1, read_sysreg_el1(SYS_ZCR)); + + /* + * On saving/restoring guest sve state, always use the + * maximum VL for the guest. The layout of the data + * when saving the sve state depends on the VL, so use + * a consistent (i.e., the maximum) guest VL. + */ + sve_cond_update_zcr_vq(vcpu_sve_max_vq(vcpu) - 1, SYS_ZCR_EL2); + } + + /* Ensure ZCR/SMCR updates for VL are seen */ + isb(); + sve_save_state(kern_hyp_va(vcpu->arch.sve_state), save_ffr); fpsimd_save_common(&vcpu->arch.ctxt.fp_regs); - write_sysreg_s(sve_vq_from_vl(kvm_host_max_vl[ARM64_VEC_SVE]) - 1, SYS_ZC= R_EL2); + + if (system_supports_sve()) + write_sysreg_s(sve_vq_from_vl(kvm_host_max_vl[ARM64_VEC_SVE]) - 1, + SYS_ZCR_EL2); } =20 static void __hyp_sve_restore_host(void) @@ -63,9 +75,76 @@ static void __hyp_sve_restore_host(void) write_sysreg_el1(ctxt_sys_reg(hctxt, ZCR_EL1), SYS_ZCR); } =20 -static void fpsimd_sve_flush(void) +static void __hyp_sme_save_guest(struct kvm_vcpu *vcpu) { - *host_data_ptr(fp_owner) =3D FP_STATE_HOST_OWNED; + unsigned long smcr_el2; + + __vcpu_assign_sys_reg(vcpu, SMCR_EL1, read_sysreg_el1(SYS_SMCR)); + __vcpu_assign_sys_reg(vcpu, SVCR, read_sysreg_s(SYS_SVCR)); + + /* + * On saving/restoring guest sve state, always use the maximum VL for + * the guest. The layout of the data when saving the sve state depends + * on the VL, so use a consistent (i.e., the maximum) guest VL. + * + * We restore the FA64 and SME2 enables for the host since we + * will always restore the host configuration so if host and + * guest VLs are the same we might suppress an update. + */ + smcr_el2 =3D vcpu_sme_max_vq(vcpu) - 1; + if (system_supports_fa64()) + smcr_el2 |=3D SMCR_ELx_FA64; + if (system_supports_sme2()) + smcr_el2 |=3D SMCR_ELx_EZT0; + sysreg_cond_update_s(SYS_SMCR_EL2, smcr_el2); + + if (vcpu_za_enabled(vcpu)) { + isb(); + sme_save_state(vcpu_sme_state(vcpu), vcpu_has_sme2(vcpu)); + } +} + +static void __hyp_sme_restore_host(void) +{ + struct kvm_cpu_context *hctxt =3D host_data_ptr(host_ctxt); + u64 smcr_el2; + + /* + * The hypervisor refuses to run if we are in streaming mode + * or have ZA enabled so there is no SME specific state to + * restore other than the system registers. + * + * Note that this constrains the PE to the maximum shared VL + * that was discovered, if we wish to use larger VLs this will + * need to be revisited. + */ + smcr_el2 =3D sve_vq_from_vl(kvm_host_max_vl[ARM64_VEC_SME]) - 1; + if (system_supports_fa64()) + smcr_el2 |=3D SMCR_ELx_FA64; + if (system_supports_sme2()) + smcr_el2 |=3D SMCR_ELx_EZT0; + sysreg_cond_update_s(SYS_SMCR_EL2, smcr_el2); + + write_sysreg_el1(ctxt_sys_reg(hctxt, SMCR_EL1), SYS_SMCR); + sme_smstop(); +} + +static void fpsimd_sve_flush(struct kvm_vcpu *vcpu) +{ + /* + * If the guest has SME then we need to restore the trap + * controls in SMCR and mode in SVCR in order to ensure that + * traps generated directly to EL1 have the correct types, + * otherwise we can defer until we load the guest state. + */ + if (vcpu_has_sme(vcpu)) { + kvm_hyp_save_fpsimd_host(vcpu); + kvm_sme_configure_traps(vcpu); + + *host_data_ptr(fp_owner) =3D FP_STATE_FREE; + } else { + *host_data_ptr(fp_owner) =3D FP_STATE_HOST_OWNED; + } } =20 static void fpsimd_sve_sync(struct kvm_vcpu *vcpu) @@ -73,8 +152,15 @@ static void fpsimd_sve_sync(struct kvm_vcpu *vcpu) struct kvm_cpu_context *hctxt =3D host_data_ptr(host_ctxt); bool has_fpmr; =20 - if (!guest_owns_fp_regs()) + if (!guest_owns_fp_regs()) { + /* + * We always at least partially configure SME for the + * guest due to traps. + */ + if (system_supports_sme()) + __hyp_sme_restore_host(); return; + } =20 /* * Traps have been disabled by __deactivate_cptr_traps(), but there @@ -82,7 +168,10 @@ static void fpsimd_sve_sync(struct kvm_vcpu *vcpu) */ isb(); =20 - if (vcpu_has_sve(vcpu)) + if (vcpu_has_sme(vcpu)) + __hyp_sme_save_guest(vcpu); + + if (vcpu_has_sve(vcpu) || vcpu_in_streaming_mode(vcpu)) __hyp_sve_save_guest(vcpu); else fpsimd_save_state(&vcpu->arch.ctxt.fp_regs); @@ -91,6 +180,9 @@ static void fpsimd_sve_sync(struct kvm_vcpu *vcpu) if (has_fpmr) __vcpu_assign_sys_reg(vcpu, FPMR, read_sysreg_s(SYS_FPMR)); =20 + if (system_supports_sme()) + __hyp_sme_restore_host(); + if (system_supports_sve()) __hyp_sve_restore_host(); else @@ -128,7 +220,7 @@ static void flush_hyp_vcpu(struct pkvm_hyp_vcpu *hyp_vc= pu) { struct kvm_vcpu *host_vcpu =3D hyp_vcpu->host_vcpu; =20 - fpsimd_sve_flush(); + fpsimd_sve_flush(host_vcpu); flush_debug_state(hyp_vcpu); =20 hyp_vcpu->vcpu.arch.ctxt =3D host_vcpu->arch.ctxt; @@ -223,10 +315,9 @@ static void handle___kvm_vcpu_run(struct kvm_cpu_conte= xt *host_ctxt) struct pkvm_hyp_vcpu *hyp_vcpu =3D pkvm_get_loaded_hyp_vcpu(); =20 /* - * KVM (and pKVM) doesn't support SME guests for now, and - * ensures that SME features aren't enabled in pstate when - * loading a vcpu. Therefore, if SME features enabled the host - * is misbehaving. + * KVM (and pKVM) refuses to run if PSTATE.{SM,ZA} are + * enabled. Therefore, if SME features enabled the + * host is misbehaving. */ if (unlikely(system_supports_sme() && read_sysreg_s(SYS_SVCR))) { ret =3D -EINVAL; --=20 2.47.3 From nobody Fri Jul 10 06:02:12 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 446C243F8B4; Thu, 9 Jul 2026 18:41:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783622512; cv=none; b=QNmWQcmwYxUYSuspNcYZZKUpwXqXftCOG2gboe4Z5qkcaPEgacjCv0dvFtSG/kFLmN+rDgMqL9uK6lhd1MmJ/jOkK60w0+rRaGopBFHS0q066F7HIVyB3zioYzyPMatLA+3QgUs591ABTC97aH4WiUuSDAvNyCYeNlEvdzqc5L4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783622512; c=relaxed/simple; bh=x/XFPzNN5/J6G5E0oqhJf08B8/sFJa7dJ49zCMEJE/4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=q44wQOUejtiOeDeGuK4/9tdpJVRBsG9VdXbNmd8OaxPv4ScAkmQ8P92+mmryLdz03Em8zHKQjTgLYKFsFMebKzNCloBT3Ns1NfDKg5xys1Ic1/NluncbHlgRxyTB84f+rjnGoJdApMA8ZhsCRmPR3iA5xreC11Vsqepb3fnQwGg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=QgMOA0S+; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="QgMOA0S+" Received: by smtp.kernel.org (Postfix) with ESMTPSA id BBB701F00A3A; Thu, 9 Jul 2026 18:41:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1783622510; bh=lXCEStw7jpxbfMPkl2Z/72HpjmmD/RSWBvdz3qpCcgU=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=QgMOA0S+Y4eap5dVYMkcLnL/Ry5Xm/wsb+x1Cj4O6YRiaArIgeBcRxmDUbKTR2Xpf UUY83AMKg6kZWp5Re3DwHf4LyUxrAbjP5Isn+KafFjvzA6K4vYJWEo217zhnKq8ZGQ AUjtNh8sfi/ip2yWrJD23Gu8ptPYgMK8rMJBiMFk3cJGL/Hh7ttdo79mtPK6oo9y8U 8TWW5TNL1Agzy6nd+9ttMJi6RvuVtAkk2DvdAJREgJiTMKK9HglKo6JnccFQvDuZwU M7k6ZVYvP2WRQ8HdOUkiW51+LEJgGhV96INcGQ3awJ/hTIciHn21ljS95CSooVtFbg JBCzjGgyKR8TQ== From: Mark Brown Date: Thu, 09 Jul 2026 19:27:44 +0100 Subject: [PATCH v12 23/29] KVM: arm64: Handle SME exceptions Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260709-kvm-arm64-sme-v12-23-d0301d79ef58@kernel.org> References: <20260709-kvm-arm64-sme-v12-0-d0301d79ef58@kernel.org> In-Reply-To: <20260709-kvm-arm64-sme-v12-0-d0301d79ef58@kernel.org> To: Marc Zyngier , Joey Gouly , Catalin Marinas , Suzuki K Poulose , Will Deacon , Paolo Bonzini , Jonathan Corbet , Shuah Khan , Oliver Upton Cc: Dave Martin , Fuad Tabba , Mark Rutland , Ben Horgan , Jean-Philippe Brucker , linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Peter Maydell , Eric Auger , Mark Brown X-Mailer: b4 0.16-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=6115; i=broonie@kernel.org; h=from:subject:message-id; bh=x/XFPzNN5/J6G5E0oqhJf08B8/sFJa7dJ49zCMEJE/4=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBqT+r8VGEq0Ppk21bwZmw/Ad5l8W+roobCEAC39 p/rAEneOFuJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCak/q/AAKCRAk1otyXVSH 0HAvB/9ZZ3LAZ0sJFynI6ylfiHczhjXwAbvQCmR2mK8S4I7ed29W8AD1V4vReLpAymk3bVXpug9 VJZrP3lzKlMTp/354zE/WGENmaWnAh2zLxGHKicNQummptbImVgMZP/6Wwzu5X5rrbAIeimpISB WmEZ2rX0xaMMhgy6vwgx/8lqEqF+dYmxo+A9U0ibDPSTBGjgjUMNtIXRz1/5k9NBF4ycOKpxJJL jf18L4y45ANVMuugAY/eY5VGhWZKrT5AGJZtPN9v4YLaOyyCCFkqL/OuX+KR+vY3zfVvpmykLKm EPdiLB+fCnc+BPGj5rihQdkIZGl/VB3v2SP8ske12xeMT5za X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB The access control for SME follows the same structure as for the base FP and SVE extensions, with control being via CPACR_ELx.SMEN and CPTR_EL2.TSM mirroring the equivalent FPSIMD and SVE controls in those registers. Add handling for these controls and exceptions mirroring the existing handling for FPSIMD and SVE. Reviewed-by: Fuad Tabba Signed-off-by: Mark Brown --- arch/arm64/kvm/handle_exit.c | 14 ++++++++++++++ arch/arm64/kvm/hyp/include/hyp/switch.h | 11 ++++++----- arch/arm64/kvm/hyp/nvhe/switch.c | 2 ++ arch/arm64/kvm/hyp/vhe/switch.c | 17 ++++++++++++----- 4 files changed, 34 insertions(+), 10 deletions(-) diff --git a/arch/arm64/kvm/handle_exit.c b/arch/arm64/kvm/handle_exit.c index 54aedf93c78b..e69bdb87f19d 100644 --- a/arch/arm64/kvm/handle_exit.c +++ b/arch/arm64/kvm/handle_exit.c @@ -237,6 +237,19 @@ static int handle_sve(struct kvm_vcpu *vcpu) return 1; } =20 +/* + * Guest access to SME registers should be routed to this handler only + * when the system doesn't support SME. + */ +static int handle_sme(struct kvm_vcpu *vcpu) +{ + if (guest_hyp_sme_traps_enabled(vcpu)) + return kvm_inject_nested_sync(vcpu, kvm_vcpu_get_esr(vcpu)); + + kvm_inject_undefined(vcpu); + return 1; +} + /* * Two possibilities to handle a trapping ptrauth instruction: * @@ -390,6 +403,7 @@ static exit_handle_fn arm_exit_handlers[] =3D { [ESR_ELx_EC_SVC64] =3D handle_svc, [ESR_ELx_EC_SYS64] =3D kvm_handle_sys_reg, [ESR_ELx_EC_SVE] =3D handle_sve, + [ESR_ELx_EC_SME] =3D handle_sme, [ESR_ELx_EC_ERET] =3D kvm_handle_eret, [ESR_ELx_EC_IABT_LOW] =3D kvm_handle_guest_abort, [ESR_ELx_EC_DABT_LOW] =3D kvm_handle_guest_abort, diff --git a/arch/arm64/kvm/hyp/include/hyp/switch.h b/arch/arm64/kvm/hyp/i= nclude/hyp/switch.h index 7c913da9babb..47f523a37cbe 100644 --- a/arch/arm64/kvm/hyp/include/hyp/switch.h +++ b/arch/arm64/kvm/hyp/include/hyp/switch.h @@ -67,11 +67,8 @@ static inline void __activate_cptr_traps_nvhe(struct kvm= _vcpu *vcpu) { u64 val =3D CPTR_NVHE_EL2_RES1 | CPTR_EL2_TAM | CPTR_EL2_TTA; =20 - /* - * Always trap SME since it's not supported in KVM. - * TSM is RES1 if SME isn't implemented. - */ - val |=3D CPTR_EL2_TSM; + if (!vcpu_has_sme(vcpu) || !guest_owns_fp_regs()) + val |=3D CPTR_EL2_TSM; =20 if (!vcpu_has_sve(vcpu) || !guest_owns_fp_regs()) val |=3D CPTR_EL2_TZ; @@ -99,6 +96,8 @@ static inline void __activate_cptr_traps_vhe(struct kvm_v= cpu *vcpu) val |=3D CPACR_EL1_FPEN; if (vcpu_has_sve(vcpu)) val |=3D CPACR_EL1_ZEN; + if (vcpu_has_sme(vcpu)) + val |=3D CPACR_EL1_SMEN; } =20 if (!vcpu_has_nv(vcpu)) @@ -140,6 +139,8 @@ static inline void __activate_cptr_traps_vhe(struct kvm= _vcpu *vcpu) val &=3D ~CPACR_EL1_FPEN; if (!(SYS_FIELD_GET(CPACR_EL1, ZEN, cptr) & BIT(0))) val &=3D ~CPACR_EL1_ZEN; + if (!(SYS_FIELD_GET(CPACR_EL1, SMEN, cptr) & BIT(0))) + val &=3D ~CPACR_EL1_SMEN; =20 if (kvm_has_feat(vcpu->kvm, ID_AA64MMFR3_EL1, S1POE, IMP)) val |=3D cptr & CPACR_EL1_E0POE; diff --git a/arch/arm64/kvm/hyp/nvhe/switch.c b/arch/arm64/kvm/hyp/nvhe/swi= tch.c index 7318e3e6a5f3..2d5029dbfb00 100644 --- a/arch/arm64/kvm/hyp/nvhe/switch.c +++ b/arch/arm64/kvm/hyp/nvhe/switch.c @@ -196,6 +196,7 @@ static const exit_handler_fn hyp_exit_handlers[] =3D { [ESR_ELx_EC_CP15_32] =3D kvm_hyp_handle_cp15_32, [ESR_ELx_EC_SYS64] =3D kvm_hyp_handle_sysreg, [ESR_ELx_EC_SVE] =3D kvm_hyp_handle_fpsimd, + [ESR_ELx_EC_SME] =3D kvm_hyp_handle_fpsimd, [ESR_ELx_EC_FP_ASIMD] =3D kvm_hyp_handle_fpsimd, [ESR_ELx_EC_IABT_LOW] =3D kvm_hyp_handle_iabt_low, [ESR_ELx_EC_DABT_LOW] =3D kvm_hyp_handle_dabt_low, @@ -208,6 +209,7 @@ static const exit_handler_fn pvm_exit_handlers[] =3D { [ESR_ELx_EC_HVC64] =3D kvm_handle_pvm_hvc64, [ESR_ELx_EC_SYS64] =3D kvm_handle_pvm_sys64, [ESR_ELx_EC_SVE] =3D kvm_handle_pvm_restricted, + [ESR_ELx_EC_SME] =3D kvm_handle_pvm_restricted, [ESR_ELx_EC_FP_ASIMD] =3D kvm_hyp_handle_fpsimd, [ESR_ELx_EC_IABT_LOW] =3D kvm_hyp_handle_iabt_low, [ESR_ELx_EC_DABT_LOW] =3D kvm_hyp_handle_dabt_low, diff --git a/arch/arm64/kvm/hyp/vhe/switch.c b/arch/arm64/kvm/hyp/vhe/switc= h.c index bbe9cebd3d9d..5fc677afcaf9 100644 --- a/arch/arm64/kvm/hyp/vhe/switch.c +++ b/arch/arm64/kvm/hyp/vhe/switch.c @@ -458,22 +458,28 @@ static bool kvm_hyp_handle_cpacr_el1(struct kvm_vcpu = *vcpu, u64 *exit_code) return true; } =20 -static bool kvm_hyp_handle_zcr_el2(struct kvm_vcpu *vcpu, u64 *exit_code) +static bool kvm_hyp_handle_vec_cr_el2(struct kvm_vcpu *vcpu, u64 *exit_cod= e) { u32 sysreg =3D esr_sys64_to_sysreg(kvm_vcpu_get_esr(vcpu)); =20 if (!vcpu_has_nv(vcpu)) return false; =20 - if (sysreg !=3D SYS_ZCR_EL2) + switch (sysreg) { + case SYS_ZCR_EL2: + case SYS_SMCR_EL2: + break; + default: return false; + } =20 if (guest_owns_fp_regs()) return false; =20 /* - * ZCR_EL2 traps are handled in the slow path, with the expectation - * that the guest's FP context has already been loaded onto the CPU. + * ZCR_EL2 and SMCR_EL2 traps are handled in the slow path, + * with the expectation that the guest's FP context has + * already been loaded onto the CPU. * * Load the guest's FP context and unconditionally forward to the * slow path for handling (i.e. return false). @@ -493,7 +499,7 @@ static bool kvm_hyp_handle_sysreg_vhe(struct kvm_vcpu *= vcpu, u64 *exit_code) if (kvm_hyp_handle_cpacr_el1(vcpu, exit_code)) return true; =20 - if (kvm_hyp_handle_zcr_el2(vcpu, exit_code)) + if (kvm_hyp_handle_vec_cr_el2(vcpu, exit_code)) return true; =20 return kvm_hyp_handle_sysreg(vcpu, exit_code); @@ -522,6 +528,7 @@ static const exit_handler_fn hyp_exit_handlers[] =3D { [0 ... ESR_ELx_EC_MAX] =3D NULL, [ESR_ELx_EC_CP15_32] =3D kvm_hyp_handle_cp15_32, [ESR_ELx_EC_SYS64] =3D kvm_hyp_handle_sysreg_vhe, + [ESR_ELx_EC_SME] =3D kvm_hyp_handle_fpsimd, [ESR_ELx_EC_SVE] =3D kvm_hyp_handle_fpsimd, [ESR_ELx_EC_FP_ASIMD] =3D kvm_hyp_handle_fpsimd, [ESR_ELx_EC_IABT_LOW] =3D kvm_hyp_handle_iabt_low, --=20 2.47.3 From nobody Fri Jul 10 06:02:12 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C6F5B43FD08; Thu, 9 Jul 2026 18:41:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783622518; cv=none; b=S+siQb14Es6TmqUH23E45uHvAafaeRrSAYI9CqCH9+4wSH+SY5u7OfbNH8KzZ/8/obnWme4eWwVPuw9lkuWXkJe+bKlI+f4e8JjwFN0S4k42Nps7a67RXT44yoPiKO/N9GXD8jYuOUMgYrve8rDNsjfP+SdNVwDxTuR7hEmY05M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783622518; c=relaxed/simple; bh=tZf10BakJWINVrDfcuSYxIcK5/guAElrikKeFmB4JK0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=NA8inWEea4UAQ7hqqOL8Y5RAT2gFAUljSmYfqCyuzibb7sc5ZLhbIwgkGO+X3XTFS9lN9DUDKYYeSgaKHabLZl6W/cp1aOCuzyxlpbEPbUJqcLGEG4tCdtbE28aotfjn6bF2p++CnNVgAfbBln0/arxUSxmyQaSErAQkPBKoSVo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=hHF/IZz1; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="hHF/IZz1" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4CA941F00A3D; Thu, 9 Jul 2026 18:41:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1783622515; bh=/bSVn4A7P2buqPsSBN19q3GFhevpNvbqSjxF/MHUfow=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=hHF/IZz1Ta9NxvzXbrgAoQr7FPeQrc7btiAG99TedhzuZi0hnE4M2DtIGWrkTnAj4 Oq6fw/BhUkqIP5ZgyRL9lAaEy7gdYZZ7CkRNltfLj+xPg33uPOHDiIly27cPw58dJR mjVkU1jDEYqYbCpCTzoIPGsSDo6LbttWupVgVlzskUSh0QE4ZMXUDJsPeu+ew8QPte BMgrRKMpCYs0Ta4ESgz8T/DUmAQz8Z8qT2jh3lB7wsXJnQWzqTuwDmIx5s+Y4RtoaC 3jM4NSFIER4ybY7S8dw7Cktp0LGtCp6APsPob/lm1jWwavvfAbt0snzCa06yuZgsAF RMjouo73fBBAw== From: Mark Brown Date: Thu, 09 Jul 2026 19:27:45 +0100 Subject: [PATCH v12 24/29] KVM: arm64: Expose SME to nested guests Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260709-kvm-arm64-sme-v12-24-d0301d79ef58@kernel.org> References: <20260709-kvm-arm64-sme-v12-0-d0301d79ef58@kernel.org> In-Reply-To: <20260709-kvm-arm64-sme-v12-0-d0301d79ef58@kernel.org> To: Marc Zyngier , Joey Gouly , Catalin Marinas , Suzuki K Poulose , Will Deacon , Paolo Bonzini , Jonathan Corbet , Shuah Khan , Oliver Upton Cc: Dave Martin , Fuad Tabba , Mark Rutland , Ben Horgan , Jean-Philippe Brucker , linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Peter Maydell , Eric Auger , Mark Brown X-Mailer: b4 0.16-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=2042; i=broonie@kernel.org; h=from:subject:message-id; bh=tZf10BakJWINVrDfcuSYxIcK5/guAElrikKeFmB4JK0=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBqT+r8JU49KyKGDpAOFI1HLxI8tL/Q3krxUnOWR SWMOiagbCyJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCak/q/AAKCRAk1otyXVSH 0ImlCACFAAWNkDdIXe42uzKeF/ybrRNEroNV/kBk6OdMUcsyVMxABv/4XZo7lASAQk/L33JK+4g X0rlhQqFTJSqlrsDOZccQoTFD2mhqB0kkfoPJcNtY0LuA+jSQ+je96Le8Zn+KdBo3yaEHCMoCdh x7z7qZwQ/ucrWDldr1E7dB4tn7I7IQ++e8HQFJHpLH2+pWavZkUuMZpFM5tt9YeWr5gt/9mze9w clk3/8JVieuDHgOzpPSzC8ZfoVBN1THqxvZn8fIJoAr9gcZTIX+awgfcyECf8sdxX5zLigaCU6D 5mI82ANhCFQtKthM7cZonJ+Z+KR88wFrFetyKTiPQdzWXZlk X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB With support for context switching SME state in place allow access to SME in nested guests. The SME floating point state is handled along with all the other floating point state, SME specific floating point exceptions are directed into the same handlers as other floating point exceptions with NV specific handling for the vector lengths already in place. TPIDR2_EL0 is context switched along with the other TPIDRs as part of the main guest register context switch. SME priority support is currently masked from all guests including nested ones. Reviewed-by: Fuad Tabba Signed-off-by: Mark Brown --- arch/arm64/include/asm/kvm_nested.h | 2 ++ arch/arm64/kvm/nested.c | 3 +-- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm64/include/asm/kvm_nested.h b/arch/arm64/include/asm/k= vm_nested.h index cdf3e8422ea1..9df3cea39b09 100644 --- a/arch/arm64/include/asm/kvm_nested.h +++ b/arch/arm64/include/asm/kvm_nested.h @@ -42,6 +42,8 @@ static inline u64 translate_cptr_el2_to_cpacr_el1(u64 cpt= r_el2) cpacr_el1 |=3D CPACR_EL1_FPEN; if (!(cptr_el2 & CPTR_EL2_TZ)) cpacr_el1 |=3D CPACR_EL1_ZEN; + if (!(cptr_el2 & CPTR_EL2_TSM)) + cpacr_el1 |=3D CPACR_EL1_SMEN; =20 cpacr_el1 |=3D cptr_el2 & (CPTR_EL2_TCPAC | CPTR_EL2_TAM); =20 diff --git a/arch/arm64/kvm/nested.c b/arch/arm64/kvm/nested.c index 50e25ab9b604..fb6087426f95 100644 --- a/arch/arm64/kvm/nested.c +++ b/arch/arm64/kvm/nested.c @@ -1630,14 +1630,13 @@ u64 limit_nv_id_reg(struct kvm *kvm, u32 reg, u64 v= al) break; =20 case SYS_ID_AA64PFR1_EL1: - /* Only support BTI, SSBS, CSV2_frac */ + /* Only support BTI, SME, SSBS, CSV2_frac */ val &=3D ~(ID_AA64PFR1_EL1_PFAR | ID_AA64PFR1_EL1_MTEX | ID_AA64PFR1_EL1_THE | ID_AA64PFR1_EL1_GCS | ID_AA64PFR1_EL1_MTE_frac | ID_AA64PFR1_EL1_NMI | - ID_AA64PFR1_EL1_SME | ID_AA64PFR1_EL1_RES0 | ID_AA64PFR1_EL1_MPAM_frac | ID_AA64PFR1_EL1_MTE); --=20 2.47.3 From nobody Fri Jul 10 06:02:12 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5DAAB43FD2F; Thu, 9 Jul 2026 18:42:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783622521; cv=none; b=qSBzSQzKAxhdG4knYVj+xGBiAMCQskmmKN6yhWs4ZAqAzNDLJcZJbcGo/9IFXtMAHLE7MFFR0IKc7U3qfNtZbuF6Mxkcikn93g/1P7+AeKd2hPNHcvAj6uZGW0y/HtvplV+mBA8ufa8phQWikUdhr3DGGcSPGnb14WqG+fu0Epw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783622521; c=relaxed/simple; bh=ZDaS+09dD5G8S5CvnlwUTGkrhzVRNzAPv9EhkemvOcc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=V//QpPHrVJpMLyCQERT+VT50cnKUXlpxXsGElNG7L++K+lBsBfvFH53Gl6LmEZBel1mGvWxcphtB/At8luiOdqPPH/rYHxiVaUB2OZ2AdpEQWm3pvCxX0dBQ624qwmP30UTe7r9cX0pB1QPTX8CFw7PY92YMxtsJKW5rvmx6wFI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=GoNrBnjj; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="GoNrBnjj" Received: by smtp.kernel.org (Postfix) with ESMTPSA id D594D1F00A3A; Thu, 9 Jul 2026 18:41:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1783622520; bh=uTaLxQeR5q1gGEMEYNufJh/C2F3NhLsUcJjyKWnkRXU=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=GoNrBnjjZ2yJmWLE+uBCRuXd20KSbirw8ZAL4NmuwDN/4cFRnsDjphzuJJ/qn5mUK gIw8YI4IBmDoLbBK5wcgmZvikJxaieDBVh/dy1KMKSoKRaRt6R0rLsKWIMYH+EdlED jHlWCcoC/7aw9x3LR/zm1E4wqI0KhBteSJt2xlXNQjGthgu7FZl4K8lPm/6ohshVpK M/BkK0Sm9W0JoBRW/JCo/evaVqbgTeEKk0czcJuPAuRPz3ONd8L/YvmWUxcRNMOE/+ 3I/202lNPB1btHDcL6kinvSAzXqygeN5X4yZKgrJKwLvImI7iCXJyBTOtxg33uFAqJ BXwUIOONXxJVw== From: Mark Brown Date: Thu, 09 Jul 2026 19:27:46 +0100 Subject: [PATCH v12 25/29] KVM: arm64: Provide interface for configuring and enabling SME for guests Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260709-kvm-arm64-sme-v12-25-d0301d79ef58@kernel.org> References: <20260709-kvm-arm64-sme-v12-0-d0301d79ef58@kernel.org> In-Reply-To: <20260709-kvm-arm64-sme-v12-0-d0301d79ef58@kernel.org> To: Marc Zyngier , Joey Gouly , Catalin Marinas , Suzuki K Poulose , Will Deacon , Paolo Bonzini , Jonathan Corbet , Shuah Khan , Oliver Upton Cc: Dave Martin , Fuad Tabba , Mark Rutland , Ben Horgan , Jean-Philippe Brucker , linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Peter Maydell , Eric Auger , Mark Brown X-Mailer: b4 0.16-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=16419; i=broonie@kernel.org; h=from:subject:message-id; bh=ZDaS+09dD5G8S5CvnlwUTGkrhzVRNzAPv9EhkemvOcc=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBqT+r9yo5w5u1H8qBK2FN/31sPkRFqqEnsXtIie WGbKIi4RseJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCak/q/QAKCRAk1otyXVSH 0MFkB/wMN2SRfyqLipj/QxbvY1vcaluhKJOUKLDgT2M7kFWOpwSVMUmSACdDteR3FAsn7Zs+3PQ jzups1t//WxDUmAclFC2svQLldbYuBRvDruoRwutgSzDVgz7GkoitYiGw1EI3A5Sn451e369NxN wZ2wGz8/rHNL1Q3FfQIqGuM8LyzMoKFCThWQGmj+uZHLiDe8MfXOz7eVykNbIGxvJF1hXeDb0A2 Mn65YCGOj1sz8G9Kynb+PAfIkDeG4WmM3Tgq6f4MumkvvpOw7RHKXgOMjw7qegY8w2wCTZ5FV3U t5mok70/sn1dapXHA+Lav7ROA94B1OB/IHHAaEWg/tmoyb3k X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB Since SME requires configuration of a vector length in order to know the size of both the streaming mode SVE state and ZA array we implement a capability for it and require that it be enabled and finalized before the SME specific state can be accessed, similarly to SVE. Due to the overlap with sizing the SVE state we finalise both SVE and SME with a single finalization, preventing any further changes to the SVE and SME configuration once KVM_ARM_VCPU_VEC (an alias for _VCPU_SVE) has been finalised. This is not a thing of great elegance but it ensures that we never have a state where one of SVE or SME is finalised and the other not, avoiding complexity. Since unlike SVE there is no architecturally manadated vector length which must be supported by all PEs we detect the case where the feature is supported but there is no shared VL and hide the feature. SME is supported for normal guests only. Signed-off-by: Mark Brown --- arch/arm64/include/asm/kvm_host.h | 8 ++- arch/arm64/include/uapi/asm/kvm.h | 1 + arch/arm64/kvm/arm.c | 10 ++++ arch/arm64/kvm/hyp/nvhe/pkvm.c | 81 ++++++++++++++++++++----- arch/arm64/kvm/hyp/nvhe/sys_regs.c | 6 ++ arch/arm64/kvm/reset.c | 119 +++++++++++++++++++++++++++++++--= ---- include/uapi/linux/kvm.h | 1 + 7 files changed, 192 insertions(+), 34 deletions(-) diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm= _host.h index 26ad8962b65d..422ff89a9881 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -39,7 +39,7 @@ =20 #define KVM_MAX_VCPUS VGIC_V3_MAX_CPUS =20 -#define KVM_VCPU_MAX_FEATURES 9 +#define KVM_VCPU_MAX_FEATURES 10 #define KVM_VCPU_VALID_FEATURES (BIT(KVM_VCPU_MAX_FEATURES) - 1) =20 #define KVM_REQ_SLEEP \ @@ -81,6 +81,7 @@ extern unsigned int __ro_after_init kvm_max_vl[ARM64_VEC_= MAX]; extern unsigned int __ro_after_init kvm_host_max_vl[ARM64_VEC_MAX]; =20 int __init kvm_arm_init_sve(void); +int __init kvm_arm_init_sme(void); =20 u32 __attribute_const__ kvm_target_cpu(void); void kvm_reset_vcpu(struct kvm_vcpu *vcpu); @@ -1800,4 +1801,9 @@ static __always_inline enum fgt_group_id __fgt_reg_to= _group_id(enum vcpu_sysreg =20 long kvm_get_cap_for_kvm_ioctl(unsigned int ioctl, long *ext); =20 +static inline bool system_supports_sme_virt(void) +{ + return system_supports_sme() && sme_max_virtualisable_vl(); +} + #endif /* __ARM64_KVM_HOST_H__ */ diff --git a/arch/arm64/include/uapi/asm/kvm.h b/arch/arm64/include/uapi/as= m/kvm.h index deccb034fce3..db240ba5555f 100644 --- a/arch/arm64/include/uapi/asm/kvm.h +++ b/arch/arm64/include/uapi/asm/kvm.h @@ -106,6 +106,7 @@ struct kvm_regs { #define KVM_ARM_VCPU_PTRAUTH_GENERIC 6 /* VCPU uses generic authentication= */ #define KVM_ARM_VCPU_HAS_EL2 7 /* Support nested virtualization */ #define KVM_ARM_VCPU_HAS_EL2_E2H0 8 /* Limit NV support to E2H RES0 */ +#define KVM_ARM_VCPU_SME 9 /* enable SME for this CPU */ =20 /* * An alias for _SVE since we finalize VL configuration for both SVE and S= ME diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c index 50adfff75be8..f9045e8ffe5e 100644 --- a/arch/arm64/kvm/arm.c +++ b/arch/arm64/kvm/arm.c @@ -463,6 +463,9 @@ int kvm_vm_ioctl_check_extension(struct kvm *kvm, long = ext) case KVM_CAP_ARM_SVE: r =3D system_supports_sve(); break; + case KVM_CAP_ARM_SME: + r =3D system_supports_sme_virt(); + break; case KVM_CAP_ARM_PTRAUTH_ADDRESS: case KVM_CAP_ARM_PTRAUTH_GENERIC: r =3D kvm_has_full_ptr_auth(); @@ -1569,6 +1572,9 @@ static unsigned long system_supported_vcpu_features(v= oid) if (!system_supports_sve()) clear_bit(KVM_ARM_VCPU_SVE, &features); =20 + if (!system_supports_sme_virt()) + clear_bit(KVM_ARM_VCPU_SME, &features); + if (!kvm_has_full_ptr_auth()) { clear_bit(KVM_ARM_VCPU_PTRAUTH_ADDRESS, &features); clear_bit(KVM_ARM_VCPU_PTRAUTH_GENERIC, &features); @@ -3032,6 +3038,10 @@ static __init int kvm_arm_init(void) if (err) return err; =20 + err =3D kvm_arm_init_sme(); + if (err) + return err; + err =3D kvm_arm_vmid_alloc_init(); if (err) { kvm_err("Failed to initialize VMID allocator.\n"); diff --git a/arch/arm64/kvm/hyp/nvhe/pkvm.c b/arch/arm64/kvm/hyp/nvhe/pkvm.c index 620f3395ea4e..ed9ce39ee92f 100644 --- a/arch/arm64/kvm/hyp/nvhe/pkvm.c +++ b/arch/arm64/kvm/hyp/nvhe/pkvm.c @@ -150,10 +150,6 @@ static int pkvm_check_pvm_cpu_features(struct kvm_vcpu= *vcpu) !kvm_has_feat(kvm, ID_AA64PFR0_EL1, AdvSIMD, IMP)) return -EINVAL; =20 - /* No SME support in KVM right now. Check to catch if it changes. */ - if (kvm_has_feat(kvm, ID_AA64PFR1_EL1, SME, IMP)) - return -EINVAL; - return 0; } =20 @@ -386,6 +382,11 @@ static void pkvm_init_features_from_host(struct pkvm_h= yp_vm *hyp_vm, const struc kvm->arch.flags |=3D host_arch_flags & BIT(KVM_ARCH_FLAG_GUEST_HAS_SVE); } =20 + if (kvm_pkvm_ext_allowed(kvm, KVM_CAP_ARM_SME)) { + set_bit(KVM_ARM_VCPU_SME, allowed_features); + kvm->arch.flags |=3D host_arch_flags & BIT(KVM_ARCH_FLAG_GUEST_HAS_SME); + } + bitmap_and(kvm->arch.vcpu_features, host_kvm->arch.vcpu_features, allowed_features, KVM_VCPU_MAX_FEATURES); } @@ -400,7 +401,8 @@ static void unpin_host_sve_state(struct pkvm_hyp_vcpu *= hyp_vcpu) { void *sve_state; =20 - if (!vcpu_has_feature(&hyp_vcpu->vcpu, KVM_ARM_VCPU_SVE)) + if (!vcpu_has_feature(&hyp_vcpu->vcpu, KVM_ARM_VCPU_SVE) && + !vcpu_has_feature(&hyp_vcpu->vcpu, KVM_ARM_VCPU_SME)) return; =20 sve_state =3D hyp_vcpu->vcpu.arch.sve_state; @@ -408,6 +410,18 @@ static void unpin_host_sve_state(struct pkvm_hyp_vcpu = *hyp_vcpu) sve_state + vcpu_sve_state_size(&hyp_vcpu->vcpu)); } =20 +static void unpin_host_sme_state(struct pkvm_hyp_vcpu *hyp_vcpu) +{ + void *sme_state; + + if (!vcpu_has_feature(&hyp_vcpu->vcpu, KVM_ARM_VCPU_SME)) + return; + + sme_state =3D hyp_vcpu->vcpu.arch.sme_state; + hyp_unpin_shared_mem(sme_state, + sme_state + vcpu_sme_state_size(&hyp_vcpu->vcpu)); +} + static void unpin_host_vcpus(struct pkvm_hyp_vcpu *hyp_vcpus[], unsigned int nr_vcpus) { @@ -421,6 +435,7 @@ static void unpin_host_vcpus(struct pkvm_hyp_vcpu *hyp_= vcpus[], =20 unpin_host_vcpu(hyp_vcpu->host_vcpu); unpin_host_sve_state(hyp_vcpu); + unpin_host_sme_state(hyp_vcpu); } } =20 @@ -447,23 +462,35 @@ static void init_pkvm_hyp_vm(struct kvm *host_kvm, st= ruct pkvm_hyp_vm *hyp_vm, mmu->pgt =3D &hyp_vm->pgt; } =20 -static int pkvm_vcpu_init_sve(struct pkvm_hyp_vcpu *hyp_vcpu, struct kvm_v= cpu *host_vcpu) +static int pkvm_vcpu_init_vec(struct pkvm_hyp_vcpu *hyp_vcpu, struct kvm_v= cpu *host_vcpu) { struct kvm_vcpu *vcpu =3D &hyp_vcpu->vcpu; - unsigned int sve_max_vl; - size_t sve_state_size; - void *sve_state; + unsigned int sve_max_vl, sme_max_vl; + size_t sve_state_size, sme_state_size; + void *sve_state, *sme_state; int ret =3D 0; =20 - if (!vcpu_has_feature(vcpu, KVM_ARM_VCPU_SVE)) { + if (!vcpu_has_feature(vcpu, KVM_ARM_VCPU_SVE) && + !vcpu_has_feature(vcpu, KVM_ARM_VCPU_SME)) { vcpu_clear_flag(vcpu, VCPU_VEC_FINALIZED); return 0; } =20 /* Limit guest vector length to the maximum supported by the host. */ - sve_max_vl =3D min(READ_ONCE(host_vcpu->arch.max_vl[ARM64_VEC_SVE]), - kvm_host_max_vl[ARM64_VEC_SVE]); - sve_state_size =3D sve_state_size_from_vl(sve_max_vl); + if (vcpu_has_feature(vcpu, KVM_ARM_VCPU_SVE)) + sve_max_vl =3D min(READ_ONCE(host_vcpu->arch.max_vl[ARM64_VEC_SVE]), + kvm_host_max_vl[ARM64_VEC_SVE]); + else + sve_max_vl =3D 0; + + if (vcpu_has_feature(vcpu, KVM_ARM_VCPU_SME)) + sme_max_vl =3D min(READ_ONCE(host_vcpu->arch.max_vl[ARM64_VEC_SME]), + kvm_host_max_vl[ARM64_VEC_SME]); + else + sme_max_vl =3D 0; + + /* We need SVE storage for the larger of normal or streaming mode */ + sve_state_size =3D sve_state_size_from_vl(max(sve_max_vl, sme_max_vl)); sve_state =3D kern_hyp_va(READ_ONCE(host_vcpu->arch.sve_state)); =20 if (!sve_state || !sve_state_size) { @@ -475,12 +502,37 @@ static int pkvm_vcpu_init_sve(struct pkvm_hyp_vcpu *h= yp_vcpu, struct kvm_vcpu *h if (ret) goto err; =20 + if (vcpu_has_feature(vcpu, KVM_ARM_VCPU_SME)) { + /* Space for ZT0 is always allocated to simplify the code. */ + sme_state_size =3D sme_state_size_from_vl(sme_max_vl, + system_supports_sme2()); + sme_state =3D kern_hyp_va(READ_ONCE(host_vcpu->arch.sme_state)); + + if (!sme_state || !sme_state_size) { + ret =3D -EINVAL; + goto err_sve_mapped; + } + + ret =3D hyp_pin_shared_mem(sme_state, sme_state + sme_state_size); + if (ret) + goto err_sve_mapped; + } else { + sme_state =3D NULL; + } + vcpu->arch.sve_state =3D sve_state; vcpu->arch.max_vl[ARM64_VEC_SVE] =3D sve_max_vl; =20 + vcpu->arch.sme_state =3D sme_state; + vcpu->arch.max_vl[ARM64_VEC_SME] =3D sme_max_vl; + return 0; + +err_sve_mapped: + hyp_unpin_shared_mem(sve_state, sve_state + sve_state_size); err: clear_bit(KVM_ARM_VCPU_SVE, vcpu->kvm->arch.vcpu_features); + clear_bit(KVM_ARM_VCPU_SME, vcpu->kvm->arch.vcpu_features); return ret; } =20 @@ -540,7 +592,7 @@ static int init_pkvm_hyp_vcpu(struct pkvm_hyp_vcpu *hyp= _vcpu, if (ret) goto done; =20 - ret =3D pkvm_vcpu_init_sve(hyp_vcpu, host_vcpu); + ret =3D pkvm_vcpu_init_vec(hyp_vcpu, host_vcpu); done: if (ret) unpin_host_vcpu(host_vcpu); @@ -926,6 +978,7 @@ int __pkvm_init_vcpu(pkvm_handle_t handle, struct kvm_v= cpu *host_vcpu, if (ret) { unpin_host_vcpu(host_vcpu); unpin_host_sve_state(hyp_vcpu); + unpin_host_sme_state(hyp_vcpu); } unlock: hyp_spin_unlock(&vm_table_lock); diff --git a/arch/arm64/kvm/hyp/nvhe/sys_regs.c b/arch/arm64/kvm/hyp/nvhe/s= ys_regs.c index 8c3fbb413a06..e2d8a28be8f5 100644 --- a/arch/arm64/kvm/hyp/nvhe/sys_regs.c +++ b/arch/arm64/kvm/hyp/nvhe/sys_regs.c @@ -67,6 +67,11 @@ static bool vm_has_ptrauth(const struct kvm *kvm) kvm_vcpu_has_feature(kvm, KVM_ARM_VCPU_PTRAUTH_GENERIC); } =20 +static bool vm_has_sme(const struct kvm *kvm) +{ + return system_supports_sme() && kvm_vcpu_has_feature(kvm, KVM_ARM_VCPU_SM= E); +} + static bool vm_has_sve(const struct kvm *kvm) { return system_supports_sve() && kvm_vcpu_has_feature(kvm, KVM_ARM_VCPU_SV= E); @@ -103,6 +108,7 @@ static const struct pvm_ftr_bits pvmid_aa64pfr0[] =3D { }; =20 static const struct pvm_ftr_bits pvmid_aa64pfr1[] =3D { + MAX_FEAT_FUNC(ID_AA64PFR1_EL1, SME, SME2, vm_has_sme), MAX_FEAT(ID_AA64PFR1_EL1, BT, IMP), MAX_FEAT(ID_AA64PFR1_EL1, SSBS, SSBS2), MAX_FEAT_ENUM(ID_AA64PFR1_EL1, MTE_frac, NI), diff --git a/arch/arm64/kvm/reset.c b/arch/arm64/kvm/reset.c index fee01c38fa13..c0c605ff22bd 100644 --- a/arch/arm64/kvm/reset.c +++ b/arch/arm64/kvm/reset.c @@ -76,6 +76,31 @@ int __init kvm_arm_init_sve(void) return 0; } =20 +int __init kvm_arm_init_sme(void) +{ + if (system_supports_sme()) { + kvm_host_max_vl[ARM64_VEC_SME] =3D sme_max_vl(); + kvm_nvhe_sym(kvm_host_max_vl[ARM64_VEC_SME]) =3D kvm_host_max_vl[ARM64_V= EC_SME]; + } + + if (system_supports_sme_virt()) { + kvm_max_vl[ARM64_VEC_SME] =3D sme_max_virtualisable_vl(); + + if (WARN_ON(kvm_max_vl[ARM64_VEC_SME] > VL_ARCH_MAX)) + kvm_max_vl[ARM64_VEC_SME] =3D VL_ARCH_MAX; + + /* + * Don't even try to make use of vector lengths that + * aren't available on all CPUs, for now: + */ + if (kvm_max_vl[ARM64_VEC_SME] < sme_max_vl()) + pr_warn("KVM: SME vector length for guests limited to %u bytes\n", + kvm_max_vl[ARM64_VEC_SME]); + } + + return 0; +} + static void kvm_vcpu_enable_sve(struct kvm_vcpu *vcpu) { vcpu->arch.max_vl[ARM64_VEC_SVE] =3D kvm_max_vl[ARM64_VEC_SVE]; @@ -88,42 +113,90 @@ static void kvm_vcpu_enable_sve(struct kvm_vcpu *vcpu) set_bit(KVM_ARCH_FLAG_GUEST_HAS_SVE, &vcpu->kvm->arch.flags); } =20 +static void kvm_vcpu_enable_sme(struct kvm_vcpu *vcpu) +{ + vcpu->arch.max_vl[ARM64_VEC_SME] =3D kvm_max_vl[ARM64_VEC_SME]; + + /* + * Userspace can still customize the vector lengths by writing + * KVM_REG_ARM64_SME_VLS. Allocation is deferred until + * kvm_arm_vcpu_finalize(), which freezes the configuration. + */ + set_bit(KVM_ARCH_FLAG_GUEST_HAS_SME, &vcpu->kvm->arch.flags); +} + /* - * Finalize vcpu's maximum SVE vector length, allocating - * vcpu->arch.sve_state as necessary. + * Finalize vcpu's maximum vector lengths, allocating + * vcpu->arch.sve_state and vcpu->arch.sme_state as necessary. */ static int kvm_vcpu_finalize_vec(struct kvm_vcpu *vcpu) { - void *buf; + void *sve_state, *sme_state; unsigned int vl; - size_t reg_sz; int ret; =20 - vl =3D vcpu->arch.max_vl[ARM64_VEC_SVE]; - /* * Responsibility for these properties is shared between * kvm_arm_init_sve(), kvm_vcpu_enable_sve() and * set_sve_vls(). Double-check here just to be sure: */ - if (WARN_ON(!sve_vl_valid(vl) || vl > sve_max_virtualisable_vl() || - vl > VL_ARCH_MAX)) - return -EIO; + if (vcpu_has_sve(vcpu)) { + vl =3D vcpu->arch.max_vl[ARM64_VEC_SVE]; + if (WARN_ON(!sve_vl_valid(vl) || + vl > sve_max_virtualisable_vl() || + vl > VL_ARCH_MAX)) + return -EIO; + } else { + vcpu->arch.max_vl[ARM64_VEC_SVE] =3D 0; + } =20 - reg_sz =3D vcpu_sve_state_size(vcpu); - buf =3D kzalloc(reg_sz, GFP_KERNEL_ACCOUNT); - if (!buf) + /* Similarly for SME */ + if (vcpu_has_sme(vcpu)) { + vl =3D vcpu->arch.max_vl[ARM64_VEC_SME]; + if (WARN_ON(!sve_vl_valid(vl) || + vl > sme_max_virtualisable_vl() || + vl > VL_ARCH_MAX)) + return -EIO; + } else { + vcpu->arch.max_vl[ARM64_VEC_SME] =3D 0; + } + + sve_state =3D kzalloc(vcpu_sve_state_size(vcpu), GFP_KERNEL_ACCOUNT); + if (!sve_state) return -ENOMEM; =20 - ret =3D kvm_share_hyp(buf, buf + reg_sz); - if (ret) { - kfree(buf); - return ret; + ret =3D kvm_share_hyp(sve_state, sve_state + vcpu_sve_state_size(vcpu)); + if (ret) + goto err_sve_alloc; + + if (vcpu_has_sme(vcpu)) { + sme_state =3D kzalloc(vcpu_sme_state_size(vcpu), + GFP_KERNEL_ACCOUNT); + if (!sme_state) { + ret =3D -ENOMEM; + goto err_sve_map; + } + + ret =3D kvm_share_hyp(sme_state, + sme_state + vcpu_sme_state_size(vcpu)); + if (ret) + goto err_sme_alloc; + } else { + sme_state =3D NULL; } -=09 - vcpu->arch.sve_state =3D buf; + + vcpu->arch.sve_state =3D sve_state; + vcpu->arch.sme_state =3D sme_state; vcpu_set_flag(vcpu, VCPU_VEC_FINALIZED); return 0; + +err_sme_alloc: + kfree(sme_state); +err_sve_map: + kvm_unshare_hyp(sve_state, sve_state + vcpu_sve_state_size(vcpu)); +err_sve_alloc: + kfree(sve_state); + return ret; } =20 int kvm_arm_vcpu_finalize(struct kvm_vcpu *vcpu, int feature) @@ -153,20 +226,26 @@ bool kvm_arm_vcpu_is_finalized(struct kvm_vcpu *vcpu) void kvm_arm_vcpu_destroy(struct kvm_vcpu *vcpu) { void *sve_state =3D vcpu->arch.sve_state; + void *sme_state =3D vcpu->arch.sme_state; =20 kvm_unshare_hyp(vcpu, vcpu + 1); if (sve_state) kvm_unshare_hyp(sve_state, sve_state + vcpu_sve_state_size(vcpu)); kfree(sve_state); free_page((unsigned long)vcpu->arch.ctxt.vncr_array); + if (sme_state) + kvm_unshare_hyp(sme_state, sme_state + vcpu_sme_state_size(vcpu)); + kfree(sme_state); kfree(vcpu->arch.vncr_tlb); kfree(vcpu->arch.ccsidr); } =20 static void kvm_vcpu_reset_vec(struct kvm_vcpu *vcpu) { - if (vcpu_has_sve(vcpu)) + if (vcpu_has_sve(vcpu) || vcpu_has_sme(vcpu)) memset(vcpu->arch.sve_state, 0, vcpu_sve_state_size(vcpu)); + if (vcpu_has_sme(vcpu)) + memset(vcpu->arch.sme_state, 0, vcpu_sme_state_size(vcpu)); } =20 /** @@ -206,6 +285,8 @@ void kvm_reset_vcpu(struct kvm_vcpu *vcpu) if (!kvm_arm_vcpu_vec_finalized(vcpu)) { if (vcpu_has_feature(vcpu, KVM_ARM_VCPU_SVE)) kvm_vcpu_enable_sve(vcpu); + if (vcpu_has_feature(vcpu, KVM_ARM_VCPU_SME)) + kvm_vcpu_enable_sme(vcpu); } else { kvm_vcpu_reset_vec(vcpu); } diff --git a/include/uapi/linux/kvm.h b/include/uapi/linux/kvm.h index 419011097fa8..9291538489ac 100644 --- a/include/uapi/linux/kvm.h +++ b/include/uapi/linux/kvm.h @@ -997,6 +997,7 @@ struct kvm_enable_cap { #define KVM_CAP_S390_KEYOP 247 #define KVM_CAP_S390_VSIE_ESAMODE 248 #define KVM_CAP_S390_HPAGE_2G 249 +#define KVM_CAP_ARM_SME 250 =20 struct kvm_irq_routing_irqchip { __u32 irqchip; --=20 2.47.3 From nobody Fri Jul 10 06:02:12 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F03C543F8BE; Thu, 9 Jul 2026 18:42:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783622526; cv=none; b=TyBAhbQ1Z2aUxZX+IRRAEGzgon7GHKMAIl4Z61DGbwjuzZJRggDC6iSzCnUX3Mb/KIIVcEH+EY/xcYwos9kQm6t1JRTUrb+w84tk8uxA0xHhMXKWD/WmRSqL+t5MVkRWMxf1xZxPadLJKVelRrrAEiN2Az+8t7jSSKK48wPm8zI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783622526; c=relaxed/simple; bh=3zzAFIxW4QntGIfc+v0S58ciMfKRPipxII9rhMorBnU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=BajwKwkCicZNqGFggSh5ej6E7a4bu+FiOroWiOxEQE1iIP5P59mHFGAv1vOd6LFWsr4ma/j6C77gMBNSBq7n++bJx3ZWZIt+9O7Br5ezA7mdNzOoH9Iko/h5zmFfqWu3ho3Zv6l3vVLSofwe+tRyJsMxdN2krPXAiso60bkNp1E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=VpaG0lqU; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="VpaG0lqU" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6881A1F000E9; Thu, 9 Jul 2026 18:42:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1783622524; bh=V9/QBsgUl+YAHSU3KRVgzfp7o3z60FnCLy+stiPlLsM=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=VpaG0lqUM9AJpjH5h2yYuDiybRa/XGorO8CR+46KxgKuXsP+ZlD24JnA3NGHjZSbj VDvCQsTokNpbKimzr6UHWc03P9iPWK2n+WS4t+Zr5u22pU59ELlG79TDr+cbUMsAgd pUdz/3yFvNgyufCzUqMngT9KXWls3TVQh3VCs0T7vvnXRF18wvfMAQZgF7ctMH31xC CnQhN3Sufw/1roZvIvf7YDQsx++KToaYsk6AnqwtucyNGyPQ0p5NH4JCC1Zk6Bl9rd O4Jwa0tz9/ePPoPCvda6A5nmR+LOLWWh+7doeeD+tYUkQJN0MON8RpOf/1cPHpqfQo qRuhFLhq/s9iA== From: Mark Brown Date: Thu, 09 Jul 2026 19:27:47 +0100 Subject: [PATCH v12 26/29] KVM: arm64: selftests: Remove spurious check for single bit safe values Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260709-kvm-arm64-sme-v12-26-d0301d79ef58@kernel.org> References: <20260709-kvm-arm64-sme-v12-0-d0301d79ef58@kernel.org> In-Reply-To: <20260709-kvm-arm64-sme-v12-0-d0301d79ef58@kernel.org> To: Marc Zyngier , Joey Gouly , Catalin Marinas , Suzuki K Poulose , Will Deacon , Paolo Bonzini , Jonathan Corbet , Shuah Khan , Oliver Upton Cc: Dave Martin , Fuad Tabba , Mark Rutland , Ben Horgan , Jean-Philippe Brucker , linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Peter Maydell , Eric Auger , Mark Brown X-Mailer: b4 0.16-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=1200; i=broonie@kernel.org; h=from:subject:message-id; bh=3zzAFIxW4QntGIfc+v0S58ciMfKRPipxII9rhMorBnU=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBqT+r+KQ1zJ80C6wnIIVYlDY8xGooQpjWeJucoZ +qY2kBb6z+JATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCak/q/gAKCRAk1otyXVSH 0B3wB/9iWEG1cKGN60DbAJRUDX2lO5oQv99lWbCu882DlgSdoN82JGfBtU6ZnDJi8u/469CrkMR kRO/PhUMi4/+Tpwxs6LT8Fw5NgV+aWwsDvJ8vBYyHmOuhX1pBYRpyP1V5+K5cYWkEcRLLBxmVh0 cs+tpR+QhvQ06Qznczflff9hA13XAsyZIQ+tPnj0oSEfka3mTIOBYnq4JbuJVJlaCgNg3UHtNFj HgP8Zry8wOJ4BNQvN5BaZQNzHQxGo7QyqfYu2YgkkcDgO2yDBKYN/Seg75MJG2mKErHBsjUfOnd QqbduqIMjyKkJRifjaYRXWPUY/EU3Mb/IKHovBkzYlwG0uUX X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB get_safe_value() currently asserts that bitfields it is generating a safe value for must be more than one bit wide but in actual fact it should always be possible to generate a safe value to write to a bitfield even if it is just the current value and the function correctly handles that. Remove the assert. Fixes: bf09ee918053e ("KVM: arm64: selftests: Remove ARM64_FEATURE_FIELD_BI= TS and its last user") Reviewed-by: Ben Horgan Signed-off-by: Mark Brown --- tools/testing/selftests/kvm/arm64/set_id_regs.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/tools/testing/selftests/kvm/arm64/set_id_regs.c b/tools/testin= g/selftests/kvm/arm64/set_id_regs.c index 7429a1055df5..9eceac84e297 100644 --- a/tools/testing/selftests/kvm/arm64/set_id_regs.c +++ b/tools/testing/selftests/kvm/arm64/set_id_regs.c @@ -279,8 +279,6 @@ u64 get_safe_value(const struct reg_ftr_bits *ftr_bits,= u64 ftr) { u64 ftr_max =3D ftr_bits->mask >> ftr_bits->shift; =20 - TEST_ASSERT(ftr_max > 1, "This test doesn't support single bit features"); - if (ftr_bits->sign =3D=3D FTR_UNSIGNED) { switch (ftr_bits->type) { case FTR_EXACT: --=20 2.47.3 From nobody Fri Jul 10 06:02:12 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 48B0344838A; Thu, 9 Jul 2026 18:42:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783622530; cv=none; b=ow77zmnSUN1r3mYYtmB2hnr8evIP98nhzUbnlRapNxir9oE8fYs/8BJ9ht6FchCJmNwGZe/W5X4onWz0RQri+BiCTnSU52lhj9HogYcXW5foRZ6uOCG828Z/X0UO4VqP1ojT76VgYInbAFp6w5aTYfe1Zh6ttv/8fi0hmOLuV2Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783622530; c=relaxed/simple; bh=DoSXFT1XFLMt5bL77ymD5uWM5fFd8Skxma7c37DB6O8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=CPf0KzqUt5mhKM4Cxvf0W3EtOMK/+MdzreuMwk58Qy21GpaSSy+ip8ca8Z7muORsVjmaESKFbq/uOeOXh/mIaBhQJXNAqsgjjwaS9RrooosXS8bGiWhkK+PmPTdsPhob/lK1W0yfK7bwfzmr2Szs40YifbsPtvGsFgb974oLWGU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=bKLI+JLq; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="bKLI+JLq" Received: by smtp.kernel.org (Postfix) with ESMTPSA id EE6971F00A3D; Thu, 9 Jul 2026 18:42:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1783622529; bh=k6q2RcAVUcHJXSDerZte/wZkUxNLtsu6zF4B+0lVk2U=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=bKLI+JLqX4NCZ2sJnMBSiuKYZ4BjOS9In2l5a0uh0V38xejRgNjCvN0hgzNEjia27 KovVpFEiIndn/Co2JEN/58EkWZM49auZQ65JliYt7s4Pia798PWP3Ilk2SKgeBy8Gr dRk59JllJbWFrzbtwtzFmbq3bx/luUs18ayGhGCkRuXDCwiWIW8JH4a3iP65Yne0FW u4WHdbNE1PcPwEwGICWNK3iTnN1fZ573OpSYG1LExUcRZzu+p24ZWzAXyqDO/5uVgl TuPr3XcVeSO6jbq5o8RlwKrx6g+48uoHmaCvYGDhzm6wL9LtcH58uUAPHKLaarqvfL ycDdh950qBDtg== From: Mark Brown Date: Thu, 09 Jul 2026 19:27:48 +0100 Subject: [PATCH v12 27/29] KVM: arm64: selftests: Skip impossible invalid value tests Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260709-kvm-arm64-sme-v12-27-d0301d79ef58@kernel.org> References: <20260709-kvm-arm64-sme-v12-0-d0301d79ef58@kernel.org> In-Reply-To: <20260709-kvm-arm64-sme-v12-0-d0301d79ef58@kernel.org> To: Marc Zyngier , Joey Gouly , Catalin Marinas , Suzuki K Poulose , Will Deacon , Paolo Bonzini , Jonathan Corbet , Shuah Khan , Oliver Upton Cc: Dave Martin , Fuad Tabba , Mark Rutland , Ben Horgan , Jean-Philippe Brucker , linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Peter Maydell , Eric Auger , Mark Brown X-Mailer: b4 0.16-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=3690; i=broonie@kernel.org; h=from:subject:message-id; bh=DoSXFT1XFLMt5bL77ymD5uWM5fFd8Skxma7c37DB6O8=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBqT+r/MiDwO0nIa0JXTdKaad8Wg+Z3zHSyBtUTi eixAMTowpyJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCak/q/wAKCRAk1otyXVSH 0GqpB/9SJ+V9vjmMk4vct0U2i+V//FUjRQ+6+kMG3OFbl/RyCbZPUcTjesS1emd0Ev7F1LWclaX Lw+FuanjD+6KLJ3fsF4ro+xWWm5uVXlsGCAJWgIiUTd+h7jsu4jwWOta8VpR7X5yySiiqPR5QyV a37BfdO0+Oi0Bu1sDWGSrXE6vT/pqHUPdlzIIvZJfl/yQsDSWMyn6JdMyLeRldD0c/XgesjPmEl xc6lPA6+4cyLNZdMNngdbUIoQ7xqY0x/XB+valUBDkqDGqxcUFrX31x7vq2Y/QilrH1yDQMtn9X /XP9UFjLhEqDUZgvwh4nwe3rMyJb5RgaBqjDywJGqwjhcOvq X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB The set_id_regs test currently assumes that there will always be invalid values available in bitfields for it to generate but this may not be the case if the architecture has defined meanings for every possible value for the bitfield. An assert added in commit bf09ee918053e ("KVM: arm64: selftests: Remove ARM64_FEATURE_FIELD_BITS and its last user") refuses to run for single bit fields which will show the issue most readily but there is no reason wider ones can't show the same issue. Rework the tests for invalid value to check if an invalid value can be generated and skip the test if not, removing the assert. Signed-off-by: Mark Brown --- tools/testing/selftests/kvm/arm64/set_id_regs.c | 64 +++++++++++++++++++++= ---- 1 file changed, 54 insertions(+), 10 deletions(-) diff --git a/tools/testing/selftests/kvm/arm64/set_id_regs.c b/tools/testin= g/selftests/kvm/arm64/set_id_regs.c index 9eceac84e297..da9349bf31ab 100644 --- a/tools/testing/selftests/kvm/arm64/set_id_regs.c +++ b/tools/testing/selftests/kvm/arm64/set_id_regs.c @@ -327,54 +327,95 @@ u64 get_safe_value(const struct reg_ftr_bits *ftr_bit= s, u64 ftr) } =20 /* Return an invalid value to a given ftr_bits an ftr value */ -u64 get_invalid_value(const struct reg_ftr_bits *ftr_bits, u64 ftr) +u64 get_invalid_value(const struct reg_ftr_bits *ftr_bits, u64 ftr, bool *= skip) { u64 ftr_max =3D ftr_bits->mask >> ftr_bits->shift; =20 - TEST_ASSERT(ftr_max > 1, "This test doesn't support single bit features"); + *skip =3D false; =20 if (ftr_bits->sign =3D=3D FTR_UNSIGNED) { switch (ftr_bits->type) { case FTR_EXACT: ftr =3D max((u64)ftr_bits->safe_val + 1, ftr + 1); + if (ftr >=3D ftr_max) + *skip =3D true; break; case FTR_LOWER_SAFE: + if (ftr =3D=3D ftr_max) + *skip =3D true; ftr++; break; case FTR_HIGHER_SAFE: + if (ftr =3D=3D 0) + *skip =3D true; ftr--; break; case FTR_HIGHER_OR_ZERO_SAFE: - if (ftr =3D=3D 0) + switch (ftr) { + case 0: ftr =3D ftr_max; - else + break; + case 1: + *skip =3D true; + break; + default: ftr--; + break; + } break; default: + *skip =3D true; break; } } else if (ftr !=3D ftr_max) { switch (ftr_bits->type) { case FTR_EXACT: ftr =3D max((u64)ftr_bits->safe_val + 1, ftr + 1); + if (ftr >=3D ftr_max) + *skip =3D true; break; case FTR_LOWER_SAFE: ftr++; break; case FTR_HIGHER_SAFE: - ftr--; + /* FIXME: "need to check for the actual highest." */ + if (ftr =3D=3D 0 || ftr =3D=3D ftr_max) + *skip =3D true; + else + ftr--; break; case FTR_HIGHER_OR_ZERO_SAFE: - if (ftr =3D=3D 0) - ftr =3D ftr_max - 1; - else + switch (ftr) { + case 0: + if (ftr_max > 1) + ftr =3D ftr_max - 1; + else + *skip =3D true; + break; + case 1: + *skip =3D true; + break; + default: ftr--; + break; + } break; default: + *skip =3D true; break; } } else { - ftr =3D 0; + switch (ftr_bits->type) { + case FTR_LOWER_SAFE: + if (ftr =3D=3D 0) + *skip =3D true; + else + ftr =3D 0; + break; + default: + *skip =3D true; + break; + } } =20 return ftr; @@ -409,12 +450,15 @@ static void test_reg_set_fail(struct kvm_vcpu *vcpu, = u64 reg, u8 shift =3D ftr_bits->shift; u64 mask =3D ftr_bits->mask; u64 val, old_val, ftr; + bool skip; int r; =20 val =3D vcpu_get_reg(vcpu, reg); ftr =3D (val & mask) >> shift; =20 - ftr =3D get_invalid_value(ftr_bits, ftr); + ftr =3D get_invalid_value(ftr_bits, ftr, &skip); + if (skip) + return; =20 old_val =3D val; ftr <<=3D shift; --=20 2.47.3 From nobody Fri Jul 10 06:02:12 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D974F43FD0B; Thu, 9 Jul 2026 18:42:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783622535; cv=none; b=huDnK0IH5qssOoaGqcvy7UhMxGxKWx0NQOMoPjcQzM0a0O/lQ1+a1QbFjDY5d4OguO6fFhU6H2IDtzRvwEl4lmaXKQNpIkQr/ue1ZiFmyX2Ub8LtRRcala3urRRjsDCFEol/CSWjyZk4faYCwhhXym6MEJq8eAY0+jnURILAd1c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783622535; c=relaxed/simple; bh=I21JH58CR/AbSnYTHYyjog9l03x/hS5CLetpI7AAePU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=FWcNAR19qCTfFmeFYvoWBB11xga4UbLXJpVjjpjMOTsX1kJkXZqDp1EAL5oU570lIHqG7t2m25v0kRH9F7pSFTI1HZWhO1ZSCGPPl1fcbHxIArTmF0ClykPt1EsI/kWXqGaI1ozLdlHn8M2mqsT5GjOSD3G8fQydkusn4jEvg0Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=mp2e3TOy; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="mp2e3TOy" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7D8D21F00A3A; Thu, 9 Jul 2026 18:42:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1783622533; bh=xQPjYFjbIcAmw/vy47XjvylGbXgKpoMyOES+M/yVDZc=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=mp2e3TOyU0qf8B0utPd31uLKeDkSJAopKBFAr7y9816HDNRy++VF3Xw6hawK3Vhry oCqyqtRLIf41Xi3eLVRW0eh4LmjB+QbLkX7/jAJxoKMwFdZIr1En/K9kcHJ8/DlIMa oG0N8MK/MlOmX2D5rYoZOYhKO/WBGdlCelDgNpYId+UQCTr3xwxtWqOri2rSLGf2Vj mf+DZ1fj/uV3iV6BNRzm2gTvr9ewEIDRfiqTA7j1SIi1nw1BT5jtiQoTbyW7BGpW8N GI+gPXu2U0mLGkPxjl4x5+dSzRhQuH4qMEKxW4jCWodGDtUC5Qs9Efn2yPyTDq4PwK 5GBzJLCHV3BiQ== From: Mark Brown Date: Thu, 09 Jul 2026 19:27:49 +0100 Subject: [PATCH v12 28/29] KVM: arm64: selftests: Add SME system registers to get-reg-list Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260709-kvm-arm64-sme-v12-28-d0301d79ef58@kernel.org> References: <20260709-kvm-arm64-sme-v12-0-d0301d79ef58@kernel.org> In-Reply-To: <20260709-kvm-arm64-sme-v12-0-d0301d79ef58@kernel.org> To: Marc Zyngier , Joey Gouly , Catalin Marinas , Suzuki K Poulose , Will Deacon , Paolo Bonzini , Jonathan Corbet , Shuah Khan , Oliver Upton Cc: Dave Martin , Fuad Tabba , Mark Rutland , Ben Horgan , Jean-Philippe Brucker , linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Peter Maydell , Eric Auger , Mark Brown X-Mailer: b4 0.16-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=3018; i=broonie@kernel.org; h=from:subject:message-id; bh=I21JH58CR/AbSnYTHYyjog9l03x/hS5CLetpI7AAePU=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBqT+sAMVuyitVIErsyHz8wft0/Wir8nS9UXHxOl yYG/UokqK6JATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCak/rAAAKCRAk1otyXVSH 0PPyB/0WSEKAeDdFKHMTED/YdtTHZkRiC3h/jR+8I+KrktMWuG59XltiylEFmja1/wONl+CgIk/ 5Qs70H1b9OQtgqdsn/x3rG6WSgvBe2ZJyGbWSbWfiPUG1nnoE4ZgnT/0vu3TR+Y2m27EYGkYXYL LSgE7FUXiFqyFSpJB8Jdssn7ler/gxhUxz4l3knVkOPFAvKYaJ3BeFvk2tvdmKM2EUL7BY0EsmH 9MOg+DZPlrG184g9njSs9j/bJADhoF3D3NEGWrpepfkD37YveYDUpM1Y8iW4Lubi5GGT6Q7/4Ub EegUhTx+9MN7ytSoIjmS+v9yjtvoOwlZ4AM42VMc+bHcbKse X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB SME adds a number of new system registers, update get-reg-list to check for them based on the visibility of SME. Signed-off-by: Mark Brown --- tools/testing/selftests/kvm/arm64/get-reg-list.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/tools/testing/selftests/kvm/arm64/get-reg-list.c b/tools/testi= ng/selftests/kvm/arm64/get-reg-list.c index 0a3a94c4cca1..876c4719e2e2 100644 --- a/tools/testing/selftests/kvm/arm64/get-reg-list.c +++ b/tools/testing/selftests/kvm/arm64/get-reg-list.c @@ -61,7 +61,13 @@ static struct feature_id_reg feat_id_regs[] =3D { REG_FEAT(HFGITR2_EL2, ID_AA64MMFR0_EL1, FGT, FGT2), REG_FEAT(HDFGRTR2_EL2, ID_AA64MMFR0_EL1, FGT, FGT2), REG_FEAT(HDFGWTR2_EL2, ID_AA64MMFR0_EL1, FGT, FGT2), - REG_FEAT(ZCR_EL2, ID_AA64PFR0_EL1, SVE, IMP), + REG_FEAT(SMCR_EL1, ID_AA64PFR1_EL1, SME, IMP), + REG_FEAT(SMCR_EL2, ID_AA64PFR1_EL1, SME, IMP), + REG_FEAT(SMIDR_EL1, ID_AA64PFR1_EL1, SME, IMP), + REG_FEAT(SMPRI_EL1, ID_AA64PFR1_EL1, SME, IMP), + REG_FEAT(SMPRIMAP_EL2, ID_AA64PFR1_EL1, SME, IMP), + REG_FEAT(TPIDR2_EL0, ID_AA64PFR1_EL1, SME, IMP), + REG_FEAT(SVCR, ID_AA64PFR1_EL1, SME, IMP), REG_FEAT(SCTLR2_EL1, ID_AA64MMFR3_EL1, SCTLRX, IMP), REG_FEAT(SCTLR2_EL2, ID_AA64MMFR3_EL1, SCTLRX, IMP), REG_FEAT(VDISR_EL2, ID_AA64PFR0_EL1, RAS, IMP), @@ -367,6 +373,7 @@ static __u64 base_regs[] =3D { ARM64_SYS_REG(3, 0, 0, 0, 0), /* MIDR_EL1 */ ARM64_SYS_REG(3, 0, 0, 0, 6), /* REVIDR_EL1 */ ARM64_SYS_REG(3, 1, 0, 0, 1), /* CLIDR_EL1 */ + ARM64_SYS_REG(3, 1, 0, 0, 6), /* SMIDR_EL1 */ ARM64_SYS_REG(3, 1, 0, 0, 7), /* AIDR_EL1 */ ARM64_SYS_REG(3, 3, 0, 0, 1), /* CTR_EL0 */ ARM64_SYS_REG(2, 0, 0, 0, 4), @@ -498,6 +505,8 @@ static __u64 base_regs[] =3D { ARM64_SYS_REG(3, 0, 1, 0, 1), /* ACTLR_EL1 */ ARM64_SYS_REG(3, 0, 1, 0, 2), /* CPACR_EL1 */ KVM_ARM64_SYS_REG(SYS_SCTLR2_EL1), + ARM64_SYS_REG(3, 0, 1, 2, 4), /* SMPRI_EL1 */ + ARM64_SYS_REG(3, 0, 1, 2, 6), /* SMCR_EL1 */ ARM64_SYS_REG(3, 0, 2, 0, 0), /* TTBR0_EL1 */ ARM64_SYS_REG(3, 0, 2, 0, 1), /* TTBR1_EL1 */ ARM64_SYS_REG(3, 0, 2, 0, 2), /* TCR_EL1 */ @@ -518,9 +527,11 @@ static __u64 base_regs[] =3D { ARM64_SYS_REG(3, 0, 13, 0, 4), /* TPIDR_EL1 */ ARM64_SYS_REG(3, 0, 14, 1, 0), /* CNTKCTL_EL1 */ ARM64_SYS_REG(3, 2, 0, 0, 0), /* CSSELR_EL1 */ + ARM64_SYS_REG(3, 3, 4, 2, 2), /* SVCR */ ARM64_SYS_REG(3, 3, 10, 2, 4), /* POR_EL0 */ ARM64_SYS_REG(3, 3, 13, 0, 2), /* TPIDR_EL0 */ ARM64_SYS_REG(3, 3, 13, 0, 3), /* TPIDRRO_EL0 */ + ARM64_SYS_REG(3, 3, 13, 0, 5), /* TPIDR2_EL0 */ ARM64_SYS_REG(3, 3, 14, 0, 1), /* CNTPCT_EL0 */ ARM64_SYS_REG(3, 3, 14, 2, 1), /* CNTP_CTL_EL0 */ ARM64_SYS_REG(3, 3, 14, 2, 2), /* CNTP_CVAL_EL0 */ @@ -730,6 +741,8 @@ static __u64 el2_regs[] =3D { SYS_REG(HFGITR_EL2), SYS_REG(HACR_EL2), SYS_REG(ZCR_EL2), + SYS_REG(SMPRIMAP_EL2), + SYS_REG(SMCR_EL2), SYS_REG(HCRX_EL2), SYS_REG(TTBR0_EL2), SYS_REG(TTBR1_EL2), --=20 2.47.3 From nobody Fri Jul 10 06:02:12 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9061B43B4A9; Thu, 9 Jul 2026 18:42:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783622539; cv=none; b=p/lcFoYaJ/HIKbeihBRMHdJf1ht2DqTj6pTo413T1GxMtbqBNICYkbDt2g0lj088vncV27zJuW2jsRoG9e13K0+chnhgvmdzwqkOQiRraJN2eZd+AR0RxYrNO0asAahuitoxn0CH63yamzicNh5rOBgH527V3MJDeKLs4bfW+yg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783622539; c=relaxed/simple; bh=q7gRFDO7XUzOJdjKk7dinZEmMYgpMJThzBI3Uxs/+tg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=pFLNJoiIaqnxL+mpzNpmkdRMdqwl3RCA7OOsoeZV3VKZLfbGmUvIFuieEa58HHTQQ+17tSaE+m48yxQC4P6uTtgMZVglTKr8KSxIpsPPjVWSS4GnjhNCPLCnZVKzIfQYTyZgQgyo6l7LwXm2pH9FUANx5MnsrvRQofZtaBslFIA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=om4MN8j4; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="om4MN8j4" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0BB121F000E9; Thu, 9 Jul 2026 18:42:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1783622538; bh=XECF9ZZpHN11rgO/zTL5kqZIcvgfBhcTmPU6H51lc1c=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=om4MN8j4T9S1gJ6RcrNGwq31Rui8bwxb6u5K24PkOrExLur4vrArun7m/ayyKeybG DRlOMhyvmeLyWYQkLI5/B/VCaZUrFC58STn6nN+nTMg02ksEUH+tbTNG73dHEsbtDj mjByXFjQWoZ77wWc89xctPmMXs+HpIq6nrfHvihBquOzFzPr4TeZRhVNj3ARHFL8Jp De3V+DCU4Ws7I58/u9BL0Yixu8GGbR6Y56/LSAjqmYpnoA1WRo41LuCmcr6ydpfU/v sJgUX26c7s+yLglWdgBcO9aSr4MjWakdqqbrv7rydFDJoLWWHDrRrvdFOIn0gua5uY i5TxpzpHs6Uew== From: Mark Brown Date: Thu, 09 Jul 2026 19:27:50 +0100 Subject: [PATCH v12 29/29] KVM: arm64: selftests: Add SME to set_id_regs test Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260709-kvm-arm64-sme-v12-29-d0301d79ef58@kernel.org> References: <20260709-kvm-arm64-sme-v12-0-d0301d79ef58@kernel.org> In-Reply-To: <20260709-kvm-arm64-sme-v12-0-d0301d79ef58@kernel.org> To: Marc Zyngier , Joey Gouly , Catalin Marinas , Suzuki K Poulose , Will Deacon , Paolo Bonzini , Jonathan Corbet , Shuah Khan , Oliver Upton Cc: Dave Martin , Fuad Tabba , Mark Rutland , Ben Horgan , Jean-Philippe Brucker , linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Peter Maydell , Eric Auger , Mark Brown X-Mailer: b4 0.16-dev X-Developer-Signature: v=1; a=openpgp-sha256; l=3538; i=broonie@kernel.org; h=from:subject:message-id; bh=q7gRFDO7XUzOJdjKk7dinZEmMYgpMJThzBI3Uxs/+tg=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBqT+sAuw7myrbcgUVgJNZQ/jetM2DjXieP+8OEe UPSUnc0/tKJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCak/rAAAKCRAk1otyXVSH 0DLXB/9PWTecBw9vRlEMUmyTZnUDGsd+6k0m+yErwCEEBlLJYYI/+3QolnJWwgqe+cXdKbYe3mG vMk1TXUu6KCx2yJNhCnqnMbQp1PQwVo0PbCJEHLRSNTyZuKEZwZuiBBpFbT+z/nL90BKC0cS8Pn a/wZ+C8k3HwcpCQ50JLe2doxOLmwu1q+LseQoBxEmPk58cjN0fJitLPg0fARl/h8n+nQwKfDPn6 LxIZz9hpYHSGysP985W5+rikM37TqfqEiBIqsaRxcfxiXJcRgV6E4iZG+O38R9pHPtZj3fdSQeR EkJy9cso+vX8Sd9RYbdSrbIID0rA1c5M+QTd8O7FaauC7hb1 X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB Add coverage of the SME ID registers to set_id_regs, ID_AA64PFR1_EL1.SME becomes writable and we add ID_AA64SMFR0_EL1 and it's subfields. Signed-off-by: Mark Brown --- tools/testing/selftests/kvm/arm64/set_id_regs.c | 30 +++++++++++++++++++++= ++++ 1 file changed, 30 insertions(+) diff --git a/tools/testing/selftests/kvm/arm64/set_id_regs.c b/tools/testin= g/selftests/kvm/arm64/set_id_regs.c index da9349bf31ab..26db507f6e73 100644 --- a/tools/testing/selftests/kvm/arm64/set_id_regs.c +++ b/tools/testing/selftests/kvm/arm64/set_id_regs.c @@ -155,6 +155,7 @@ static const struct reg_ftr_bits ftr_id_aa64pfr0_el1[] = =3D { static const struct reg_ftr_bits ftr_id_aa64pfr1_el1[] =3D { REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR1_EL1, DF2, 0), REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR1_EL1, CSV2_frac, 0), + REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR1_EL1, SME, 0), REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR1_EL1, SSBS, ID_AA64PFR1_EL1_SSBS_= NI), REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR1_EL1, BT, 0), REG_FTR_END, @@ -212,6 +213,33 @@ static const struct reg_ftr_bits ftr_id_aa64mmfr3_el1[= ] =3D { REG_FTR_END, }; =20 +static const struct reg_ftr_bits ftr_id_aa64smfr0_el1[] =3D { + REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64SMFR0_EL1, FA64, 0), + REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64SMFR0_EL1, LUTv2, 0), + REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64SMFR0_EL1, SMEver, 0), + REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64SMFR0_EL1, I16I64, 0), + REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64SMFR0_EL1, F64F64, 0), + REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64SMFR0_EL1, I16I32, 0), + REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64SMFR0_EL1, B16B16, 0), + REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64SMFR0_EL1, F16F16, 0), + REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64SMFR0_EL1, F8F16, 0), + REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64SMFR0_EL1, F8F32, 0), + REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64SMFR0_EL1, I8I32, 0), + REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64SMFR0_EL1, F16F32, 0), + REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64SMFR0_EL1, B16F32, 0), + REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64SMFR0_EL1, BI32I32, 0), + REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64SMFR0_EL1, F32F32, 0), + REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64SMFR0_EL1, SF8FMA, 0), + REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64SMFR0_EL1, SF8DP4, 0), + REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64SMFR0_EL1, SF8DP2, 0), + REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64SMFR0_EL1, SBitPerm, 0), + REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64SMFR0_EL1, AES, 0), + REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64SMFR0_EL1, SFEXPA, 0), + REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64SMFR0_EL1, STMOP, 0), + REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64SMFR0_EL1, SMOP4, 0), + REG_FTR_END, +}; + static const struct reg_ftr_bits ftr_id_aa64zfr0_el1[] =3D { REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, F64MM, 0), REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, F32MM, 0), @@ -244,6 +272,7 @@ static struct test_feature_reg test_regs[] =3D { TEST_REG(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1_el1), TEST_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2_el1), TEST_REG(SYS_ID_AA64MMFR3_EL1, ftr_id_aa64mmfr3_el1), + TEST_REG(SYS_ID_AA64SMFR0_EL1, ftr_id_aa64smfr0_el1), TEST_REG(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0_el1), }; =20 @@ -263,6 +292,7 @@ static void guest_code(void) GUEST_REG_SYNC(SYS_ID_AA64MMFR1_EL1); GUEST_REG_SYNC(SYS_ID_AA64MMFR2_EL1); GUEST_REG_SYNC(SYS_ID_AA64MMFR3_EL1); + GUEST_REG_SYNC(SYS_ID_AA64SMFR0_EL1); GUEST_REG_SYNC(SYS_ID_AA64ZFR0_EL1); GUEST_REG_SYNC(SYS_MPIDR_EL1); GUEST_REG_SYNC(SYS_CLIDR_EL1); --=20 2.47.3