From nobody Mon Aug 24 20:41:01 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id EAF1A3DD521 for ; Wed, 8 Jul 2026 14:44:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783521863; cv=none; b=MDpvOV04MdeBSUIhCtz6gRGqCfolSjKbv3i6DLoLD1iEfwLIb7SOQHRHW/t4D8em57RQZKovXbpHw96AspHGhWQRFwKGUicPoPFctsv802OqaRaNc9jwEINzNhEaAlsIXrD22RsqyL0pj/cG/05lPeYFUG6FsQNAqypZwuvQiS4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783521863; c=relaxed/simple; bh=tetLVoUTiMzTHiqb6qREc2LJ1mi75j3jXctvOdMJdmc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=VwlTpTFcPt0ePVJvQt/3vuPcKrTx8ecdbRrITW4MbNtrsudUvFa+GgilfuUgq7dHMGsuwNlfPFU3f1Qmph0XvSo53P+hAoXHRNMs52KzRQpWov3Fr78Bg9HfZuUpEqFiuvREyydse+6Oj1wmUmPQHZeeKdZFkEIBL89OAyc9RtQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=PoAzkEB3; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="PoAzkEB3" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E65751CDD; Wed, 8 Jul 2026 07:44:16 -0700 (PDT) Received: from a079125.blr.arm.com (a079125.arm.com [10.164.21.43]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 69A4B3F7B4; Wed, 8 Jul 2026 07:44:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1783521861; bh=tetLVoUTiMzTHiqb6qREc2LJ1mi75j3jXctvOdMJdmc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=PoAzkEB3AdCqEi5+xMMcjhDTGGcVJTJ88f25wbbAijdHAEvPVcQCCqbmQGoE7r7KZ 5KqeSSE+etfRspyybPtIP2DoDA4Lp1NCe+IMtDW+W+GoUsa+ezsDIDl/uWumxcutJY q7Xnq3VKs74QjGSrSqqSiBIucuryN5C+maKSySWY= From: Linu Cherian To: Catalin Marinas , Will Deacon , Ryan Roberts , Kevin Brodsky , Anshuman Khandual , Suzuki K Poulose , Mark Rutland Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Linu Cherian Subject: [PATCH v2 6/6] arm64: cpufeature: Detect BBML3 based on MMFR2 ID Date: Wed, 8 Jul 2026 20:13:31 +0530 Message-ID: <20260708144331.679816-7-linu.cherian@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260708144331.679816-1-linu.cherian@arm.com> References: <20260708144331.679816-1-linu.cherian@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add MMFR2 ID based BBML3 feature detection, so that compliant cpus doesn't need to be added to the midr list. Signed-off-by: Linu Cherian Reviewed-by: Anshuman Khandual --- arch/arm64/kernel/cpufeature.c | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index e9ecaa036479..3f4a36f152d0 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -2133,6 +2133,12 @@ static bool hvhe_possible(const struct arm64_cpu_cap= abilities *entry, =20 bool cpu_supports_bbml3(void) { + u64 mmfr2; + + mmfr2 =3D __read_sysreg_by_encoding(SYS_ID_AA64MMFR2_EL1); + if (SYS_FIELD_GET(ID_AA64MMFR2_EL1, BBM, mmfr2) >=3D ID_AA64MMFR2_EL1_BBM= _3) + return true; + /* CPUs that support BBML3 but dont advertise through MMFR2 ID */ static const struct midr_range supports_bbml3_list[] =3D { MIDR_REV_RANGE(MIDR_CORTEX_X4, 0, 3, 0xf), @@ -2153,15 +2159,10 @@ bool cpu_supports_bbml3(void) {} }; =20 - if (!is_midr_in_range_list(supports_bbml3_list)) - return false; - - /* - * We currently ignore the ID_AA64MMFR2_EL1 register, and only care - * about whether the MIDR check passes. - */ + if (is_midr_in_range_list(supports_bbml3_list)) + return true; =20 - return true; + return false; } =20 static bool has_bbml3(const struct arm64_cpu_capabilities *caps, int scope) --=20 2.43.0