From nobody Tue Aug 25 10:46:55 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 421164657F6 for ; Wed, 8 Jul 2026 14:44:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783521850; cv=none; b=mTE1q0v/kh71fwPZLheZYDkopi87RW56M1FZgwnAk7LKIWv3ED1sPlCOo+Pb+ezFjKMX8RruJn4v1Z+sgBkIwpkQJe6XUmBT43H3cLQZZgDDy9gPXVZycTgxFapuqEyt0F1zdYoyocKAI6Wn7ka3NlxKi6rWxtRRSYemAfprPA4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783521850; c=relaxed/simple; bh=da+1swfZL2auAVAa38gH0HjBTNkoIG9H/N2feo5/2Pc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=TXt+61ssCmjz3gDb4vXg8eHPh2ThumfSa72VxRP5jfb/Pbj1MXpiDkAgRIB2K43nqDGsusYAnra7rsvxYRoj5AqckUy3yfC6o4TWZ1vNICNX5YwxNLP5nU6RaCy7BOSfBL7KKXFK3Kxq+1QNn6YfnIXqSOBNii8V7sXE/XgNwBA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=vK9iNDz6; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="vK9iNDz6" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 61A7E1CDD; Wed, 8 Jul 2026 07:44:03 -0700 (PDT) Received: from a079125.blr.arm.com (a079125.arm.com [10.164.21.43]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id D80653F7B4; Wed, 8 Jul 2026 07:44:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1783521847; bh=da+1swfZL2auAVAa38gH0HjBTNkoIG9H/N2feo5/2Pc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=vK9iNDz6EjNXC2V317m7LXvZCxxfKGeUvy/+yayiqBS4oRbUDHvdzXOcCss54I/Lw uXWkph/EziC4D0lV9w2yIPzO1Kbk++QttGPH4TLq9iZTJJueRtflwHKXkMRnZQ13I7 DuHoFv7l9RBkd6I+Nw4VVKR4mbisLO7mueSzfGaM= From: Linu Cherian To: Catalin Marinas , Will Deacon , Ryan Roberts , Kevin Brodsky , Anshuman Khandual , Suzuki K Poulose , Mark Rutland Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Linu Cherian Subject: [PATCH v2 2/6] arm64: cputype: Add C1-Nano definitions Date: Wed, 8 Jul 2026 20:13:27 +0530 Message-ID: <20260708144331.679816-3-linu.cherian@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260708144331.679816-1-linu.cherian@arm.com> References: <20260708144331.679816-1-linu.cherian@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add cputype definitions for C1-Nano. The definition can be found in C1-Nano TRM, https://developer.arm.com/documentation/107753/0002 as part of MIDR_EL1 bit descriptions. This is going to be used in the bbml3 support list. Signed-off-by: Linu Cherian Reviewed-by: Anshuman Khandual --- arch/arm64/include/asm/cputype.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cput= ype.h index e41fae46426b..1fa29616e586 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -100,6 +100,7 @@ #define ARM_CPU_PART_CORTEX_A720AE 0xD89 #define ARM_CPU_PART_C1_ULTRA 0xD8C #define ARM_CPU_PART_NEOVERSE_N3 0xD8E +#define ARM_CPU_PART_C1_NANO 0xD8A #define ARM_CPU_PART_C1_PRO 0xD8B #define ARM_CPU_PART_C1_PREMIUM 0xD90 =20 @@ -195,6 +196,7 @@ #define MIDR_CORTEX_A720AE MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CO= RTEX_A720AE) #define MIDR_C1_ULTRA MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_C1_ULTR= A) #define MIDR_NEOVERSE_N3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOV= ERSE_N3) +#define MIDR_C1_NANO MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_C1_NANO) #define MIDR_C1_PRO MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_C1_PRO) #define MIDR_C1_PREMIUM MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_C1_PR= EMIUM) #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_T= HUNDERX) --=20 2.43.0