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[PATCH v2 3/6] arm64: cpufeature: Extend bbml2_noabort support list

Linu Cherian posted 6 patches 1 month ago
There is a newer version of this series
[PATCH v2 3/6] arm64: cpufeature: Extend bbml2_noabort support list
Posted by Linu Cherian 1 month ago 
Add below cpus to the midr list, which supports
BBML2_NOABORT.

Cortex A520(AE)
Cortex A715
Cortex A720(AE)
Cortex A725
Neoverse N3
C1-Nano
C1-Pro
C1-Ultra
C1-Premium

C1-Ultra and C1-Premium both suffer from erratum 3683289,
where Break-Before-Make must be followed to avoid a livelock.
For both CPUs, the erratum is fixed from r1p1.
Hence we do not enable BBML2_NOABORT for CPU revisions <= r1p0.

The relevant SDENs are:
* C1-Ultra: https://developer.arm.com/documentation/111077/9-00/
* C1-Premium: https://developer.arm.com/documentation/111078/9-00/

Signed-off-by: Linu Cherian <linu.cherian@arm.com>
---
 arch/arm64/kernel/cpufeature.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 9a22df0c5120..adcabea80fcb 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -2152,6 +2152,15 @@ bool cpu_supports_bbml2_noabort(void)
 		MIDR_ALL_VERSIONS(MIDR_NVIDIA_OLYMPUS),
 		MIDR_ALL_VERSIONS(MIDR_AMPERE1),
 		MIDR_ALL_VERSIONS(MIDR_AMPERE1A),
+		MIDR_ALL_VERSIONS(MIDR_CORTEX_A520AE),
+		MIDR_ALL_VERSIONS(MIDR_CORTEX_A715),
+		MIDR_ALL_VERSIONS(MIDR_CORTEX_A720AE),
+		MIDR_ALL_VERSIONS(MIDR_CORTEX_A725),
+		MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N3),
+		MIDR_ALL_VERSIONS(MIDR_C1_NANO),
+		MIDR_ALL_VERSIONS(MIDR_C1_PRO),
+		MIDR_REV_RANGE(MIDR_C1_ULTRA, 1, 1, 0xf),
+		MIDR_REV_RANGE(MIDR_C1_PREMIUM, 1, 1, 0xf),
 		{}
 	};
 
-- 
2.43.0
Re: [PATCH v2 3/6] arm64: cpufeature: Extend bbml2_noabort support list
Posted by Suzuki K Poulose 1 month ago 
On 08/07/2026 15:43, Linu Cherian wrote:
> Add below cpus to the midr list, which supports
> BBML2_NOABORT.
> 
> Cortex A520(AE)
> Cortex A715
> Cortex A720(AE)
> Cortex A725
> Neoverse N3
> C1-Nano
> C1-Pro
> C1-Ultra
> C1-Premium
> 
> C1-Ultra and C1-Premium both suffer from erratum 3683289,
> where Break-Before-Make must be followed to avoid a livelock.
> For both CPUs, the erratum is fixed from r1p1.
> Hence we do not enable BBML2_NOABORT for CPU revisions <= r1p0.

Please could you also update the list of errata here :

Documentation/arch/arm64/silicon-errata.rst

> 
> The relevant SDENs are:
> * C1-Ultra: https://developer.arm.com/documentation/111077/9-00/
> * C1-Premium: https://developer.arm.com/documentation/111078/9-00/
> 
> Signed-off-by: Linu Cherian <linu.cherian@arm.com>
> ---
>   arch/arm64/kernel/cpufeature.c | 9 +++++++++
>   1 file changed, 9 insertions(+)
> 
> diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
> index 9a22df0c5120..adcabea80fcb 100644
> --- a/arch/arm64/kernel/cpufeature.c
> +++ b/arch/arm64/kernel/cpufeature.c
> @@ -2152,6 +2152,15 @@ bool cpu_supports_bbml2_noabort(void)
>   		MIDR_ALL_VERSIONS(MIDR_NVIDIA_OLYMPUS),
>   		MIDR_ALL_VERSIONS(MIDR_AMPERE1),
>   		MIDR_ALL_VERSIONS(MIDR_AMPERE1A),
> +		MIDR_ALL_VERSIONS(MIDR_CORTEX_A520AE),
> +		MIDR_ALL_VERSIONS(MIDR_CORTEX_A715),
> +		MIDR_ALL_VERSIONS(MIDR_CORTEX_A720AE),
> +		MIDR_ALL_VERSIONS(MIDR_CORTEX_A725),
> +		MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N3),
> +		MIDR_ALL_VERSIONS(MIDR_C1_NANO),
> +		MIDR_ALL_VERSIONS(MIDR_C1_PRO),

And mention it here, so that it is evident from the code alone ?

> +		MIDR_REV_RANGE(MIDR_C1_ULTRA, 1, 1, 0xf),
> +		MIDR_REV_RANGE(MIDR_C1_PREMIUM, 1, 1, 0xf),


Suzuki


>   		{}
>   	};
>
Re: [PATCH v2 3/6] arm64: cpufeature: Extend bbml2_noabort support list
Posted by Linu Cherian 3 weeks, 3 days ago 
On Wed, Jul 08, 2026 at 03:53:59PM +0100, Suzuki K Poulose wrote:
> On 08/07/2026 15:43, Linu Cherian wrote:
> > Add below cpus to the midr list, which supports
> > BBML2_NOABORT.
> > 
> > Cortex A520(AE)
> > Cortex A715
> > Cortex A720(AE)
> > Cortex A725
> > Neoverse N3
> > C1-Nano
> > C1-Pro
> > C1-Ultra
> > C1-Premium
> > 
> > C1-Ultra and C1-Premium both suffer from erratum 3683289,
> > where Break-Before-Make must be followed to avoid a livelock.
> > For both CPUs, the erratum is fixed from r1p1.
> > Hence we do not enable BBML2_NOABORT for CPU revisions <= r1p0.
> 
> Please could you also update the list of errata here :
> 
> Documentation/arch/arm64/silicon-errata.rst

Ack.

> 
> > 
> > The relevant SDENs are:
> > * C1-Ultra: https://developer.arm.com/documentation/111077/9-00/
> > * C1-Premium: https://developer.arm.com/documentation/111078/9-00/
> > 
> > Signed-off-by: Linu Cherian <linu.cherian@arm.com>
> > ---
> >   arch/arm64/kernel/cpufeature.c | 9 +++++++++
> >   1 file changed, 9 insertions(+)
> > 
> > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
> > index 9a22df0c5120..adcabea80fcb 100644
> > --- a/arch/arm64/kernel/cpufeature.c
> > +++ b/arch/arm64/kernel/cpufeature.c
> > @@ -2152,6 +2152,15 @@ bool cpu_supports_bbml2_noabort(void)
> >   		MIDR_ALL_VERSIONS(MIDR_NVIDIA_OLYMPUS),
> >   		MIDR_ALL_VERSIONS(MIDR_AMPERE1),
> >   		MIDR_ALL_VERSIONS(MIDR_AMPERE1A),
> > +		MIDR_ALL_VERSIONS(MIDR_CORTEX_A520AE),
> > +		MIDR_ALL_VERSIONS(MIDR_CORTEX_A715),
> > +		MIDR_ALL_VERSIONS(MIDR_CORTEX_A720AE),
> > +		MIDR_ALL_VERSIONS(MIDR_CORTEX_A725),
> > +		MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N3),
> > +		MIDR_ALL_VERSIONS(MIDR_C1_NANO),
> > +		MIDR_ALL_VERSIONS(MIDR_C1_PRO),
> 
> And mention it here, so that it is evident from the code alone ?
> 
Ack.

> > +		MIDR_REV_RANGE(MIDR_C1_ULTRA, 1, 1, 0xf),
> > +		MIDR_REV_RANGE(MIDR_C1_PREMIUM, 1, 1, 0xf),
> 
> 
> Suzuki
> 
> 
> >   		{}
> >   	};
>
Re: [PATCH v2 3/6] arm64: cpufeature: Extend bbml2_noabort support list
Posted by Anshuman Khandual 4 weeks ago 

On 08/07/26 8:23 PM, Suzuki K Poulose wrote:
> On 08/07/2026 15:43, Linu Cherian wrote:
>> Add below cpus to the midr list, which supports
>> BBML2_NOABORT.
>>
>> Cortex A520(AE)
>> Cortex A715
>> Cortex A720(AE)
>> Cortex A725
>> Neoverse N3
>> C1-Nano
>> C1-Pro
>> C1-Ultra
>> C1-Premium
>>
>> C1-Ultra and C1-Premium both suffer from erratum 3683289,
>> where Break-Before-Make must be followed to avoid a livelock.
>> For both CPUs, the erratum is fixed from r1p1.
>> Hence we do not enable BBML2_NOABORT for CPU revisions <= r1p0.
> 
> Please could you also update the list of errata here :
> 
> Documentation/arch/arm64/silicon-errata.rst

Agreed. There are existing errata entries for C1-Ultra
and C1-Premimum although this errata will not have any
corresponding ARM64_ERRATUM_ associated for now.
> 
>>
>> The relevant SDENs are:
>> * C1-Ultra: https://developer.arm.com/documentation/111077/9-00/
>> * C1-Premium: https://developer.arm.com/documentation/111078/9-00/
>>
>> Signed-off-by: Linu Cherian <linu.cherian@arm.com>
>> ---
>>   arch/arm64/kernel/cpufeature.c | 9 +++++++++
>>   1 file changed, 9 insertions(+)
>>
>> diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
>> index 9a22df0c5120..adcabea80fcb 100644
>> --- a/arch/arm64/kernel/cpufeature.c
>> +++ b/arch/arm64/kernel/cpufeature.c
>> @@ -2152,6 +2152,15 @@ bool cpu_supports_bbml2_noabort(void)
>>           MIDR_ALL_VERSIONS(MIDR_NVIDIA_OLYMPUS),
>>           MIDR_ALL_VERSIONS(MIDR_AMPERE1),
>>           MIDR_ALL_VERSIONS(MIDR_AMPERE1A),
>> +        MIDR_ALL_VERSIONS(MIDR_CORTEX_A520AE),
>> +        MIDR_ALL_VERSIONS(MIDR_CORTEX_A715),
>> +        MIDR_ALL_VERSIONS(MIDR_CORTEX_A720AE),
>> +        MIDR_ALL_VERSIONS(MIDR_CORTEX_A725),
>> +        MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N3),
>> +        MIDR_ALL_VERSIONS(MIDR_C1_NANO),
>> +        MIDR_ALL_VERSIONS(MIDR_C1_PRO),
> 
> And mention it here, so that it is evident from the code alone ?
> 
>> +        MIDR_REV_RANGE(MIDR_C1_ULTRA, 1, 1, 0xf),
>> +        MIDR_REV_RANGE(MIDR_C1_PREMIUM, 1, 1, 0xf),
> 
> 
> Suzuki
> 
> 
>>           {}
>>       };
>>   
>

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