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[129.46.232.65]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-69a19d799dfsm8960807a12.17.2026.07.08.07.33.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Jul 2026 07:33:49 -0700 (PDT) From: Wenmeng Liu Date: Wed, 08 Jul 2026 22:33:31 +0800 Subject: [PATCH v3 1/3] dt-bindings: media: i2c: og0ve1b: Add OmniVision OG0VA1B camera sensor Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260708-og0va1b-v3-1-de8e44455a42@oss.qualcomm.com> References: <20260708-og0va1b-v3-0-de8e44455a42@oss.qualcomm.com> In-Reply-To: <20260708-og0va1b-v3-0-de8e44455a42@oss.qualcomm.com> To: Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sakari Ailus , Vladimir Zapolskiy Cc: linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Wenmeng Liu , Conor Dooley X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1783521218; l=2177; i=wenmeng.liu@oss.qualcomm.com; s=20250925; h=from:subject:message-id; bh=TcAXQjm3y4bxY72fFI+XTJk2M6ZXHTIsdSnWHX2Ufxk=; b=eOQlSqTcykO4M//Paj47OebtxtOxi9wvnK5xZ2N72tc4H9OFa9quCPN+CddBZxo8k5/X4/RBm udMqlrxvMMoDynl4QpFDMS4DKO6x8B86OondLn8L3o8bp22VIN1xWZv X-Developer-Key: i=wenmeng.liu@oss.qualcomm.com; a=ed25519; pk=fQJjf9C3jGDjE1zj2kO3NQLTbQEaZObVcXAzx5WLPX0= X-Authority-Analysis: v=2.4 cv=GJc41ONK c=1 sm=1 tr=0 ts=6a4e5fd0 cx=c_pps a=mPf7EqFMSY9/WdsSgAYMbA==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=gEfo2CItAAAA:8 a=XYAwZIGsAAAA:8 a=KKAkSRfTAAAA:8 a=EUspDBNiAAAA:8 a=M65GHGH_L51Dv4RaLaoA:9 a=QEXdDO2ut3YA:10 a=dawVfQjAaf238kedN5IG:22 a=sptkURWiP4Gy88Gu7hUp:22 a=E8ToXWR_bxluHZ7gmE-Z:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwNzA4MDE0MyBTYWx0ZWRfXzkc/SneQrDQr d07XBWIa+nElPBDTQd2ojYFUkY8c+lLZs+HaYXtuGcGGfzXIakmr9UK0WbHu3oUgf1N1jdJEfHP ixYqPE8aM9xwRQmR4LB494/Ur2iTqJc= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzA4MDE0MyBTYWx0ZWRfXyDb3HUIS2ZnP 1VTT37LC8DprlulCLLsrlEBSYroNa83P2BElpMvOR3KMV1swUiZ7gwYX7FQR6g8sBGE4hnVZKJA PY7k+i4n6q0+Stl87taIEdeE77lV02ERkzxtzIXlE2mByL24oubCyk933eRrwUkT/rCEPD3zSXS 1D6jMsjZAF9dLlNb9/uwbjo/20DtzyCpN2ZFOouv9kz1AZhrHaaUo3rP5MHAUV7UBlWrSX9b5fK cpn/uVQlDcBUeUOXIg/Cgm2mxCG48p+m7tq58R2STS985QhZJ7NDnJVoQT/xFKYF72XJ3LXctmn 5MLwLhySARtCuN65OPc1JniJYrEPm7HfaJOqHLIAguEuc6zIm3eEBNrrjhGRurhNHTDyyIPHDrM 8cR2y2VaAgZDGXDr4QLtBDJEVtoOxqxq6RsAaQfFYu55u3EuZbPeoMio8AuIfAxh2yHw+utxG4T IM7vtKjp7zSM76RbwkQ== X-Proofpoint-ORIG-GUID: qWWoZ7VriIJLRV9ks5NOnVjt6HXLAR0D X-Proofpoint-GUID: qWWoZ7VriIJLRV9ks5NOnVjt6HXLAR0D X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-08_02,2026-07-08_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 clxscore=1015 priorityscore=1501 malwarescore=0 impostorscore=0 adultscore=0 bulkscore=0 spamscore=0 lowpriorityscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607080143 The OmniVision OG0VA1B is a monochrome image sensor closely related to the already supported OG0VE1B. It shares the same SCCB control interface, power supplies and MIPI D-PHY description, but differs in its chip ID, register programming and output format. Generalise the binding title and description to cover both sensors. Acked-by: Conor Dooley Reviewed-by: Vladimir Zapolskiy Signed-off-by: Wenmeng Liu --- .../devicetree/bindings/media/i2c/ovti,og0ve1b.yaml | 15 ++++++++---= ---- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/media/i2c/ovti,og0ve1b.yaml = b/Documentation/devicetree/bindings/media/i2c/ovti,og0ve1b.yaml index bd2f1ae23e6547032361924a6953000bab1129df..b6fa9645c7c6cb3fa907478684d= 02b01d916fea1 100644 --- a/Documentation/devicetree/bindings/media/i2c/ovti,og0ve1b.yaml +++ b/Documentation/devicetree/bindings/media/i2c/ovti,og0ve1b.yaml @@ -4,14 +4,13 @@ $id: http://devicetree.org/schemas/media/i2c/ovti,og0ve1b.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# =20 -title: OmniVision OG0VE1B Image Sensor +title: OmniVision OG0VA1B and OG0VE1B Image Sensors =20 description: - OmniVision OG0VE1B image sensor is a low power consuming monochrome - image sensor. The sensor is controlled over a serial camera control - bus protocol (SCCB), the widest supported image size is 640x480 at - 120 frames per second rate, data output format is 8/10-bit RAW - transferred over one-lane MIPI D-PHY at up to 800 Mbps. + OmniVision OG0VA1B and OG0VE1B are low power consuming monochrome image + sensors. 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Introduce a sensor_data structure, populated through i2c_get_match_data(), to hold the chip ID, MCLK frequency, link frequencies and supported modes. Test pattern programming is described by a per-sensor callback, and each mode stores its media bus format code (rather than a bits-per-pixel value) so that sensors with a different output format can be supported. Signed-off-by: Wenmeng Liu Reviewed-by: Vladimir Zapolskiy Tested-by: Vladimir Zapolskiy --- drivers/media/i2c/og0ve1b.c | 99 ++++++++++++++++++++++++++++++++---------= ---- 1 file changed, 71 insertions(+), 28 deletions(-) diff --git a/drivers/media/i2c/og0ve1b.c b/drivers/media/i2c/og0ve1b.c index 84a28cdcade10f8fbcf945999e88f84641b9bc0d..041342fbe3c822400388f58a03e= 6057e186f060f 100644 --- a/drivers/media/i2c/og0ve1b.c +++ b/drivers/media/i2c/og0ve1b.c @@ -65,11 +65,23 @@ struct og0ve1b_mode { u32 height; /* Frame height in pixels */ u32 hts; /* Horizontal timing size */ u32 vts; /* Default vertical timing size */ - u32 bpp; /* Bits per pixel */ + u32 code; /* MEDIA_BUS_FMT code */ =20 const struct og0ve1b_reg_list reg_list; /* Sensor register setting */ }; =20 +struct og0ve1b; + +struct og0ve1b_sensor_data { + u64 chip_id; + unsigned long mclk_freq; + int (*enable_test_pattern)(struct og0ve1b *og0ve1b, u32 pattern); + const s64 *link_freq_menu; + int num_link_freqs; + const struct og0ve1b_mode *modes; + int num_modes; +}; + static const char * const og0ve1b_test_pattern_menu[] =3D { "Disabled", "Vertical Colour Bars", @@ -99,6 +111,8 @@ struct og0ve1b { =20 /* Saved register value */ u64 pre_isp; + + const struct og0ve1b_sensor_data *data; }; =20 static const struct cci_reg_sequence og0ve1b_640x480_120fps_mode[] =3D { @@ -247,13 +261,13 @@ static const struct cci_reg_sequence og0ve1b_640x480_= 120fps_mode[] =3D { { CCI_REG8(0x3f47), 0x35 }, }; =20 -static const struct og0ve1b_mode supported_modes[] =3D { +static const struct og0ve1b_mode og0ve1b_supported_modes[] =3D { { .width =3D 640, .height =3D 480, .hts =3D 792, .vts =3D 568, - .bpp =3D 8, + .code =3D MEDIA_BUS_FMT_Y8_1X8, .reg_list =3D { .regs =3D og0ve1b_640x480_120fps_mode, .num_regs =3D ARRAY_SIZE(og0ve1b_640x480_120fps_mode), @@ -273,11 +287,21 @@ static int og0ve1b_enable_test_pattern(struct og0ve1b= *og0ve1b, u32 pattern) return cci_write(og0ve1b->regmap, OG0VE1B_REG_PRE_ISP, val, NULL); } =20 +static const struct og0ve1b_sensor_data og0ve1b_data =3D { + .chip_id =3D OG0VE1B_CHIP_ID, + .mclk_freq =3D OG0VE1B_MCLK_FREQ_24MHZ, + .enable_test_pattern =3D og0ve1b_enable_test_pattern, + .link_freq_menu =3D og0ve1b_link_freq_menu, + .num_link_freqs =3D ARRAY_SIZE(og0ve1b_link_freq_menu), + .modes =3D og0ve1b_supported_modes, + .num_modes =3D ARRAY_SIZE(og0ve1b_supported_modes), +}; + static int og0ve1b_set_ctrl(struct v4l2_ctrl *ctrl) { struct og0ve1b *og0ve1b =3D container_of(ctrl->handler, struct og0ve1b, ctrl_handler); - const struct og0ve1b_mode *mode =3D &supported_modes[0]; + const struct og0ve1b_mode *mode =3D &og0ve1b->data->modes[0]; s64 exposure_max; int ret; =20 @@ -314,7 +338,7 @@ static int og0ve1b_set_ctrl(struct v4l2_ctrl *ctrl) ctrl->val + mode->height, NULL); break; case V4L2_CID_TEST_PATTERN: - ret =3D og0ve1b_enable_test_pattern(og0ve1b, ctrl->val); + ret =3D og0ve1b->data->enable_test_pattern(og0ve1b, ctrl->val); break; default: ret =3D -EINVAL; @@ -330,10 +354,19 @@ static const struct v4l2_ctrl_ops og0ve1b_ctrl_ops = =3D { .s_ctrl =3D og0ve1b_set_ctrl, }; =20 +static s64 og0ve1b_pixel_rate(const struct og0ve1b_sensor_data *data) +{ + const struct og0ve1b_mode *mode =3D &data->modes[0]; + unsigned int bpp =3D mode->code =3D=3D MEDIA_BUS_FMT_Y8_1X8 ? 8 : 10; + + return data->link_freq_menu[0] / bpp; +} + static int og0ve1b_init_controls(struct og0ve1b *og0ve1b) { struct v4l2_ctrl_handler *ctrl_hdlr =3D &og0ve1b->ctrl_handler; - const struct og0ve1b_mode *mode =3D &supported_modes[0]; + const struct og0ve1b_mode *mode =3D &og0ve1b->data->modes[0]; + const struct og0ve1b_sensor_data *data =3D og0ve1b->data; s64 exposure_max, pixel_rate, h_blank, v_blank; struct v4l2_fwnode_device_properties props; struct v4l2_ctrl *ctrl; @@ -343,12 +376,12 @@ static int og0ve1b_init_controls(struct og0ve1b *og0v= e1b) =20 ctrl =3D v4l2_ctrl_new_int_menu(ctrl_hdlr, &og0ve1b_ctrl_ops, V4L2_CID_LINK_FREQ, - ARRAY_SIZE(og0ve1b_link_freq_menu) - 1, - 0, og0ve1b_link_freq_menu); + data->num_link_freqs - 1, + 0, data->link_freq_menu); if (ctrl) ctrl->flags |=3D V4L2_CTRL_FLAG_READ_ONLY; =20 - pixel_rate =3D og0ve1b_link_freq_menu[0] / mode->bpp; + pixel_rate =3D og0ve1b_pixel_rate(data); v4l2_ctrl_new_std(ctrl_hdlr, &og0ve1b_ctrl_ops, V4L2_CID_PIXEL_RATE, 0, pixel_rate, 1, pixel_rate); =20 @@ -407,7 +440,7 @@ static int og0ve1b_init_controls(struct og0ve1b *og0ve1= b) static void og0ve1b_update_pad_format(const struct og0ve1b_mode *mode, struct v4l2_mbus_framefmt *fmt) { - fmt->code =3D MEDIA_BUS_FMT_Y8_1X8; + fmt->code =3D mode->code; fmt->width =3D mode->width; fmt->height =3D mode->height; fmt->field =3D V4L2_FIELD_NONE; @@ -421,8 +454,8 @@ static int og0ve1b_enable_streams(struct v4l2_subdev *s= d, struct v4l2_subdev_state *state, u32 pad, u64 streams_mask) { - const struct og0ve1b_reg_list *reg_list =3D &supported_modes[0].reg_list; struct og0ve1b *og0ve1b =3D to_og0ve1b(sd); + const struct og0ve1b_reg_list *reg_list =3D &og0ve1b->data->modes[0].reg_= list; int ret; =20 ret =3D pm_runtime_resume_and_get(og0ve1b->dev); @@ -484,13 +517,14 @@ static int og0ve1b_set_pad_format(struct v4l2_subdev = *sd, struct v4l2_subdev_state *state, struct v4l2_subdev_format *fmt) { + struct og0ve1b *og0ve1b =3D to_og0ve1b(sd); struct v4l2_mbus_framefmt *format; const struct og0ve1b_mode *mode; =20 format =3D v4l2_subdev_state_get_format(state, 0); =20 - mode =3D v4l2_find_nearest_size(supported_modes, - ARRAY_SIZE(supported_modes), + mode =3D v4l2_find_nearest_size(og0ve1b->data->modes, + og0ve1b->data->num_modes, width, height, fmt->format.width, fmt->format.height); @@ -505,10 +539,12 @@ static int og0ve1b_enum_mbus_code(struct v4l2_subdev = *sd, struct v4l2_subdev_state *sd_state, struct v4l2_subdev_mbus_code_enum *code) { + struct og0ve1b *og0ve1b =3D to_og0ve1b(sd); + if (code->index > 0) return -EINVAL; =20 - code->code =3D MEDIA_BUS_FMT_Y8_1X8; + code->code =3D og0ve1b->data->modes[0].code; =20 return 0; } @@ -517,15 +553,18 @@ static int og0ve1b_enum_frame_size(struct v4l2_subdev= *sd, struct v4l2_subdev_state *sd_state, struct v4l2_subdev_frame_size_enum *fse) { - if (fse->index >=3D ARRAY_SIZE(supported_modes)) + struct og0ve1b *og0ve1b =3D to_og0ve1b(sd); + const struct og0ve1b_sensor_data *data =3D og0ve1b->data; + + if (fse->index >=3D data->num_modes) return -EINVAL; =20 - if (fse->code !=3D MEDIA_BUS_FMT_Y8_1X8) + if (fse->code !=3D data->modes[fse->index].code) return -EINVAL; =20 - fse->min_width =3D supported_modes[fse->index].width; + fse->min_width =3D data->modes[fse->index].width; fse->max_width =3D fse->min_width; - fse->min_height =3D supported_modes[fse->index].height; + fse->min_height =3D data->modes[fse->index].height; fse->max_height =3D fse->min_height; =20 return 0; @@ -534,13 +573,14 @@ static int og0ve1b_enum_frame_size(struct v4l2_subdev= *sd, static int og0ve1b_init_state(struct v4l2_subdev *sd, struct v4l2_subdev_state *state) { + const struct og0ve1b_mode *mode =3D &to_og0ve1b(sd)->data->modes[0]; struct v4l2_subdev_format fmt =3D { .which =3D V4L2_SUBDEV_FORMAT_TRY, .pad =3D 0, .format =3D { - .code =3D MEDIA_BUS_FMT_Y8_1X8, - .width =3D supported_modes[0].width, - .height =3D supported_modes[0].height, + .code =3D mode->code, + .width =3D mode->width, + .height =3D mode->height, }, }; =20 @@ -586,9 +626,9 @@ static int og0ve1b_identify_sensor(struct og0ve1b *og0v= e1b) return ret; } =20 - if (val !=3D OG0VE1B_CHIP_ID) { - dev_err(og0ve1b->dev, "chip id mismatch: %x!=3D%llx\n", - OG0VE1B_CHIP_ID, val); + if (val !=3D og0ve1b->data->chip_id) { + dev_err(og0ve1b->dev, "chip id mismatch: %llx!=3D%llx\n", + og0ve1b->data->chip_id, val); return -ENODEV; } =20 @@ -624,8 +664,8 @@ static int og0ve1b_check_hwcfg(struct og0ve1b *og0ve1b) ret =3D v4l2_link_freq_to_bitmap(og0ve1b->dev, bus_cfg.link_frequencies, bus_cfg.nr_of_link_frequencies, - og0ve1b_link_freq_menu, - ARRAY_SIZE(og0ve1b_link_freq_menu), + og0ve1b->data->link_freq_menu, + og0ve1b->data->num_link_freqs, &freq_bitmap); =20 v4l2_fwnode_endpoint_free(&bus_cfg); @@ -686,6 +726,9 @@ static int og0ve1b_probe(struct i2c_client *client) return -ENOMEM; =20 og0ve1b->dev =3D &client->dev; + og0ve1b->data =3D i2c_get_match_data(client); + if (!og0ve1b->data) + return -ENODEV; =20 v4l2_i2c_subdev_init(&og0ve1b->sd, client, &og0ve1b_subdev_ops); =20 @@ -700,7 +743,7 @@ static int og0ve1b_probe(struct i2c_client *client) "failed to get XVCLK clock\n"); =20 freq =3D clk_get_rate(og0ve1b->xvclk); - if (freq && freq !=3D OG0VE1B_MCLK_FREQ_24MHZ) + if (freq && freq !=3D og0ve1b->data->mclk_freq) return dev_err_probe(og0ve1b->dev, -EINVAL, "XVCLK clock frequency %lu is not supported\n", freq); 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[129.46.232.65]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-69a19d799dfsm8960807a12.17.2026.07.08.07.33.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Jul 2026 07:34:01 -0700 (PDT) From: Wenmeng Liu Date: Wed, 08 Jul 2026 22:33:33 +0800 Subject: [PATCH v3 3/3] media: i2c: og0ve1b: Add support for OmniVision OG0VA1B Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260708-og0va1b-v3-3-de8e44455a42@oss.qualcomm.com> References: <20260708-og0va1b-v3-0-de8e44455a42@oss.qualcomm.com> In-Reply-To: <20260708-og0va1b-v3-0-de8e44455a42@oss.qualcomm.com> To: Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sakari Ailus , Vladimir Zapolskiy Cc: linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Wenmeng Liu X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1783521218; l=13795; i=wenmeng.liu@oss.qualcomm.com; s=20250925; h=from:subject:message-id; bh=W9GQ6QR1JtY+YQtEccM46qsoY4lGhyLNE1fe8YxR7W4=; b=OJxBEqmDNnE+mpvn4QgrWkjbdOM+4xIYymQ2xYAUZUt9rDFlGZ+vTSfZalCs8Bq77atAjlP1A NNS62HjbnMDAI9EvKSbIlcwBSxsjyIwhohtOBPeOA8OsFgPHQLpAwKF X-Developer-Key: i=wenmeng.liu@oss.qualcomm.com; a=ed25519; pk=fQJjf9C3jGDjE1zj2kO3NQLTbQEaZObVcXAzx5WLPX0= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzA4MDE0MyBTYWx0ZWRfX7hHnXNAhxthg 7PzIfYoI9uiX7sv/ywrpycx2KQk+Wr2t85OrGwGgODPe6BbixEzxv00NoxiCsxU6NJcfLiFxeSO p7bQwUdYsxJnJH1w6+ao6213XhiW8e4Au+X/UytqibsBOwD/u1vTiFz+tmbhMWhO2Fn2IwHvEWM dNXee+vVdHiV8baM7vRDI4zZhaMFDETv82jpNXbnFE9Y+GmRJOqW8+n1KP3l/cckCKxw7/UEPEG O35XXBsWQocfP17azD2b/VIKqnvDwD4C8RUcThMJWrSz2NxvUdkV8UFKRP44eQLMi4z7nh2k+hp 39AtMolNbY/HG+A1z1M+RBWl5XnlitfeE/5qGSHNitDBKm47yUnzrKnYq33elbb8jrZpGLYBYY7 0GD5SJpa/ky31Z9lLBHN33Tzn8bvgydqCVHJeF98f0jJJgZhuak2YIO1ItffBbXkiE/GtklqTD1 VVB6A3FTLgCrzBV8p9w== X-Proofpoint-ORIG-GUID: CXYzgaF4okuZYrwSK8i5RIhxzQTOtaWx X-Authority-Analysis: v=2.4 cv=NfTWEWD4 c=1 sm=1 tr=0 ts=6a4e5fdd cx=c_pps a=WeENfcodrlLV9YRTxbY/uA==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=EUspDBNiAAAA:8 a=KKAkSRfTAAAA:8 a=tvl-DPrvojhGWlv_sV8A:9 a=QEXdDO2ut3YA:10 a=kacYvNCVWA4VmyqE58fU:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwNzA4MDE0MyBTYWx0ZWRfX4WnAzuwE8IcU bxoB6rj/Y/ThJH6symZt5/4krA0uMnnjaUn/GYyMZEiUFB0GT2MQhwFjHVuSu2GcR97BlSs4lSr 6F3Xdz5K28LP3+gNiZL9z1x1qZ5uP5Y= X-Proofpoint-GUID: CXYzgaF4okuZYrwSK8i5RIhxzQTOtaWx X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-08_02,2026-07-08_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=0 phishscore=0 bulkscore=0 clxscore=1015 priorityscore=1501 impostorscore=0 malwarescore=0 adultscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607080143 The OmniVision OG0VA1B is a monochrome image sensor closely related to the OG0VE1B. It shares the SCCB control interface, power supplies and the single-lane MIPI D-PHY description, and differs in its chip id, the test pattern register, the register programming and the output format (10-bit RAW instead of 8-bit). Add an og0ve1b_sensor_data entry describing the OG0VA1B together with its 640x480 60fps register sequence. Signed-off-by: Wenmeng Liu Reviewed-by: Vladimir Zapolskiy Tested-by: Vladimir Zapolskiy # og0ve1b --- drivers/media/i2c/og0ve1b.c | 278 ++++++++++++++++++++++++++++++++++++++++= ++-- 1 file changed, 266 insertions(+), 12 deletions(-) diff --git a/drivers/media/i2c/og0ve1b.c b/drivers/media/i2c/og0ve1b.c index 041342fbe3c822400388f58a03e6057e186f060f..c558cdd43314931db35e463641d= d28e10b94ec8a 100644 --- a/drivers/media/i2c/og0ve1b.c +++ b/drivers/media/i2c/og0ve1b.c @@ -14,10 +14,14 @@ #include #include =20 +#define OG0VA1B_LINK_FREQ_480MHZ (480 * HZ_PER_MHZ) +#define OG0VA1B_MCLK_FREQ_19_2MHZ (19200 * HZ_PER_KHZ) + #define OG0VE1B_LINK_FREQ_500MHZ (500 * HZ_PER_MHZ) #define OG0VE1B_MCLK_FREQ_24MHZ (24 * HZ_PER_MHZ) =20 -#define OG0VE1B_REG_CHIP_ID CCI_REG24(0x300a) +#define OG0V_REG_CHIP_ID CCI_REG24(0x300a) +#define OG0VA1B_CHIP_ID 0xc75641 #define OG0VE1B_CHIP_ID 0xc75645 =20 #define OG0VE1B_REG_MODE_SELECT CCI_REG8(0x0100) @@ -45,12 +49,18 @@ #define OG0VE1B_REG_VTS CCI_REG16(0x380e) #define OG0VE1B_VTS_MAX 0xffff =20 -/* Test pattern */ +/* Test pattern - OG0VA1B uses 0x5100, OG0VE1B uses 0x5e00 */ +#define OG0VA1B_REG_TEST_PATTERN CCI_REG8(0x5100) +#define OG0VA1B_TEST_PATTERN_BAR_SHIFT 2 #define OG0VE1B_REG_PRE_ISP CCI_REG8(0x5e00) #define OG0VE1B_TEST_PATTERN_ENABLE BIT(7) =20 #define to_og0ve1b(_sd) container_of(_sd, struct og0ve1b, sd) =20 +static const s64 og0va1b_link_freq_menu[] =3D { + OG0VA1B_LINK_FREQ_480MHZ, +}; + static const s64 og0ve1b_link_freq_menu[] =3D { OG0VE1B_LINK_FREQ_500MHZ, }; @@ -73,15 +83,31 @@ struct og0ve1b_mode { struct og0ve1b; =20 struct og0ve1b_sensor_data { + const char *name; u64 chip_id; unsigned long mclk_freq; int (*enable_test_pattern)(struct og0ve1b *og0ve1b, u32 pattern); + const char * const *test_pattern_menu; + int num_test_patterns; + bool cache_test_pattern_reg; + /* Exposure register unit: OG0VE1B 1/16 line (4), OG0VA1B whole lines (0)= . */ + unsigned int exposure_shift; + /* Pixel rate multiplier: OG0VA1B uses CSI-2 DDR (2), OG0VE1B keeps 1. */ + unsigned int pixel_rate_mul; const s64 *link_freq_menu; int num_link_freqs; const struct og0ve1b_mode *modes; int num_modes; }; =20 +static const char * const og0va1b_test_pattern_menu[] =3D { + "Disabled", + "Standard Color Bar", + "Top-Bottom Darker Color Bar", + "Right-Left Darker Color Bar", + "Bottom-Top Darker Color Bar", +}; + static const char * const og0ve1b_test_pattern_menu[] =3D { "Disabled", "Vertical Colour Bars", @@ -115,6 +141,196 @@ struct og0ve1b { const struct og0ve1b_sensor_data *data; }; =20 +static const struct cci_reg_sequence og0va1b_640x480_60fps_mode[] =3D { + { CCI_REG8(0x0302), 0x31 }, + { CCI_REG8(0x0303), 0x02 }, + { CCI_REG8(0x0304), 0x01 }, + { CCI_REG8(0x0305), 0x90 }, + { CCI_REG8(0x0306), 0x00 }, + { CCI_REG8(0x0323), 0x02 }, + { CCI_REG8(0x0325), 0x68 }, + { CCI_REG8(0x0326), 0xd8 }, + { CCI_REG8(0x3006), 0x0e }, + { CCI_REG8(0x300d), 0x08 }, + { CCI_REG8(0x3018), 0xf0 }, + { CCI_REG8(0x301c), 0xf0 }, + { CCI_REG8(0x3020), 0x20 }, + { CCI_REG8(0x3040), 0x0f }, + { CCI_REG8(0x3022), 0x01 }, + { CCI_REG8(0x3107), 0x40 }, + { CCI_REG8(0x3216), 0x01 }, + { CCI_REG8(0x3217), 0x00 }, + { CCI_REG8(0x3218), 0xc0 }, + { CCI_REG8(0x3219), 0x55 }, + { CCI_REG8(0x3506), 0x01 }, + { CCI_REG8(0x3507), 0x50 }, + { CCI_REG8(0x3508), 0x01 }, + { CCI_REG8(0x3509), 0x00 }, + { CCI_REG8(0x350a), 0x01 }, + { CCI_REG8(0x350b), 0x00 }, + { CCI_REG8(0x350c), 0x00 }, + { CCI_REG8(0x3541), 0x00 }, + { CCI_REG8(0x3542), 0x40 }, + { CCI_REG8(0x3605), 0x90 }, + { CCI_REG8(0x3606), 0x41 }, + { CCI_REG8(0x3612), 0x00 }, + { CCI_REG8(0x3620), 0x08 }, + { CCI_REG8(0x3630), 0x17 }, + { CCI_REG8(0x3631), 0x99 }, + { CCI_REG8(0x3639), 0x88 }, + { CCI_REG8(0x3668), 0x00 }, + { CCI_REG8(0x3674), 0x00 }, + { CCI_REG8(0x3677), 0x3f }, + { CCI_REG8(0x368f), 0x06 }, + { CCI_REG8(0x36a2), 0x19 }, + { CCI_REG8(0x36a4), 0xf1 }, + { CCI_REG8(0x36a5), 0x2d }, + { CCI_REG8(0x3706), 0x30 }, + { CCI_REG8(0x370d), 0x72 }, + { CCI_REG8(0x3713), 0x86 }, + { CCI_REG8(0x3715), 0x03 }, + { CCI_REG8(0x3716), 0x00 }, + { CCI_REG8(0x376d), 0x24 }, + { CCI_REG8(0x3770), 0x3a }, + { CCI_REG8(0x3778), 0x00 }, + { CCI_REG8(0x37a8), 0x03 }, + { CCI_REG8(0x37a9), 0x00 }, + { CCI_REG8(0x37df), 0x7d }, + { CCI_REG8(0x3800), 0x00 }, + { CCI_REG8(0x3801), 0x00 }, + { CCI_REG8(0x3802), 0x00 }, + { CCI_REG8(0x3803), 0x00 }, + { CCI_REG8(0x3804), 0x02 }, + { CCI_REG8(0x3805), 0x8f }, + { CCI_REG8(0x3806), 0x01 }, + { CCI_REG8(0x3807), 0xef }, + { CCI_REG8(0x3808), 0x02 }, + { CCI_REG8(0x3809), 0x80 }, + { CCI_REG8(0x380a), 0x01 }, + { CCI_REG8(0x380b), 0xe0 }, + { CCI_REG8(0x380c), 0x01 }, + { CCI_REG8(0x380d), 0x78 }, + { CCI_REG8(0x380e), 0x08 }, + { CCI_REG8(0x380f), 0x30 }, + { CCI_REG8(0x3810), 0x00 }, + { CCI_REG8(0x3811), 0x08 }, + { CCI_REG8(0x3812), 0x00 }, + { CCI_REG8(0x3813), 0x08 }, + { CCI_REG8(0x3814), 0x11 }, + { CCI_REG8(0x3815), 0x11 }, + { CCI_REG8(0x3816), 0x00 }, + { CCI_REG8(0x3817), 0x01 }, + { CCI_REG8(0x3818), 0x00 }, + { CCI_REG8(0x3819), 0x05 }, + { CCI_REG8(0x3820), 0x40 }, + { CCI_REG8(0x3821), 0x04 }, + { CCI_REG8(0x3823), 0x00 }, + { CCI_REG8(0x3826), 0x00 }, + { CCI_REG8(0x3827), 0x00 }, + { CCI_REG8(0x382b), 0x52 }, + { CCI_REG8(0x384a), 0xa2 }, + { CCI_REG8(0x3858), 0x00 }, + { CCI_REG8(0x3859), 0x00 }, + { CCI_REG8(0x3860), 0x00 }, + { CCI_REG8(0x3861), 0x00 }, + { CCI_REG8(0x3866), 0x0c }, + { CCI_REG8(0x3867), 0x07 }, + { CCI_REG8(0x3884), 0x00 }, + { CCI_REG8(0x3885), 0x08 }, + { CCI_REG8(0x3888), 0x50 }, + { CCI_REG8(0x3893), 0x6c }, + { CCI_REG8(0x3898), 0x00 }, + { CCI_REG8(0x389a), 0x04 }, + { CCI_REG8(0x389b), 0x01 }, + { CCI_REG8(0x389c), 0x0b }, + { CCI_REG8(0x389d), 0xdc }, + { CCI_REG8(0x38b1), 0x04 }, + { CCI_REG8(0x38b2), 0x00 }, + { CCI_REG8(0x38b3), 0x08 }, + { CCI_REG8(0x38c1), 0x46 }, + { CCI_REG8(0x38c9), 0x02 }, + { CCI_REG8(0x38d4), 0x06 }, + { CCI_REG8(0x38d5), 0x5a }, + { CCI_REG8(0x38d6), 0x08 }, + { CCI_REG8(0x38d7), 0x3a }, + { CCI_REG8(0x391f), 0x00 }, + { CCI_REG8(0x3920), 0xaa }, + { CCI_REG8(0x3921), 0x00 }, + { CCI_REG8(0x3922), 0x00 }, + { CCI_REG8(0x3923), 0x00 }, + { CCI_REG8(0x3924), 0x00 }, + { CCI_REG8(0x3925), 0x00 }, + { CCI_REG8(0x3926), 0x00 }, + { CCI_REG8(0x3927), 0x00 }, + { CCI_REG8(0x3928), 0x10 }, + { CCI_REG8(0x3929), 0x01 }, + { CCI_REG8(0x392a), 0xb4 }, + { CCI_REG8(0x392b), 0x00 }, + { CCI_REG8(0x392c), 0x10 }, + { CCI_REG8(0x392d), 0x01 }, + { CCI_REG8(0x392e), 0x78 }, + { CCI_REG8(0x392f), 0x4a }, + { CCI_REG8(0x391e), 0x01 }, + { CCI_REG8(0x389f), 0x08 }, + { CCI_REG8(0x38a0), 0x00 }, + { CCI_REG8(0x38a1), 0x00 }, + { CCI_REG8(0x3a06), 0x06 }, + { CCI_REG8(0x3a07), 0x78 }, + { CCI_REG8(0x3a08), 0x08 }, + { CCI_REG8(0x3a09), 0x80 }, + { CCI_REG8(0x3a52), 0x00 }, + { CCI_REG8(0x3a53), 0x01 }, + { CCI_REG8(0x3a54), 0x0c }, + { CCI_REG8(0x3a55), 0x04 }, + { CCI_REG8(0x3a58), 0x0c }, + { CCI_REG8(0x3a59), 0x04 }, + { CCI_REG8(0x4000), 0xcf }, + { CCI_REG8(0x4003), 0x40 }, + { CCI_REG8(0x4008), 0x04 }, + { CCI_REG8(0x4009), 0x13 }, + { CCI_REG8(0x400a), 0x02 }, + { CCI_REG8(0x400b), 0x34 }, + { CCI_REG8(0x4010), 0x71 }, + { CCI_REG8(0x4042), 0xc3 }, + { CCI_REG8(0x4306), 0x04 }, + { CCI_REG8(0x4307), 0x12 }, + { CCI_REG8(0x4500), 0x70 }, + { CCI_REG8(0x4509), 0x00 }, + { CCI_REG8(0x450b), 0x83 }, + { CCI_REG8(0x4604), 0x68 }, + { CCI_REG8(0x481b), 0x44 }, + { CCI_REG8(0x481f), 0x30 }, + { CCI_REG8(0x4823), 0x44 }, + { CCI_REG8(0x4825), 0x35 }, + { CCI_REG8(0x4837), 0x11 }, + { CCI_REG8(0x4f00), 0x04 }, + { CCI_REG8(0x4f10), 0x04 }, + { CCI_REG8(0x4f21), 0x01 }, + { CCI_REG8(0x4f22), 0x00 }, + { CCI_REG8(0x4f23), 0x54 }, + { CCI_REG8(0x4f24), 0x51 }, + { CCI_REG8(0x4f25), 0x41 }, + { CCI_REG8(0x5000), 0x3f }, + { CCI_REG8(0x5001), 0x80 }, + { CCI_REG8(0x500a), 0x00 }, + { CCI_REG8(0x5100), 0x00 }, + { CCI_REG8(0x5111), 0x20 }, +}; + +static const struct og0ve1b_mode og0va1b_supported_modes[] =3D { + { + .width =3D 640, + .height =3D 480, + .hts =3D 752, + .vts =3D 2096, + .code =3D MEDIA_BUS_FMT_Y10_1X10, + .reg_list =3D { + .regs =3D og0va1b_640x480_60fps_mode, + .num_regs =3D ARRAY_SIZE(og0va1b_640x480_60fps_mode), + }, + }, +}; + static const struct cci_reg_sequence og0ve1b_640x480_120fps_mode[] =3D { { CCI_REG8(0x30a0), 0x02 }, { CCI_REG8(0x30a1), 0x00 }, @@ -275,6 +491,17 @@ static const struct og0ve1b_mode og0ve1b_supported_mod= es[] =3D { }, }; =20 +static int og0va1b_enable_test_pattern(struct og0ve1b *og0ve1b, u32 patter= n) +{ + u64 val =3D 0; + + if (pattern) + val =3D ((pattern - 1) << OG0VA1B_TEST_PATTERN_BAR_SHIFT) | + OG0VE1B_TEST_PATTERN_ENABLE; + + return cci_write(og0ve1b->regmap, OG0VA1B_REG_TEST_PATTERN, val, NULL); +} + static int og0ve1b_enable_test_pattern(struct og0ve1b *og0ve1b, u32 patter= n) { u64 val =3D og0ve1b->pre_isp; @@ -287,10 +514,31 @@ static int og0ve1b_enable_test_pattern(struct og0ve1b= *og0ve1b, u32 pattern) return cci_write(og0ve1b->regmap, OG0VE1B_REG_PRE_ISP, val, NULL); } =20 +static const struct og0ve1b_sensor_data og0va1b_data =3D { + .name =3D "og0va1b", + .chip_id =3D OG0VA1B_CHIP_ID, + .mclk_freq =3D OG0VA1B_MCLK_FREQ_19_2MHZ, + .enable_test_pattern =3D og0va1b_enable_test_pattern, + .test_pattern_menu =3D og0va1b_test_pattern_menu, + .num_test_patterns =3D ARRAY_SIZE(og0va1b_test_pattern_menu), + .exposure_shift =3D 0, + .pixel_rate_mul =3D 2, + .link_freq_menu =3D og0va1b_link_freq_menu, + .num_link_freqs =3D ARRAY_SIZE(og0va1b_link_freq_menu), + .modes =3D og0va1b_supported_modes, + .num_modes =3D ARRAY_SIZE(og0va1b_supported_modes), +}; + static const struct og0ve1b_sensor_data og0ve1b_data =3D { + .name =3D "og0ve1b", .chip_id =3D OG0VE1B_CHIP_ID, .mclk_freq =3D OG0VE1B_MCLK_FREQ_24MHZ, .enable_test_pattern =3D og0ve1b_enable_test_pattern, + .test_pattern_menu =3D og0ve1b_test_pattern_menu, + .num_test_patterns =3D ARRAY_SIZE(og0ve1b_test_pattern_menu), + .cache_test_pattern_reg =3D true, + .exposure_shift =3D 4, + .pixel_rate_mul =3D 1, .link_freq_menu =3D og0ve1b_link_freq_menu, .num_link_freqs =3D ARRAY_SIZE(og0ve1b_link_freq_menu), .modes =3D og0ve1b_supported_modes, @@ -331,7 +579,8 @@ static int og0ve1b_set_ctrl(struct v4l2_ctrl *ctrl) break; case V4L2_CID_EXPOSURE: ret =3D cci_write(og0ve1b->regmap, OG0VE1B_REG_EXPOSURE, - ctrl->val << 4, NULL); + ctrl->val << og0ve1b->data->exposure_shift, + NULL); break; case V4L2_CID_VBLANK: ret =3D cci_write(og0ve1b->regmap, OG0VE1B_REG_VTS, @@ -359,7 +608,7 @@ static s64 og0ve1b_pixel_rate(const struct og0ve1b_sens= or_data *data) const struct og0ve1b_mode *mode =3D &data->modes[0]; unsigned int bpp =3D mode->code =3D=3D MEDIA_BUS_FMT_Y8_1X8 ? 8 : 10; =20 - return data->link_freq_menu[0] / bpp; + return data->link_freq_menu[0] * data->pixel_rate_mul / bpp; } =20 static int og0ve1b_init_controls(struct og0ve1b *og0ve1b) @@ -412,8 +661,8 @@ static int og0ve1b_init_controls(struct og0ve1b *og0ve1= b) =20 v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &og0ve1b_ctrl_ops, V4L2_CID_TEST_PATTERN, - ARRAY_SIZE(og0ve1b_test_pattern_menu) - 1, - 0, 0, og0ve1b_test_pattern_menu); + data->num_test_patterns - 1, + 0, 0, data->test_pattern_menu); =20 if (ctrl_hdlr->error) return ctrl_hdlr->error; @@ -620,7 +869,7 @@ static int og0ve1b_identify_sensor(struct og0ve1b *og0v= e1b) u64 val; int ret; =20 - ret =3D cci_read(og0ve1b->regmap, OG0VE1B_REG_CHIP_ID, &val, NULL); + ret =3D cci_read(og0ve1b->regmap, OG0V_REG_CHIP_ID, &val, NULL); if (ret) { dev_err(og0ve1b->dev, "failed to read chip id: %d\n", ret); return ret; @@ -632,10 +881,12 @@ static int og0ve1b_identify_sensor(struct og0ve1b *og= 0ve1b) return -ENODEV; } =20 - ret =3D cci_read(og0ve1b->regmap, OG0VE1B_REG_PRE_ISP, - &og0ve1b->pre_isp, NULL); - if (ret) - dev_err(og0ve1b->dev, "failed to read pre_isp: %d\n", ret); + if (og0ve1b->data->cache_test_pattern_reg) { + ret =3D cci_read(og0ve1b->regmap, OG0VE1B_REG_PRE_ISP, + &og0ve1b->pre_isp, NULL); + if (ret) + dev_err(og0ve1b->dev, "failed to read pre_isp: %d\n", ret); + } =20 return ret; } @@ -731,6 +982,8 @@ static int og0ve1b_probe(struct i2c_client *client) return -ENODEV; =20 v4l2_i2c_subdev_init(&og0ve1b->sd, client, &og0ve1b_subdev_ops); + v4l2_i2c_subdev_set_name(&og0ve1b->sd, client, + og0ve1b->data->name, NULL); =20 og0ve1b->regmap =3D devm_cci_regmap_init_i2c(client, 16); if (IS_ERR(og0ve1b->regmap)) @@ -862,6 +1115,7 @@ static const struct dev_pm_ops og0ve1b_pm_ops =3D { }; =20 static const struct of_device_id og0ve1b_of_match[] =3D { + { .compatible =3D "ovti,og0va1b", .data =3D &og0va1b_data }, { .compatible =3D "ovti,og0ve1b", .data =3D &og0ve1b_data }, { /* sentinel */ } }; @@ -880,5 +1134,5 @@ static struct i2c_driver og0ve1b_i2c_driver =3D { module_i2c_driver(og0ve1b_i2c_driver); =20 MODULE_AUTHOR("Vladimir Zapolskiy "); -MODULE_DESCRIPTION("OmniVision OG0VE1B sensor driver"); +MODULE_DESCRIPTION("OmniVision OG0VE1B/OG0VA1B sensor driver"); MODULE_LICENSE("GPL"); --=20 2.34.1