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About what smi-sub-common is, please check the below diagram, we add it in mediatek,smi-common.yaml file. Signed-off-by: Zhengnan Chen Signed-off-by: Congcong Yao --- .../mediatek,smi-common.yaml | 18 ++++++++++++++++++ .../memory-controllers/mediatek,smi-larb.yaml | 3 +++ 2 files changed, 21 insertions(+) diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,= smi-common.yaml b/Documentation/devicetree/bindings/memory-controllers/medi= atek,smi-common.yaml index 0762e0ff66ef..4e1deeff92b1 100644 --- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-com= mon.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-com= mon.yaml @@ -25,6 +25,21 @@ description: | SMI generation 1 to transform the smi clock into emi clock domain, but t= hat is not needed for SMI generation 2. =20 + The smi-common connects with smi-larb and IOMMU. The maximum inputs numb= er of + a smi-common is 8. In SMI generation 2, the engines number may be over 8. + In this case, we use a smi-sub-common to merge some larbs. + The block diagram something is like: + + IOMMU + | | + smi-common + --------------------------- + | | ... + larb0 sub-common ... <-max number is 8 + ---------------- + | | ... + larb1 larbX ... <-max number is 8 + properties: compatible: oneOf: @@ -40,6 +55,8 @@ properties: - mediatek,mt8186-smi-common - mediatek,mt8188-smi-common-vdo - mediatek,mt8188-smi-common-vpp + - mediatek,mt8189-smi-common + - mediatek,mt8189-smi-sub-common - mediatek,mt8192-smi-common - mediatek,mt8195-smi-common-vdo - mediatek,mt8195-smi-common-vpp @@ -108,6 +125,7 @@ allOf: compatible: contains: enum: + - mediatek,mt8189-smi-sub-common - mediatek,mt8195-smi-sub-common then: required: diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,= smi-larb.yaml b/Documentation/devicetree/bindings/memory-controllers/mediat= ek,smi-larb.yaml index 2e7fac4b5094..9a5dafd7c07e 100644 --- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-lar= b.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-lar= b.yaml @@ -27,6 +27,7 @@ properties: - mediatek,mt8183-smi-larb - mediatek,mt8186-smi-larb - mediatek,mt8188-smi-larb + - mediatek,mt8189-smi-larb - mediatek,mt8192-smi-larb - mediatek,mt8195-smi-larb =20 @@ -85,6 +86,7 @@ allOf: - mediatek,mt8183-smi-larb - mediatek,mt8186-smi-larb - mediatek,mt8188-smi-larb + - mediatek,mt8189-smi-larb - mediatek,mt8195-smi-larb =20 then: @@ -119,6 +121,7 @@ allOf: - mediatek,mt6779-smi-larb - mediatek,mt8186-smi-larb - mediatek,mt8188-smi-larb + - mediatek,mt8189-smi-larb - mediatek,mt8192-smi-larb - mediatek,mt8195-smi-larb =20 --=20 2.43.0 From nobody Mon Jul 6 12:35:07 2026 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 791373BAD9D; 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charset="utf-8" From: Zhengnan Chen Add the necessary platform data and ostdl setting to enable support for mt8189 smi. Signed-off-by: Zhengnan Chen Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Yong Wu Signed-off-by: Congcong Yao --- drivers/memory/mtk-smi.c | 44 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c index aaeba8ab211e..f2d5462af681 100644 --- a/drivers/memory/mtk-smi.c +++ b/drivers/memory/mtk-smi.c @@ -401,6 +401,30 @@ static const u8 mtk_smi_larb_mt8188_ostd[][SMI_LARB_PO= RT_NR_MAX] =3D { [25] =3D {0x01}, }; =20 +static const u8 mtk_smi_larb_mt8189_ostd[][SMI_LARB_PORT_NR_MAX] =3D { + [0] =3D {0x8, 0x20, 0x20, 0x20, 0x20, 0x20, 0x10, 0x0,}, + [1] =3D {0x8, 0x20, 0x20, 0x20, 0x20, 0x20, 0x10, 0x0,}, + [2] =3D {0x7, 0x7, 0x4, 0x4, 0x0, 0x0, 0x2, 0x2, 0x7, 0x7, 0x0,}, + [4] =3D {0x2F, 0x1E, 0x9, 0x1, 0x1, 0x1, 0x1, 0x2, 0x2, 0x5, 0x1, 0x17,}, + [7] =3D {0x20, 0x2, 0x1, 0x1, 0x1, 0x4, 0x2, 0x1, 0x1, 0x2, 0x3, 0x2, + 0xA, 0xF, 0x4, 0x6, 0x5, 0x1,}, + [9] =3D {0x6, 0x3, 0xC, 0x6, 0x1, 0x4, 0x3, 0x1, 0x2, 0x4, 0x5, 0x2, + 0x4, 0x2, 0x3, 0xB, 0x1, 0x4, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, + 0x1, 0x1,}, + [11] =3D {0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, + 0x1, 0x1, 0x1, 0xB, 0x1, 0x4, 0x6, 0x5, 0x6, 0x1, 0x5, 0x2, + 0x9, 0x5,}, + [13] =3D {0x2, 0x8, 0x8, 0x8, 0x4, 0x4, 0x4, 0x4, 0x4, 0xE, 0x4, 0x1, + 0x6, 0x6, 0x2,}, + [14] =3D {0x1, 0x1, 0x1, 0x20, 0xE, 0x4, 0x8, 0x8, 0x6, 0x4,}, + [16] =3D {0x1E, 0xC, 0x2, 0x8, 0xE, 0x2, 0x1E, 0x10, 0x4, 0x2, 0x2, 0x2, + 0x2, 0x2, 0x4, 0x2, 0x4,}, + [17] =3D {0x1E, 0xC, 0x2, 0x8, 0xE, 0x2, 0x1E, 0x10, 0x4, 0x2, 0x2, 0x2, + 0x2, 0x2, 0x4, 0x2, 0x4,}, + [19] =3D {0x2, 0x1, 0x3, 0x1,}, + [20] =3D {0x7, 0x7, 0x3, 0x3, 0x1, 0x1,}, +}; + static const u8 mtk_smi_larb_mt8192_ostd[][SMI_LARB_PORT_NR_MAX] =3D { [0] =3D {0x2, 0x2, 0x28, 0xa, 0xc, 0x28,}, [1] =3D {0x2, 0x2, 0x18, 0x18, 0x18, 0xa, 0xc, 0x28,}, @@ -533,6 +557,13 @@ static const struct mtk_smi_larb_gen mtk_smi_larb_mt81= 88 =3D { .ostd =3D mtk_smi_larb_mt8188_ostd, }; =20 +static const struct mtk_smi_larb_gen mtk_smi_larb_mt8189 =3D { + .config_port =3D mtk_smi_larb_config_port_gen2_general, + .flags_general =3D MTK_SMI_FLAG_THRT_UPDATE | MTK_SMI_FLAG_SW= _FLAG | + MTK_SMI_FLAG_SLEEP_CTL | MTK_SMI_FLAG_CFG_PORT_SEC_CTL, + .ostd =3D mtk_smi_larb_mt8189_ostd, +}; + static const struct mtk_smi_larb_gen mtk_smi_larb_mt8192 =3D { .config_port =3D mtk_smi_larb_config_port_gen2_general, .ostd =3D mtk_smi_larb_mt8192_ostd, @@ -556,6 +587,7 @@ static const struct of_device_id mtk_smi_larb_of_ids[] = =3D { {.compatible =3D "mediatek,mt8183-smi-larb", .data =3D &mtk_smi_larb_mt81= 83}, {.compatible =3D "mediatek,mt8186-smi-larb", .data =3D &mtk_smi_larb_mt81= 86}, {.compatible =3D "mediatek,mt8188-smi-larb", .data =3D &mtk_smi_larb_mt81= 88}, + {.compatible =3D "mediatek,mt8189-smi-larb", .data =3D &mtk_smi_larb_mt81= 89}, {.compatible =3D "mediatek,mt8192-smi-larb", .data =3D &mtk_smi_larb_mt81= 92}, {.compatible =3D "mediatek,mt8195-smi-larb", .data =3D &mtk_smi_larb_mt81= 95}, {} @@ -808,6 +840,16 @@ static const struct mtk_smi_common_plat mtk_smi_common= _mt8188_vpp =3D { .init =3D mtk_smi_common_mt8195_init, }; =20 +static const struct mtk_smi_common_plat mtk_smi_common_mt8189 =3D { + .type =3D MTK_SMI_GEN2, + .bus_sel =3D F_MMU1_LARB(1) | F_MMU1_LARB(3) | F_MMU1_LARB(5) | + F_MMU1_LARB(7), +}; + +static const struct mtk_smi_common_plat mtk_smi_sub_common_mt8189 =3D { + .type =3D MTK_SMI_GEN2_SUB_COMM, +}; + static const struct mtk_smi_common_plat mtk_smi_common_mt8192 =3D { .type =3D MTK_SMI_GEN2, .has_gals =3D true, @@ -852,6 +894,8 @@ static const struct of_device_id mtk_smi_common_of_ids[= ] =3D { {.compatible =3D "mediatek,mt8186-smi-common", .data =3D &mtk_smi_common_= mt8186}, {.compatible =3D "mediatek,mt8188-smi-common-vdo", .data =3D &mtk_smi_com= mon_mt8188_vdo}, {.compatible =3D "mediatek,mt8188-smi-common-vpp", .data =3D &mtk_smi_com= mon_mt8188_vpp}, + {.compatible =3D "mediatek,mt8189-smi-common", .data =3D &mtk_smi_common_= mt8189}, + {.compatible =3D "mediatek,mt8189-smi-sub-common", .data =3D &mtk_smi_sub= _common_mt8189}, {.compatible =3D "mediatek,mt8192-smi-common", .data =3D &mtk_smi_common_= mt8192}, {.compatible =3D "mediatek,mt8195-smi-common-vdo", .data =3D &mtk_smi_com= mon_mt8195_vdo}, {.compatible =3D "mediatek,mt8195-smi-common-vpp", .data =3D &mtk_smi_com= mon_mt8195_vpp}, --=20 2.43.0