From nobody Wed Jul 1 12:06:03 2026 Received: from twmbx01.aspeedtech.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2CD1F3B3BE5; Wed, 1 Jul 2026 06:58:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782889118; cv=none; b=hO3UUrMZgBiBTvoRKnt8Ecyz6fAWM9taPY3jilGBL6AaInKL5TILHM17foGgT6kez/APQWi9tWQiL3AAmheQpwExqfbhX0Izf6L15Hw9ImaNE5rep0Q7qyZMqR3Nm3yz6lA1CG6e8arDCE3JsODr66ZhoNbGdiV8daP2HRKeziQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782889118; c=relaxed/simple; bh=PMotyQehgGrEVoSSxouKDsCZuOfMr0EXxz1QwPMc58k=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=eII/LVZI3sH/CaZfFanbze3cCgH2D3As8bxBBBM/LguwfUZVhOC8eHYmZcD/3p5680zEEf09kzGeDzsmBoC2em8PG07o+W9WWPtXSft0vuNjR1Nqoxxo5zmAMO4A7KWIvotYDpp0zb8LDzYnWoqW4vvLtB11r/2j0t9hVS32zFg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 1 Jul 2026 14:58:18 +0800 Received: from [127.0.1.1] (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Wed, 1 Jul 2026 14:58:18 +0800 From: Ryan Chen Date: Wed, 1 Jul 2026 14:58:17 +0800 Subject: [PATCH v3 1/3] dt-bindings: phy: aspeed: Document AST2700 USB3.2 PHY Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260701-upstream_usb3phy-v3-1-00e12315b6f9@aspeedtech.com> References: <20260701-upstream_usb3phy-v3-0-00e12315b6f9@aspeedtech.com> In-Reply-To: <20260701-upstream_usb3phy-v3-0-00e12315b6f9@aspeedtech.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , "Andrew Jeffery" , Philipp Zabel CC: , , , , , Ryan Chen , Krzysztof Kozlowski X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1782889098; l=1695; i=ryan_chen@aspeedtech.com; s=20251126; h=from:subject:message-id; bh=PMotyQehgGrEVoSSxouKDsCZuOfMr0EXxz1QwPMc58k=; b=hFYD8zr7qSwYWi6q+U7ERKc+wEuXk5ozWnoYh3PntDKqnIiHF9YUjjcmrw0X6MNajmxg8Kify Fc5OD8AAIs5D9K5zHG+UO9vW52Z/J5fAJ34frQ6l1q6meyT4e65Uu4d X-Developer-Key: i=ryan_chen@aspeedtech.com; a=ed25519; pk=Xe73xY6tcnkuRjjbVAB/oU30KdB3FvG4nuJuILj7ZVc= Document AST2700 USB3.2 PHY. This IP is connected between USB3 controller and PHY module. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Ryan Chen --- .../bindings/phy/aspeed,ast2700-usb3-phy.yaml | 48 ++++++++++++++++++= ++++ 1 file changed, 48 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/aspeed,ast2700-usb3-phy.= yaml b/Documentation/devicetree/bindings/phy/aspeed,ast2700-usb3-phy.yaml new file mode 100644 index 000000000000..b83037aa0438 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/aspeed,ast2700-usb3-phy.yaml @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/aspeed,ast2700-usb3-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ASPEED AST2700 USB 3.2 PHY + +maintainers: + - Ryan Chen + +properties: + compatible: + const: aspeed,ast2700-usb3-phy + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + '#phy-cells': + const: 0 + +required: + - compatible + - reg + - clocks + - resets + - '#phy-cells' + +additionalProperties: false + +examples: + - | + #include + #include + + usb-phy@12010000 { + compatible =3D "aspeed,ast2700-usb3-phy"; + reg =3D <0x12010000 0xc0>; + clocks =3D <&syscon0 SCU0_CLK_GATE_PORTAUSB2CLK>; + resets =3D <&syscon0 SCU0_RESET_PORTA_PHY3>; + #phy-cells =3D <0>; + }; --=20 2.34.1 From nobody Wed Jul 1 12:06:03 2026 Received: from twmbx01.aspeedtech.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5B5973B47F3; Wed, 1 Jul 2026 06:58:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782889120; cv=none; b=tTQs9jP6GNqw58It88OdfdlS4euwaCATknnhn5EyGuguH6z+WNpPSHmiglOlzSnPB7k8425WAO/3O51CL9mv2P6V+3yJnllwrNGrA7A4o3VNXJ5gWnUEvDRhrVxSwfECbYvBsjVtrriQKh83IwAD2RFr/I2YMLjAgUco8lriLzQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782889120; c=relaxed/simple; bh=1ev22esjMN6mzTKH+myy5O4JjFTSQ+E4rn/t7pEFxP0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=kX91gGV6yD6/kg5rst+UkC+v/G985K1WpK9b0Q56S4VIOQsaLO0pFUxzI4L0n/TSmRleznS7WGuR8LOQ9hDej18W8BB8CQjxrZVLQ8olKO7XnxyaKPzF4bRvOT2uqjKRyS1j/ORUMkWvQZNY40OHLV/Fo7WXECJRrxCUpQ9fgiQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 1 Jul 2026 14:58:18 +0800 Received: from [127.0.1.1] (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Wed, 1 Jul 2026 14:58:18 +0800 From: Ryan Chen Date: Wed, 1 Jul 2026 14:58:18 +0800 Subject: [PATCH v3 2/3] phy: aspeed: Add AST2700 USB3.2 PHY driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260701-upstream_usb3phy-v3-2-00e12315b6f9@aspeedtech.com> References: <20260701-upstream_usb3phy-v3-0-00e12315b6f9@aspeedtech.com> In-Reply-To: <20260701-upstream_usb3phy-v3-0-00e12315b6f9@aspeedtech.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , "Andrew Jeffery" , Philipp Zabel CC: , , , , , Ryan Chen X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1782889098; l=10148; i=ryan_chen@aspeedtech.com; s=20251126; h=from:subject:message-id; bh=1ev22esjMN6mzTKH+myy5O4JjFTSQ+E4rn/t7pEFxP0=; b=Dwz//yd2vACbJCQav8UpOpqijMcS1qS79BB0HnEGhxqImaKBR+nDB4WrFJIP7+J4DDvs5CcNd IXHYQkL0DVTAkdGFHGqIqMnjpNQm/DMeEMSwW7dVT1Hs5YJ7QcVNQQ5 X-Developer-Key: i=ryan_chen@aspeedtech.com; a=ed25519; pk=Xe73xY6tcnkuRjjbVAB/oU30KdB3FvG4nuJuILj7ZVc= Add AST2700 USB3.2 PHY driver support. Signed-off-by: Ryan Chen --- drivers/phy/Kconfig | 1 + drivers/phy/Makefile | 1 + drivers/phy/aspeed/Kconfig | 15 +++ drivers/phy/aspeed/Makefile | 2 + drivers/phy/aspeed/phy-aspeed-usb3.c | 236 +++++++++++++++++++++++++++++++= ++++ 5 files changed, 255 insertions(+) diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index 19f3b7d12b7d..85fa381978f8 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -171,6 +171,7 @@ config PHY_XGENE source "drivers/phy/allwinner/Kconfig" source "drivers/phy/amlogic/Kconfig" source "drivers/phy/apple/Kconfig" +source "drivers/phy/aspeed/Kconfig" source "drivers/phy/axiado/Kconfig" source "drivers/phy/broadcom/Kconfig" source "drivers/phy/cadence/Kconfig" diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index d7aa516bcc49..c6dd02003bbe 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -23,6 +23,7 @@ obj-$(CONFIG_PHY_XGENE) +=3D phy-xgene.o obj-$(CONFIG_GENERIC_PHY) +=3D allwinner/ \ amlogic/ \ apple/ \ + aspeed/ \ axiado/ \ broadcom/ \ cadence/ \ diff --git a/drivers/phy/aspeed/Kconfig b/drivers/phy/aspeed/Kconfig new file mode 100644 index 000000000000..7b5f48db2be8 --- /dev/null +++ b/drivers/phy/aspeed/Kconfig @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0-only + +# +# PHY drivers for ASPEED +# + +config PHY_ASPEED_USB3 + tristate "ASPEED USB3 PHY driver" + select GENERIC_PHY + depends on (ARCH_ASPEED || COMPILE_TEST) + help + Enable this to support the USB 3.2 PHY on the Aspeed AST2700 SoC. + It supports SuperSpeedPlus Gen2x1 (10 Gbps), SuperSpeed (5 Gbps), + High Speed (480 Mbps), Full Speed (12 Mbps) and Low Speed + (1.5 Mbps), and is paired with the DWC3 USB controller. diff --git a/drivers/phy/aspeed/Makefile b/drivers/phy/aspeed/Makefile new file mode 100644 index 000000000000..d96d9d73a009 --- /dev/null +++ b/drivers/phy/aspeed/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +obj-$(CONFIG_PHY_ASPEED_USB3) +=3D phy-aspeed-usb3.o diff --git a/drivers/phy/aspeed/phy-aspeed-usb3.c b/drivers/phy/aspeed/phy-= aspeed-usb3.c new file mode 100644 index 000000000000..eff148faa14c --- /dev/null +++ b/drivers/phy/aspeed/phy-aspeed-usb3.c @@ -0,0 +1,236 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2026 Aspeed Technology Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define PHY3S00 0x00 +#define PHY3S00_INIT_DONE BIT(15) +#define PHY3S00_SRAM_BYPASS BIT(7) +#define PHY3S00_SRAM_EXT_LOAD BIT(6) +#define PHY3S04 0x04 +#define PHY3C00 0x08 +#define PHY3C04 0x0C +#define PHY3P00 0x10 +#define PHY3P00_RX_ADAPT_AFE_EN_G1 BIT(0) +#define PHY3P00_RX_ADAPT_AFE_EN_G2 BIT(1) +#define PHY3P00_RX_ADAPT_DFE_EN_G1 BIT(2) +#define PHY3P00_RX_ADAPT_DFE_EN_G2 BIT(3) +#define PHY3P00_RX_CDR_VCO_LOWFREQ_G1 BIT(4) +#define PHY3P00_RX_CDR_VCO_LOWFREQ_G2 BIT(5) +#define PHY3P00_RX_EQ_AFE_GAIN_G1 GENMASK(9, 6) +#define PHY3P00_RX_EQ_AFE_GAIN_G2 GENMASK(13, 10) +#define PHY3P00_RX_EQ_ATT_LVL_G1 GENMASK(16, 14) +#define PHY3P00_RX_EQ_ATT_LVL_G2 GENMASK(19, 17) +#define PHY3P00_RX_EQ_CTLE_BOOST_G1 GENMASK(24, 20) +#define PHY3P00_RX_EQ_CTLE_BOOST_G2 GENMASK(29, 25) +#define PHY3P00_RX_EQ_DELTA_IQ_G1_LO GENMASK(31, 30) + +#define PHY3P04 0x14 +#define PHY3P04_RX_EQ_DELTA_IQ_G1_HI GENMASK(1, 0) +#define PHY3P04_RX_EQ_DELTA_IQ_G2 GENMASK(5, 2) +#define PHY3P04_RX_EQ_DFE_TAP1_G1 GENMASK(13, 6) +#define PHY3P04_RX_EQ_DFE_TAP1_G2 GENMASK(21, 14) +#define PHY3P04_RX_LOS_LFPS_EN BIT(22) +#define PHY3P04_RX_LOS_THRESHOLD GENMASK(25, 23) +#define PHY3P04_RX_TERM_CTRL GENMASK(28, 26) +#define PHY3P04_TX_EQ_MAIN_G1_LO GENMASK(31, 29) + +#define PHY3P08 0x18 +#define PHY3P08_TX_EQ_MAIN_G1_HI GENMASK(1, 0) +#define PHY3P08_TX_EQ_MAIN_G2 GENMASK(6, 2) +#define PHY3P08_TX_EQ_OVRD BIT(7) +#define PHY3P08_TX_EQ_POST_G1 GENMASK(12, 9) +#define PHY3P08_TX_EQ_POST_G2 GENMASK(16, 13) +#define PHY3P08_TX_EQ_PRE_G1 GENMASK(20, 17) +#define PHY3P08_TX_EQ_PRE_G2 GENMASK(24, 21) +#define PHY3P08_TX_IBOOST_LVL GENMASK(28, 25) +#define PHY3P08_TX_TERM_CTRL GENMASK(31, 29) + +#define PHY3P0C 0x1C +#define PHY3P0C_TX_VBOOST_EN BIT(0) + +#define PHY3CMD 0x40 + +#define PHY3P_RX_EQ_CTLE_BOOST_G1_DEFAULT 0x7 +#define PHY3P_RX_EQ_CTLE_BOOST_G2_DEFAULT 0x7 +#define PHY3P_RX_EQ_DELTA_IQ_G1_DEFAULT 0x3 +#define PHY3P_RX_EQ_DELTA_IQ_G2_DEFAULT 0x5 +#define PHY3P_RX_LOS_THRESHOLD_DEFAULT 0x3 +#define PHY3P_RX_TERM_CTRL_DEFAULT 0x2 +#define PHY3P_TX_EQ_MAIN_G1_DEFAULT 0xa +#define PHY3P_TX_EQ_MAIN_G2_DEFAULT 0x9 +#define PHY3P_TX_EQ_POST_G1_DEFAULT 0x4 +#define PHY3P_TX_EQ_POST_G2_DEFAULT 0x3 +#define PHY3P_TX_EQ_PRE_G2_DEFAULT 0x2 +#define PHY3P_TX_IBOOST_LVL_DEFAULT 0xf +#define PHY3P_TX_TERM_CTRL_DEFAULT 0x2 + +#define PHY3P00_DEFAULT ( \ + PHY3P00_RX_ADAPT_AFE_EN_G1 | \ + PHY3P00_RX_ADAPT_AFE_EN_G2 | \ + PHY3P00_RX_ADAPT_DFE_EN_G1 | \ + PHY3P00_RX_ADAPT_DFE_EN_G2 | \ + FIELD_PREP(PHY3P00_RX_EQ_CTLE_BOOST_G1, PHY3P_RX_EQ_CTLE_BOOST_G1_DEFAULT= ) | \ + FIELD_PREP(PHY3P00_RX_EQ_CTLE_BOOST_G2, PHY3P_RX_EQ_CTLE_BOOST_G2_DEFAULT= ) | \ + FIELD_PREP(PHY3P00_RX_EQ_DELTA_IQ_G1_LO, \ + PHY3P_RX_EQ_DELTA_IQ_G1_DEFAULT & 0x3) \ +) + +#define PHY3P04_DEFAULT ( \ + FIELD_PREP(PHY3P04_RX_EQ_DELTA_IQ_G1_HI, \ + PHY3P_RX_EQ_DELTA_IQ_G1_DEFAULT >> 2) | \ + FIELD_PREP(PHY3P04_RX_EQ_DELTA_IQ_G2, PHY3P_RX_EQ_DELTA_IQ_G2_DEFAULT) | \ + PHY3P04_RX_LOS_LFPS_EN | \ + FIELD_PREP(PHY3P04_RX_LOS_THRESHOLD, PHY3P_RX_LOS_THRESHOLD_DEFAULT) | \ + FIELD_PREP(PHY3P04_RX_TERM_CTRL, PHY3P_RX_TERM_CTRL_DEFAULT) | \ + FIELD_PREP(PHY3P04_TX_EQ_MAIN_G1_LO, \ + PHY3P_TX_EQ_MAIN_G1_DEFAULT & 0x7) \ +) + +#define PHY3P08_DEFAULT ( \ + FIELD_PREP(PHY3P08_TX_EQ_MAIN_G1_HI, PHY3P_TX_EQ_MAIN_G1_DEFAULT >> 3) | \ + FIELD_PREP(PHY3P08_TX_EQ_MAIN_G2, PHY3P_TX_EQ_MAIN_G2_DEFAULT) | \ + FIELD_PREP(PHY3P08_TX_EQ_POST_G1, PHY3P_TX_EQ_POST_G1_DEFAULT) | \ + FIELD_PREP(PHY3P08_TX_EQ_POST_G2, PHY3P_TX_EQ_POST_G2_DEFAULT) | \ + FIELD_PREP(PHY3P08_TX_EQ_PRE_G2, PHY3P_TX_EQ_PRE_G2_DEFAULT) | \ + FIELD_PREP(PHY3P08_TX_IBOOST_LVL, PHY3P_TX_IBOOST_LVL_DEFAULT) | \ + FIELD_PREP(PHY3P08_TX_TERM_CTRL, PHY3P_TX_TERM_CTRL_DEFAULT) \ +) + +#define PHY3P0C_DEFAULT \ + PHY3P0C_TX_VBOOST_EN + +struct aspeed_usb3_phy { + void __iomem *regs; + struct reset_control *rst; + struct device *dev; + struct clk *clk; +}; + +static int aspeed_usb3_phy_init(struct phy *phy) +{ + struct aspeed_usb3_phy *aspeed_phy =3D phy_get_drvdata(phy); + u32 val; + int ret; + + ret =3D clk_prepare_enable(aspeed_phy->clk); + if (ret) { + dev_err(aspeed_phy->dev, "Failed to enable clock %d\n", ret); + return ret; + } + + ret =3D reset_control_deassert(aspeed_phy->rst); + if (ret) { + clk_disable_unprepare(aspeed_phy->clk); + return ret; + } + + /* Wait for USB3 PHY internal SRAM initialization done */ + ret =3D readl_poll_timeout(aspeed_phy->regs + PHY3S00, val, + val & PHY3S00_INIT_DONE, + USEC_PER_MSEC, 10 * USEC_PER_MSEC); + if (ret) { + dev_err(aspeed_phy->dev, "SRAM init timeout\n"); + goto err_assert_reset; + } + + val =3D readl(aspeed_phy->regs + PHY3S00); + val |=3D PHY3S00_SRAM_BYPASS; + writel(val, aspeed_phy->regs + PHY3S00); + + /* Set protocol1_ext signals as default PHY3 settings based on SNPS docum= ents. + * Including PCFGI[54]: protocol1_ext_rx_los_lfps_en for better compatibi= lity + */ + writel(PHY3P00_DEFAULT, aspeed_phy->regs + PHY3P00); + writel(PHY3P04_DEFAULT, aspeed_phy->regs + PHY3P04); + writel(PHY3P08_DEFAULT, aspeed_phy->regs + PHY3P08); + writel(PHY3P0C_DEFAULT, aspeed_phy->regs + PHY3P0C); + + return 0; + +err_assert_reset: + reset_control_assert(aspeed_phy->rst); + clk_disable_unprepare(aspeed_phy->clk); + return ret; +} + +static int aspeed_usb3_phy_exit(struct phy *phy) +{ + struct aspeed_usb3_phy *aspeed_phy =3D phy_get_drvdata(phy); + + reset_control_assert(aspeed_phy->rst); + clk_disable_unprepare(aspeed_phy->clk); + + return 0; +} + +static const struct phy_ops aspeed_usb3_phy_ops =3D { + .init =3D aspeed_usb3_phy_init, + .exit =3D aspeed_usb3_phy_exit, + .owner =3D THIS_MODULE, +}; + +static int aspeed_usb3_phy_probe(struct platform_device *pdev) +{ + struct aspeed_usb3_phy *aspeed_phy; + struct phy_provider *phy_provider; + struct device *dev =3D &pdev->dev; + struct phy *phy; + + aspeed_phy =3D devm_kzalloc(dev, sizeof(*aspeed_phy), GFP_KERNEL); + if (!aspeed_phy) + return -ENOMEM; + + aspeed_phy->dev =3D dev; + + aspeed_phy->clk =3D devm_clk_get(dev, NULL); + if (IS_ERR(aspeed_phy->clk)) + return PTR_ERR(aspeed_phy->clk); + + aspeed_phy->rst =3D devm_reset_control_get_exclusive(dev, NULL); + if (IS_ERR(aspeed_phy->rst)) + return PTR_ERR(aspeed_phy->rst); + + aspeed_phy->regs =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(aspeed_phy->regs)) + return PTR_ERR(aspeed_phy->regs); + + phy =3D devm_phy_create(dev, NULL, &aspeed_usb3_phy_ops); + if (IS_ERR(phy)) + return PTR_ERR(phy); + + phy_set_drvdata(phy, aspeed_phy); + + phy_provider =3D devm_of_phy_provider_register(dev, of_phy_simple_xlate); + return PTR_ERR_OR_ZERO(phy_provider); +} + +static const struct of_device_id aspeed_usb3_phy_match_table[] =3D { + { + .compatible =3D "aspeed,ast2700-usb3-phy", + }, + { } +}; +MODULE_DEVICE_TABLE(of, aspeed_usb3_phy_match_table); + +static struct platform_driver aspeed_usb3_phy_driver =3D { + .probe =3D aspeed_usb3_phy_probe, + .driver =3D { + .name =3D KBUILD_MODNAME, + .of_match_table =3D aspeed_usb3_phy_match_table, + }, +}; +module_platform_driver(aspeed_usb3_phy_driver); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("ASPEED USB3.2 PHY Driver"); --=20 2.34.1 From nobody Wed Jul 1 12:06:03 2026 Received: from twmbx01.aspeedtech.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8F42C3B3C0D; Wed, 1 Jul 2026 06:58:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782889122; cv=none; b=OkjyfpO3vy4zRnbfoyTa0nREVkYKunyX9MQwwFuFMR+yhI879sJZ2R7KiegWa914esKl4YCdzdca0oDNaWnNxbDaaFXGBEVjfSHceQ/XPdDS7tWk3Jkn4rH+8GYJqfTBtLli5+QgNN1i7XZhjuwWYSk8rJvL7BXtsQJpCy0VqzI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782889122; c=relaxed/simple; bh=njRESqLfQG7J4os1F1U/PJtipN00LX9glpTZuXwuxRE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=c2QjhG4tEQHHiRJH3eZY2Ld85vfnvm+NgXaL1EczItChCrr7ug26It3iuXBl3cLqK7j4PjqxAlg7YZc5DWANl6HcRqtGnBu22jIDO05zI+1aLTqnQ45BOOibWWdB71MqhVbC+CoyzrVkejnbBkqeOYLoja7q404NzHX/2vqk1eI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 1 Jul 2026 14:58:18 +0800 Received: from [127.0.1.1] (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Wed, 1 Jul 2026 14:58:18 +0800 From: Ryan Chen Date: Wed, 1 Jul 2026 14:58:19 +0800 Subject: [PATCH v3 3/3] MAINTAINERS: Add ASPEED USB3 PHY driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260701-upstream_usb3phy-v3-3-00e12315b6f9@aspeedtech.com> References: <20260701-upstream_usb3phy-v3-0-00e12315b6f9@aspeedtech.com> In-Reply-To: <20260701-upstream_usb3phy-v3-0-00e12315b6f9@aspeedtech.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , "Andrew Jeffery" , Philipp Zabel CC: , , , , , Ryan Chen X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1782889098; l=861; i=ryan_chen@aspeedtech.com; s=20251126; h=from:subject:message-id; bh=njRESqLfQG7J4os1F1U/PJtipN00LX9glpTZuXwuxRE=; b=9nDC6roHxfGcpoe43h1qTGG9AwTHok6mjgtTbKiriMRNV5LYvorZCkvRv1RyoRS7m+iQGHzcm V8uVk5DQGeSBKe0/CjGZXbG8nfFOos6gvV42A+70KRo+SPXsxdJ0+vv X-Developer-Key: i=ryan_chen@aspeedtech.com; a=ed25519; pk=Xe73xY6tcnkuRjjbVAB/oU30KdB3FvG4nuJuILj7ZVc= Add maintainer entry for ASPEED USB3 PHY driver. Signed-off-by: Ryan Chen --- MAINTAINERS | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 895a87b571c3..10c08f322618 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -4062,6 +4062,14 @@ S: Maintained F: Documentation/devicetree/bindings/usb/aspeed,ast2600-udc.yaml F: drivers/usb/gadget/udc/aspeed_udc.c =20 +ASPEED USB3 PHY DRIVER +M: Ryan Chen +L: linux-aspeed@lists.ozlabs.org (moderated for non-subscribers) +L: linux-phy@lists.infradead.org +S: Maintained +F: Documentation/devicetree/bindings/phy/aspeed,ast2700-usb3-phy.yaml +F: drivers/phy/aspeed/phy-aspeed-usb3.c + ASPEED VIDEO ENGINE DRIVER M: Eddie James L: linux-media@vger.kernel.org --=20 2.34.1