From nobody Thu Jul 16 17:05:11 2026 Received: from out-184.mta0.migadu.com (out-184.mta0.migadu.com [91.218.175.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6871E3EEAF0 for ; Wed, 1 Jul 2026 08:47:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.218.175.184 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782895656; cv=none; b=lT8NiSN8aEg+lsO9ESJDFGjyW7iVNGpnJlTbIUM3QMzfakJaiFdGNPy7aSvc+x48lZ+K0Q5r3rrsEi8Me5SPsjREEQVpXpK5VV68nyyAaGESAhTe4e2ELxLpSI4eqCzebbZBWZxShdhlpMe93TMGgKCK4o+fECgE1VGJ8v83mj8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782895656; c=relaxed/simple; bh=9VOnVvzjsZzR8hJplWz7LMgbcZ7QnXk10tohv83NyKA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=anpJaiWkDnSFre84XlFsOvsDEXwKr+yH5aiyYTd/KCkGcSESMbGZoNlXag7ihR12pTb9b4sEMvjGUciefulhDfcaxS1Vy52/W0fp2HozivgHf7lljIki4evRMVJqEhL0ECcR/Vx1txxHjiy6ehcOFFlEIE/JVmaBHP/IGc5f4Qs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=viR8aRra; arc=none smtp.client-ip=91.218.175.184 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="viR8aRra" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1782895642; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=9jkYTJZ76o1QfeUeruk/BApgLfDf2mjQsJprrfSgBCQ=; b=viR8aRra2txaWnJTugOoW7+0kM9QWgabNryKjWO2M3CkuQ5Fxi/WApRf8MqOM3omSVqx8U 8yq/pM6cTJhEXNkauymsk1cZ7x8YNrpEOb5kfQeKBUV349+tUy0AMs5/15VmmvIgQEAVGe QfG6yuER74q3Tt+b/Qsk/bmlP27zJUI= From: Atish Patra Date: Wed, 01 Jul 2026 01:46:49 -0700 Subject: [PATCH v8 01/22] RISC-V: perf: fix resource cleanup on driver probe failure Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260701-counter_delegation-v8-1-7909f863a645@meta.com> References: <20260701-counter_delegation-v8-0-7909f863a645@meta.com> In-Reply-To: <20260701-counter_delegation-v8-0-7909f863a645@meta.com> To: Jiri Olsa , Paul Walmsley , Mark Rutland , Rob Herring , Anup Patel , Namhyung Kim , Arnaldo Carvalho de Melo , Krzysztof Kozlowski , Atish Patra , Ian Rogers , Will Deacon , James Clark Cc: linux-arm-kernel@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-perf-users@vger.kernel.org, Conor Dooley X-Migadu-Flow: FLOW_OUT From: Atish Patra Sashiko pointed out various UAF and memory leak issues around pmu_sbi_device_probe() error paths. If the probe fails, here are list of cleanups needed. a. Already registered pmu must be freed b. per cpu IRQ must be released c. pmu_ctr_list data structure must be freed d. cpu hotplug state must be cleaned up only if added. Fix the resource cleanup by reorganizing the code around probe failure. Reported-by: Sashiko AI Signed-off-by: Atish Patra --- drivers/perf/riscv_pmu_sbi.c | 33 +++++++++++++++++++++++++++------ 1 file changed, 27 insertions(+), 6 deletions(-) diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index 385af5e6e6d0..5c8924ce1f38 100644 --- a/drivers/perf/riscv_pmu_sbi.c +++ b/drivers/perf/riscv_pmu_sbi.c @@ -1220,22 +1220,29 @@ static int pmu_sbi_setup_irqs(struct riscv_pmu *pmu= , struct platform_device *pde DOMAIN_BUS_ANY); if (!domain) { pr_err("Failed to find INTC IRQ root domain\n"); - return -ENODEV; + ret =3D -ENODEV; + goto err; } =20 riscv_pmu_irq =3D irq_create_mapping(domain, riscv_pmu_irq_num); if (!riscv_pmu_irq) { pr_err("Failed to map PMU interrupt for node\n"); - return -ENODEV; + ret =3D -ENODEV; + goto err; } =20 ret =3D request_percpu_irq(riscv_pmu_irq, pmu_sbi_ovf_handler, "riscv-pmu= ", hw_events); if (ret) { pr_err("registering percpu irq failed [%d]\n", ret); - return ret; + irq_dispose_mapping(riscv_pmu_irq); + riscv_pmu_irq =3D 0; + goto err; } =20 return 0; +err: + riscv_pmu_use_irq =3D false; + return ret; } =20 #ifdef CONFIG_CPU_PM @@ -1302,7 +1309,8 @@ static void riscv_pmu_destroy(struct riscv_pmu *pmu) } } riscv_pm_pmu_unregister(pmu); - cpuhp_state_remove_instance(CPUHP_AP_PERF_RISCV_STARTING, &pmu->node); + if (!hlist_unhashed(&pmu->node)) + cpuhp_state_remove_instance(CPUHP_AP_PERF_RISCV_STARTING, &pmu->node); } =20 static void pmu_sbi_event_init(struct perf_event *event) @@ -1424,6 +1432,7 @@ static int pmu_sbi_device_probe(struct platform_devic= e *pdev) struct riscv_pmu *pmu =3D NULL; int ret =3D -ENODEV; int num_counters; + bool irq_requested =3D false; =20 pr_info("SBI PMU extension is available\n"); pmu =3D riscv_pmu_alloc(); @@ -1452,6 +1461,7 @@ static int pmu_sbi_device_probe(struct platform_devic= e *pdev) pmu->pmu.capabilities |=3D PERF_PMU_CAP_NO_INTERRUPT; pmu->pmu.capabilities |=3D PERF_PMU_CAP_NO_EXCLUDE; } + irq_requested =3D (ret =3D=3D 0); =20 pmu->pmu.attr_groups =3D riscv_pmu_attr_groups; pmu->pmu.parent =3D &pdev->dev; @@ -1470,11 +1480,11 @@ static int pmu_sbi_device_probe(struct platform_dev= ice *pdev) =20 ret =3D riscv_pm_pmu_register(pmu); if (ret) - goto out_unregister; + goto out_destroy; =20 ret =3D perf_pmu_register(&pmu->pmu, "cpu", PERF_TYPE_RAW); if (ret) - goto out_unregister; + goto out_destroy; =20 /* SBI PMU Snapsphot is only available in SBI v2.0 */ if (sbi_v2_available) { @@ -1515,9 +1525,20 @@ static int pmu_sbi_device_probe(struct platform_devi= ce *pdev) return 0; =20 out_unregister: + perf_pmu_unregister(&pmu->pmu); + +out_destroy: riscv_pmu_destroy(pmu); + if (irq_requested) { + free_percpu_irq(riscv_pmu_irq, pmu->hw_events); + irq_dispose_mapping(riscv_pmu_irq); + riscv_pmu_irq =3D 0; + } =20 out_free: + free_percpu(pmu->hw_events); + kfree(pmu_ctr_list); + pmu_ctr_list =3D NULL; kfree(pmu); return ret; } --=20 2.53.0-Meta From nobody Thu Jul 16 17:05:11 2026 Received: from out-172.mta1.migadu.com (out-172.mta1.migadu.com [95.215.58.172]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CD6F03B9929 for ; Wed, 1 Jul 2026 08:47:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782895649; cv=none; b=pPl+ggd6JkFQ4uO6itX5LeXCRLCh14T/fXad7fNbN3Jbi/pboW3/3al3BoNcmXI8h9pSEEkmI1TDyTCOurOmw0hm75vlKMf7XLuhsj1FBOKyrr8mF6jF2dYObv7Bhz4q/+G99SVBUFC8ooCmb2fzPCn+K1DR6j2m9TBGnErxbI0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782895649; c=relaxed/simple; bh=49sToyKTSjS66TuV/1Gvj6ise9Amt4gQHPByMHgSiiE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=HdUClvbRB9uggCkV+IaXUWOsfCAPsBZ5a0FU5l7WYwVl/iLWWAOmMf1Qfbji22YEaKR70PIEaY2VbQYl2a1T6tpafowVhoLJzV5RMVK8IIjnlDXrHJpuffGZ23eOfDEUmvz7btftkwPK3y+2cuf/F+J1Zc0iE7ctLevnPEOG0Pk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=mGAu0O5p; arc=none smtp.client-ip=95.215.58.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="mGAu0O5p" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1782895645; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=gg1b4NvG9irnTlONKFumTIckFqfflTt6uFIpf+8fltI=; b=mGAu0O5p3zzJMOJu8qMNFgcSKrgX6osZU3GAoSLRlOMN10orW6+CZfaU9yfENWqMHTFSsP 8YFkH7Qt9+3dgkbpQpQdYAn0ouLmDSJtQMJCltLHCnJTEOrwsW4eaaCCpx4LALgw1sHTzt 1Qk1rPXD5165bCku5pIxwAFiDvCL690= From: Atish Patra Date: Wed, 01 Jul 2026 01:46:50 -0700 Subject: [PATCH v8 02/22] RISC-V: Add Sxcsrind ISA extension CSR definitions Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260701-counter_delegation-v8-2-7909f863a645@meta.com> References: <20260701-counter_delegation-v8-0-7909f863a645@meta.com> In-Reply-To: <20260701-counter_delegation-v8-0-7909f863a645@meta.com> To: Jiri Olsa , Paul Walmsley , Mark Rutland , Rob Herring , Anup Patel , Namhyung Kim , Arnaldo Carvalho de Melo , Krzysztof Kozlowski , Atish Patra , Ian Rogers , Will Deacon , James Clark Cc: linux-arm-kernel@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-perf-users@vger.kernel.org, Conor Dooley X-Migadu-Flow: FLOW_OUT From: Kaiwen Xue This adds definitions of new CSRs and bits defined in Sxcsrind ISA extension. These CSR enables indirect accesses mechanism to access any CSRs in M-, S-, and VS-mode. The range of the select values and ireg will be define by the ISA extension using Sxcsrind extension. Signed-off-by: Kaiwen Xue Reviewed-by: Cl=C3=A9ment L=C3=A9ger Signed-off-by: Atish Patra --- arch/riscv/include/asm/csr.h | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 31b8988f4488..b4551a6cf7cb 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -347,6 +347,12 @@ /* Supervisor-Level Window to Indirectly Accessed Registers (AIA) */ #define CSR_SISELECT 0x150 #define CSR_SIREG 0x151 +/* Supervisor-Level Window to Indirectly Accessed Registers (Sxcsrind) */ +#define CSR_SIREG2 0x152 +#define CSR_SIREG3 0x153 +#define CSR_SIREG4 0x155 +#define CSR_SIREG5 0x156 +#define CSR_SIREG6 0x157 =20 /* Supervisor-Level Interrupts (AIA) */ #define CSR_STOPEI 0x15c @@ -394,6 +400,14 @@ /* VS-Level Window to Indirectly Accessed Registers (H-extension with AIA)= */ #define CSR_VSISELECT 0x250 #define CSR_VSIREG 0x251 +/* + * VS-Level Window to Indirectly Accessed Registers (H-extension with Sxcs= rind) + */ +#define CSR_VSIREG2 0x252 +#define CSR_VSIREG3 0x253 +#define CSR_VSIREG4 0x255 +#define CSR_VSIREG5 0x256 +#define CSR_VSIREG6 0x257 =20 /* VS-Level Interrupts (H-extension with AIA) */ #define CSR_VSTOPEI 0x25c @@ -436,6 +450,12 @@ /* Machine-Level Window to Indirectly Accessed Registers (AIA) */ #define CSR_MISELECT 0x350 #define CSR_MIREG 0x351 +/* Machine-Level Window to Indirectly Accessed Registers (Sxcsrind) */ +#define CSR_MIREG2 0x352 +#define CSR_MIREG3 0x353 +#define CSR_MIREG4 0x355 +#define CSR_MIREG5 0x356 +#define CSR_MIREG6 0x357 =20 /* Machine-Level Interrupts (AIA) */ #define CSR_MTOPEI 0x35c @@ -498,6 +518,11 @@ # define CSR_IEH CSR_MIEH # define CSR_ISELECT CSR_MISELECT # define CSR_IREG CSR_MIREG +# define CSR_IREG2 CSR_MIREG2 +# define CSR_IREG3 CSR_MIREG3 +# define CSR_IREG4 CSR_MIREG4 +# define CSR_IREG5 CSR_MIREG5 +# define CSR_IREG6 CSR_MIREG6 # define CSR_IPH CSR_MIPH # define CSR_TOPEI CSR_MTOPEI # define CSR_TOPI CSR_MTOPI @@ -523,6 +548,11 @@ # define CSR_IEH CSR_SIEH # define CSR_ISELECT CSR_SISELECT # define CSR_IREG CSR_SIREG +# define CSR_IREG2 CSR_SIREG2 +# define CSR_IREG3 CSR_SIREG3 +# define CSR_IREG4 CSR_SIREG4 +# define CSR_IREG5 CSR_SIREG5 +# define CSR_IREG6 CSR_SIREG6 # define CSR_IPH CSR_SIPH # define CSR_TOPEI CSR_STOPEI # define CSR_TOPI CSR_STOPI --=20 2.53.0-Meta From nobody Thu Jul 16 17:05:11 2026 Received: from out-173.mta1.migadu.com (out-173.mta1.migadu.com [95.215.58.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EED093EEAC3 for ; Wed, 1 Jul 2026 08:47:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.173 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782895652; cv=none; b=efx1GMf7/5ojb1KQwX0gtCop0nDU5CuoylJkcLxG4mvwCY6GVyssOOVmS3LPnL9oZ7LhVzCxq3PcKbvUwOXsinumsMWIfoczuEkbu3k3xLdk+2c5iwCb6fPI4ndjfR+44Lw8hJy4qQQ0JP8ez28+laSXYwPZHi+FMxbUQ9KyrOc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782895652; c=relaxed/simple; bh=GGx0NZaHhk7E2NAtvsdpcvF5HPVyVNDE83nBISLAwX0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=iWiRVFMH6+pc2yEpn4D/B1ByWuLmq8JHPTga7dpvK8usBr9FaPzby055Ap/CoIY74yyjTh+htmNYzslLd8QwUcYvByYMxYuqU9bzqkvLdMUkdQTQcxdpyp1OkKHu953G7kdkvS+6KuUwd0UVLnKa2E6ZOA69boW8vn4YvM1/c30= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=XdGo4gU8; arc=none smtp.client-ip=95.215.58.173 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="XdGo4gU8" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1782895649; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=zryXcVid5vc6uq/c5lbU5QHgsNUYuSSps54Hsm8mVUc=; b=XdGo4gU8XQeKBXWODO+iiFuMa7aetuVrSOedZ1ucMgb69TvVBhcEbR0G1m2SebTSYbBxTP OoGx+Q09LDBwe3j02hL5KdkJpTsJVN2e9Qy6TTyxfcIBQdFWHm3N9SzVmWObxB5AALysaa L1pbiMmaX1v4cjPDGzDYryeJPNx8Cno= From: Atish Patra Date: Wed, 01 Jul 2026 01:46:51 -0700 Subject: [PATCH v8 03/22] RISC-V: Add Sxcsrind ISA extension definition and parsing Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260701-counter_delegation-v8-3-7909f863a645@meta.com> References: <20260701-counter_delegation-v8-0-7909f863a645@meta.com> In-Reply-To: <20260701-counter_delegation-v8-0-7909f863a645@meta.com> To: Jiri Olsa , Paul Walmsley , Mark Rutland , Rob Herring , Anup Patel , Namhyung Kim , Arnaldo Carvalho de Melo , Krzysztof Kozlowski , Atish Patra , Ian Rogers , Will Deacon , James Clark Cc: linux-arm-kernel@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-perf-users@vger.kernel.org, Conor Dooley X-Migadu-Flow: FLOW_OUT From: Atish Patra The S[m|s]csrind extension extends the indirect CSR access mechanism defined in Smaia/Ssaia extensions. This patch just enables the definition and parsing. Signed-off-by: Atish Patra --- arch/riscv/include/asm/hwcap.h | 4 ++++ arch/riscv/kernel/cpufeature.c | 2 ++ 2 files changed, 6 insertions(+) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 7ef8e5f55c8d..d4a7b90e2d78 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -112,6 +112,8 @@ #define RISCV_ISA_EXT_ZCLSD 103 #define RISCV_ISA_EXT_ZICFILP 104 #define RISCV_ISA_EXT_ZICFISS 105 +#define RISCV_ISA_EXT_SSCSRIND 106 +#define RISCV_ISA_EXT_SMCSRIND 107 =20 #define RISCV_ISA_EXT_XLINUXENVCFG 127 =20 @@ -121,9 +123,11 @@ #ifdef CONFIG_RISCV_M_MODE #define RISCV_ISA_EXT_SxAIA RISCV_ISA_EXT_SMAIA #define RISCV_ISA_EXT_SUPM RISCV_ISA_EXT_SMNPM +#define RISCV_ISA_EXT_SxCSRIND RISCV_ISA_EXT_SMCSRIND #else #define RISCV_ISA_EXT_SxAIA RISCV_ISA_EXT_SSAIA #define RISCV_ISA_EXT_SUPM RISCV_ISA_EXT_SSNPM +#define RISCV_ISA_EXT_SxCSRIND RISCV_ISA_EXT_SSCSRIND #endif =20 #endif /* _ASM_RISCV_HWCAP_H */ diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index f46aa5602d74..3fa0a563fb21 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -576,11 +576,13 @@ const struct riscv_isa_ext_data riscv_isa_ext[] =3D { __RISCV_ISA_EXT_BUNDLE_VALIDATE(zvksg, riscv_zvksg_bundled_exts, riscv_ex= t_vector_crypto_validate), __RISCV_ISA_EXT_DATA_VALIDATE(zvkt, RISCV_ISA_EXT_ZVKT, riscv_ext_vector_= crypto_validate), __RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA), + __RISCV_ISA_EXT_DATA(smcsrind, RISCV_ISA_EXT_SMCSRIND), __RISCV_ISA_EXT_DATA(smmpm, RISCV_ISA_EXT_SMMPM), __RISCV_ISA_EXT_SUPERSET(smnpm, RISCV_ISA_EXT_SMNPM, riscv_xlinuxenvcfg_e= xts), __RISCV_ISA_EXT_DATA(smstateen, RISCV_ISA_EXT_SMSTATEEN), __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA), __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), + __RISCV_ISA_EXT_DATA(sscsrind, RISCV_ISA_EXT_SSCSRIND), __RISCV_ISA_EXT_SUPERSET(ssnpm, RISCV_ISA_EXT_SSNPM, riscv_xlinuxenvcfg_e= xts), __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC), __RISCV_ISA_EXT_DATA(svade, RISCV_ISA_EXT_SVADE), --=20 2.53.0-Meta From nobody Thu Jul 16 17:05:11 2026 Received: from out-179.mta1.migadu.com (out-179.mta1.migadu.com [95.215.58.179]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 69CB23EF0A0 for ; Wed, 1 Jul 2026 08:47:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.179 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782895656; cv=none; b=Tdxnepvy0+CBqR+uRUWxhKQeJ5lAq6zCj8Kw401yJsNPF34OMenBXCEkJW4mrU78a7nMfhFE8HL0DBc8kNRECBIGFajHucmYC2RtljgQEa0TKARUpRVQOPRXtCepMojmNKCS+cMgLc60R0M2N67a0A8Hb/zjF3WzqBRzahAIKiU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782895656; c=relaxed/simple; bh=A3gRyl4ltUH9yUsRKVqvAMCjF315BmzM3okD18OgTNY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=D67S9JE1ahhKULOARPgS9/rT7rzushbLqAkfIOqEhJlUndHFwmBWDBo7iFnL10nrKPZhnN40lh2bidht75Dow/Wq9sARk9tI0x7Ri/U2uxU9WjSpq1DqOI3Jkb10ZETsRdOMw/RqbOfz6UMQJCCh4arVjWcerKUNYKmNDtxlavU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=h4ZVPuN7; arc=none smtp.client-ip=95.215.58.179 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="h4ZVPuN7" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1782895652; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=q3CU0znujUTwcxjeKNolaCbQsHD6AswnEQkiO1fL85Y=; b=h4ZVPuN74ylcIjDvtDiE9C6IU/R16DyA59zWn/3nQKQidAqMCx8sdQv7Amia68ooxMEwQz mlyA7yuRlFOjNn5Zblo29Zy1Fc2IxS+BQoaCEuJfeUsM4EwVv7ttTMZfZxwESQmUuCmocr /6IkNJqlll6D/svFSUmOWZU2DxUo1po= From: Atish Patra Date: Wed, 01 Jul 2026 01:46:52 -0700 Subject: [PATCH v8 04/22] dt-bindings: riscv: add Sxcsrind ISA extension description Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260701-counter_delegation-v8-4-7909f863a645@meta.com> References: <20260701-counter_delegation-v8-0-7909f863a645@meta.com> In-Reply-To: <20260701-counter_delegation-v8-0-7909f863a645@meta.com> To: Jiri Olsa , Paul Walmsley , Mark Rutland , Rob Herring , Anup Patel , Namhyung Kim , Arnaldo Carvalho de Melo , Krzysztof Kozlowski , Atish Patra , Ian Rogers , Will Deacon , James Clark Cc: linux-arm-kernel@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-perf-users@vger.kernel.org, Conor Dooley X-Migadu-Flow: FLOW_OUT From: Atish Patra Add the S[m|s]csrind ISA extension description. Acked-by: Rob Herring (Arm) Signed-off-by: Atish Patra --- Documentation/devicetree/bindings/riscv/extensions.yaml | 16 +++++++++++++= +++ 1 file changed, 16 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Docu= mentation/devicetree/bindings/riscv/extensions.yaml index 2b0a8a93bb21..15cf0e2ee3ed 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -181,6 +181,14 @@ properties: changes to interrupts as frozen at commit ccbddab ("Merge pull request #42 from riscv/jhauser-2023-RC4") of riscv-aia. =20 + - const: smcsrind + description: | + The standard Smcsrind machine-level extension extends the + indirect CSR access mechanism defined by the Smaia extension. = This + extension allows other ISA extensions to use indirect CSR acce= ss + mechanism in M-mode as ratified in the 20240326 version of the + privileged ISA specification. + - const: smmpm description: | The standard Smmpm extension for M-mode pointer masking as @@ -226,6 +234,14 @@ properties: Profiles Version 1.0, with commit b1d806605f87 ("Updated to ratified state.") =20 + - const: sscsrind + description: | + The standard Sscsrind supervisor-level extension extends the + indirect CSR access mechanism defined by the Ssaia extension. = This + extension allows other ISA extensions to use indirect CSR acce= ss + mechanism in S-mode as ratified in the 20240326 version of the + privileged ISA specification. + - const: ssnpm description: | The standard Ssnpm extension for next-mode pointer masking as --=20 2.53.0-Meta From nobody Thu Jul 16 17:05:11 2026 Received: from out-184.mta0.migadu.com (out-184.mta0.migadu.com [91.218.175.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 036B93F0AAD for ; Wed, 1 Jul 2026 08:47:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.218.175.184 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782895659; cv=none; b=VEJVLO8FntDTxH9l79nPlGe5AYnnzUzejznoF90+68biC8+70hI7oZTBwFA8Kk9sT0YO0shnRkNxmUlro+/UOr0Bbz8OMfB7C5cMqIIMX/NQxRkGtxoz8ac2pyFUjP6cvNaQa2Y9tKXQ3pjk8uweNV58kB3uLmAlLkj4/wVEoAg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782895659; c=relaxed/simple; bh=X0Ytfo5nfc/ZAvUV4srlZKxHcRChLJW/pos91pHygGI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=nYMjjJh+Of9u/OTH5PvJhGLVOTiubPBLqH3PCKeGR41N/DbUwfcSIL5vSgfUdJXq+L0MppDWBGUaxXAoQL62s+DGYgd+9EsfA95Xdk2AITgORuFKvGbdNdvI2RN2Cfi80xtVyJg+WiMgFp+j/2L7wv/MC6wKem4Bq8W/oNMLAvk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=whxuRCIu; arc=none smtp.client-ip=91.218.175.184 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="whxuRCIu" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1782895655; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=9R0sEcrEcJj1+N/TVKuoWiSfW8zF14v2/MRWt/PM07E=; b=whxuRCIui+TJwB1+Sa4xIs9mUoqTZUDV+0FRvAwvj3RGl+TXUMqEHEjtcCFoYzPB98RgfK wGgfRkTSwrnQlf35J0OXpQ2WwxHaowNGKWBDruK0qco4I/+4G3BeK02slgbk4pf77c56o+ ms8djRlltf0qwxz+Cpr05F/3qno4/uY= From: Atish Patra Date: Wed, 01 Jul 2026 01:46:53 -0700 Subject: [PATCH v8 05/22] RISC-V: Define indirect CSR access helpers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260701-counter_delegation-v8-5-7909f863a645@meta.com> References: <20260701-counter_delegation-v8-0-7909f863a645@meta.com> In-Reply-To: <20260701-counter_delegation-v8-0-7909f863a645@meta.com> To: Jiri Olsa , Paul Walmsley , Mark Rutland , Rob Herring , Anup Patel , Namhyung Kim , Arnaldo Carvalho de Melo , Krzysztof Kozlowski , Atish Patra , Ian Rogers , Will Deacon , James Clark Cc: linux-arm-kernel@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-perf-users@vger.kernel.org, Conor Dooley X-Migadu-Flow: FLOW_OUT From: Atish Patra The indirect CSR requires multiple instructions to read/write CSR. Add a few helper functions for ease of usage. Signed-off-by: Atish Patra --- arch/riscv/include/asm/csr_ind.h | 41 ++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 41 insertions(+) diff --git a/arch/riscv/include/asm/csr_ind.h b/arch/riscv/include/asm/csr_= ind.h new file mode 100644 index 000000000000..1b15e358484d --- /dev/null +++ b/arch/riscv/include/asm/csr_ind.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _ASM_RISCV_CSR_IND_H +#define _ASM_RISCV_CSR_IND_H + +#include + +#include + +#define csr_ind_read(iregcsr, iselbase, iseloff) ({ \ + unsigned long __value =3D 0; \ + unsigned long __flags; \ + local_irq_save(__flags); \ + csr_write(CSR_ISELECT, (iselbase) + (iseloff)); \ + __value =3D csr_read(iregcsr); \ + local_irq_restore(__flags); \ + __value; \ +}) + +#define csr_ind_write(iregcsr, iselbase, iseloff, value) ({ \ + unsigned long __flags; \ + local_irq_save(__flags); \ + csr_write(CSR_ISELECT, (iselbase) + (iseloff)); \ + csr_write(iregcsr, (value)); \ + local_irq_restore(__flags); \ +}) + +#define csr_ind_warl(iregcsr, iselbase, iseloff, warl_val) ({ \ + unsigned long __old_val =3D 0, __value =3D 0; \ + unsigned long __flags; \ + local_irq_save(__flags); \ + csr_write(CSR_ISELECT, (iselbase) + (iseloff)); \ + __old_val =3D csr_read(iregcsr); \ + csr_write(iregcsr, (warl_val)); \ + __value =3D csr_read(iregcsr); \ + csr_write(iregcsr, __old_val); \ + local_irq_restore(__flags); \ + __value; \ +}) + +#endif --=20 2.53.0-Meta From nobody Thu Jul 16 17:05:11 2026 Received: from out-182.mta1.migadu.com (out-182.mta1.migadu.com [95.215.58.182]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E71D63EEAE5 for ; Wed, 1 Jul 2026 08:47:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.182 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782895669; cv=none; b=U2WODHcmEee/AEXX/8JomjKjz7tuLd06TVbRdNIqa5ln02V+c7LWCHKS1VWGbGKk3VmtXjYNq6m/nfeNul5eE6x0eYwIvVRsWv18URgCkA9COE36VfbiPGQUz+3O5qzZYToBxLW16ODs/2cpkWVj9NvX/CChBCjophLt5x7RXwc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782895669; c=relaxed/simple; bh=V3JGAAEePdvjL1jOKXrT144NEjnftOft8iA7Fv7XtmA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=idaJRT+sHg455kX+EO6mHQgIKK9z4TjF0TJv413a0ToVHlyZPsNAp4nymeUHc2stq/AV7sbWYn3d1Ho8qupyqjC2pbYU1AxuLNQ9sAD27irZ8o8c05X2oazeIXvmQHXjDeUhmaUUrqzhZWTFgSUwFtVuL3Jih3QlvM9uwufkiCg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=hA7Q7Ziq; arc=none smtp.client-ip=95.215.58.182 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="hA7Q7Ziq" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1782895666; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=dCJ2r81edroj2Hmgi/7A55is/dQobvLAXnLASBXtpg8=; b=hA7Q7Ziqj0FcrguHs1jTijVS/PGxrXPk8PqaMozHWTdozmjFOtcq7ATQjFyPUCbGURhvYA aFVu3M5KBssn2Bge4t8fBCPEPxeowXkEh0MvOiS7rW1FLFu7Wxya8IBCOYcWSXCyWmAv6K a75H3/1QG8AwXRVKhulLBPahHsqPxaw= From: Atish Patra Date: Wed, 01 Jul 2026 01:46:54 -0700 Subject: [PATCH v8 06/22] RISC-V: Add Smcntrpmf extension parsing Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260701-counter_delegation-v8-6-7909f863a645@meta.com> References: <20260701-counter_delegation-v8-0-7909f863a645@meta.com> In-Reply-To: <20260701-counter_delegation-v8-0-7909f863a645@meta.com> To: Jiri Olsa , Paul Walmsley , Mark Rutland , Rob Herring , Anup Patel , Namhyung Kim , Arnaldo Carvalho de Melo , Krzysztof Kozlowski , Atish Patra , Ian Rogers , Will Deacon , James Clark Cc: linux-arm-kernel@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-perf-users@vger.kernel.org, Conor Dooley X-Migadu-Flow: FLOW_OUT From: Atish Patra Smcntrpmf extension allows M-mode to enable privilege mode filtering for cycle/instret counters. However, the cyclecfg/instretcfg CSRs are available in Ssccfg only if Smcntrpmf is present. That's why, kernel needs to detect presence of Smcntrpmf extension and enable privilege mode filtering for cycle/instret counters. Reviewed-by: Cl=C3=A9ment L=C3=A9ger Signed-off-by: Atish Patra --- arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/kernel/cpufeature.c | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index d4a7b90e2d78..51ad55b9677a 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -114,6 +114,7 @@ #define RISCV_ISA_EXT_ZICFISS 105 #define RISCV_ISA_EXT_SSCSRIND 106 #define RISCV_ISA_EXT_SMCSRIND 107 +#define RISCV_ISA_EXT_SMCNTRPMF 108 =20 #define RISCV_ISA_EXT_XLINUXENVCFG 127 =20 diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 3fa0a563fb21..1452521d740a 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -576,6 +576,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] =3D { __RISCV_ISA_EXT_BUNDLE_VALIDATE(zvksg, riscv_zvksg_bundled_exts, riscv_ex= t_vector_crypto_validate), __RISCV_ISA_EXT_DATA_VALIDATE(zvkt, RISCV_ISA_EXT_ZVKT, riscv_ext_vector_= crypto_validate), __RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA), + __RISCV_ISA_EXT_DATA(smcntrpmf, RISCV_ISA_EXT_SMCNTRPMF), __RISCV_ISA_EXT_DATA(smcsrind, RISCV_ISA_EXT_SMCSRIND), __RISCV_ISA_EXT_DATA(smmpm, RISCV_ISA_EXT_SMMPM), __RISCV_ISA_EXT_SUPERSET(smnpm, RISCV_ISA_EXT_SMNPM, riscv_xlinuxenvcfg_e= xts), --=20 2.53.0-Meta From nobody Thu Jul 16 17:05:11 2026 Received: from out-189.mta1.migadu.com (out-189.mta1.migadu.com [95.215.58.189]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5BF3B3EDE60 for ; Wed, 1 Jul 2026 08:48:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.189 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782895681; cv=none; b=sJSJLhcG8llCvSoMvAE0arJ82hsABFKJyIb8AluAF5h3ANKKZbnX4/CANtrECj5Fi0jeEF3GbpJd/5naH7GKAPrw9pzijCsSUtweDshrolXzRMki6kRKIGyACLPUhdGDyIi+04giUqqsEOt8017sjy45HTKp2xMZ552kKJEp31w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782895681; c=relaxed/simple; bh=3OO28ccJEwCgkWwCOHvCmAYVgiOqJBRQW0AyXwGFpog=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=QO/QwpiDnr+/9J9E5fogc2c6749PkQyjMUsgo4Zql8tqux6F4z7SP4zoMJK7tVsTEgoS96jAgSmJu+jZ6s1iWVkq7w8MHEXyc0kcH85LWNHOVT6vVHvT2XqIiO7OynI+SAvMCULkdCRI3CMlKNAdIwS9l+Hc+zDEK9SL4jzqcfI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=sLWDqQwB; arc=none smtp.client-ip=95.215.58.189 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="sLWDqQwB" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1782895678; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=8bnW4aRchUEMVnjaS3sJtvhYx7e7VZaYZUym5ODbnk8=; b=sLWDqQwBf+App3Pu7RHBlkjSnfaG2rRct/pqV+ERk3rbG4LZOhOR4spFpRL+8i/aJrIm7m J7hX2zImAVjM5dunqvNXhbt6+5T/hp3lNklFu/pVjvvDAPwuISEyk3Xudw2mqCmFvqiWAT bO7+HZKS7QkzcWfUd4DKAXUO4MjJ0BM= From: Atish Patra Date: Wed, 01 Jul 2026 01:46:55 -0700 Subject: [PATCH v8 07/22] dt-bindings: riscv: add Smcntrpmf ISA extension description Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260701-counter_delegation-v8-7-7909f863a645@meta.com> References: <20260701-counter_delegation-v8-0-7909f863a645@meta.com> In-Reply-To: <20260701-counter_delegation-v8-0-7909f863a645@meta.com> To: Jiri Olsa , Paul Walmsley , Mark Rutland , Rob Herring , Anup Patel , Namhyung Kim , Arnaldo Carvalho de Melo , Krzysztof Kozlowski , Atish Patra , Ian Rogers , Will Deacon , James Clark Cc: linux-arm-kernel@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-perf-users@vger.kernel.org, Conor Dooley X-Migadu-Flow: FLOW_OUT From: Atish Patra Add the description for Smcntrpmf ISA extension Acked-by: Rob Herring (Arm) Signed-off-by: Atish Patra --- Documentation/devicetree/bindings/riscv/extensions.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Docu= mentation/devicetree/bindings/riscv/extensions.yaml index 15cf0e2ee3ed..2493766e956d 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -181,6 +181,12 @@ properties: changes to interrupts as frozen at commit ccbddab ("Merge pull request #42 from riscv/jhauser-2023-RC4") of riscv-aia. =20 + - const: smcntrpmf + description: | + The standard Smcntrpmf machine-level extension for the machine= mode + to enable privilege mode filtering for cycle and instret count= ers as + ratified in the 20240326 version of the privileged ISA specifi= cation. + - const: smcsrind description: | The standard Smcsrind machine-level extension extends the --=20 2.53.0-Meta From nobody Thu Jul 16 17:05:11 2026 Received: from out-177.mta0.migadu.com (out-177.mta0.migadu.com [91.218.175.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 144413F0A97 for ; Wed, 1 Jul 2026 08:48:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.218.175.177 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782895685; cv=none; b=frlOnV/Yva28gFSanemk31si67hccDd/QBrrB0iR1DewqIJtBVqo9tMNH3BDBEESyCAwKiHfjo/cZw1kpPhXgiMW2U4fFVOgLoPKyv+Mnl7E7Hn/H66O10xi4wW1LysnkAF2qa66B9DbBPQsgYhaaarqByLaT3J4uJs3bVQOC+Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782895685; c=relaxed/simple; bh=il7iB5GJVyw6ArXF9j9C7bPvLSXXTbFE4ka4RDhEEp0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=iB4V8NMguRcoUPU9ylAf2kXTKpnevgbCDLl4PGTUO5+W3OZ68uNQt7zsvKAzcCT3tFCiMWeP5LFMDYAN6BIZgE9kc1Jo6XDE46JJU8vjow1up0wD48EZ1oMsbqlwzWMtviVskVx1Lvz+XMf29pbBFWYw9iWTgblpMgSF7XRa3Ig= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=TZpcz/tc; arc=none smtp.client-ip=91.218.175.177 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="TZpcz/tc" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1782895682; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ZjmKzXbjKhCHmtx2rpBPlFTDcxKMT/ZJGQfdrok6APM=; b=TZpcz/tcDmgNJpbk7rVVRQHfOFwQW1XD7YhpKNQbMVr5YJt86zC+sxz0Bv0bDS3d/1WmRl xW/uV5oKqa00tdOT23dKcxzdNXF++T2lHwsf+v8/jv3EQqa9+l5EOjq4Jo/MzVaP7Af+X8 lZS874teHyhoBmwM7KH6CtfCLG5riGs= From: Atish Patra Date: Wed, 01 Jul 2026 01:46:56 -0700 Subject: [PATCH v8 08/22] RISC-V: Add Sscfg extension CSR definition Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260701-counter_delegation-v8-8-7909f863a645@meta.com> References: <20260701-counter_delegation-v8-0-7909f863a645@meta.com> In-Reply-To: <20260701-counter_delegation-v8-0-7909f863a645@meta.com> To: Jiri Olsa , Paul Walmsley , Mark Rutland , Rob Herring , Anup Patel , Namhyung Kim , Arnaldo Carvalho de Melo , Krzysztof Kozlowski , Atish Patra , Ian Rogers , Will Deacon , James Clark Cc: linux-arm-kernel@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-perf-users@vger.kernel.org, Conor Dooley X-Migadu-Flow: FLOW_OUT From: Kaiwen Xue This adds the scountinhibit CSR definition and S-mode accessible hpmevent bits defined by smcdeleg/ssccfg. scountinhibit allows S-mode to start/stop counters directly from S-mode without invoking SBI calls to M-mode. It is also used to figure out the counters delegated to S-mode by the M-mode as well. Signed-off-by: Kaiwen Xue Reviewed-by: Cl=C3=A9ment L=C3=A9ger --- arch/riscv/include/asm/csr.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index b4551a6cf7cb..a3b24b88e401 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -241,6 +241,23 @@ #define SMSTATEEN0_HSENVCFG (_ULL(1) << SMSTATEEN0_HSENVCFG_SHIFT) #define SMSTATEEN0_SSTATEEN0_SHIFT 63 #define SMSTATEEN0_SSTATEEN0 (_ULL(1) << SMSTATEEN0_SSTATEEN0_SHIFT) +/* HPMEVENT bits. These are accessible in S-mode via Smcdeleg/Ssccfg */ +#define HPMEVENT_OF (BIT_ULL(63)) +#define HPMEVENT_MINH (BIT_ULL(62)) +#define HPMEVENT_SINH (BIT_ULL(61)) +#define HPMEVENT_UINH (BIT_ULL(60)) +#define HPMEVENT_VSINH (BIT_ULL(59)) +#define HPMEVENT_VUINH (BIT_ULL(58)) +#ifndef CONFIG_64BIT +#define HPMEVENTH_OF (BIT(31)) +#define HPMEVENTH_MINH (BIT(30)) +#define HPMEVENTH_SINH (BIT(29)) +#define HPMEVENTH_UINH (BIT(28)) +#define HPMEVENTH_VSINH (BIT(27)) +#define HPMEVENTH_VUINH (BIT(26)) +#endif + +#define SISELECT_SSCCFG_BASE 0x40 =20 /* mseccfg bits */ #define MSECCFG_PMM ENVCFG_PMM @@ -322,6 +339,7 @@ #define CSR_SCOUNTEREN 0x106 #define CSR_SENVCFG 0x10a #define CSR_SSTATEEN0 0x10c +#define CSR_SCOUNTINHIBIT 0x120 #define CSR_SSCRATCH 0x140 #define CSR_SEPC 0x141 #define CSR_SCAUSE 0x142 --=20 2.53.0-Meta From nobody Thu Jul 16 17:05:11 2026 Received: from out-186.mta1.migadu.com (out-186.mta1.migadu.com [95.215.58.186]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 09C2A3BADB2 for ; Wed, 1 Jul 2026 08:48:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.186 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782895690; cv=none; b=kI2RA72taSaSKrsKNgCpFMjoM0UMlnpcu31K0+L00xSWwsxgyqLvw3Ha6qlr1Ercka+hcfjrReVTb0c/EXFI1Ni63uruVRRziszdKEnJtKR84XSQCGWFwx48geux9r9KZzaThSum7obEQ0WqmLkyrQiQE6IPBsBkAEOo+YRKDfg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782895690; c=relaxed/simple; bh=qI7ylPGhf6GPYHa6rJhXo0UFdpIqMb7rB+hO27t6rWw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=UWSrSf7SQkI2rGKLUaj68stjcTnIjtcWjlLTpU9wwlc3my9+B2AVz96jro/197Sx2/LEsn0v8SeX2Xp2Aj/1LodxpNUkX/DGzWAEnibmzmgK9a0jfPDONw3Ulwhij0mz9hGulmIALGGj6fleFR/6gwzUkyWJ80QK2MFGggUvIxY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=v1gNmMw9; arc=none smtp.client-ip=95.215.58.186 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="v1gNmMw9" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1782895687; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=NUBImEnq8hbrnJQhJKzk1cL/zkOMmDZcmfYv80HVE44=; b=v1gNmMw9Wu1L5HNO6yl+V63bNZR6/+6HB2iv55T4FTzUR5NzkErdYEC44v2wSXNUOKQyEj W2Po252VXBCQ3dyho3sXOFMnEvr6BC/Kre7QOHw1i2iVhLzMMAKnv6Hi/VJUGM2MlW566m mRaozIt0ZRdTPnqCSkm+kaFKgmSkghU= From: Atish Patra Date: Wed, 01 Jul 2026 01:46:57 -0700 Subject: [PATCH v8 09/22] RISC-V: Add Ssccfg/Smcdeleg ISA extension definition and parsing Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260701-counter_delegation-v8-9-7909f863a645@meta.com> References: <20260701-counter_delegation-v8-0-7909f863a645@meta.com> In-Reply-To: <20260701-counter_delegation-v8-0-7909f863a645@meta.com> To: Jiri Olsa , Paul Walmsley , Mark Rutland , Rob Herring , Anup Patel , Namhyung Kim , Arnaldo Carvalho de Melo , Krzysztof Kozlowski , Atish Patra , Ian Rogers , Will Deacon , James Clark Cc: linux-arm-kernel@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-perf-users@vger.kernel.org, Conor Dooley X-Migadu-Flow: FLOW_OUT From: Atish Patra Smcdeleg extension allows the M-mode to delegate selected counters to S-mode so that it can access those counters and correpsonding hpmevent CSRs without M-mode. Ssccfg (=E2=80=98Ss=E2=80=99 for Privileged architecture and Supervisor-lev= el extension, =E2=80=98ccfg=E2=80=99 for Counter Configuration) provides acces= s to delegated counters and new supervisor-level state. This patch just enables these definitions and enable parsing. Signed-off-by: Atish Patra --- arch/riscv/include/asm/hwcap.h | 2 ++ arch/riscv/kernel/cpufeature.c | 24 ++++++++++++++++++++++++ 2 files changed, 26 insertions(+) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 51ad55b9677a..089353b250b0 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -115,6 +115,8 @@ #define RISCV_ISA_EXT_SSCSRIND 106 #define RISCV_ISA_EXT_SMCSRIND 107 #define RISCV_ISA_EXT_SMCNTRPMF 108 +#define RISCV_ISA_EXT_SSCCFG 109 +#define RISCV_ISA_EXT_SMCDELEG 110 =20 #define RISCV_ISA_EXT_XLINUXENVCFG 127 =20 diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 1452521d740a..1fe647e03515 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -330,6 +330,27 @@ static const unsigned int riscv_a_exts[] =3D { RISCV_ISA_EXT_ZKNE, \ RISCV_ISA_EXT_ZKNH =20 +static int riscv_ext_smcdeleg_validate(const struct riscv_isa_ext_data *da= ta, + const unsigned long *isa_bitmap) +{ + if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_SSCSRIND) && + __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_ZIHPM) && + __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_ZICNTR)) + return 0; + + return -EPROBE_DEFER; +} + +static int riscv_ext_ssccfg_validate(const struct riscv_isa_ext_data *data, + const unsigned long *isa_bitmap) +{ + if (!riscv_ext_smcdeleg_validate(data, isa_bitmap) && + __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_SMCDELEG)) + return 0; + + return -EPROBE_DEFER; +} + static const unsigned int riscv_zk_bundled_exts[] =3D { RISCV_ISA_EXT_ZKN, RISCV_ISA_EXT_ZKR, @@ -576,12 +597,15 @@ const struct riscv_isa_ext_data riscv_isa_ext[] =3D { __RISCV_ISA_EXT_BUNDLE_VALIDATE(zvksg, riscv_zvksg_bundled_exts, riscv_ex= t_vector_crypto_validate), __RISCV_ISA_EXT_DATA_VALIDATE(zvkt, RISCV_ISA_EXT_ZVKT, riscv_ext_vector_= crypto_validate), __RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA), + __RISCV_ISA_EXT_DATA_VALIDATE(smcdeleg, RISCV_ISA_EXT_SMCDELEG, + riscv_ext_smcdeleg_validate), __RISCV_ISA_EXT_DATA(smcntrpmf, RISCV_ISA_EXT_SMCNTRPMF), __RISCV_ISA_EXT_DATA(smcsrind, RISCV_ISA_EXT_SMCSRIND), __RISCV_ISA_EXT_DATA(smmpm, RISCV_ISA_EXT_SMMPM), __RISCV_ISA_EXT_SUPERSET(smnpm, RISCV_ISA_EXT_SMNPM, riscv_xlinuxenvcfg_e= xts), __RISCV_ISA_EXT_DATA(smstateen, RISCV_ISA_EXT_SMSTATEEN), __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA), + __RISCV_ISA_EXT_DATA_VALIDATE(ssccfg, RISCV_ISA_EXT_SSCCFG, riscv_ext_ssc= cfg_validate), __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), __RISCV_ISA_EXT_DATA(sscsrind, RISCV_ISA_EXT_SSCSRIND), __RISCV_ISA_EXT_SUPERSET(ssnpm, RISCV_ISA_EXT_SSNPM, riscv_xlinuxenvcfg_e= xts), --=20 2.53.0-Meta From nobody Thu Jul 16 17:05:11 2026 Received: from out-181.mta1.migadu.com (out-181.mta1.migadu.com [95.215.58.181]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 269AF3F0A9E for ; Wed, 1 Jul 2026 08:48:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.181 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782895693; cv=none; b=SsmeZtGqhV6GQJ/kYqhVsSR3FWcEd7bdOlkfgfu4gropm26obLiqdsglVGmKkmPVblmqVHm6tAxHQII2u+B6lpoN9OkrTaa7R2a/WogTuoNDWZOaU9MTQJqirtuVZ5tLfoF2Bu3mrbVroRWm7zqQ/lcrbSVfzVyFdnpovdmvucQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782895693; c=relaxed/simple; bh=DMlDviBD4xs9HqEdZpdNmhs7JEUKHNCtiUuP6Nt4Hi4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=qJiZ1hR1XVJgZ6n17uscq0EkbgBjCuJhF6UEfnhm+xYRDPa2K9tXqq8fxNhUm2mMzF4mJvisR10uFF9Xjdm/D9jd+zR9lIH8rvzpHiwQseYE0EmnhIeR9RMNUHHydWAYg5xoszhN5LJGJ1+vFSFPA5ruHFwcb2LxUqs/sXWhvYM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=GsJnxoaL; arc=none smtp.client-ip=95.215.58.181 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="GsJnxoaL" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1782895690; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=zCjQpneLNRBCiuygsyfB7UCIbsXua9nygQEyYm86NNo=; b=GsJnxoaLdmIe9Nx4TsUIlm9oe7OJ9WdgCCop+EWIV7gunJDF4rokwuC5O1qtPrncbnVfAI zyiLDFfmrCnZ7ECxO5MjFuzf+PXI7qp4iJZe3QTcr7OUOVSB463Bn43ODKI15bxxXKVFKT BdMGsuIucs6x4XEn1SCPqwWM5VwMjoQ= From: Atish Patra Date: Wed, 01 Jul 2026 01:46:58 -0700 Subject: [PATCH v8 10/22] dt-bindings: riscv: add Counter delegation ISA extensions description Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260701-counter_delegation-v8-10-7909f863a645@meta.com> References: <20260701-counter_delegation-v8-0-7909f863a645@meta.com> In-Reply-To: <20260701-counter_delegation-v8-0-7909f863a645@meta.com> To: Jiri Olsa , Paul Walmsley , Mark Rutland , Rob Herring , Anup Patel , Namhyung Kim , Arnaldo Carvalho de Melo , Krzysztof Kozlowski , Atish Patra , Ian Rogers , Will Deacon , James Clark Cc: linux-arm-kernel@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-perf-users@vger.kernel.org, Conor Dooley X-Migadu-Flow: FLOW_OUT From: Atish Patra Add description for the Smcdeleg/Ssccfg extension. Signed-off-by: Atish Patra Acked-by: Conor Dooley --- .../devicetree/bindings/riscv/extensions.yaml | 41 ++++++++++++++++++= ++++ 1 file changed, 41 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Docu= mentation/devicetree/bindings/riscv/extensions.yaml index 2493766e956d..eef5eeb198d0 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -181,6 +181,13 @@ properties: changes to interrupts as frozen at commit ccbddab ("Merge pull request #42 from riscv/jhauser-2023-RC4") of riscv-aia. =20 + - const: smcdeleg + description: | + The standard Smcdeleg machine-level extension for the machine = mode + to delegate the hpmcounters to supervisor mode so that they are + directly accessible in the supervisor mode as ratified in the + 20240213 version of the privileged ISA specification. + - const: smcntrpmf description: | The standard Smcntrpmf machine-level extension for the machine= mode @@ -220,6 +227,14 @@ properties: behavioural changes to interrupts as frozen at commit ccbddab ("Merge pull request #42 from riscv/jhauser-2023-RC4") of risc= v-aia. =20 + - const: ssccfg + description: | + The standard Ssccfg supervisor-level extension for configuring + the delegated hpmcounters to be accessible directly in supervi= sor + mode as ratified in the 20240213 version of the privileged ISA + specification. This extension depends on Sscsrind, Smcdeleg, Z= ihpm, + Zicntr extensions. + - const: ssccptr description: | The standard Ssccptr extension for main memory (cacheability a= nd @@ -1135,6 +1150,32 @@ properties: allOf: - const: zilsd - const: zca + # Smcdeleg depends on Sscsrind, Zihpm, Zicntr + - if: + contains: + const: smcdeleg + then: + allOf: + - contains: + const: sscsrind + - contains: + const: zihpm + - contains: + const: zicntr + # Ssccfg depends on Smcdeleg, Sscsrind, Zihpm, Zicntr + - if: + contains: + const: ssccfg + then: + allOf: + - contains: + const: smcdeleg + - contains: + const: sscsrind + - contains: + const: zihpm + - contains: + const: zicntr =20 allOf: # Zcf extension does not exist on rv64 --=20 2.53.0-Meta From nobody Thu Jul 16 17:05:11 2026 Received: from out-170.mta0.migadu.com (out-170.mta0.migadu.com [91.218.175.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C667D3F23D5 for ; Wed, 1 Jul 2026 08:48:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.218.175.170 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782895698; cv=none; b=ghVnvp/qPnsPmReOIOHwhIvDGeVcSmysXWfxMeRDVvxLWdSoMIHaeunhsTILkzLWSxVG0qn8vaBBqyQTIXQdxKTboyWZn1xDrRO0mSl4rk73KGHVbk5fhFyGmIUSqMB4YP5LWDpZ/XjmDwJkOtfZGpuBFmJGK4R+YZQP8qRDwF4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782895698; c=relaxed/simple; bh=e8ZeePekNA3svLRvK8o2iWEJu9352fF9lrxFTY2RxAI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=aqfyWATEADWssWLBzTG4ur5OL9Hv3BmAQN3a/H39uWaohKz4lw9app1Eg8de3rvApLOQ4H2u+0Zuob8JAwdKxf4ZxweTo5IHcFaJPgT7TvGtALRiD7aXIZhD/BzszGgslo4CGhriuC/l+cqeQo+6Neg/E0uPUIW0B2cJJ1f78Q0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=CdfVyHo3; arc=none smtp.client-ip=91.218.175.170 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="CdfVyHo3" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1782895694; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=vv3IlMYpUIHvCCcAQYvSqXAalcDbqNOfwDufVevgvOQ=; b=CdfVyHo3lidVndx98QKxC97SmgkYw4pNUpYI78Yny6tlE3aTnrkV/hKtJTUzk0ozns83EM zjrrWOlb4wjbbBJqqlB3pm4V+R14cFozor9F4cetS1lhaK+OFpUh3exejR5vZLUEsjlHsU 4gAkxIZTHXNWGsDSy3JmQmFXixn9zVo= From: Atish Patra Date: Wed, 01 Jul 2026 01:46:59 -0700 Subject: [PATCH v8 11/22] RISC-V: perf: Restructure the SBI PMU code Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260701-counter_delegation-v8-11-7909f863a645@meta.com> References: <20260701-counter_delegation-v8-0-7909f863a645@meta.com> In-Reply-To: <20260701-counter_delegation-v8-0-7909f863a645@meta.com> To: Jiri Olsa , Paul Walmsley , Mark Rutland , Rob Herring , Anup Patel , Namhyung Kim , Arnaldo Carvalho de Melo , Krzysztof Kozlowski , Atish Patra , Ian Rogers , Will Deacon , James Clark Cc: linux-arm-kernel@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-perf-users@vger.kernel.org, Conor Dooley X-Migadu-Flow: FLOW_OUT From: Atish Patra With Ssccfg/Smcdeleg, supervisor mode can program and access the hpmcounters and events directly, without the SBI PMU extension. The SBI PMU extension is still required for firmware counters. Restructure the existing SBI PMU code so the hpmcounter/event helpers can be shared between the SBI and the counter delegation paths that follow. The driver, file, module and Kconfig names are intentionally kept unchanged to avoid backport churn and userspace breakage (module listings, udev rules, cmdline options). No functional change intended. Signed-off-by: Atish Patra --- drivers/perf/Kconfig | 14 ++- drivers/perf/riscv_pmu_sbi.c | 238 +++++++++++++++++++++++++--------------= ---- 2 files changed, 150 insertions(+), 102 deletions(-) diff --git a/drivers/perf/Kconfig b/drivers/perf/Kconfig index ab90932fc2d0..3245bb2969e1 100644 --- a/drivers/perf/Kconfig +++ b/drivers/perf/Kconfig @@ -97,13 +97,17 @@ config RISCV_PMU_LEGACY =20 config RISCV_PMU_SBI depends on RISCV_PMU && RISCV_SBI - bool "RISC-V PMU based on SBI PMU extension" + bool "RISC-V PMU based on SBI PMU extension and/or counter delegation" default y help - Say y if you want to use the CPU performance monitor - using SBI PMU extension on RISC-V based systems. This option provides - full perf feature support i.e. counter overflow, privilege mode - filtering, counter configuration. + Say y if you want to use the CPU performance monitor on RISC-V based + systems. This single driver supports both hardware counter access + mechanisms: it uses the counter delegation (Smcdeleg/Ssccfg) ISA + extension to program and read the hpmcounters directly in supervisor + mode when available, and uses the SBI PMU extension for firmware + counters and when counter delegation is not present. This option + provides full perf feature support i.e. counter overflow, privilege + mode filtering, counter configuration. =20 config STARFIVE_STARLINK_PMU depends on ARCH_STARFIVE || COMPILE_TEST diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index 5c8924ce1f38..74d934238821 100644 --- a/drivers/perf/riscv_pmu_sbi.c +++ b/drivers/perf/riscv_pmu_sbi.c @@ -88,6 +88,8 @@ static const struct attribute_group *riscv_pmu_attr_group= s[] =3D { static int sysctl_perf_user_access __read_mostly =3D SYSCTL_USER_ACCESS; =20 /* + * This structure is SBI specific but counter delegation also require coun= ter + * width, csr mapping. Reuse it for now. * RISC-V doesn't have heterogeneous harts yet. This need to be part of * per_cpu in case of harts with different pmu counters */ @@ -100,7 +102,7 @@ static unsigned int riscv_pmu_irq; /* Cache the available counters in a bitmask */ static unsigned long cmask; =20 -static int pmu_event_find_cache(u64 config); +static int sbi_pmu_event_find_cache(u64 config); struct sbi_pmu_event_data { union { union { @@ -121,7 +123,7 @@ struct sbi_pmu_event_data { }; }; =20 -static struct sbi_pmu_event_data pmu_hw_event_map[] =3D { +static struct sbi_pmu_event_data pmu_hw_event_sbi_map[] =3D { [PERF_COUNT_HW_CPU_CYCLES] =3D {.hw_gen_event =3D { SBI_PMU_HW_CPU_CYCLES, SBI_PMU_EVENT_TYPE_HW, 0}}, @@ -155,7 +157,7 @@ static struct sbi_pmu_event_data pmu_hw_event_map[] =3D= { }; =20 #define C(x) PERF_COUNT_HW_CACHE_##x -static struct sbi_pmu_event_data pmu_cache_event_map[PERF_COUNT_HW_CACHE_M= AX] +static struct sbi_pmu_event_data pmu_cache_event_sbi_map[PERF_COUNT_HW_CAC= HE_MAX] [PERF_COUNT_HW_CACHE_OP_MAX] [PERF_COUNT_HW_CACHE_RESULT_MAX] =3D { [C(L1D)] =3D { @@ -302,7 +304,7 @@ static struct sbi_pmu_event_data pmu_cache_event_map[PE= RF_COUNT_HW_CACHE_MAX] =20 static int pmu_sbi_check_event_info(void) { - int num_events =3D ARRAY_SIZE(pmu_hw_event_map) + PERF_COUNT_HW_CACHE_MAX= * + int num_events =3D ARRAY_SIZE(pmu_hw_event_sbi_map) + PERF_COUNT_HW_CACHE= _MAX * PERF_COUNT_HW_CACHE_OP_MAX * PERF_COUNT_HW_CACHE_RESULT_MAX; struct riscv_pmu_event_info *event_info_shmem; phys_addr_t base_addr; @@ -313,14 +315,14 @@ static int pmu_sbi_check_event_info(void) if (!event_info_shmem) return -ENOMEM; =20 - for (i =3D 0; i < ARRAY_SIZE(pmu_hw_event_map); i++) - event_info_shmem[count++].event_idx =3D pmu_hw_event_map[i].event_idx; + for (i =3D 0; i < ARRAY_SIZE(pmu_hw_event_sbi_map); i++) + event_info_shmem[count++].event_idx =3D pmu_hw_event_sbi_map[i].event_id= x; =20 - for (i =3D 0; i < ARRAY_SIZE(pmu_cache_event_map); i++) { - for (j =3D 0; j < ARRAY_SIZE(pmu_cache_event_map[i]); j++) { - for (k =3D 0; k < ARRAY_SIZE(pmu_cache_event_map[i][j]); k++) + for (i =3D 0; i < ARRAY_SIZE(pmu_cache_event_sbi_map); i++) { + for (j =3D 0; j < ARRAY_SIZE(pmu_cache_event_sbi_map[i]); j++) { + for (k =3D 0; k < ARRAY_SIZE(pmu_cache_event_sbi_map[i][j]); k++) event_info_shmem[count++].event_idx =3D - pmu_cache_event_map[i][j][k].event_idx; + pmu_cache_event_sbi_map[i][j][k].event_idx; } } =20 @@ -336,19 +338,19 @@ static int pmu_sbi_check_event_info(void) goto free_mem; } =20 - for (i =3D 0; i < ARRAY_SIZE(pmu_hw_event_map); i++) { + for (i =3D 0; i < ARRAY_SIZE(pmu_hw_event_sbi_map); i++) { if (!(event_info_shmem[i].output & RISCV_PMU_EVENT_INFO_OUTPUT_MASK)) - pmu_hw_event_map[i].event_idx =3D -ENOENT; + pmu_hw_event_sbi_map[i].event_idx =3D -ENOENT; } =20 - count =3D ARRAY_SIZE(pmu_hw_event_map); + count =3D ARRAY_SIZE(pmu_hw_event_sbi_map); =20 - for (i =3D 0; i < ARRAY_SIZE(pmu_cache_event_map); i++) { - for (j =3D 0; j < ARRAY_SIZE(pmu_cache_event_map[i]); j++) { - for (k =3D 0; k < ARRAY_SIZE(pmu_cache_event_map[i][j]); k++) { + for (i =3D 0; i < ARRAY_SIZE(pmu_cache_event_sbi_map); i++) { + for (j =3D 0; j < ARRAY_SIZE(pmu_cache_event_sbi_map[i]); j++) { + for (k =3D 0; k < ARRAY_SIZE(pmu_cache_event_sbi_map[i][j]); k++) { if (!(event_info_shmem[count].output & RISCV_PMU_EVENT_INFO_OUTPUT_MASK)) - pmu_cache_event_map[i][j][k].event_idx =3D -ENOENT; + pmu_cache_event_sbi_map[i][j][k].event_idx =3D -ENOENT; count++; } } @@ -360,7 +362,7 @@ static int pmu_sbi_check_event_info(void) return result; } =20 -static void pmu_sbi_check_event(struct sbi_pmu_event_data *edata) +static void rvpmu_sbi_check_event(struct sbi_pmu_event_data *edata) { struct sbiret ret; =20 @@ -375,7 +377,7 @@ static void pmu_sbi_check_event(struct sbi_pmu_event_da= ta *edata) } } =20 -static void pmu_sbi_check_std_events(struct work_struct *work) +static void rvpmu_sbi_check_std_events(struct work_struct *work) { int ret; =20 @@ -386,23 +388,23 @@ static void pmu_sbi_check_std_events(struct work_stru= ct *work) return; } =20 - for (int i =3D 0; i < ARRAY_SIZE(pmu_hw_event_map); i++) - pmu_sbi_check_event(&pmu_hw_event_map[i]); + for (int i =3D 0; i < ARRAY_SIZE(pmu_hw_event_sbi_map); i++) + rvpmu_sbi_check_event(&pmu_hw_event_sbi_map[i]); =20 - for (int i =3D 0; i < ARRAY_SIZE(pmu_cache_event_map); i++) - for (int j =3D 0; j < ARRAY_SIZE(pmu_cache_event_map[i]); j++) - for (int k =3D 0; k < ARRAY_SIZE(pmu_cache_event_map[i][j]); k++) - pmu_sbi_check_event(&pmu_cache_event_map[i][j][k]); + for (int i =3D 0; i < ARRAY_SIZE(pmu_cache_event_sbi_map); i++) + for (int j =3D 0; j < ARRAY_SIZE(pmu_cache_event_sbi_map[i]); j++) + for (int k =3D 0; k < ARRAY_SIZE(pmu_cache_event_sbi_map[i][j]); k++) + rvpmu_sbi_check_event(&pmu_cache_event_sbi_map[i][j][k]); } =20 -static DECLARE_WORK(check_std_events_work, pmu_sbi_check_std_events); +static DECLARE_WORK(check_std_events_work, rvpmu_sbi_check_std_events); =20 -static int pmu_sbi_ctr_get_width(int idx) +static int rvpmu_ctr_get_width(int idx) { return pmu_ctr_list[idx].width; } =20 -static bool pmu_sbi_ctr_is_fw(int cidx) +static bool rvpmu_ctr_is_fw(int cidx) { union sbi_pmu_ctr_info *info; =20 @@ -421,10 +423,10 @@ int riscv_pmu_get_event_info(u32 type, u64 config, u6= 4 *econfig) case PERF_TYPE_HARDWARE: if (config >=3D PERF_COUNT_HW_MAX) return -EINVAL; - ret =3D pmu_hw_event_map[config].event_idx; + ret =3D pmu_hw_event_sbi_map[config].event_idx; break; case PERF_TYPE_HW_CACHE: - ret =3D pmu_event_find_cache(config); + ret =3D sbi_pmu_event_find_cache(config); break; case PERF_TYPE_RAW: /* @@ -509,12 +511,12 @@ int riscv_pmu_get_hpm_info(u32 *hw_ctr_width, u32 *nu= m_hw_ctr) } EXPORT_SYMBOL_GPL(riscv_pmu_get_hpm_info); =20 -static uint8_t pmu_sbi_csr_index(struct perf_event *event) +static uint8_t rvpmu_csr_index(struct perf_event *event) { return pmu_ctr_list[event->hw.idx].csr - CSR_CYCLE; } =20 -static unsigned long pmu_sbi_get_filter_flags(struct perf_event *event) +static unsigned long rvpmu_sbi_get_filter_flags(struct perf_event *event) { unsigned long cflags =3D 0; bool guest_events =3D false; @@ -535,7 +537,7 @@ static unsigned long pmu_sbi_get_filter_flags(struct pe= rf_event *event) return cflags; } =20 -static int pmu_sbi_ctr_get_idx(struct perf_event *event) +static int rvpmu_sbi_ctr_get_idx(struct perf_event *event) { struct hw_perf_event *hwc =3D &event->hw; struct riscv_pmu *rvpmu =3D to_riscv_pmu(event->pmu); @@ -545,7 +547,7 @@ static int pmu_sbi_ctr_get_idx(struct perf_event *event) uint64_t cbase =3D 0, cmask =3D rvpmu->cmask; unsigned long cflags =3D 0; =20 - cflags =3D pmu_sbi_get_filter_flags(event); + cflags =3D rvpmu_sbi_get_filter_flags(event); =20 /* * In legacy mode, we have to force the fixed counters for those events @@ -582,7 +584,7 @@ static int pmu_sbi_ctr_get_idx(struct perf_event *event) return -ENOENT; =20 /* Additional sanity check for the counter id */ - if (pmu_sbi_ctr_is_fw(idx)) { + if (rvpmu_ctr_is_fw(idx)) { if (!test_and_set_bit(idx, cpuc->used_fw_ctrs)) return idx; } else { @@ -593,7 +595,7 @@ static int pmu_sbi_ctr_get_idx(struct perf_event *event) return -ENOENT; } =20 -static void pmu_sbi_ctr_clear_idx(struct perf_event *event) +static void rvpmu_ctr_clear_idx(struct perf_event *event) { =20 struct hw_perf_event *hwc =3D &event->hw; @@ -601,13 +603,13 @@ static void pmu_sbi_ctr_clear_idx(struct perf_event *= event) struct cpu_hw_events *cpuc =3D this_cpu_ptr(rvpmu->hw_events); int idx =3D hwc->idx; =20 - if (pmu_sbi_ctr_is_fw(idx)) + if (rvpmu_ctr_is_fw(idx)) clear_bit(idx, cpuc->used_fw_ctrs); else clear_bit(idx, cpuc->used_hw_ctrs); } =20 -static int pmu_event_find_cache(u64 config) +static int sbi_pmu_event_find_cache(u64 config) { unsigned int cache_type, cache_op, cache_result, ret; =20 @@ -623,7 +625,7 @@ static int pmu_event_find_cache(u64 config) if (cache_result >=3D PERF_COUNT_HW_CACHE_RESULT_MAX) return -EINVAL; =20 - ret =3D pmu_cache_event_map[cache_type][cache_op][cache_result].event_idx; + ret =3D pmu_cache_event_sbi_map[cache_type][cache_op][cache_result].event= _idx; =20 return ret; } @@ -639,7 +641,7 @@ static bool pmu_sbi_is_fw_event(struct perf_event *even= t) return false; } =20 -static int pmu_sbi_event_map(struct perf_event *event, u64 *econfig) +static int rvpmu_sbi_event_map(struct perf_event *event, u64 *econfig) { u32 type =3D event->attr.type; u64 config =3D event->attr.config; @@ -736,7 +738,7 @@ static int pmu_sbi_snapshot_setup(struct riscv_pmu *pmu= , int cpu) return 0; } =20 -static u64 pmu_sbi_ctr_read(struct perf_event *event) +static u64 rvpmu_sbi_ctr_read(struct perf_event *event) { struct hw_perf_event *hwc =3D &event->hw; int idx =3D hwc->idx; @@ -778,25 +780,25 @@ static u64 pmu_sbi_ctr_read(struct perf_event *event) return val; } =20 -static void pmu_sbi_set_scounteren(void *arg) +static void rvpmu_set_scounteren(void *arg) { struct perf_event *event =3D (struct perf_event *)arg; =20 if (event->hw.idx !=3D -1) csr_write(CSR_SCOUNTEREN, - csr_read(CSR_SCOUNTEREN) | BIT(pmu_sbi_csr_index(event))); + csr_read(CSR_SCOUNTEREN) | BIT(rvpmu_csr_index(event))); } =20 -static void pmu_sbi_reset_scounteren(void *arg) +static void rvpmu_reset_scounteren(void *arg) { struct perf_event *event =3D (struct perf_event *)arg; =20 if (event->hw.idx !=3D -1) csr_write(CSR_SCOUNTEREN, - csr_read(CSR_SCOUNTEREN) & ~BIT(pmu_sbi_csr_index(event))); + csr_read(CSR_SCOUNTEREN) & ~BIT(rvpmu_csr_index(event))); } =20 -static void pmu_sbi_ctr_start(struct perf_event *event, u64 ival) +static void rvpmu_sbi_ctr_start(struct perf_event *event, u64 ival) { struct sbiret ret; struct hw_perf_event *hwc =3D &event->hw; @@ -816,10 +818,10 @@ static void pmu_sbi_ctr_start(struct perf_event *even= t, u64 ival) =20 if ((hwc->flags & PERF_EVENT_FLAG_USER_ACCESS) && (hwc->flags & PERF_EVENT_FLAG_USER_READ_CNT)) - pmu_sbi_set_scounteren((void *)event); + rvpmu_set_scounteren((void *)event); } =20 -static void pmu_sbi_ctr_stop(struct perf_event *event, unsigned long flag) +static void rvpmu_sbi_ctr_stop(struct perf_event *event, unsigned long fla= g) { struct sbiret ret; struct hw_perf_event *hwc =3D &event->hw; @@ -829,7 +831,7 @@ static void pmu_sbi_ctr_stop(struct perf_event *event, = unsigned long flag) =20 if ((hwc->flags & PERF_EVENT_FLAG_USER_ACCESS) && (hwc->flags & PERF_EVENT_FLAG_USER_READ_CNT)) - pmu_sbi_reset_scounteren((void *)event); + rvpmu_reset_scounteren((void *)event); =20 if (sbi_pmu_snapshot_available()) flag |=3D SBI_PMU_STOP_FLAG_TAKE_SNAPSHOT; @@ -855,7 +857,7 @@ static void pmu_sbi_ctr_stop(struct perf_event *event, = unsigned long flag) } } =20 -static int pmu_sbi_find_num_ctrs(void) +static int rvpmu_sbi_find_num_ctrs(void) { struct sbiret ret; =20 @@ -866,7 +868,7 @@ static int pmu_sbi_find_num_ctrs(void) return sbi_err_map_linux_errno(ret.error); } =20 -static int pmu_sbi_get_ctrinfo(int nctr, unsigned long *mask) +static int rvpmu_sbi_get_ctrinfo(int nctr, unsigned long *mask) { struct sbiret ret; int i, num_hw_ctr =3D 0, num_fw_ctr =3D 0; @@ -897,7 +899,7 @@ static int pmu_sbi_get_ctrinfo(int nctr, unsigned long = *mask) return 0; } =20 -static inline void pmu_sbi_stop_all(struct riscv_pmu *pmu) +static inline void rvpmu_sbi_stop_all(struct riscv_pmu *pmu) { /* * No need to check the error because we are disabling all the counters @@ -907,7 +909,7 @@ static inline void pmu_sbi_stop_all(struct riscv_pmu *p= mu) 0, pmu->cmask, SBI_PMU_STOP_FLAG_RESET, 0, 0, 0); } =20 -static inline void pmu_sbi_stop_hw_ctrs(struct riscv_pmu *pmu) +static inline void rvpmu_sbi_stop_hw_ctrs(struct riscv_pmu *pmu) { struct cpu_hw_events *cpu_hw_evt =3D this_cpu_ptr(pmu->hw_events); struct riscv_pmu_snapshot_data *sdata =3D cpu_hw_evt->snapshot_addr; @@ -951,8 +953,8 @@ static inline void pmu_sbi_stop_hw_ctrs(struct riscv_pm= u *pmu) * while the overflowed counters need to be started with updated initializ= ation * value. */ -static inline void pmu_sbi_start_ovf_ctrs_sbi(struct cpu_hw_events *cpu_hw= _evt, - u64 ctr_ovf_mask) +static inline void rvpmu_sbi_start_ovf_ctrs_sbi(struct cpu_hw_events *cpu_= hw_evt, + u64 ctr_ovf_mask) { int idx =3D 0, i; struct perf_event *event; @@ -992,8 +994,8 @@ static inline void pmu_sbi_start_ovf_ctrs_sbi(struct cp= u_hw_events *cpu_hw_evt, } } =20 -static inline void pmu_sbi_start_ovf_ctrs_snapshot(struct cpu_hw_events *c= pu_hw_evt, - u64 ctr_ovf_mask) +static inline void rvpmu_sbi_start_ovf_ctrs_snapshot(struct cpu_hw_events = *cpu_hw_evt, + u64 ctr_ovf_mask) { int i, idx =3D 0; struct perf_event *event; @@ -1027,18 +1029,18 @@ static inline void pmu_sbi_start_ovf_ctrs_snapshot(= struct cpu_hw_events *cpu_hw_ } } =20 -static void pmu_sbi_start_overflow_mask(struct riscv_pmu *pmu, - u64 ctr_ovf_mask) +static void rvpmu_sbi_start_overflow_mask(struct riscv_pmu *pmu, + u64 ctr_ovf_mask) { struct cpu_hw_events *cpu_hw_evt =3D this_cpu_ptr(pmu->hw_events); =20 if (sbi_pmu_snapshot_available()) - pmu_sbi_start_ovf_ctrs_snapshot(cpu_hw_evt, ctr_ovf_mask); + rvpmu_sbi_start_ovf_ctrs_snapshot(cpu_hw_evt, ctr_ovf_mask); else - pmu_sbi_start_ovf_ctrs_sbi(cpu_hw_evt, ctr_ovf_mask); + rvpmu_sbi_start_ovf_ctrs_sbi(cpu_hw_evt, ctr_ovf_mask); } =20 -static irqreturn_t pmu_sbi_ovf_handler(int irq, void *dev) +static irqreturn_t rvpmu_ovf_handler(int irq, void *dev) { struct perf_sample_data data; struct pt_regs *regs; @@ -1070,7 +1072,7 @@ static irqreturn_t pmu_sbi_ovf_handler(int irq, void = *dev) } =20 pmu =3D to_riscv_pmu(event->pmu); - pmu_sbi_stop_hw_ctrs(pmu); + rvpmu_sbi_stop_hw_ctrs(pmu); =20 /* Overflow status register should only be read after counter are stopped= */ if (sbi_pmu_snapshot_available()) @@ -1139,13 +1141,55 @@ static irqreturn_t pmu_sbi_ovf_handler(int irq, voi= d *dev) hw_evt->state =3D 0; } =20 - pmu_sbi_start_overflow_mask(pmu, overflowed_ctrs); + rvpmu_sbi_start_overflow_mask(pmu, overflowed_ctrs); perf_sample_event_took(sched_clock() - start_clock); =20 return IRQ_HANDLED; } =20 -static int pmu_sbi_starting_cpu(unsigned int cpu, struct hlist_node *node) +static void rvpmu_ctr_start(struct perf_event *event, u64 ival) +{ + rvpmu_sbi_ctr_start(event, ival); + /* TODO: Counter delegation implementation */ +} + +static void rvpmu_ctr_stop(struct perf_event *event, unsigned long flag) +{ + rvpmu_sbi_ctr_stop(event, flag); + /* TODO: Counter delegation implementation */ +} + +static int rvpmu_find_num_ctrs(void) +{ + return rvpmu_sbi_find_num_ctrs(); + /* TODO: Counter delegation implementation */ +} + +static int rvpmu_get_ctrinfo(int nctr, unsigned long *mask) +{ + return rvpmu_sbi_get_ctrinfo(nctr, mask); + /* TODO: Counter delegation implementation */ +} + +static int rvpmu_event_map(struct perf_event *event, u64 *econfig) +{ + return rvpmu_sbi_event_map(event, econfig); + /* TODO: Counter delegation implementation */ +} + +static int rvpmu_ctr_get_idx(struct perf_event *event) +{ + return rvpmu_sbi_ctr_get_idx(event); + /* TODO: Counter delegation implementation */ +} + +static u64 rvpmu_ctr_read(struct perf_event *event) +{ + return rvpmu_sbi_ctr_read(event); + /* TODO: Counter delegation implementation */ +} + +static int rvpmu_starting_cpu(unsigned int cpu, struct hlist_node *node) { struct riscv_pmu *pmu =3D hlist_entry_safe(node, struct riscv_pmu, node); struct cpu_hw_events *cpu_hw_evt =3D this_cpu_ptr(pmu->hw_events); @@ -1160,7 +1204,7 @@ static int pmu_sbi_starting_cpu(unsigned int cpu, str= uct hlist_node *node) csr_write(CSR_SCOUNTEREN, 0x2); =20 /* Stop all the counters so that they can be enabled from perf */ - pmu_sbi_stop_all(pmu); + rvpmu_sbi_stop_all(pmu); =20 if (riscv_pmu_use_irq) { cpu_hw_evt->irq =3D riscv_pmu_irq; @@ -1174,7 +1218,7 @@ static int pmu_sbi_starting_cpu(unsigned int cpu, str= uct hlist_node *node) return 0; } =20 -static int pmu_sbi_dying_cpu(unsigned int cpu, struct hlist_node *node) +static int rvpmu_dying_cpu(unsigned int cpu, struct hlist_node *node) { if (riscv_pmu_use_irq) { disable_percpu_irq(riscv_pmu_irq); @@ -1189,7 +1233,7 @@ static int pmu_sbi_dying_cpu(unsigned int cpu, struct= hlist_node *node) return 0; } =20 -static int pmu_sbi_setup_irqs(struct riscv_pmu *pmu, struct platform_devic= e *pdev) +static int rvpmu_setup_irqs(struct riscv_pmu *pmu, struct platform_device = *pdev) { int ret; struct cpu_hw_events __percpu *hw_events =3D pmu->hw_events; @@ -1231,7 +1275,7 @@ static int pmu_sbi_setup_irqs(struct riscv_pmu *pmu, = struct platform_device *pde goto err; } =20 - ret =3D request_percpu_irq(riscv_pmu_irq, pmu_sbi_ovf_handler, "riscv-pmu= ", hw_events); + ret =3D request_percpu_irq(riscv_pmu_irq, rvpmu_ovf_handler, "riscv-pmu",= hw_events); if (ret) { pr_err("registering percpu irq failed [%d]\n", ret); irq_dispose_mapping(riscv_pmu_irq); @@ -1313,7 +1357,7 @@ static void riscv_pmu_destroy(struct riscv_pmu *pmu) cpuhp_state_remove_instance(CPUHP_AP_PERF_RISCV_STARTING, &pmu->node); } =20 -static void pmu_sbi_event_init(struct perf_event *event) +static void rvpmu_event_init(struct perf_event *event) { /* * The permissions are set at event_init so that we do not depend @@ -1327,7 +1371,7 @@ static void pmu_sbi_event_init(struct perf_event *eve= nt) event->hw.flags |=3D PERF_EVENT_FLAG_LEGACY; } =20 -static void pmu_sbi_event_mapped(struct perf_event *event, struct mm_struc= t *mm) +static void rvpmu_event_mapped(struct perf_event *event, struct mm_struct = *mm) { if (event->hw.flags & PERF_EVENT_FLAG_NO_USER_ACCESS) return; @@ -1355,14 +1399,14 @@ static void pmu_sbi_event_mapped(struct perf_event = *event, struct mm_struct *mm) * that it is possible to do so to avoid any race. * And we must notify all cpus here because threads that currently run * on other cpus will try to directly access the counter too without - * calling pmu_sbi_ctr_start. + * calling rvpmu_sbi_ctr_start. */ if (event->hw.flags & PERF_EVENT_FLAG_USER_ACCESS) on_each_cpu_mask(mm_cpumask(mm), - pmu_sbi_set_scounteren, (void *)event, 1); + rvpmu_set_scounteren, (void *)event, 1); } =20 -static void pmu_sbi_event_unmapped(struct perf_event *event, struct mm_str= uct *mm) +static void rvpmu_event_unmapped(struct perf_event *event, struct mm_struc= t *mm) { if (event->hw.flags & PERF_EVENT_FLAG_NO_USER_ACCESS) return; @@ -1384,7 +1428,7 @@ static void pmu_sbi_event_unmapped(struct perf_event = *event, struct mm_struct *m =20 if (event->hw.flags & PERF_EVENT_FLAG_USER_ACCESS) on_each_cpu_mask(mm_cpumask(mm), - pmu_sbi_reset_scounteren, (void *)event, 1); + rvpmu_reset_scounteren, (void *)event, 1); } =20 static void riscv_pmu_update_counter_access(void *info) @@ -1427,7 +1471,7 @@ static const struct ctl_table sbi_pmu_sysctl_table[] = =3D { }, }; =20 -static int pmu_sbi_device_probe(struct platform_device *pdev) +static int rvpmu_device_probe(struct platform_device *pdev) { struct riscv_pmu *pmu =3D NULL; int ret =3D -ENODEV; @@ -1439,7 +1483,7 @@ static int pmu_sbi_device_probe(struct platform_devic= e *pdev) if (!pmu) return -ENOMEM; =20 - num_counters =3D pmu_sbi_find_num_ctrs(); + num_counters =3D rvpmu_find_num_ctrs(); if (num_counters < 0) { pr_err("SBI PMU extension doesn't provide any counters\n"); goto out_free; @@ -1452,10 +1496,10 @@ static int pmu_sbi_device_probe(struct platform_dev= ice *pdev) } =20 /* cache all the information about counters now */ - if (pmu_sbi_get_ctrinfo(num_counters, &cmask)) + if (rvpmu_get_ctrinfo(num_counters, &cmask)) goto out_free; =20 - ret =3D pmu_sbi_setup_irqs(pmu, pdev); + ret =3D rvpmu_setup_irqs(pmu, pdev); if (ret < 0) { pr_info("Perf sampling/filtering is not supported as sscof extension is = not available\n"); pmu->pmu.capabilities |=3D PERF_PMU_CAP_NO_INTERRUPT; @@ -1466,17 +1510,17 @@ static int pmu_sbi_device_probe(struct platform_dev= ice *pdev) pmu->pmu.attr_groups =3D riscv_pmu_attr_groups; pmu->pmu.parent =3D &pdev->dev; pmu->cmask =3D cmask; - pmu->ctr_start =3D pmu_sbi_ctr_start; - pmu->ctr_stop =3D pmu_sbi_ctr_stop; - pmu->event_map =3D pmu_sbi_event_map; - pmu->ctr_get_idx =3D pmu_sbi_ctr_get_idx; - pmu->ctr_get_width =3D pmu_sbi_ctr_get_width; - pmu->ctr_clear_idx =3D pmu_sbi_ctr_clear_idx; - pmu->ctr_read =3D pmu_sbi_ctr_read; - pmu->event_init =3D pmu_sbi_event_init; - pmu->event_mapped =3D pmu_sbi_event_mapped; - pmu->event_unmapped =3D pmu_sbi_event_unmapped; - pmu->csr_index =3D pmu_sbi_csr_index; + pmu->ctr_start =3D rvpmu_ctr_start; + pmu->ctr_stop =3D rvpmu_ctr_stop; + pmu->event_map =3D rvpmu_event_map; + pmu->ctr_get_idx =3D rvpmu_ctr_get_idx; + pmu->ctr_get_width =3D rvpmu_ctr_get_width; + pmu->ctr_clear_idx =3D rvpmu_ctr_clear_idx; + pmu->ctr_read =3D rvpmu_ctr_read; + pmu->event_init =3D rvpmu_event_init; + pmu->event_mapped =3D rvpmu_event_mapped; + pmu->event_unmapped =3D rvpmu_event_unmapped; + pmu->csr_index =3D rvpmu_csr_index; =20 ret =3D riscv_pm_pmu_register(pmu); if (ret) @@ -1543,14 +1587,14 @@ static int pmu_sbi_device_probe(struct platform_dev= ice *pdev) return ret; } =20 -static struct platform_driver pmu_sbi_driver =3D { - .probe =3D pmu_sbi_device_probe, +static struct platform_driver rvpmu_driver =3D { + .probe =3D rvpmu_device_probe, .driver =3D { .name =3D RISCV_PMU_SBI_PDEV_NAME, }, }; =20 -static int __init pmu_sbi_devinit(void) +static int __init rvpmu_devinit(void) { int ret; struct platform_device *pdev; @@ -1568,20 +1612,20 @@ static int __init pmu_sbi_devinit(void) =20 ret =3D cpuhp_setup_state_multi(CPUHP_AP_PERF_RISCV_STARTING, "perf/riscv/pmu:starting", - pmu_sbi_starting_cpu, pmu_sbi_dying_cpu); + rvpmu_starting_cpu, rvpmu_dying_cpu); if (ret) { pr_err("CPU hotplug notifier could not be registered: %d\n", ret); return ret; } =20 - ret =3D platform_driver_register(&pmu_sbi_driver); + ret =3D platform_driver_register(&rvpmu_driver); if (ret) return ret; =20 pdev =3D platform_device_register_simple(RISCV_PMU_SBI_PDEV_NAME, -1, NUL= L, 0); if (IS_ERR(pdev)) { - platform_driver_unregister(&pmu_sbi_driver); + platform_driver_unregister(&rvpmu_driver); return PTR_ERR(pdev); } =20 @@ -1590,4 +1634,4 @@ static int __init pmu_sbi_devinit(void) =20 return ret; } -device_initcall(pmu_sbi_devinit) +device_initcall(rvpmu_devinit) --=20 2.53.0-Meta From nobody Thu Jul 16 17:05:11 2026 Received: from out-188.mta1.migadu.com (out-188.mta1.migadu.com [95.215.58.188]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 339D03EFD1F for ; Wed, 1 Jul 2026 08:48:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.188 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782895701; cv=none; b=QiKn74fsI3WwWEt0n1x7qDzQLbFbpf4vpR2zHxGaWIqepHFudjMeQI/RALxn0EYdVVRJJ9becT1/klMAOlctLdVoELhMT8UjkMX/gByZdcgR57YeRfzzg+R018e8NpyDkEqohsTVirkwHN3oj3wq9IcfXIlFEyxkvIgztR9eX24= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782895701; c=relaxed/simple; bh=CrawCWTeE/Q9CTbk39eP0maK8Ji7gPI1W3QcvTx6p2A=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=mXapWdtV18ou9UcJyQX6NvHNHV32x/NOFU9e60fu4gTbXv1iWTkIx9tjDA7Z8oNjvN4/TSAEP3RcR+lt9CvGl1sGqy+O4dMLw6v7y7/TUMJRK0kDRbPhPQyzpQ7b0NVuL1k10iFI+ZSYqH1IN9XdIZbTJb2CmpofYl8NxXPAgeE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=HAtekGoX; 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DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1782895697; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=EtqTOgDlLTl3/J04XYK88Q4DQK5pQiwKnJeyPQRo3/Q=; b=HAtekGoXjhlhMx5H1+9v5OlzPy9w6d4f/aM2YI783FKHavo9IdCabyZLfd4Fdnh6XrZu4j NPBlB34AZGc1mlpI2kIetNNnmiDgnXY3DKEKwJhXSpuZzvcx2QdYgzpcqfVQRAFd+k6pkv CCupG0gGsb34+h2zYqJpR5KNb9PuhNs= From: Atish Patra Date: Wed, 01 Jul 2026 01:47:00 -0700 Subject: [PATCH v8 12/22] RISC-V: perf: Modify the counter discovery mechanism Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260701-counter_delegation-v8-12-7909f863a645@meta.com> References: <20260701-counter_delegation-v8-0-7909f863a645@meta.com> In-Reply-To: <20260701-counter_delegation-v8-0-7909f863a645@meta.com> To: Jiri Olsa , Paul Walmsley , Mark Rutland , Rob Herring , Anup Patel , Namhyung Kim , Arnaldo Carvalho de Melo , Krzysztof Kozlowski , Atish Patra , Ian Rogers , Will Deacon , James Clark Cc: linux-arm-kernel@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-perf-users@vger.kernel.org, Conor Dooley X-Migadu-Flow: FLOW_OUT From: Atish Patra If both counter delegation and SBI PMU is present, the counter delegation will be used for hardware pmu counters while the SBI PMU will be used for firmware counters. Thus, the driver has to probe the counters info via SBI PMU to distinguish the firmware counters. The hybrid scheme also requires improvements of the informational logging messages to indicate the user about underlying interface used for each use case. Signed-off-by: Atish Patra --- drivers/perf/riscv_pmu_sbi.c | 139 ++++++++++++++++++++++++++++++++-------= ---- 1 file changed, 104 insertions(+), 35 deletions(-) diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index 74d934238821..c20f1e33c65d 100644 --- a/drivers/perf/riscv_pmu_sbi.c +++ b/drivers/perf/riscv_pmu_sbi.c @@ -67,6 +67,20 @@ static bool sbi_v3_available; static DEFINE_STATIC_KEY_FALSE(sbi_pmu_snapshot_available); #define sbi_pmu_snapshot_available() \ static_branch_unlikely(&sbi_pmu_snapshot_available) +static DEFINE_STATIC_KEY_FALSE(riscv_pmu_sbi_available); +static DEFINE_STATIC_KEY_FALSE(riscv_pmu_cdeleg_available); + +/* Avoid unnecessary code patching in the one time booting path*/ +#define riscv_pmu_cdeleg_available_boot() \ + static_key_enabled(&riscv_pmu_cdeleg_available) +#define riscv_pmu_sbi_available_boot() \ + static_key_enabled(&riscv_pmu_sbi_available) + +/* Perform a runtime code patching with static key */ +#define riscv_pmu_cdeleg_available() \ + static_branch_unlikely(&riscv_pmu_cdeleg_available) +#define riscv_pmu_sbi_available() \ + static_branch_likely(&riscv_pmu_sbi_available) =20 static struct attribute *riscv_arch_formats_attr[] =3D { &format_attr_event.attr, @@ -89,7 +103,8 @@ static int sysctl_perf_user_access __read_mostly =3D SYS= CTL_USER_ACCESS; =20 /* * This structure is SBI specific but counter delegation also require coun= ter - * width, csr mapping. Reuse it for now. + * width, csr mapping. Reuse it for now we can have firmware counters for + * platfroms with counter delegation support. * RISC-V doesn't have heterogeneous harts yet. This need to be part of * per_cpu in case of harts with different pmu counters */ @@ -101,6 +116,8 @@ static unsigned int riscv_pmu_irq; =20 /* Cache the available counters in a bitmask */ static unsigned long cmask; +/* Cache the available firmware counters in another bitmask */ +static unsigned long firmware_cmask; =20 static int sbi_pmu_event_find_cache(u64 config); struct sbi_pmu_event_data { @@ -868,34 +885,38 @@ static int rvpmu_sbi_find_num_ctrs(void) return sbi_err_map_linux_errno(ret.error); } =20 -static int rvpmu_sbi_get_ctrinfo(int nctr, unsigned long *mask) +static u32 rvpmu_deleg_find_ctrs(void) +{ + /* TODO */ + return 0; +} + +static int rvpmu_sbi_get_ctrinfo(u32 nsbi_ctr, u32 *num_fw_ctr, u32 *num_h= w_ctr) { struct sbiret ret; - int i, num_hw_ctr =3D 0, num_fw_ctr =3D 0; + int i; union sbi_pmu_ctr_info cinfo; =20 - pmu_ctr_list =3D kzalloc_objs(*pmu_ctr_list, nctr); - if (!pmu_ctr_list) - return -ENOMEM; - - for (i =3D 0; i < nctr; i++) { + for (i =3D 0; i < nsbi_ctr; i++) { ret =3D sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_GET_INFO, i, 0, 0, 0,= 0, 0); if (ret.error) /* The logical counter ids are not expected to be contiguous */ continue; =20 - *mask |=3D BIT(i); - cinfo.value =3D ret.value; - if (cinfo.type =3D=3D SBI_PMU_CTR_TYPE_FW) - num_fw_ctr++; - else - num_hw_ctr++; - pmu_ctr_list[i].value =3D cinfo.value; + if (cinfo.type =3D=3D SBI_PMU_CTR_TYPE_FW) { + /* Track firmware counters in a different mask */ + firmware_cmask |=3D BIT(i); + pmu_ctr_list[i].value =3D cinfo.value; + *num_fw_ctr =3D *num_fw_ctr + 1; + } else if (cinfo.type =3D=3D SBI_PMU_CTR_TYPE_HW && + !riscv_pmu_cdeleg_available_boot()) { + *num_hw_ctr =3D *num_hw_ctr + 1; + cmask |=3D BIT(i); + pmu_ctr_list[i].value =3D cinfo.value; + } } =20 - pr_info("%d firmware and %d hardware counters\n", num_fw_ctr, num_hw_ctr); - return 0; } =20 @@ -906,7 +927,7 @@ static inline void rvpmu_sbi_stop_all(struct riscv_pmu = *pmu) * which may include counters that are not enabled yet. */ sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_STOP, - 0, pmu->cmask, SBI_PMU_STOP_FLAG_RESET, 0, 0, 0); + 0, pmu->cmask | firmware_cmask, SBI_PMU_STOP_FLAG_RESET, 0, 0, 0); } =20 static inline void rvpmu_sbi_stop_hw_ctrs(struct riscv_pmu *pmu) @@ -1159,16 +1180,48 @@ static void rvpmu_ctr_stop(struct perf_event *event= , unsigned long flag) /* TODO: Counter delegation implementation */ } =20 -static int rvpmu_find_num_ctrs(void) +static int rvpmu_find_ctrs(void) { - return rvpmu_sbi_find_num_ctrs(); - /* TODO: Counter delegation implementation */ -} + int num_sbi_counters =3D 0; + u32 num_deleg_counters =3D 0; + u32 num_hw_ctr =3D 0, num_fw_ctr =3D 0, num_ctr =3D 0; + /* + * We don't know how many firmware counters are available. Just allocate + * for maximum counters the driver can support. The default is 64 anyways. + */ + pmu_ctr_list =3D kcalloc(RISCV_MAX_COUNTERS, sizeof(*pmu_ctr_list), + GFP_KERNEL); + if (!pmu_ctr_list) + return -ENOMEM; =20 -static int rvpmu_get_ctrinfo(int nctr, unsigned long *mask) -{ - return rvpmu_sbi_get_ctrinfo(nctr, mask); - /* TODO: Counter delegation implementation */ + if (riscv_pmu_cdeleg_available_boot()) + num_deleg_counters =3D rvpmu_deleg_find_ctrs(); + + /* This is required for firmware counters even if the above is true */ + if (riscv_pmu_sbi_available_boot()) { + num_sbi_counters =3D rvpmu_sbi_find_num_ctrs(); + if (num_sbi_counters < 0) { + kfree(pmu_ctr_list); + pmu_ctr_list =3D NULL; + return num_sbi_counters; + } + if (num_sbi_counters > RISCV_MAX_COUNTERS) + num_sbi_counters =3D RISCV_MAX_COUNTERS; + } + + /* cache all the information about counters now */ + if (riscv_pmu_sbi_available_boot()) + rvpmu_sbi_get_ctrinfo(num_sbi_counters, &num_fw_ctr, &num_hw_ctr); + + if (riscv_pmu_cdeleg_available_boot()) { + pr_info("%u firmware and %u hardware counters\n", num_fw_ctr, num_deleg_= counters); + num_ctr =3D num_fw_ctr + num_deleg_counters; + } else { + pr_info("%u firmware and %u hardware counters\n", num_fw_ctr, num_hw_ctr= ); + num_ctr =3D num_sbi_counters; + } + + return num_ctr; } =20 static int rvpmu_event_map(struct perf_event *event, u64 *econfig) @@ -1478,12 +1531,21 @@ static int rvpmu_device_probe(struct platform_devic= e *pdev) int num_counters; bool irq_requested =3D false; =20 - pr_info("SBI PMU extension is available\n"); + if (riscv_pmu_cdeleg_available_boot()) { + pr_info("hpmcounters will use the counter delegation ISA extension\n"); + if (riscv_pmu_sbi_available_boot()) + pr_info("Firmware counters will use SBI PMU extension\n"); + else + pr_info("Firmware counters will not be available as SBI PMU extension i= s not present\n"); + } else if (riscv_pmu_sbi_available_boot()) { + pr_info("Both hpmcounters and firmware counters will use SBI PMU extensi= on\n"); + } + pmu =3D riscv_pmu_alloc(); if (!pmu) return -ENOMEM; =20 - num_counters =3D rvpmu_find_num_ctrs(); + num_counters =3D rvpmu_find_ctrs(); if (num_counters < 0) { pr_err("SBI PMU extension doesn't provide any counters\n"); goto out_free; @@ -1495,9 +1557,6 @@ static int rvpmu_device_probe(struct platform_device = *pdev) pr_info("SBI returned more than maximum number of counters. Limiting the= number of counters to %d\n", num_counters); } =20 - /* cache all the information about counters now */ - if (rvpmu_get_ctrinfo(num_counters, &cmask)) - goto out_free; =20 ret =3D rvpmu_setup_irqs(pmu, pdev); if (ret < 0) { @@ -1599,13 +1658,23 @@ static int __init rvpmu_devinit(void) int ret; struct platform_device *pdev; =20 - if (sbi_spec_version < sbi_mk_version(0, 3) || - !sbi_probe_extension(SBI_EXT_PMU)) { - return 0; - } + if (sbi_spec_version >=3D sbi_mk_version(0, 3) && + sbi_probe_extension(SBI_EXT_PMU)) + static_branch_enable(&riscv_pmu_sbi_available); =20 if (sbi_spec_version >=3D sbi_mk_version(2, 0)) sbi_v2_available =3D true; + /* + * We need all three extensions to be present to access the counters + * in S-mode via Supervisor Counter delegation. + */ + if (riscv_isa_extension_available(NULL, SSCCFG) && + riscv_isa_extension_available(NULL, SMCDELEG) && + riscv_isa_extension_available(NULL, SSCSRIND)) + static_branch_enable(&riscv_pmu_cdeleg_available); + + if (!(riscv_pmu_sbi_available_boot() || riscv_pmu_cdeleg_available_boot()= )) + return 0; =20 if (sbi_spec_version >=3D sbi_mk_version(3, 0)) sbi_v3_available =3D true; --=20 2.53.0-Meta From nobody Thu Jul 16 17:05:11 2026 Received: from out-170.mta1.migadu.com (out-170.mta1.migadu.com [95.215.58.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 724323EFD24 for ; Wed, 1 Jul 2026 08:48:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.170 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782895707; cv=none; b=NaF19ZZQ36ePvEFaZOxSC/8Di7zTvjpPtIIi5mhK1DYdTPjUeJldoZTVz0+QdqA7vE04qWUozaF9LjjEBGExVtg7EbqlMYFHlqqwkM8PPxtAz07PcCg238mYeWZQ2TkV1Q6LovrOHG8adL5p3DoQU2ETAMmi1rrkfQEZTDAuBxc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782895707; c=relaxed/simple; bh=JLLXVjVqnLz32wfza32XxNG+wJtE/gFupupKjSwZ/Eo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Z90pGwBTyxtrPYYju7ns0jANbxZ05N0++8KDPdY1BN0EB6VRgC+UInggLyxzbH+yWCQKeVSfNu8aPhy8VrfWdnc7qk8M8r4wFWT/1rnNyI4YtOaTeH4a9XbpX5LjS6PeD2sVcCiaOn+2aa+MLylq2vg2ODFO+js310j+zbuqbQw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=jT4yqzK8; arc=none smtp.client-ip=95.215.58.170 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="jT4yqzK8" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1782895703; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=+BZzbITC0E4sK8QIC43hKZGtTowm2ni8ynKK2Oo4rf0=; b=jT4yqzK8h5SQM2MrxoYQcWfzv7NkZ8DTVFazZyRncW6Dhye6jut6jLOPubxu/Vp0ncTSZ7 8J/8GHrnabvVZ1665K57gB+8QOFc5rLjVgX06yoigEZq7Act35Y27NDMZRNEag7uLyrDGG fR1b5GFTCxr/hU1DAajON0ngtqvOMQY= From: Atish Patra Date: Wed, 01 Jul 2026 01:47:01 -0700 Subject: [PATCH v8 13/22] RISC-V: perf: Add a mechanism to defined legacy event encoding Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260701-counter_delegation-v8-13-7909f863a645@meta.com> References: <20260701-counter_delegation-v8-0-7909f863a645@meta.com> In-Reply-To: <20260701-counter_delegation-v8-0-7909f863a645@meta.com> To: Jiri Olsa , Paul Walmsley , Mark Rutland , Rob Herring , Anup Patel , Namhyung Kim , Arnaldo Carvalho de Melo , Krzysztof Kozlowski , Atish Patra , Ian Rogers , Will Deacon , James Clark Cc: linux-arm-kernel@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-perf-users@vger.kernel.org, Conor Dooley X-Migadu-Flow: FLOW_OUT From: Atish Patra RISC-V ISA doesn't define any standard event encodings or specify any event to counter mapping. Thus, event encoding information and corresponding counter mapping fot those events needs to be provided in the driver for each vendor. Add a framework to support that. The individual platform events will be added later. Signed-off-by: Atish Patra --- drivers/perf/riscv_pmu_sbi.c | 70 ++++++++++++++++++++++++++++++++++++++++= +++- 1 file changed, 69 insertions(+), 1 deletion(-) diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index c20f1e33c65d..2568c6808f5d 100644 --- a/drivers/perf/riscv_pmu_sbi.c +++ b/drivers/perf/riscv_pmu_sbi.c @@ -10,6 +10,7 @@ =20 #define pr_fmt(fmt) "riscv-pmu-sbi: " fmt =20 +#include #include #include #include @@ -379,6 +380,71 @@ static int pmu_sbi_check_event_info(void) return result; } =20 +/* + * Vendor specific PMU events. + */ +struct riscv_pmu_event { + u64 event_id; + u32 counter_mask; +}; + +#define HW_OP_UNSUPPORTED U64_MAX +#define CACHE_OP_UNSUPPORTED U64_MAX + +#define PERF_MAP_ALL_UNSUPPORTED \ + [0 ... PERF_COUNT_HW_MAX - 1] =3D {HW_OP_UNSUPPORTED, 0x0} + +#define PERF_CACHE_MAP_ALL_UNSUPPORTED \ +[0 ... PERF_COUNT_HW_CACHE_MAX - 1] =3D { \ + [0 ... PERF_COUNT_HW_CACHE_OP_MAX - 1] =3D { \ + [0 ... PERF_COUNT_HW_CACHE_RESULT_MAX - 1] =3D { \ + CACHE_OP_UNSUPPORTED, 0x0 \ + }, \ + }, \ +} + +struct riscv_vendor_pmu_events { + unsigned long vendorid; + unsigned long archid; + unsigned long implid; + const struct riscv_pmu_event *hw_event_map; + const struct riscv_pmu_event (*cache_event_map)[PERF_COUNT_HW_CACHE_OP_MA= X] + [PERF_COUNT_HW_CACHE_RESULT_MAX]; +}; + +#define RISCV_VENDOR_PMU_EVENTS(_vendorid, _archid, _implid, _hw_event_map= , _cache_event_map) \ + { .vendorid =3D _vendorid, .archid =3D _archid, .implid =3D _implid, \ + .hw_event_map =3D _hw_event_map, .cache_event_map =3D _cache_event_map = }, + +static struct riscv_vendor_pmu_events pmu_vendor_events_table[] =3D { +}; + +static const struct riscv_pmu_event *current_pmu_hw_event_map; +static const struct riscv_pmu_event (*current_pmu_cache_event_map)[PERF_CO= UNT_HW_CACHE_OP_MAX] + [PERF_COUNT_HW_CACHE_RESULT_MAX]; + +static void __init rvpmu_vendor_register_events(void) +{ + int cpu =3D raw_smp_processor_id(); + unsigned long vendor_id =3D riscv_cached_mvendorid(cpu); + unsigned long impl_id =3D riscv_cached_mimpid(cpu); + unsigned long arch_id =3D riscv_cached_marchid(cpu); + + for (int i =3D 0; i < ARRAY_SIZE(pmu_vendor_events_table); i++) { + if (pmu_vendor_events_table[i].vendorid =3D=3D vendor_id && + pmu_vendor_events_table[i].implid =3D=3D impl_id && + pmu_vendor_events_table[i].archid =3D=3D arch_id) { + current_pmu_hw_event_map =3D pmu_vendor_events_table[i].hw_event_map; + current_pmu_cache_event_map =3D pmu_vendor_events_table[i].cache_event_= map; + break; + } + } + + if (!current_pmu_hw_event_map || !current_pmu_cache_event_map) { + pr_info("No default PMU events found\n"); + } +} + static void rvpmu_sbi_check_event(struct sbi_pmu_event_data *edata) { struct sbiret ret; @@ -1670,8 +1736,10 @@ static int __init rvpmu_devinit(void) */ if (riscv_isa_extension_available(NULL, SSCCFG) && riscv_isa_extension_available(NULL, SMCDELEG) && - riscv_isa_extension_available(NULL, SSCSRIND)) + riscv_isa_extension_available(NULL, SSCSRIND)) { static_branch_enable(&riscv_pmu_cdeleg_available); + rvpmu_vendor_register_events(); + } =20 if (!(riscv_pmu_sbi_available_boot() || riscv_pmu_cdeleg_available_boot()= )) return 0; --=20 2.53.0-Meta From nobody Thu Jul 16 17:05:11 2026 Received: from out-189.mta0.migadu.com (out-189.mta0.migadu.com [91.218.175.189]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2293B3F44CA for ; Wed, 1 Jul 2026 08:48:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.218.175.189 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782895711; cv=none; b=tSpn96BAKBPwFMPOi2UgR34PbPrH2l4BpE08aDuvyLi0So8LT31fZujkJa6pKBwweoBo/stbTC+tzhNxVm93S70N0OgcFxX6pv5mZH6wl1yz12kOKPsz2qp9TI8Jbg1CKV5Dd/TSTumw8BGdWAa53uhpsNYn7rQbEBt5QLKcssY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782895711; c=relaxed/simple; bh=MHZlJwiSWbIfMY6Ikh6BV7oRgaUajc+I2aul9JNSP6M=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=hz74NtXsLwYPt7IKtytI84DGhWsZ2Ni7h1g8gczQyJTM243wEQH7kVtCztDM/365Sp4s0XrHm+cpBAo/QwNs/XH6A9zJpWixRXeumqnBpkog8eDZup1nsGmE/uHAFL6ThPs9mNw7a3OrLE+WpBf2JwmWlCrVPpiAkFdnWBRGshg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=IU8dtTnz; arc=none smtp.client-ip=91.218.175.189 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="IU8dtTnz" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1782895707; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=KXzWCEYEoTgf+FVkLTZAe428tSj2IYGVlGaowwoFR8I=; b=IU8dtTnz46PluzqMUz3VGJ42B/GUPPFGI6ZIdVoApayuMMT6lSt0i0KAWKqrXgFtcTle8l RkkTA/NRP10WvnQtEyzlew9M/kPhH5T6/XVtcrNAUUxzzmyzLu0CWRrQFhxFz1xdqGGW7g imw4plUz3Uz+sGaH3cQ7l1s9oI/9f14= From: Atish Patra Date: Wed, 01 Jul 2026 01:47:02 -0700 Subject: [PATCH v8 14/22] RISC-V: perf: Implement supervisor counter delegation support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260701-counter_delegation-v8-14-7909f863a645@meta.com> References: <20260701-counter_delegation-v8-0-7909f863a645@meta.com> In-Reply-To: <20260701-counter_delegation-v8-0-7909f863a645@meta.com> To: Jiri Olsa , Paul Walmsley , Mark Rutland , Rob Herring , Anup Patel , Namhyung Kim , Arnaldo Carvalho de Melo , Krzysztof Kozlowski , Atish Patra , Ian Rogers , Will Deacon , James Clark Cc: linux-arm-kernel@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-perf-users@vger.kernel.org, Conor Dooley X-Migadu-Flow: FLOW_OUT From: Atish Patra There are few new RISC-V ISA exensions (ssccfg, sscsrind, smcntrpmf) which allows the hpmcounter/hpmevents to be programmed directly from S-mode. The implementation detects the ISA extension at runtime and uses them if available instead of SBI PMU extension. SBI PMU extension will still be used for firmware counters if the user requests it. The current linux driver relies on event encoding defined by SBI PMU specification for standard perf events. However, there are no standard event encoding available in the ISA. In the future, we may want to decouple the counter delegation and SBI PMU completely. In that case, counter delegation supported platforms must rely on the event encoding defined in the perf json file or in the pmu driver. For firmware events, it will continue to use the SBI PMU encoding as one can not support firmware event without SBI PMU. Signed-off-by: Atish Patra --- arch/riscv/include/asm/csr.h | 1 + drivers/perf/riscv_pmu_sbi.c | 578 +++++++++++++++++++++++++++++++++----= ---- include/linux/perf/riscv_pmu.h | 3 + 3 files changed, 478 insertions(+), 104 deletions(-) diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index a3b24b88e401..cd22b5168689 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -258,6 +258,7 @@ #endif =20 #define SISELECT_SSCCFG_BASE 0x40 +#define HPMEVENT_MASK GENMASK_ULL(63, 56) =20 /* mseccfg bits */ #define MSECCFG_PMM ENVCFG_PMM diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index 2568c6808f5d..7995da4a98a1 100644 --- a/drivers/perf/riscv_pmu_sbi.c +++ b/drivers/perf/riscv_pmu_sbi.c @@ -28,6 +28,8 @@ #include #include #include +#include +#include =20 #define ALT_SBI_PMU_OVERFLOW(__ovl) \ asm volatile(ALTERNATIVE_2( \ @@ -60,7 +62,20 @@ asm volatile(ALTERNATIVE( \ #define PERF_EVENT_FLAG_USER_ACCESS BIT(SYSCTL_USER_ACCESS) #define PERF_EVENT_FLAG_LEGACY BIT(SYSCTL_LEGACY) =20 -PMU_FORMAT_ATTR(event, "config:0-55"); +#define RVPMU_SBI_PMU_FORMAT_ATTR "config:0-47" +#define RVPMU_CDELEG_PMU_FORMAT_ATTR "config:0-55" + +static ssize_t __maybe_unused rvpmu_format_show(struct device *dev, struct= device_attribute *attr, + char *buf); + +#define RVPMU_ATTR_ENTRY(_name, _func, _config) ( \ + &((struct dev_ext_attribute[]) { \ + { __ATTR(_name, 0444, _func, NULL), (void *)_config } \ + })[0].attr.attr) + +#define RVPMU_FORMAT_ATTR_ENTRY(_name, _config) \ + RVPMU_ATTR_ENTRY(_name, rvpmu_format_show, (char *)_config) + PMU_FORMAT_ATTR(firmware, "config:62-63"); =20 static bool sbi_v2_available; @@ -68,7 +83,11 @@ static bool sbi_v3_available; static DEFINE_STATIC_KEY_FALSE(sbi_pmu_snapshot_available); #define sbi_pmu_snapshot_available() \ static_branch_unlikely(&sbi_pmu_snapshot_available) + static DEFINE_STATIC_KEY_FALSE(riscv_pmu_sbi_available); +#define riscv_pmu_sbi_available() \ + static_branch_likely(&riscv_pmu_sbi_available) + static DEFINE_STATIC_KEY_FALSE(riscv_pmu_cdeleg_available); =20 /* Avoid unnecessary code patching in the one time booting path*/ @@ -83,19 +102,35 @@ static DEFINE_STATIC_KEY_FALSE(riscv_pmu_cdeleg_availa= ble); #define riscv_pmu_sbi_available() \ static_branch_likely(&riscv_pmu_sbi_available) =20 -static struct attribute *riscv_arch_formats_attr[] =3D { - &format_attr_event.attr, +static struct attribute *riscv_sbi_pmu_formats_attr[] =3D { + RVPMU_FORMAT_ATTR_ENTRY(event, RVPMU_SBI_PMU_FORMAT_ATTR), &format_attr_firmware.attr, NULL, }; =20 -static struct attribute_group riscv_pmu_format_group =3D { +static struct attribute_group riscv_sbi_pmu_format_group =3D { .name =3D "format", - .attrs =3D riscv_arch_formats_attr, + .attrs =3D riscv_sbi_pmu_formats_attr, }; =20 -static const struct attribute_group *riscv_pmu_attr_groups[] =3D { - &riscv_pmu_format_group, +static const struct attribute_group *riscv_sbi_pmu_attr_groups[] =3D { + &riscv_sbi_pmu_format_group, + NULL, +}; + +static struct attribute *riscv_cdeleg_pmu_formats_attr[] =3D { + RVPMU_FORMAT_ATTR_ENTRY(event, RVPMU_CDELEG_PMU_FORMAT_ATTR), + &format_attr_firmware.attr, + NULL, +}; + +static struct attribute_group riscv_cdeleg_pmu_format_group =3D { + .name =3D "format", + .attrs =3D riscv_cdeleg_pmu_formats_attr, +}; + +static const struct attribute_group *riscv_cdeleg_pmu_attr_groups[] =3D { + &riscv_cdeleg_pmu_format_group, NULL, }; =20 @@ -482,6 +517,14 @@ static void rvpmu_sbi_check_std_events(struct work_str= uct *work) =20 static DECLARE_WORK(check_std_events_work, rvpmu_sbi_check_std_events); =20 +static ssize_t rvpmu_format_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct dev_ext_attribute *eattr =3D container_of(attr, + struct dev_ext_attribute, attr); + return sysfs_emit(buf, "%s\n", (char *)eattr->var); +} + static int rvpmu_ctr_get_width(int idx) { return pmu_ctr_list[idx].width; @@ -599,6 +642,38 @@ static uint8_t rvpmu_csr_index(struct perf_event *even= t) return pmu_ctr_list[event->hw.idx].csr - CSR_CYCLE; } =20 +static uint64_t get_deleg_priv_filter_bits(struct perf_event *event) +{ + u64 priv_filter_bits =3D 0; + bool guest_events =3D false; + + if (event->attr.config1 & RISCV_PMU_CONFIG1_GUEST_EVENTS) + guest_events =3D true; + if (event->attr.exclude_kernel) + priv_filter_bits |=3D guest_events ? HPMEVENT_VSINH : HPMEVENT_SINH; + if (event->attr.exclude_user) + priv_filter_bits |=3D guest_events ? HPMEVENT_VUINH : HPMEVENT_UINH; + if (guest_events && event->attr.exclude_hv) + priv_filter_bits |=3D HPMEVENT_SINH; + if (event->attr.exclude_host) + priv_filter_bits |=3D HPMEVENT_UINH | HPMEVENT_SINH; + if (event->attr.exclude_guest) + priv_filter_bits |=3D HPMEVENT_VSINH | HPMEVENT_VUINH; + + return priv_filter_bits; +} + +static bool pmu_sbi_is_fw_event(struct perf_event *event) +{ + u32 type =3D event->attr.type; + u64 config =3D event->attr.config; + + if (type =3D=3D PERF_TYPE_RAW && ((config >> 63) =3D=3D 1)) + return true; + else + return false; +} + static unsigned long rvpmu_sbi_get_filter_flags(struct perf_event *event) { unsigned long cflags =3D 0; @@ -627,7 +702,8 @@ static int rvpmu_sbi_ctr_get_idx(struct perf_event *eve= nt) struct cpu_hw_events *cpuc =3D this_cpu_ptr(rvpmu->hw_events); struct sbiret ret; int idx; - uint64_t cbase =3D 0, cmask =3D rvpmu->cmask; + u64 cbase =3D 0; + unsigned long ctr_mask =3D rvpmu->cmask; unsigned long cflags =3D 0; =20 cflags =3D rvpmu_sbi_get_filter_flags(event); @@ -640,21 +716,23 @@ static int rvpmu_sbi_ctr_get_idx(struct perf_event *e= vent) if ((hwc->flags & PERF_EVENT_FLAG_LEGACY) && (event->attr.type =3D=3D PER= F_TYPE_HARDWARE)) { if (event->attr.config =3D=3D PERF_COUNT_HW_CPU_CYCLES) { cflags |=3D SBI_PMU_CFG_FLAG_SKIP_MATCH; - cmask =3D 1; + ctr_mask =3D 1; } else if (event->attr.config =3D=3D PERF_COUNT_HW_INSTRUCTIONS) { cflags |=3D SBI_PMU_CFG_FLAG_SKIP_MATCH; - cmask =3D BIT(CSR_INSTRET - CSR_CYCLE); + ctr_mask =3D BIT(CSR_INSTRET - CSR_CYCLE); } + } else if (pmu_sbi_is_fw_event(event)) { + ctr_mask =3D firmware_cmask; } =20 /* retrieve the available counter index */ #if defined(CONFIG_32BIT) ret =3D sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_CFG_MATCH, cbase, - cmask, cflags, hwc->event_base, hwc->config, + ctr_mask, cflags, hwc->event_base, hwc->config, hwc->config >> 32); #else ret =3D sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_CFG_MATCH, cbase, - cmask, cflags, hwc->event_base, hwc->config, 0); + ctr_mask, cflags, hwc->event_base, hwc->config, 0); #endif if (ret.error) { pr_debug("Not able to find a counter for event %lx config %llx\n", @@ -663,7 +741,7 @@ static int rvpmu_sbi_ctr_get_idx(struct perf_event *eve= nt) } =20 idx =3D ret.value; - if (!test_bit(idx, &rvpmu->cmask) || !pmu_ctr_list[idx].value) + if (!test_bit(idx, &ctr_mask) || !pmu_ctr_list[idx].value) return -ENOENT; =20 /* Additional sanity check for the counter id */ @@ -713,29 +791,98 @@ static int sbi_pmu_event_find_cache(u64 config) return ret; } =20 -static bool pmu_sbi_is_fw_event(struct perf_event *event) +static int rvpmu_sbi_event_map(struct perf_event *event, u64 *econfig) { u32 type =3D event->attr.type; u64 config =3D event->attr.config; =20 - if ((type =3D=3D PERF_TYPE_RAW) && ((config >> 63) =3D=3D 1)) - return true; - else - return false; + /* + * Ensure we are finished checking standard hardware events for + * validity before allowing userspace to configure any events. + */ + flush_work(&check_std_events_work); + + return riscv_pmu_get_event_info(type, config, econfig); } =20 -static int rvpmu_sbi_event_map(struct perf_event *event, u64 *econfig) +static int cdeleg_pmu_event_find_cache(u64 config, u64 *eventid, uint32_t = *counter_mask) +{ + unsigned int cache_type, cache_op, cache_result; + + if (!current_pmu_cache_event_map) + return -ENOENT; + + cache_type =3D (config >> 0) & 0xff; + if (cache_type >=3D PERF_COUNT_HW_CACHE_MAX) + return -EINVAL; + + cache_op =3D (config >> 8) & 0xff; + if (cache_op >=3D PERF_COUNT_HW_CACHE_OP_MAX) + return -EINVAL; + + cache_result =3D (config >> 16) & 0xff; + if (cache_result >=3D PERF_COUNT_HW_CACHE_RESULT_MAX) + return -EINVAL; + + if (eventid) + *eventid =3D current_pmu_cache_event_map[cache_type][cache_op] + [cache_result].event_id; + if (counter_mask) + *counter_mask =3D current_pmu_cache_event_map[cache_type][cache_op] + [cache_result].counter_mask; + + return 0; +} + +static int rvpmu_cdeleg_event_map(struct perf_event *event, u64 *econfig) { u32 type =3D event->attr.type; u64 config =3D event->attr.config; + int ret =3D 0; =20 /* - * Ensure we are finished checking standard hardware events for - * validity before allowing userspace to configure any events. + * There are two ways standard perf events can be mapped to platform spec= ific + * encoding. + * 1. The vendor may specify the encodings in the driver. + * 2. The Perf tool for RISC-V may remap the standard perf event to platf= orm + * specific encoding. + * + * As RISC-V ISA doesn't define any standard event encoding. Thus, perf t= ool allows + * vendor to define it via json file. The encoding defined in the json wi= ll override + * the perf legacy encoding. However, some user may want to run performan= ce + * monitoring without perf tool as well. That's why, vendors may specify = the event + * encoding in the driver as well if they want to support that use case t= oo. + * If an encoding is defined in the json, it will be encoded as a raw eve= nt. */ - flush_work(&check_std_events_work); =20 - return riscv_pmu_get_event_info(type, config, econfig); + switch (type) { + case PERF_TYPE_HARDWARE: + if (config >=3D PERF_COUNT_HW_MAX) + return -EINVAL; + if (!current_pmu_hw_event_map) + return -ENOENT; + + *econfig =3D current_pmu_hw_event_map[config].event_id; + if (*econfig =3D=3D HW_OP_UNSUPPORTED) + ret =3D -ENOENT; + break; + case PERF_TYPE_HW_CACHE: + ret =3D cdeleg_pmu_event_find_cache(config, econfig, NULL); + if (ret) + break; + if (*econfig =3D=3D CACHE_OP_UNSUPPORTED) + ret =3D -ENOENT; + break; + case PERF_TYPE_RAW: + *econfig =3D config & RISCV_PMU_DELEG_RAW_EVENT_MASK; + break; + default: + ret =3D -ENOENT; + break; + } + + /* event_base is not used for counter delegation */ + return ret; } =20 static void pmu_sbi_snapshot_free(struct riscv_pmu *pmu) @@ -821,7 +968,7 @@ static int pmu_sbi_snapshot_setup(struct riscv_pmu *pmu= , int cpu) return 0; } =20 -static u64 rvpmu_sbi_ctr_read(struct perf_event *event) +static u64 rvpmu_ctr_read(struct perf_event *event) { struct hw_perf_event *hwc =3D &event->hw; int idx =3D hwc->idx; @@ -898,10 +1045,6 @@ static void rvpmu_sbi_ctr_start(struct perf_event *ev= ent, u64 ival) if (ret.error && (ret.error !=3D SBI_ERR_ALREADY_STARTED)) pr_err("Starting counter idx %d failed with error %d\n", hwc->idx, sbi_err_map_linux_errno(ret.error)); - - if ((hwc->flags & PERF_EVENT_FLAG_USER_ACCESS) && - (hwc->flags & PERF_EVENT_FLAG_USER_READ_CNT)) - rvpmu_set_scounteren((void *)event); } =20 static void rvpmu_sbi_ctr_stop(struct perf_event *event, unsigned long fla= g) @@ -912,10 +1055,6 @@ static void rvpmu_sbi_ctr_stop(struct perf_event *eve= nt, unsigned long flag) struct cpu_hw_events *cpu_hw_evt =3D this_cpu_ptr(pmu->hw_events); struct riscv_pmu_snapshot_data *sdata =3D cpu_hw_evt->snapshot_addr; =20 - if ((hwc->flags & PERF_EVENT_FLAG_USER_ACCESS) && - (hwc->flags & PERF_EVENT_FLAG_USER_READ_CNT)) - rvpmu_reset_scounteren((void *)event); - if (sbi_pmu_snapshot_available()) flag |=3D SBI_PMU_STOP_FLAG_TAKE_SNAPSHOT; =20 @@ -951,12 +1090,6 @@ static int rvpmu_sbi_find_num_ctrs(void) return sbi_err_map_linux_errno(ret.error); } =20 -static u32 rvpmu_deleg_find_ctrs(void) -{ - /* TODO */ - return 0; -} - static int rvpmu_sbi_get_ctrinfo(u32 nsbi_ctr, u32 *num_fw_ctr, u32 *num_h= w_ctr) { struct sbiret ret; @@ -1034,55 +1167,75 @@ static inline void rvpmu_sbi_stop_hw_ctrs(struct ri= scv_pmu *pmu) } } =20 -/* - * This function starts all the used counters in two step approach. - * Any counter that did not overflow can be start in a single step - * while the overflowed counters need to be started with updated initializ= ation - * value. - */ -static inline void rvpmu_sbi_start_ovf_ctrs_sbi(struct cpu_hw_events *cpu_= hw_evt, - u64 ctr_ovf_mask) +static void rvpmu_deleg_ctr_start_mask(unsigned long mask) { - int idx =3D 0, i; - struct perf_event *event; - unsigned long flag =3D SBI_PMU_START_FLAG_SET_INIT_VALUE; - unsigned long ctr_start_mask =3D 0; - uint64_t max_period; - struct hw_perf_event *hwc; - u64 init_val =3D 0; + unsigned long scountinhibit_val =3D 0; =20 - for (i =3D 0; i < BITS_TO_LONGS(RISCV_MAX_COUNTERS); i++) { - ctr_start_mask =3D cpu_hw_evt->used_hw_ctrs[i] & ~ctr_ovf_mask; - /* Start all the counters that did not overflow in a single shot */ - if (ctr_start_mask) { - sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, i * BITS_PER_LONG, - ctr_start_mask, 0, 0, 0, 0); - } - } + scountinhibit_val =3D csr_read(CSR_SCOUNTINHIBIT); + scountinhibit_val &=3D ~mask; + + csr_write(CSR_SCOUNTINHIBIT, scountinhibit_val); +} + +static void rvpmu_deleg_ctr_enable_irq(struct perf_event *event) +{ + unsigned long hpmevent_curr; + unsigned long of_mask; + struct hw_perf_event *hwc =3D &event->hw; + int counter_idx =3D hwc->idx; + unsigned long sip_val =3D csr_read(CSR_SIP); + + if (!is_sampling_event(event) || (sip_val & SIP_LCOFIP)) + return; =20 - /* Reinitialize and start all the counter that overflowed */ - while (ctr_ovf_mask) { - if (ctr_ovf_mask & 0x01) { - event =3D cpu_hw_evt->events[idx]; - hwc =3D &event->hw; - max_period =3D riscv_pmu_ctr_get_width_mask(event); - init_val =3D local64_read(&hwc->prev_count) & max_period; #if defined(CONFIG_32BIT) - sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, idx, 1, - flag, init_val, init_val >> 32, 0); + hpmevent_curr =3D csr_ind_read(CSR_SIREG5, SISELECT_SSCCFG_BASE, counter_= idx); + of_mask =3D (u32)~HPMEVENTH_OF; #else - sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, idx, 1, - flag, init_val, 0, 0); + hpmevent_curr =3D csr_ind_read(CSR_SIREG2, SISELECT_SSCCFG_BASE, counter_= idx); + of_mask =3D ~HPMEVENT_OF; #endif - perf_event_update_userpage(event); - } - ctr_ovf_mask =3D ctr_ovf_mask >> 1; - idx++; - } + + hpmevent_curr &=3D of_mask; +#if defined(CONFIG_32BIT) + csr_ind_write(CSR_SIREG5, SISELECT_SSCCFG_BASE, counter_idx, hpmevent_cur= r); +#else + csr_ind_write(CSR_SIREG2, SISELECT_SSCCFG_BASE, counter_idx, hpmevent_cur= r); +#endif +} + +static void rvpmu_deleg_ctr_start(struct perf_event *event, u64 ival) +{ + unsigned long scountinhibit_val =3D 0; + struct hw_perf_event *hwc =3D &event->hw; + +#if defined(CONFIG_32BIT) + csr_ind_write(CSR_SIREG, SISELECT_SSCCFG_BASE, hwc->idx, ival & 0xFFFFFFF= F); + csr_ind_write(CSR_SIREG4, SISELECT_SSCCFG_BASE, hwc->idx, ival >> BITS_PE= R_LONG); +#else + csr_ind_write(CSR_SIREG, SISELECT_SSCCFG_BASE, hwc->idx, ival); +#endif + + rvpmu_deleg_ctr_enable_irq(event); + + scountinhibit_val =3D csr_read(CSR_SCOUNTINHIBIT); + scountinhibit_val &=3D ~BIT(hwc->idx); + + csr_write(CSR_SCOUNTINHIBIT, scountinhibit_val); +} + +static void rvpmu_deleg_ctr_stop_mask(unsigned long mask) +{ + unsigned long scountinhibit_val =3D 0; + + scountinhibit_val =3D csr_read(CSR_SCOUNTINHIBIT); + scountinhibit_val |=3D mask; + + csr_write(CSR_SCOUNTINHIBIT, scountinhibit_val); } =20 -static inline void rvpmu_sbi_start_ovf_ctrs_snapshot(struct cpu_hw_events = *cpu_hw_evt, - u64 ctr_ovf_mask) +static void rvpmu_sbi_start_ovf_ctrs_snapshot(struct cpu_hw_events *cpu_hw= _evt, + u64 ctr_ovf_mask) { int i, idx =3D 0; struct perf_event *event; @@ -1116,15 +1269,53 @@ static inline void rvpmu_sbi_start_ovf_ctrs_snapsho= t(struct cpu_hw_events *cpu_h } } =20 -static void rvpmu_sbi_start_overflow_mask(struct riscv_pmu *pmu, - u64 ctr_ovf_mask) +/* + * This function starts all the used counters in two step approach. + * Any counter that did not overflow can be start in a single step + * while the overflowed counters need to be started with updated initializ= ation + * value. + */ +static void rvpmu_start_overflow_mask(struct riscv_pmu *pmu, u64 ctr_ovf_m= ask) { + int idx =3D 0, i; + struct perf_event *event; + unsigned long ctr_start_mask =3D 0; + u64 max_period, init_val =3D 0; + struct hw_perf_event *hwc; struct cpu_hw_events *cpu_hw_evt =3D this_cpu_ptr(pmu->hw_events); =20 if (sbi_pmu_snapshot_available()) - rvpmu_sbi_start_ovf_ctrs_snapshot(cpu_hw_evt, ctr_ovf_mask); - else - rvpmu_sbi_start_ovf_ctrs_sbi(cpu_hw_evt, ctr_ovf_mask); + return rvpmu_sbi_start_ovf_ctrs_snapshot(cpu_hw_evt, ctr_ovf_mask); + + /* Start all the counters that did not overflow */ + if (riscv_pmu_cdeleg_available()) { + ctr_start_mask =3D cpu_hw_evt->used_hw_ctrs[0] & ~ctr_ovf_mask; + rvpmu_deleg_ctr_start_mask(ctr_start_mask); + } else { + for (i =3D 0; i < BITS_TO_LONGS(RISCV_MAX_COUNTERS); i++) { + ctr_start_mask =3D cpu_hw_evt->used_hw_ctrs[i] & ~ctr_ovf_mask; + /* Start all the counters that did not overflow in a single shot */ + sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, i * BITS_PER_LONG, + ctr_start_mask, 0, 0, 0, 0); + } + } + + /* Reinitialize and start all the counter that overflowed */ + while (ctr_ovf_mask) { + if (ctr_ovf_mask & 0x01) { + event =3D cpu_hw_evt->events[idx]; + hwc =3D &event->hw; + max_period =3D riscv_pmu_ctr_get_width_mask(event); + init_val =3D local64_read(&hwc->prev_count) & max_period; + if (riscv_pmu_cdeleg_available()) + rvpmu_deleg_ctr_start(event, init_val); + else + rvpmu_sbi_ctr_start(event, init_val); + perf_event_update_userpage(event); + } + ctr_ovf_mask =3D ctr_ovf_mask >> 1; + idx++; + } } =20 static irqreturn_t rvpmu_ovf_handler(int irq, void *dev) @@ -1159,10 +1350,18 @@ static irqreturn_t rvpmu_ovf_handler(int irq, void = *dev) } =20 pmu =3D to_riscv_pmu(event->pmu); - rvpmu_sbi_stop_hw_ctrs(pmu); + if (riscv_pmu_cdeleg_available()) + rvpmu_deleg_ctr_stop_mask(cpu_hw_evt->used_hw_ctrs[0]); + else + rvpmu_sbi_stop_hw_ctrs(pmu); =20 - /* Overflow status register should only be read after counter are stopped= */ - if (sbi_pmu_snapshot_available()) + /* + * Overflow status register should only be read after counter are stopped. + * In counter delegation mode the overflows are reported in scountovf, not + * in the SBI snapshot area, so read the CSR directly even when an SBI PMU + * snapshot is also available. + */ + if (sbi_pmu_snapshot_available() && !riscv_pmu_cdeleg_available()) overflow =3D sdata->ctr_overflow_mask; else ALT_SBI_PMU_OVERFLOW(overflow); @@ -1228,22 +1427,183 @@ static irqreturn_t rvpmu_ovf_handler(int irq, void= *dev) hw_evt->state =3D 0; } =20 - rvpmu_sbi_start_overflow_mask(pmu, overflowed_ctrs); + rvpmu_start_overflow_mask(pmu, overflowed_ctrs); perf_sample_event_took(sched_clock() - start_clock); =20 return IRQ_HANDLED; } =20 +static int get_deleg_hw_ctr_width(int counter_offset) +{ + unsigned long hpm_warl; + int num_bits; + + if (counter_offset < 3 || counter_offset > 31) + return 0; + + hpm_warl =3D csr_ind_warl(CSR_SIREG, SISELECT_SSCCFG_BASE, counter_offset= , -1); + if (!hpm_warl) + return 0; + num_bits =3D __fls(hpm_warl); + +#if defined(CONFIG_32BIT) + /* + * The low half contributes a full BITS_PER_LONG bits when the counter is + * wider than 32 bits; the high half's __fls() gives the remaining width. + */ + hpm_warl =3D csr_ind_warl(CSR_SIREG4, SISELECT_SSCCFG_BASE, counter_offse= t, -1); + if (hpm_warl) + num_bits =3D BITS_PER_LONG + __fls(hpm_warl); +#endif + return num_bits; +} + +static int rvpmu_deleg_find_ctrs(void) +{ + int i, num_hw_ctr =3D 0; + union sbi_pmu_ctr_info cinfo; + unsigned long scountinhibit_old =3D 0; + + /* Do a WARL write/read to detect which hpmcounters have been delegated */ + scountinhibit_old =3D csr_read(CSR_SCOUNTINHIBIT); + csr_write(CSR_SCOUNTINHIBIT, -1); + cmask =3D csr_read(CSR_SCOUNTINHIBIT); + + csr_write(CSR_SCOUNTINHIBIT, scountinhibit_old); + + for_each_set_bit(i, &cmask, RISCV_MAX_HW_COUNTERS) { + if (unlikely(i =3D=3D 1)) + continue; /* This should never happen as TM is read only */ + cinfo.value =3D 0; + cinfo.type =3D SBI_PMU_CTR_TYPE_HW; + /* + * If counter delegation is enabled, the csr stored to the cinfo will + * be a virtual counter that the delegation attempts to read. + */ + cinfo.csr =3D CSR_CYCLE + i; + if (i =3D=3D 0 || i =3D=3D 2) + cinfo.width =3D 63; + else + cinfo.width =3D get_deleg_hw_ctr_width(i); + + num_hw_ctr++; + pmu_ctr_list[i].value =3D cinfo.value; + } + + return num_hw_ctr; +} + +static int get_deleg_fixed_hw_idx(struct cpu_hw_events *cpuc, struct perf_= event *event) +{ + return -EINVAL; +} + +static int get_deleg_next_hpm_hw_idx(struct cpu_hw_events *cpuc, struct pe= rf_event *event) +{ + unsigned long hw_ctr_mask =3D 0; + + /* + * TODO: Treat every hpmcounter can monitor every event for now. + * The event to counter mapping should come from the json file. + * The mapping should also tell if sampling is supported or not. + */ + + /* Select only hpmcounters */ + hw_ctr_mask =3D cmask & (~0x7); + hw_ctr_mask &=3D ~(cpuc->used_hw_ctrs[0]); + return __ffs(hw_ctr_mask); +} + +static void update_deleg_hpmevent(int counter_idx, uint64_t event_value, u= int64_t filter_bits) +{ + u64 hpmevent_value =3D 0; + + /* OF bit should be enable during the start if sampling is requested */ + hpmevent_value =3D (event_value & ~HPMEVENT_MASK) | filter_bits | HPMEVEN= T_OF; +#if defined(CONFIG_32BIT) + csr_ind_write(CSR_SIREG2, SISELECT_SSCCFG_BASE, counter_idx, hpmevent_val= ue & 0xFFFFFFFF); + if (riscv_isa_extension_available(NULL, SSCOFPMF)) + csr_ind_write(CSR_SIREG5, SISELECT_SSCCFG_BASE, counter_idx, + hpmevent_value >> BITS_PER_LONG); +#else + csr_ind_write(CSR_SIREG2, SISELECT_SSCCFG_BASE, counter_idx, hpmevent_val= ue); +#endif +} + +static int rvpmu_deleg_ctr_get_idx(struct perf_event *event) +{ + struct hw_perf_event *hwc =3D &event->hw; + struct riscv_pmu *rvpmu =3D to_riscv_pmu(event->pmu); + struct cpu_hw_events *cpuc =3D this_cpu_ptr(rvpmu->hw_events); + unsigned long hw_ctr_max_id; + u64 priv_filter; + int idx; + + /* + * TODO: We should not rely on SBI Perf encoding to check if the event + * is a fixed one or not. + */ + if (!is_sampling_event(event)) { + idx =3D get_deleg_fixed_hw_idx(cpuc, event); + if (idx =3D=3D 0 || idx =3D=3D 2) { + /* Priv mode filter bits are only available if smcntrpmf is present */ + if (riscv_isa_extension_available(NULL, SMCNTRPMF)) + goto found_idx; + else + goto skip_update; + } + } + + if (!cmask) + goto out_err; + hw_ctr_max_id =3D __fls(cmask); + idx =3D get_deleg_next_hpm_hw_idx(cpuc, event); + if (idx < 3 || idx > hw_ctr_max_id) + goto out_err; +found_idx: + priv_filter =3D get_deleg_priv_filter_bits(event); + update_deleg_hpmevent(idx, hwc->config, priv_filter); +skip_update: + if (!test_and_set_bit(idx, cpuc->used_hw_ctrs)) + return idx; +out_err: + return -ENOENT; +} + static void rvpmu_ctr_start(struct perf_event *event, u64 ival) { - rvpmu_sbi_ctr_start(event, ival); - /* TODO: Counter delegation implementation */ + struct hw_perf_event *hwc =3D &event->hw; + + if (riscv_pmu_cdeleg_available() && !pmu_sbi_is_fw_event(event)) + rvpmu_deleg_ctr_start(event, ival); + else + rvpmu_sbi_ctr_start(event, ival); + + if ((hwc->flags & PERF_EVENT_FLAG_USER_ACCESS) && + (hwc->flags & PERF_EVENT_FLAG_USER_READ_CNT)) + rvpmu_set_scounteren((void *)event); } =20 static void rvpmu_ctr_stop(struct perf_event *event, unsigned long flag) { - rvpmu_sbi_ctr_stop(event, flag); - /* TODO: Counter delegation implementation */ + struct hw_perf_event *hwc =3D &event->hw; + + if ((hwc->flags & PERF_EVENT_FLAG_USER_ACCESS) && + (hwc->flags & PERF_EVENT_FLAG_USER_READ_CNT)) + rvpmu_reset_scounteren((void *)event); + + if (riscv_pmu_cdeleg_available() && !pmu_sbi_is_fw_event(event)) { + /* + * The counter is already stopped. No need to stop again. Counter + * mapping will be reset in clear_idx function. + */ + if (flag !=3D RISCV_PMU_STOP_FLAG_RESET) + rvpmu_deleg_ctr_stop_mask(BIT(hwc->idx)); + else + update_deleg_hpmevent(hwc->idx, 0, 0); + } else { + rvpmu_sbi_ctr_stop(event, flag); + } } =20 static int rvpmu_find_ctrs(void) @@ -1292,20 +1652,18 @@ static int rvpmu_find_ctrs(void) =20 static int rvpmu_event_map(struct perf_event *event, u64 *econfig) { - return rvpmu_sbi_event_map(event, econfig); - /* TODO: Counter delegation implementation */ + if (riscv_pmu_cdeleg_available() && !pmu_sbi_is_fw_event(event)) + return rvpmu_cdeleg_event_map(event, econfig); + else + return rvpmu_sbi_event_map(event, econfig); } =20 static int rvpmu_ctr_get_idx(struct perf_event *event) { - return rvpmu_sbi_ctr_get_idx(event); - /* TODO: Counter delegation implementation */ -} - -static u64 rvpmu_ctr_read(struct perf_event *event) -{ - return rvpmu_sbi_ctr_read(event); - /* TODO: Counter delegation implementation */ + if (riscv_pmu_cdeleg_available() && !pmu_sbi_is_fw_event(event)) + return rvpmu_deleg_ctr_get_idx(event); + else + return rvpmu_sbi_ctr_get_idx(event); } =20 static int rvpmu_starting_cpu(unsigned int cpu, struct hlist_node *node) @@ -1323,7 +1681,16 @@ static int rvpmu_starting_cpu(unsigned int cpu, stru= ct hlist_node *node) csr_write(CSR_SCOUNTEREN, 0x2); =20 /* Stop all the counters so that they can be enabled from perf */ - rvpmu_sbi_stop_all(pmu); + if (riscv_pmu_cdeleg_available()) { + rvpmu_deleg_ctr_stop_mask(cmask); + if (riscv_pmu_sbi_available()) { + /* Stop the firmware counters as well */ + sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_STOP, 0, firmware_cmask, + 0, 0, 0, 0); + } + } else { + rvpmu_sbi_stop_all(pmu); + } =20 if (riscv_pmu_use_irq) { cpu_hw_evt->irq =3D riscv_pmu_irq; @@ -1632,8 +1999,11 @@ static int rvpmu_device_probe(struct platform_device= *pdev) } irq_requested =3D (ret =3D=3D 0); =20 - pmu->pmu.attr_groups =3D riscv_pmu_attr_groups; pmu->pmu.parent =3D &pdev->dev; + if (riscv_pmu_cdeleg_available_boot()) + pmu->pmu.attr_groups =3D riscv_cdeleg_pmu_attr_groups; + else + pmu->pmu.attr_groups =3D riscv_sbi_pmu_attr_groups; pmu->cmask =3D cmask; pmu->ctr_start =3D rvpmu_ctr_start; pmu->ctr_stop =3D rvpmu_ctr_stop; diff --git a/include/linux/perf/riscv_pmu.h b/include/linux/perf/riscv_pmu.h index f82a28040594..3c64151cb038 100644 --- a/include/linux/perf/riscv_pmu.h +++ b/include/linux/perf/riscv_pmu.h @@ -20,6 +20,7 @@ */ =20 #define RISCV_MAX_COUNTERS 64 +#define RISCV_MAX_HW_COUNTERS 32 #define RISCV_OP_UNSUPP (-EOPNOTSUPP) #define RISCV_PMU_SBI_PDEV_NAME "riscv-pmu-sbi" #define RISCV_PMU_LEGACY_PDEV_NAME "riscv-pmu-legacy" @@ -28,6 +29,8 @@ =20 #define RISCV_PMU_CONFIG1_GUEST_EVENTS 0x1 =20 +#define RISCV_PMU_DELEG_RAW_EVENT_MASK GENMASK_ULL(55, 0) + struct cpu_hw_events { /* currently enabled events */ int n_events; --=20 2.53.0-Meta From nobody Thu Jul 16 17:05:11 2026 Received: from out-173.mta1.migadu.com (out-173.mta1.migadu.com [95.215.58.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C28E13EEAC3 for ; Wed, 1 Jul 2026 08:48:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.173 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782895723; cv=none; b=EWei2TBadw3ib5S9zJc5fQhC8yr3XodVEc1nd//e0UcfYR2UTgiU/FMym4xLgBYg3/d1QqFvTQ1Xrx+cwAqBHon9zFee9HvUuelfbJGCW+4ZjradC/6nhduEWMVwh4eCtOmhNSodn3Gs/DkwD+V09FEiD2vYLTSEEurKV2HkMsE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782895723; c=relaxed/simple; bh=nEHnKBt6yn9At5sBnjqNhHhsfxdSpQLCIcq4Y8rJw20=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=uWIG7v/dL46V+pDByLFIJmljJ4P8kJVkhdAS3mBRksTpyYIOukMFK+RuUsGeyQMEONvRmUs+Fvn/RIluz/Cz3ZRdkkZMfpwbHHYzXfMjP74LDqPn8pKsjwVT/O2v0H6cnWnHSJD2d/kUN7rKoigcqDhOBTMtlUuwrDE6A3EOo6s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=XnPNVO83; arc=none smtp.client-ip=95.215.58.173 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="XnPNVO83" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1782895720; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=2exj47iWI8m59zE0VktO/cVpTYfa8tTYnWLe+Y16FOA=; b=XnPNVO83CvB8pqol+h3agWAEzUMnVIbjNbjLQkY8J3Es/yt6a2KoNAeFQHckgw8kMGZPGp VJzkif3pNZlXews/KdijZngTSCNV0r4mdke3GZADTzr0qCC7bUd5K3tRQNWWMsiii5Tzzx G6j63yShnMRlbojIvX/Q51LrGSwfXl0= From: Atish Patra Date: Wed, 01 Jul 2026 01:47:03 -0700 Subject: [PATCH v8 15/22] RISC-V: perf: Skip PMU SBI extension when not implemented Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260701-counter_delegation-v8-15-7909f863a645@meta.com> References: <20260701-counter_delegation-v8-0-7909f863a645@meta.com> In-Reply-To: <20260701-counter_delegation-v8-0-7909f863a645@meta.com> To: Jiri Olsa , Paul Walmsley , Mark Rutland , Rob Herring , Anup Patel , Namhyung Kim , Arnaldo Carvalho de Melo , Krzysztof Kozlowski , Atish Patra , Ian Rogers , Will Deacon , James Clark Cc: linux-arm-kernel@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-perf-users@vger.kernel.org, Conor Dooley X-Migadu-Flow: FLOW_OUT From: Charlie Jenkins When the PMU SBI extension is not implemented, sbi_v2_available should not be set to true. The SBI implementation for counter config matching and firmware counter read should also be skipped when the SBI extension is not implemented. Signed-off-by: Atish Patra Signed-off-by: Charlie Jenkins --- drivers/perf/riscv_pmu_sbi.c | 49 ++++++++++++++++++++++++++--------------= ---- 1 file changed, 29 insertions(+), 20 deletions(-) diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index 7995da4a98a1..fcf8fbb6fd86 100644 --- a/drivers/perf/riscv_pmu_sbi.c +++ b/drivers/perf/riscv_pmu_sbi.c @@ -495,27 +495,32 @@ static void rvpmu_sbi_check_event(struct sbi_pmu_even= t_data *edata) } } =20 -static void rvpmu_sbi_check_std_events(struct work_struct *work) +static void rvpmu_check_std_events(struct work_struct *work) { int ret; =20 - if (sbi_v3_available) { - ret =3D pmu_sbi_check_event_info(); - if (ret) - pr_err("pmu_sbi_check_event_info failed with error %d\n", ret); - return; - } + if (riscv_pmu_sbi_available()) { + if (sbi_v3_available) { + ret =3D pmu_sbi_check_event_info(); + if (ret) + pr_err("pmu_sbi_check_event_info failed with error %d\n", ret); + return; + } =20 - for (int i =3D 0; i < ARRAY_SIZE(pmu_hw_event_sbi_map); i++) - rvpmu_sbi_check_event(&pmu_hw_event_sbi_map[i]); + for (int i =3D 0; i < ARRAY_SIZE(pmu_hw_event_sbi_map); i++) + rvpmu_sbi_check_event(&pmu_hw_event_sbi_map[i]); =20 - for (int i =3D 0; i < ARRAY_SIZE(pmu_cache_event_sbi_map); i++) - for (int j =3D 0; j < ARRAY_SIZE(pmu_cache_event_sbi_map[i]); j++) - for (int k =3D 0; k < ARRAY_SIZE(pmu_cache_event_sbi_map[i][j]); k++) - rvpmu_sbi_check_event(&pmu_cache_event_sbi_map[i][j][k]); + for (int i =3D 0; i < ARRAY_SIZE(pmu_cache_event_sbi_map); i++) + for (int j =3D 0; j < ARRAY_SIZE(pmu_cache_event_sbi_map[i]); j++) + for (int k =3D 0; k < ARRAY_SIZE(pmu_cache_event_sbi_map[i][j]); k++) + rvpmu_sbi_check_event(&pmu_cache_event_sbi_map[i][j][k]); + } else { + DO_ONCE_LITE_IF(1, pr_info, + "Boot time config matching not required for smcdeleg\n"); + } } =20 -static DECLARE_WORK(check_std_events_work, rvpmu_sbi_check_std_events); +static DECLARE_WORK(check_std_events_work, rvpmu_check_std_events); =20 static ssize_t rvpmu_format_show(struct device *dev, struct device_attribute *attr, char *buf) @@ -708,6 +713,9 @@ static int rvpmu_sbi_ctr_get_idx(struct perf_event *eve= nt) =20 cflags =3D rvpmu_sbi_get_filter_flags(event); =20 + if (!riscv_pmu_sbi_available()) + return -ENOENT; + /* * In legacy mode, we have to force the fixed counters for those events * but not in the user access mode as we want to use the other counters @@ -985,7 +993,7 @@ static u64 rvpmu_ctr_read(struct perf_event *event) return val; } =20 - if (pmu_sbi_is_fw_event(event)) { + if (pmu_sbi_is_fw_event(event) && riscv_pmu_sbi_available()) { ret =3D sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_FW_READ, hwc->idx, 0, 0, 0, 0, 0); if (ret.error) @@ -2094,12 +2102,13 @@ static int __init rvpmu_devinit(void) int ret; struct platform_device *pdev; =20 - if (sbi_spec_version >=3D sbi_mk_version(0, 3) && - sbi_probe_extension(SBI_EXT_PMU)) - static_branch_enable(&riscv_pmu_sbi_available); + if (sbi_probe_extension(SBI_EXT_PMU)) { + if (sbi_spec_version >=3D sbi_mk_version(0, 3)) + static_branch_enable(&riscv_pmu_sbi_available); + if (sbi_spec_version >=3D sbi_mk_version(2, 0)) + sbi_v2_available =3D true; + } =20 - if (sbi_spec_version >=3D sbi_mk_version(2, 0)) - sbi_v2_available =3D true; /* * We need all three extensions to be present to access the counters * in S-mode via Supervisor Counter delegation. --=20 2.53.0-Meta From nobody Thu Jul 16 17:05:11 2026 Received: from out-184.mta0.migadu.com (out-184.mta0.migadu.com [91.218.175.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 720163F44D0 for ; Wed, 1 Jul 2026 08:48:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.218.175.184 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782895726; cv=none; b=fAmfmZXZ9b0OEP/Hfcl1rlNe2AM3lMTjYNJ1ic7cJTBC18ECJ+NTeCGZ7iFH2wBoOGKDF5RjwStknc8Bmq9vfEbkXR9L+HTFsFNjndVha8GXHNuIoXNdHNgy63qG9hTC+CPourI1xnGMcnDOJPuwMuws9saMVAclVeByiJUwFDE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782895726; c=relaxed/simple; bh=RZRTDYshChhPUk5ppA0XeArZ0z0swbQ/LeHcdMeMCi8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; 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DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1782895723; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=+gXSgXYMV7F3MdrOzbBo23B5HEUkNxGus+YTKY34K/0=; b=of5w2bTqIyt3VveWurzZ+HxSJA0IXdmZdwGCH1CuM8hPfp7arlCXhvpTS62KJMOdcSprQc icIMUSZJrMibduyJQSN20+v9VnUQEbgjm9hge/VnMeptjgrmOw4ix4JFKOApORLRoDGhnD VYA3cNB18VmOWJX+vDDmMUVCgXtJbUE= From: Atish Patra Date: Wed, 01 Jul 2026 01:47:04 -0700 Subject: [PATCH v8 16/22] RISC-V: perf: Use config2/vendor table for event to counter mapping Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260701-counter_delegation-v8-16-7909f863a645@meta.com> References: <20260701-counter_delegation-v8-0-7909f863a645@meta.com> In-Reply-To: <20260701-counter_delegation-v8-0-7909f863a645@meta.com> To: Jiri Olsa , Paul Walmsley , Mark Rutland , Rob Herring , Anup Patel , Namhyung Kim , Arnaldo Carvalho de Melo , Krzysztof Kozlowski , Atish Patra , Ian Rogers , Will Deacon , James Clark Cc: linux-arm-kernel@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-perf-users@vger.kernel.org, Conor Dooley X-Migadu-Flow: FLOW_OUT From: Atish Patra The counter restriction specified in the json file is passed to the drivers via config2 paarameter in perf attributes. This allows any platform vendor to define their custom mapping between event and hpmcounters without any rules defined in the ISA. For legacy events, the platform vendor may define the mapping in the driver in the vendor event table. The fixed cycle and instruction counters are fixed (0 and 2 respectively) by the ISA and maps to the legacy events. The platform vendor must specify this in the driver if intended to be used while profiling. Otherwise, they can just specify the alternate hpmcounters that may monitor and/or sample the cycle/instruction counts. Signed-off-by: Atish Patra --- drivers/perf/riscv_pmu_sbi.c | 95 +++++++++++++++++++++++++++++++++++---= ---- include/linux/perf/riscv_pmu.h | 2 + 2 files changed, 81 insertions(+), 16 deletions(-) diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index fcf8fbb6fd86..19d9e4750424 100644 --- a/drivers/perf/riscv_pmu_sbi.c +++ b/drivers/perf/riscv_pmu_sbi.c @@ -77,6 +77,7 @@ static ssize_t __maybe_unused rvpmu_format_show(struct de= vice *dev, struct devic RVPMU_ATTR_ENTRY(_name, rvpmu_format_show, (char *)_config) =20 PMU_FORMAT_ATTR(firmware, "config:62-63"); +PMU_FORMAT_ATTR(counterid_mask, "config2:0-31"); =20 static bool sbi_v2_available; static bool sbi_v3_available; @@ -121,6 +122,7 @@ static const struct attribute_group *riscv_sbi_pmu_attr= _groups[] =3D { static struct attribute *riscv_cdeleg_pmu_formats_attr[] =3D { RVPMU_FORMAT_ATTR_ENTRY(event, RVPMU_CDELEG_PMU_FORMAT_ATTR), &format_attr_firmware.attr, + &format_attr_counterid_mask.attr, NULL, }; =20 @@ -1501,24 +1503,85 @@ static int rvpmu_deleg_find_ctrs(void) return num_hw_ctr; } =20 +/* + * The json file must correctly specify counter 0 or counter 2 is available + * in the counter lists for cycle/instret events. Otherwise, the drivers h= ave + * no way to figure out if a fixed counter must be used and pick a program= mable + * counter if available. + */ static int get_deleg_fixed_hw_idx(struct cpu_hw_events *cpuc, struct perf_= event *event) { - return -EINVAL; + bool guest_events =3D event->attr.config1 & RISCV_PMU_CONFIG1_GUEST_EVENT= S; + int idx; + + /* event_base is 0 on the delegation path; match via the original perf at= trs. */ + if (guest_events) { + if (event->attr.type !=3D PERF_TYPE_HARDWARE) + return -EINVAL; + if (event->attr.config =3D=3D PERF_COUNT_HW_CPU_CYCLES) + idx =3D 0; /* CY counter */ + else if (event->attr.config =3D=3D PERF_COUNT_HW_INSTRUCTIONS) + idx =3D 2; /* IR counter */ + else + return -EINVAL; + } else if (event->attr.config2 & RISCV_PMU_CYCLE_FIXED_CTR_MASK) { + idx =3D 0; /* CY counter */ + } else if (event->attr.config2 & RISCV_PMU_INSTRUCTION_FIXED_CTR_MASK) { + idx =3D 2; /* IR counter */ + } else { + return -EINVAL; + } + + /* Take the fixed counter only if delegated and free, else fall back. */ + if (!(cmask & BIT(idx)) || test_bit(idx, cpuc->used_hw_ctrs)) + return -EINVAL; + + return idx; } =20 static int get_deleg_next_hpm_hw_idx(struct cpu_hw_events *cpuc, struct pe= rf_event *event) { - unsigned long hw_ctr_mask =3D 0; + u32 hw_ctr_mask =3D 0, temp_mask =3D 0; + u32 type =3D event->attr.type; + u64 config =3D event->attr.config; + int ret; =20 - /* - * TODO: Treat every hpmcounter can monitor every event for now. - * The event to counter mapping should come from the json file. - * The mapping should also tell if sampling is supported or not. - */ + /* Select only available hpmcounters */ + hw_ctr_mask =3D cmask & (~0x7) & ~(cpuc->used_hw_ctrs[0]); + + switch (type) { + case PERF_TYPE_HARDWARE: + temp_mask =3D current_pmu_hw_event_map[config].counter_mask; + break; + case PERF_TYPE_HW_CACHE: + ret =3D cdeleg_pmu_event_find_cache(config, NULL, &temp_mask); + if (ret) + return ret; + break; + case PERF_TYPE_RAW: + /* + * Mask off the counters that can't monitor this event (specified via js= on) + * The counter mask for this event is set in config2 via the property 'C= ounter' + * in the json file or manual configuration of config2. If the config2 i= s not set, + * it is assumed all the available hpmcounters can monitor this event. + * Note: This assumption may fail for virtualization use case where they= hypervisor + * (e.g. KVM) virtualizes the counter. Any event to counter mapping prov= ided by the + * guest is meaningless from a hypervisor perspective. Thus, the hypervi= sor doesn't + * set config2 when creating kernel counter and relies default host mapp= ing. + */ + if (event->attr.config2) + temp_mask =3D event->attr.config2; + break; + default: + break; + } + + if (temp_mask) + hw_ctr_mask &=3D temp_mask; + + if (!hw_ctr_mask) + return -EINVAL; =20 - /* Select only hpmcounters */ - hw_ctr_mask =3D cmask & (~0x7); - hw_ctr_mask &=3D ~(cpuc->used_hw_ctrs[0]); return __ffs(hw_ctr_mask); } =20 @@ -1547,10 +1610,6 @@ static int rvpmu_deleg_ctr_get_idx(struct perf_event= *event) u64 priv_filter; int idx; =20 - /* - * TODO: We should not rely on SBI Perf encoding to check if the event - * is a fixed one or not. - */ if (!is_sampling_event(event)) { idx =3D get_deleg_fixed_hw_idx(cpuc, event); if (idx =3D=3D 0 || idx =3D=3D 2) { @@ -1570,10 +1629,14 @@ static int rvpmu_deleg_ctr_get_idx(struct perf_even= t *event) goto out_err; found_idx: priv_filter =3D get_deleg_priv_filter_bits(event); + if (test_and_set_bit(idx, cpuc->used_hw_ctrs)) + goto out_err; update_deleg_hpmevent(idx, hwc->config, priv_filter); + return idx; skip_update: - if (!test_and_set_bit(idx, cpuc->used_hw_ctrs)) - return idx; + if (test_and_set_bit(idx, cpuc->used_hw_ctrs)) + goto out_err; + return idx; out_err: return -ENOENT; } diff --git a/include/linux/perf/riscv_pmu.h b/include/linux/perf/riscv_pmu.h index 3c64151cb038..b23b71cb4e66 100644 --- a/include/linux/perf/riscv_pmu.h +++ b/include/linux/perf/riscv_pmu.h @@ -30,6 +30,8 @@ #define RISCV_PMU_CONFIG1_GUEST_EVENTS 0x1 =20 #define RISCV_PMU_DELEG_RAW_EVENT_MASK GENMASK_ULL(55, 0) +#define RISCV_PMU_CYCLE_FIXED_CTR_MASK 0x01 +#define RISCV_PMU_INSTRUCTION_FIXED_CTR_MASK 0x04 =20 struct cpu_hw_events { /* currently enabled events */ --=20 2.53.0-Meta From nobody Thu Jul 16 17:05:11 2026 Received: from out-182.mta0.migadu.com (out-182.mta0.migadu.com [91.218.175.182]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AB3523F4845 for ; Wed, 1 Jul 2026 08:48:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.218.175.182 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782895730; cv=none; b=Zhfa5ghUdzw9kEw/v7wlNbJd5RiE1Lp3o5HsWs2CfkC+ACp038f5csL2dvWoPUFYredWePJ7HvxfGhNedhTszvfGcUk7EbLI8gvAWSL52ZKjJFCTD+ZgqmuHq0P/l4NQr9a+bYWnGJmEVJmW6VjjKoqxt+CWyjb6y1mErYBFOM8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782895730; c=relaxed/simple; bh=ArUheZCA3RDd3OrUUVHs4fa60ItvTNb3kPvfSi4WogQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=lGRGY9GzrHP3pf3h+6B1EU8ljj54I3cjoPoe6czZf1+Kh3zJtevV5oBBkrtbmfUhYFdUNjRh5YZgvCsRlCHRk9rCSzTnGwrpPpLTTi7qtv9MgtgIiBmVUSctTAF9F0sFBD+BH0Q/CgZ95WCIZzPBcQGsRc9X29aGzjYXelnNQug= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=RoCoBX0P; arc=none smtp.client-ip=91.218.175.182 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="RoCoBX0P" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1782895727; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=sUW0XZri82aMtP6xGb1BMJz4KHWoX5dfoO6IaJkuwoM=; b=RoCoBX0PfwZQeU9w77RFFBy+s+rOO0O4oDNUt3zvziV7gp8qGhdfcfWyyvkOhq2J2nRcSo vFXJtyIKwjqEeMojsNRAFxVOs7NPp9YOeUVQA4itBl5/qWq2FDSd8ase1pAfMi/04y43L/ dLHo7mTjOESzkaZCwGAdXUmdPe0CpHY= From: Atish Patra Date: Wed, 01 Jul 2026 01:47:05 -0700 Subject: [PATCH v8 17/22] RISC-V: perf: Add legacy event encodings via sysfs Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260701-counter_delegation-v8-17-7909f863a645@meta.com> References: <20260701-counter_delegation-v8-0-7909f863a645@meta.com> In-Reply-To: <20260701-counter_delegation-v8-0-7909f863a645@meta.com> To: Jiri Olsa , Paul Walmsley , Mark Rutland , Rob Herring , Anup Patel , Namhyung Kim , Arnaldo Carvalho de Melo , Krzysztof Kozlowski , Atish Patra , Ian Rogers , Will Deacon , James Clark Cc: linux-arm-kernel@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-perf-users@vger.kernel.org, Conor Dooley X-Migadu-Flow: FLOW_OUT From: Atish Patra Define sysfs details for the legacy events so that any tool can parse these to understand the minimum set of legacy events supported by the platform. The sysfs entry will describe both event encoding and corresponding counter map so that an perf event can be programmed accordingly. Signed-off-by: Atish Patra --- drivers/perf/riscv_pmu_sbi.c | 22 ++++++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-) diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index 19d9e4750424..8d56bef95a1b 100644 --- a/drivers/perf/riscv_pmu_sbi.c +++ b/drivers/perf/riscv_pmu_sbi.c @@ -131,7 +131,20 @@ static struct attribute_group riscv_cdeleg_pmu_format_= group =3D { .attrs =3D riscv_cdeleg_pmu_formats_attr, }; =20 +#define RVPMU_EVENT_ATTR_RESOLVE(m) #m +#define RVPMU_EVENT_CMASK_ATTR(_name, _var, config, mask) \ + PMU_EVENT_ATTR_STRING(_name, rvpmu_event_attr_##_var, \ + "event=3D" RVPMU_EVENT_ATTR_RESOLVE(config) \ + ",counterid_mask=3D" RVPMU_EVENT_ATTR_RESOLVE(mask)) + +#define RVPMU_EVENT_ATTR_PTR(name) (&rvpmu_event_attr_##name.attr.attr) + +static struct attribute_group riscv_cdeleg_pmu_event_group __ro_after_init= =3D { + .name =3D "events", +}; + static const struct attribute_group *riscv_cdeleg_pmu_attr_groups[] =3D { + &riscv_cdeleg_pmu_event_group, &riscv_cdeleg_pmu_format_group, NULL, }; @@ -447,11 +460,14 @@ struct riscv_vendor_pmu_events { const struct riscv_pmu_event *hw_event_map; const struct riscv_pmu_event (*cache_event_map)[PERF_COUNT_HW_CACHE_OP_MA= X] [PERF_COUNT_HW_CACHE_RESULT_MAX]; + struct attribute **attrs_events; }; =20 -#define RISCV_VENDOR_PMU_EVENTS(_vendorid, _archid, _implid, _hw_event_map= , _cache_event_map) \ +#define RISCV_VENDOR_PMU_EVENTS(_vendorid, _archid, _implid, _hw_event_map= , \ + _cache_event_map, _attrs) \ { .vendorid =3D _vendorid, .archid =3D _archid, .implid =3D _implid, \ - .hw_event_map =3D _hw_event_map, .cache_event_map =3D _cache_event_map = }, + .hw_event_map =3D _hw_event_map, .cache_event_map =3D _cache_event_map,= \ + .attrs_events =3D _attrs }, =20 static struct riscv_vendor_pmu_events pmu_vendor_events_table[] =3D { }; @@ -473,6 +489,8 @@ static void __init rvpmu_vendor_register_events(void) pmu_vendor_events_table[i].archid =3D=3D arch_id) { current_pmu_hw_event_map =3D pmu_vendor_events_table[i].hw_event_map; current_pmu_cache_event_map =3D pmu_vendor_events_table[i].cache_event_= map; + riscv_cdeleg_pmu_event_group.attrs =3D + pmu_vendor_events_table[i].attrs_events; break; } } --=20 2.53.0-Meta From nobody Thu Jul 16 17:05:11 2026 Received: from out-176.mta1.migadu.com (out-176.mta1.migadu.com [95.215.58.176]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 906F53F4DFD for ; Wed, 1 Jul 2026 08:48:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.176 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782895734; cv=none; b=tZi59l/ZcJgJabLxVn9gTAbwaWDvJ7wndrpb+f/79o39onQpif/+OdhXaFoMlzVe0CXD8OXpM7kzoxHi03vA31AcaXqWYN1qyx5xjtE6FteYPCOp+yPIOQHjTIFRXN/dt2ePxXhoEmojKp1kXkpmwk/Q6Kb528Y2aGHZnHw9fPA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782895734; c=relaxed/simple; bh=hHbdnttRcIwSaLlig0mRieB9Ne9ycoY/WHmdXhNxYJQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=DD8qWzdbGu+FBNvbovReLUHxvWz5FOmaAnpvVYR0RBqtwai20yhP61HIphwSCGO3Q6k+2HAP61Ur03Z4YlwoSQty9Mb/ofFRJtai0L17CK1RjsSRe8CcyyCRL09o9mq9Z/dQaJJrfGNDjbYwEIxKwcDr+XNn3396irZ2p1GJWmw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=Fj1VyxK7; arc=none smtp.client-ip=95.215.58.176 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="Fj1VyxK7" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1782895730; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=B7OAVI61QCG9swWmfE7yqtDuGV/OQ+fEPL58DyfrzLw=; b=Fj1VyxK7J+37FD7vP9f/P93B/DY/Pvc34Fgtk6N2PFXTDVG8akv8TcGw1hsFJliVwrOlOb BSU4fGnAhfS+S5d924d78fX6gm0L0wYsAEgtcyeFkL/iLogIpWJMuHj6pOdDrJ4jOJqopc kNdSXuYhvcjSKckGAt5v6EEwM3bnBgo= From: Atish Patra Date: Wed, 01 Jul 2026 01:47:06 -0700 Subject: [PATCH v8 18/22] RISC-V: perf: Add Qemu virt machine events Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260701-counter_delegation-v8-18-7909f863a645@meta.com> References: <20260701-counter_delegation-v8-0-7909f863a645@meta.com> In-Reply-To: <20260701-counter_delegation-v8-0-7909f863a645@meta.com> To: Jiri Olsa , Paul Walmsley , Mark Rutland , Rob Herring , Anup Patel , Namhyung Kim , Arnaldo Carvalho de Melo , Krzysztof Kozlowski , Atish Patra , Ian Rogers , Will Deacon , James Clark Cc: linux-arm-kernel@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-perf-users@vger.kernel.org, Conor Dooley X-Migadu-Flow: FLOW_OUT From: Atish Patra Qemu virt machine supports a very minimal set of legacy perf events. Add them to the vendor table so that users can use them when counter delegation is enabled. Qemu is identified by its marchid. Older Qemu reports all-zero mvendorid/marchid/mimpid, while newer Qemu reports the marchid 0x2a (42) allocated to it in the RISC-V ISA manual [1]. Register the events for both ids so they are available across Qemu versions. [1] https://github.com/riscv/riscv-isa-manual/blob/main/marchid.md Signed-off-by: Atish Patra --- arch/riscv/include/asm/vendorid_list.h | 6 ++++++ drivers/perf/riscv_pmu_sbi.c | 39 ++++++++++++++++++++++++++++++= ++++ 2 files changed, 45 insertions(+) diff --git a/arch/riscv/include/asm/vendorid_list.h b/arch/riscv/include/as= m/vendorid_list.h index 7f5030ee1fcf..beaf9236dba7 100644 --- a/arch/riscv/include/asm/vendorid_list.h +++ b/arch/riscv/include/asm/vendorid_list.h @@ -11,4 +11,10 @@ #define SIFIVE_VENDOR_ID 0x489 #define THEAD_VENDOR_ID 0x5b7 =20 +#define QEMU_VIRT_VENDOR_ID 0x000 +#define QEMU_VIRT_IMPL_ID 0x000 +#define QEMU_VIRT_ARCH_ID 0x000 +/* Newer Qemu reports the spec-allocated marchid 0x2a (42) for non-vendor = CPUs */ +#define QEMU_VIRT_ARCH_ID_SPEC 0x2a + #endif diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index 8d56bef95a1b..6d528eafb525 100644 --- a/drivers/perf/riscv_pmu_sbi.c +++ b/drivers/perf/riscv_pmu_sbi.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include #include @@ -469,7 +470,45 @@ struct riscv_vendor_pmu_events { .hw_event_map =3D _hw_event_map, .cache_event_map =3D _cache_event_map,= \ .attrs_events =3D _attrs }, =20 +/* QEMU virt PMU events */ +static const struct riscv_pmu_event qemu_virt_hw_event_map[PERF_COUNT_HW_M= AX] =3D { + PERF_MAP_ALL_UNSUPPORTED, + [PERF_COUNT_HW_CPU_CYCLES] =3D {0x01, 0xFFFFFFF8}, + [PERF_COUNT_HW_INSTRUCTIONS] =3D {0x02, 0xFFFFFFF8} +}; + +static const struct riscv_pmu_event qemu_virt_cache_event_map[PERF_COUNT_H= W_CACHE_MAX] + [PERF_COUNT_HW_CACHE_OP_MAX] + [PERF_COUNT_HW_CACHE_RESULT_MAX] =3D { + PERF_CACHE_MAP_ALL_UNSUPPORTED, + [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] =3D {0x10019, 0xFFFFFFF8}, + [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] =3D {0x1001B, 0xFFFFFFF8}, + + [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] =3D {0x10021, 0xFFFFFFF8}, +}; + +RVPMU_EVENT_CMASK_ATTR(cycles, cycles, 0x01, 0xFFFFFFF8); +RVPMU_EVENT_CMASK_ATTR(instructions, instructions, 0x02, 0xFFFFFFF8); +RVPMU_EVENT_CMASK_ATTR(dTLB-load-misses, dTLB_load_miss, 0x10019, 0xFFFFFF= F8); +RVPMU_EVENT_CMASK_ATTR(dTLB-store-misses, dTLB_store_miss, 0x1001B, 0xFFFF= FFF8); +RVPMU_EVENT_CMASK_ATTR(iTLB-load-misses, iTLB_load_miss, 0x10021, 0xFFFFFF= F8); + +static struct attribute *qemu_virt_event_group[] =3D { + RVPMU_EVENT_ATTR_PTR(cycles), + RVPMU_EVENT_ATTR_PTR(instructions), + RVPMU_EVENT_ATTR_PTR(dTLB_load_miss), + RVPMU_EVENT_ATTR_PTR(dTLB_store_miss), + RVPMU_EVENT_ATTR_PTR(iTLB_load_miss), + NULL, +}; + static struct riscv_vendor_pmu_events pmu_vendor_events_table[] =3D { + RISCV_VENDOR_PMU_EVENTS(QEMU_VIRT_VENDOR_ID, QEMU_VIRT_ARCH_ID, QEMU_VIRT= _IMPL_ID, + qemu_virt_hw_event_map, qemu_virt_cache_event_map, + qemu_virt_event_group) + RISCV_VENDOR_PMU_EVENTS(QEMU_VIRT_VENDOR_ID, QEMU_VIRT_ARCH_ID_SPEC, QEMU= _VIRT_IMPL_ID, + qemu_virt_hw_event_map, qemu_virt_cache_event_map, + qemu_virt_event_group) }; =20 static const struct riscv_pmu_event *current_pmu_hw_event_map; --=20 2.53.0-Meta From nobody Thu Jul 16 17:05:11 2026 Received: from out-177.mta0.migadu.com (out-177.mta0.migadu.com [91.218.175.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9D5A23F44E9 for ; Wed, 1 Jul 2026 08:48:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.218.175.177 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782895737; cv=none; b=XIETUezisJGtmIEKAcKUGWrjyssX0lvpsPKfqCe1GPKJnRAfLFg1iERDHHHp93f9QMST21I6c2UKJT4I+MHXL/Ogi7TOxmwxzqbX0OAGE10aBJ3xuv/4Gwe7m0C+LZj8Fcftgs/5YQotRuPL0YoC9z5sadS2JkRmK/GqUQ1y0Gw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782895737; c=relaxed/simple; bh=7+QyHXLZWIIqfYatInR7dyOy9r9Ly8G9bisg+Wx0E3I=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=jyCz18smGf7Oz2197+ZEEqNQoWGXpPZL6QRLk6BRf1SHsMCKikvYwcTSvX63TVdJMmqMYgc2NTs1zvsjztHjYlBbZIgI3mnyM6upAHbpzq2Sy597cfCvwCD8v66kMYEbxtPaqFHMLJIga4oSryVsXN/VyXnPItKK217TSwVMJgs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=ggCC8TGb; arc=none smtp.client-ip=91.218.175.177 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="ggCC8TGb" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1782895733; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=AyzKCBN3s9oeO1EVWFT/ClSVjk7GzsdBFf8WMlFESxc=; b=ggCC8TGbawNchQkwiPC4S7FSHw7Yu9r6rSQ/WYxEEiDkQGLPE4kWFEMAYuUFS2/j24n0fZ pbJ170kNzoDN+jkkkXK4bUTqdXiOIdxs/0QY0Gv0Iyu+S6FWGftMsUN8bPgRRkvDHoQgVR WwMuHMVMqg3aca7nBWwPAjXAjsFciI0= From: Atish Patra Date: Wed, 01 Jul 2026 01:47:07 -0700 Subject: [PATCH v8 19/22] tools/perf: Support event code for arch standard events Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260701-counter_delegation-v8-19-7909f863a645@meta.com> References: <20260701-counter_delegation-v8-0-7909f863a645@meta.com> In-Reply-To: <20260701-counter_delegation-v8-0-7909f863a645@meta.com> To: Jiri Olsa , Paul Walmsley , Mark Rutland , Rob Herring , Anup Patel , Namhyung Kim , Arnaldo Carvalho de Melo , Krzysztof Kozlowski , Atish Patra , Ian Rogers , Will Deacon , James Clark Cc: linux-arm-kernel@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-perf-users@vger.kernel.org, Conor Dooley X-Migadu-Flow: FLOW_OUT From: Atish Patra RISC-V relies on the event encoding from the json file. That includes arch standard events. If event code is present, event is already updated with correct encoding. No need to update it again which results in losing the event encoding. Signed-off-by: Atish Patra Reviewed-by: Ian Rogers --- tools/perf/pmu-events/arch/riscv/arch-standard.json | 10 ++++++++++ tools/perf/pmu-events/jevents.py | 9 ++++++++- 2 files changed, 18 insertions(+), 1 deletion(-) diff --git a/tools/perf/pmu-events/arch/riscv/arch-standard.json b/tools/pe= rf/pmu-events/arch/riscv/arch-standard.json new file mode 100644 index 000000000000..96e21f088558 --- /dev/null +++ b/tools/perf/pmu-events/arch/riscv/arch-standard.json @@ -0,0 +1,10 @@ +[ + { + "EventName": "cycles", + "BriefDescription": "cycle executed" + }, + { + "EventName": "instructions", + "BriefDescription": "instruction retired" + } +] diff --git a/tools/perf/pmu-events/jevents.py b/tools/perf/pmu-events/jeven= ts.py index 3a1bcdcdc685..0cf9d26315b3 100755 --- a/tools/perf/pmu-events/jevents.py +++ b/tools/perf/pmu-events/jevents.py @@ -413,7 +413,14 @@ class JsonEvent: self.long_desc =3D None if arch_std: if arch_std.lower() in _arch_std_events: - event =3D _arch_std_events[arch_std.lower()].event + # Inherit the arch-standard encoding only if this event defines no + # explicit encoding of its own. Events with explicit EventCode, + # ConfigCode, etc. may carry alternate encodings and appended modi= fiers + # that must survive. + if ('EventCode' not in jd and 'ExtSel' not in jd and + configcode is None and eventidcode is None and + legacy_hw_config is None and legacy_cache_config is None): + event =3D _arch_std_events[arch_std.lower()].event # Copy from the architecture standard event to self for undefined = fields. for attr, value in _arch_std_events[arch_std.lower()].__dict__.ite= ms(): if hasattr(self, attr) and not getattr(self, attr): --=20 2.53.0-Meta From nobody Thu Jul 16 17:05:11 2026 Received: from out-180.mta0.migadu.com (out-180.mta0.migadu.com [91.218.175.180]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0BC623F44EC for ; Wed, 1 Jul 2026 08:48:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.218.175.180 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782895740; cv=none; b=EZj+mI1UJbLj2diYACH7VpzLpY/X3jbGCChUP9BWOU0+CKl7jxpk2AUH3BXTQX0KrUtem0DrMcg+dV8s+0NVNBfUyUHETm8GTpj81y5HqzkwJxUNm0nFnKHGE2+pVdcEQlTu3Y5S2t7xN1SD/tpzOmGr2WydVXPMqWKrN1xJiwU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782895740; c=relaxed/simple; bh=yvZmsI+YKkyKcpQOntY3K3DA5Carxis58c2zbF7uL+o=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=JTo0Jtav3kLfREt4Xq117P+Qjk22be5MALPWuIAVetCDMaH7kAQqXik75nqWQfunRSizJmyCS5aTDSibYDAPcPagR2Pxh40tlElIVnrDsnpY1t6aP6Ha/Nwdbx3LASmpLQ2GMQShM0Jt6cCEz1vTsi9sGeTmk/EK/P4srntxb6Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=PVOo7ZBm; arc=none smtp.client-ip=91.218.175.180 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="PVOo7ZBm" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1782895737; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Vtg6gtjTXG/5kZ90vLQ3ZK8HeIu7FaVLNgb7sibmyzw=; b=PVOo7ZBmM6YIM0NolMjtxLKfchiQEr7jsQyDsVfx1ILzRodHDDodTu/+8yZ/a8/ZWI+xsS loVXakO8WmEY/K3R/2MI5d+kkGXuY6uZti8GYMEisHs+IN0qKtKhw3y1/G2iNRPhgF8yLE bNBxjuDWrFbO0ZnwwXQ3Rtp1dmB6abc= From: Atish Patra Date: Wed, 01 Jul 2026 01:47:08 -0700 Subject: [PATCH v8 20/22] tools/perf: Add RISC-V CounterIDMask event field Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260701-counter_delegation-v8-20-7909f863a645@meta.com> References: <20260701-counter_delegation-v8-0-7909f863a645@meta.com> In-Reply-To: <20260701-counter_delegation-v8-0-7909f863a645@meta.com> To: Jiri Olsa , Paul Walmsley , Mark Rutland , Rob Herring , Anup Patel , Namhyung Kim , Arnaldo Carvalho de Melo , Krzysztof Kozlowski , Atish Patra , Ian Rogers , Will Deacon , James Clark Cc: linux-arm-kernel@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-perf-users@vger.kernel.org, Conor Dooley X-Migadu-Flow: FLOW_OUT From: Atish Patra Counter delegation lets supervisor mode choose the hpmcounter for an event, but the hardware may only allow a given event on a subset of counters. Add a RISC-V specific "CounterIDMask" json event field, handled like the other arch-specific entries in event_fields[], that carries the allowed-counter bitmask through to the driver's existing counterid_mask (config2:0-31) format. The value is the bitmask directly so no counter-list to bitmask conversion is needed, and because the field is RISC-V specific it is a no-op for every other architecture's events (unlike the shared "Counter" field). Signed-off-by: Atish Patra Reviewed-by: Ian Rogers --- tools/perf/pmu-events/jevents.py | 1 + 1 file changed, 1 insertion(+) diff --git a/tools/perf/pmu-events/jevents.py b/tools/perf/pmu-events/jeven= ts.py index 0cf9d26315b3..516fb73886ed 100755 --- a/tools/perf/pmu-events/jevents.py +++ b/tools/perf/pmu-events/jevents.py @@ -396,6 +396,7 @@ class JsonEvent: ('EnAllSlices', 'enallslices=3D'), ('SliceId', 'sliceid=3D'), ('ThreadMask', 'threadmask=3D'), + ('CounterIDMask', 'counterid_mask=3D'), ] for key, value in event_fields: if key in jd and not is_zero(jd[key]): --=20 2.53.0-Meta From nobody Thu Jul 16 17:05:11 2026 Received: from out-173.mta0.migadu.com (out-173.mta0.migadu.com [91.218.175.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 96FBF3F0779 for ; Wed, 1 Jul 2026 08:49:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.218.175.173 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782895745; cv=none; b=ufsfOuhZjUxR+iyaDWY7Suf0/JWu0D680bSEGRTHq1bC1ogT46z/YAKyP/Rg6vDVgKQmBTzfUAenZArlGVN15m2AKA8v+5ytaQxtZ2GPNfGtwQZk9ojtvmi/V9lP/gGvY59fFt2DjnZaFr7Aj0oQ/yhV5NERw0SIkoihKmM+l78= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782895745; c=relaxed/simple; bh=TRQUQK1N1laVmfi+/z8Tzbr63EM/xjtFPowISmSkmco=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Swd8ZWHIIVsryzNVGxUnlKnhB+4PHAeuvXwGL8wF7532lqSWZ0muIa8bywNouiQoJksHuGK2W5QYdbisEUGAOPTNCl78BjpkuTvpuepTHQUO1xTaw2alcf+I/ymkvbuDrKOpCpTBlJObEEoyg6HVnqmJdJypn54bxK8y11uNAb4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=uiLH+Uh9; arc=none smtp.client-ip=91.218.175.173 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="uiLH+Uh9" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1782895740; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=S8V8xtoKAqPlqqdP66L19gg4AeWHREfPI94nLKFh6Tk=; b=uiLH+Uh9dSNQoPC8h35NhiprnhamkymjKrSZfhp5i7VWRDdYEQfxzf1+izxnVLZHjMPFdW Irb4Biq7+mvnafDeeOOeK+cLN8zFyvXbp+2h/MBYrmuZn6bRvcgDio4rKEq1dCP5yqytrR boC+/qSkoW2lzlnlYwySyWjT3Gviwc8= From: Atish Patra Date: Wed, 01 Jul 2026 01:47:09 -0700 Subject: [PATCH v8 21/22] TEST(do-not-upstream): fake qemu-virt PMU events for cdeleg counter-mask testing Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260701-counter_delegation-v8-21-7909f863a645@meta.com> References: <20260701-counter_delegation-v8-0-7909f863a645@meta.com> In-Reply-To: <20260701-counter_delegation-v8-0-7909f863a645@meta.com> To: Jiri Olsa , Paul Walmsley , Mark Rutland , Rob Herring , Anup Patel , Namhyung Kim , Arnaldo Carvalho de Melo , Krzysztof Kozlowski , Atish Patra , Ian Rogers , Will Deacon , James Clark Cc: linux-arm-kernel@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-perf-users@vger.kernel.org, Conor Dooley X-Migadu-Flow: FLOW_OUT From: Atish Patra Adds fake-any/fake-ctr3/fake-ctr34 (event codes 0xF0x QEMU doesn't model) w= ith counterid_masks, to exercise the counter-delegation allocation + counter-ma= sk constraint in QEMU (events read 0 =3D allocated/programmed, vs 'not support= ed'). Signed-off-by: Atish Patra --- drivers/perf/riscv_pmu_sbi.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index 6d528eafb525..725816c274e5 100644 --- a/drivers/perf/riscv_pmu_sbi.c +++ b/drivers/perf/riscv_pmu_sbi.c @@ -492,6 +492,12 @@ RVPMU_EVENT_CMASK_ATTR(instructions, instructions, 0x0= 2, 0xFFFFFFF8); RVPMU_EVENT_CMASK_ATTR(dTLB-load-misses, dTLB_load_miss, 0x10019, 0xFFFFFF= F8); RVPMU_EVENT_CMASK_ATTR(dTLB-store-misses, dTLB_store_miss, 0x1001B, 0xFFFF= FFF8); RVPMU_EVENT_CMASK_ATTR(iTLB-load-misses, iTLB_load_miss, 0x10021, 0xFFFFFF= F8); +/* + * FAKE events for cdeleg mechanism testing: event codes QEMU does NOT mod= el. + */ +RVPMU_EVENT_CMASK_ATTR(fake-any, fake_any, 0xF00, 0xFFFFFFF8); +RVPMU_EVENT_CMASK_ATTR(fake-ctr3, fake_ctr3, 0xF01, 0x8); +RVPMU_EVENT_CMASK_ATTR(fake-ctr34, fake_ctr34, 0xF02, 0x18); =20 static struct attribute *qemu_virt_event_group[] =3D { RVPMU_EVENT_ATTR_PTR(cycles), @@ -499,6 +505,9 @@ static struct attribute *qemu_virt_event_group[] =3D { RVPMU_EVENT_ATTR_PTR(dTLB_load_miss), RVPMU_EVENT_ATTR_PTR(dTLB_store_miss), RVPMU_EVENT_ATTR_PTR(iTLB_load_miss), + RVPMU_EVENT_ATTR_PTR(fake_any), + RVPMU_EVENT_ATTR_PTR(fake_ctr3), + RVPMU_EVENT_ATTR_PTR(fake_ctr34), NULL, }; =20 --=20 2.53.0-Meta From nobody Thu Jul 16 17:05:11 2026 Received: from out-184.mta0.migadu.com (out-184.mta0.migadu.com [91.218.175.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1C6B93F825B for ; Wed, 1 Jul 2026 08:49:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.218.175.184 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782895747; cv=none; b=RHIsbW02IyPzHescULdnWCy0/mEgY4HE64gqWInt46ST0rL4s4U7v02KSmimZOQ681Z4y+R4QrqWoEmqm1xCL0Vr2d2Jf75bGwVGKs5FUbAjDML15X88DeRaM8LMZV7Nrelk4EP3oOgv4eJ1q263EmZxOdA8CkGLc1CXy/i96g8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782895747; c=relaxed/simple; bh=rlr1JrpvEX5VV6u+bodY3ZJOPnTthq0L3jv7H/1JuPE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=L7n/sRHbHr8zdoExXSWeDA/YqYvPx2VLwkdowRMP6uHs66IqSIS41KE827hQDmuihaEnOAwlOg5R/Cn/bTI4PdNcs/M34Owt0l+uVM/dq0r13loFnp9n9WulCY00Ju1hFambXI2SxyIvltCqKohoD6xpNkej4yIVBFgmO6VcHaA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=idSR86bR; arc=none smtp.client-ip=91.218.175.184 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="idSR86bR" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1782895744; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=KM/aix7Aoq3ErthWJJhVZGT/lKJGUMSauEvdAp3MmGs=; b=idSR86bRfn7ZYGRhVuVR1igwFO20aocVs5vam+0JJ+tJGd448gZUIXXUlg9IrVOLUd/PTR /siamZ9g5fKUuv6zXvwXpewzO3GXbmLPwplqdsbJ8GESTvjSmemWFngNPwed43KRINxxvK trG53oCWbp07eerA/xgJ08iaxCOtdV8= From: Atish Patra Date: Wed, 01 Jul 2026 01:47:10 -0700 Subject: [PATCH v8 22/22] TEST(do-not-upstream): fake qemu vendor JSON + mapfile entry for CounterIDMask path Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260701-counter_delegation-v8-22-7909f863a645@meta.com> References: <20260701-counter_delegation-v8-0-7909f863a645@meta.com> In-Reply-To: <20260701-counter_delegation-v8-0-7909f863a645@meta.com> To: Jiri Olsa , Paul Walmsley , Mark Rutland , Rob Herring , Anup Patel , Namhyung Kim , Arnaldo Carvalho de Melo , Krzysztof Kozlowski , Atish Patra , Ian Rogers , Will Deacon , James Clark Cc: linux-arm-kernel@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-perf-users@vger.kernel.org, Conor Dooley X-Migadu-Flow: FLOW_OUT From: Atish Patra arch/riscv/qemu/virt/events.json: fake-json-{any,ctr3,ctr34,ctr6} with Even= tCode + CounterIDMask; mapfile.csv: 0x0-0x0-0x0 -> qemu/virt. Exercises jevents CounterIDMask -> counterid_mask=3D -> config2 -> cdeleg counter allocation. Signed-off-by: Atish Patra --- tools/perf/pmu-events/arch/riscv/mapfile.csv | 2 ++ .../pmu-events/arch/riscv/qemu/virt/events.json | 26 ++++++++++++++++++= ++++ 2 files changed, 28 insertions(+) diff --git a/tools/perf/pmu-events/arch/riscv/mapfile.csv b/tools/perf/pmu-= events/arch/riscv/mapfile.csv index 87cfb0e0849f..2fa3c3fd4663 100644 --- a/tools/perf/pmu-events/arch/riscv/mapfile.csv +++ b/tools/perf/pmu-events/arch/riscv/mapfile.csv @@ -24,3 +24,5 @@ 0x602-0x3-0x0,v1,openhwgroup/cva6,core 0x67e-0x80000000db0000[89]0-0x[[:xdigit:]]+,v1,starfive/dubhe-80,core 0x31e-0x8000000000008a45-0x[[:xdigit:]]+,v1,andes/ax45,core +0x0-0x0-0x0,v1,qemu/virt,core +0x0-0x2a-0x0,v1,qemu/virt,core diff --git a/tools/perf/pmu-events/arch/riscv/qemu/virt/events.json b/tools= /perf/pmu-events/arch/riscv/qemu/virt/events.json new file mode 100644 index 000000000000..294c4ed645f6 --- /dev/null +++ b/tools/perf/pmu-events/arch/riscv/qemu/virt/events.json @@ -0,0 +1,26 @@ +[ + { + "EventName": "fake-json-any", + "EventCode": "0xF10", + "CounterIDMask": "0xFFFFFFF8", + "BriefDescription": "FAKE json event (any hpmcounter 3-31) - QEMU does= not model 0xF10" + }, + { + "EventName": "fake-json-ctr3", + "EventCode": "0xF11", + "CounterIDMask": "0x8", + "BriefDescription": "FAKE json event constrained to hpmcounter3" + }, + { + "EventName": "fake-json-ctr34", + "EventCode": "0xF12", + "CounterIDMask": "0x18", + "BriefDescription": "FAKE json event constrained to hpmcounter3,4" + }, + { + "EventName": "fake-json-ctr6", + "EventCode": "0xF13", + "CounterIDMask": "0x40", + "BriefDescription": "FAKE json event constrained to hpmcounter6 (out o= f a small pmu-mask)" + } +] --=20 2.53.0-Meta