From nobody Sat Jul 11 18:16:52 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C5DE534F48A; Tue, 30 Jun 2026 09:36:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782812215; cv=none; b=YhEiGXtSPS10XQNR0dKetFwhpqgzakwbmLqm/MC7Ih1/UXK46j5GUz//O1/gLMAWAWpU/sOPfTZHF7Mo9xf4OJl8IBA+y7NavsXo4SpzqLAx+QLiENRRpdpAD6Wav9y0kDsbCImMQZFKG4mRk6Q6TYt0KAkH7JSuv27F0qiUViE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782812215; c=relaxed/simple; bh=2tAYpMSeO4bfNLswdXCh+ThWhi64GAwX9YYackqjnug=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=DExhC+sBvl3Go6k1k0tQdMBjV+fsl2CPYfTZmctibu3wQE1ry/cAZ9m9m/oxejqto+RGJlIpW90xJlXwem93xiUX24IkmfvYLal/0XIxWC96WdfwUJN1iGMUaKipRHIUvsbn9VFAwYU7OcXmR/UOST5UUMe/8KTK7RN6+Z+qpoA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=OCPPcgWj; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="OCPPcgWj" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1782812213; x=1814348213; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=2tAYpMSeO4bfNLswdXCh+ThWhi64GAwX9YYackqjnug=; b=OCPPcgWj6bxTfsY1IF3ScnjKrXg0quJ2qbMhMttUapV9zCADUeOnMh8p rvx3VRndSfecngWIAqc0VAwzW6z5GV8H0lw1VmDG5YRi8ebQq6OHOen2v Eyi3/NbSh3gk9/n4eiFrWbc1UHJDWQU+p86fWkqDrw4rWUP8+g7Ek+Jhu QgS45M0SKglHOumFjLcjCS7KwNrprg3/a9MRKldy2H6LRHrZ/oNGvl6p1 S0GA7yjJn0Z7xaDMWTs0t3/xabyaB5OIwFEQBbyWdILzsCbRDZpuQvXDd xG1qlMtYK5BWaSdxTdSVUhMNozoBXYNSK/mmpvrRfZKZQZ07yULS/iPgx Q==; X-CSE-ConnectionGUID: 2JXdgwFwQdOouRSaGB3M3A== X-CSE-MsgGUID: AsENgV2kR2OeB4vzjIHB8w== X-IronPort-AV: E=Sophos;i="6.24,233,1774335600"; d="scan'208";a="59032645" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Jun 2026 02:36:52 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.87.72) by chn-vm-ex3.mchp-main.com (10.10.87.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.2.2562.43; Tue, 30 Jun 2026 02:36:52 -0700 Received: from che-ll-i67070.microchip.com (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Tue, 30 Jun 2026 02:36:43 -0700 From: Varshini Rajendran To: , , , , , , , , , , , , , , , , , , , , , , , CC: Krzysztof Kozlowski Subject: [PATCH v3 01/13] dt-bindings: iio: adc: at91-sama5d2: document sama7d65 Date: Tue, 30 Jun 2026 15:05:51 +0530 Message-ID: <20260630093603.38663-2-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260630093603.38663-1-varshini.rajendran@microchip.com> References: <20260630093603.38663-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add dt-binding documentation for sama7d65 ADC. sama7d65 requires an individual compatible to address the differences from its predecessor sama7g5. The main difference is the temperature calibration layout and its handling. Signed-off-by: Varshini Rajendran Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/iio/adc/atmel,sama5d2-adc.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/iio/adc/atmel,sama5d2-adc.ya= ml b/Documentation/devicetree/bindings/iio/adc/atmel,sama5d2-adc.yaml index 4817b840977a..e8a65fdcd018 100644 --- a/Documentation/devicetree/bindings/iio/adc/atmel,sama5d2-adc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/atmel,sama5d2-adc.yaml @@ -15,6 +15,7 @@ properties: - atmel,sama5d2-adc - microchip,sam9x60-adc - microchip,sama7g5-adc + - microchip,sama7d65-adc =20 reg: maxItems: 1 --=20 2.34.1 From nobody Sat Jul 11 18:16:52 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9EB8734F48A; Tue, 30 Jun 2026 09:37:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782812223; cv=none; b=W9kMg9uEJLbmOMBiGhjca09lRiqtrwbIGx4SbASAWcmIeIyh6TWB0awJR3zXTg5LFXxeQHhI2xtNAOhKXWcgWfBZ5hjX3G+BXfQsh8n7zusKqf3G+hxNPWsNylorBNNVC/zw3ArEOEP52J4y4TDxZHOR0rSTgQYpTNcbp9Gg1nA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782812223; c=relaxed/simple; bh=b2HE2/l9IrpGvkPLNtqbKq6IrgROI2wKPVDiGDKGxTU=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=fPDdzfLQNrmJpGStpoO2ouqqradVrDVeq8QmJ0viQU7N6JiUeLNpUIPA8N5jbj1oULtgOKgOy8rtp5wwQEKWnL6jNApcMsK6x/SpinlJBYk8qlS7LZpYg8n5Ti6ikyIYUa8OeKe4bi7ULz7IRoIwGAGJga69SjT+aBD6bmlvhho= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=07X5LiZS; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="07X5LiZS" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1782812223; x=1814348223; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=b2HE2/l9IrpGvkPLNtqbKq6IrgROI2wKPVDiGDKGxTU=; b=07X5LiZSEDl4U/t0ZxepwYLyXpj1FV2ORiEm0Mq1cBM43RbkYvWb3feV IW6uDKZhObwBlW7xoAxE79EG3rw+pkn0JxDhsmkvNp1NHQ83x2WporDNn qFZXm/9qdoVXV8rYS+5WTgWvgk4wkVKUNnBm1a4hRsq9RnPDhaMKZ5UQD gfm6+qUEKAnQ208sgcaS7k4wB5I5Xe/Qm1n+dnhK5/Ts++JOBaHy1cE2v qK+gpls379rtUsGUJWWVe6tU/a9WQ5uNzCaznRaC0/IQ+V9QfgB5YQh5A 2ybez0TV3Gg/9teyL5csPLnN9iSJMdzrlTzMFC+j+GN4pWnqf9qo6Ndpv Q==; X-CSE-ConnectionGUID: ke3uW/xuQkuIIzeAFFBFjw== X-CSE-MsgGUID: qDgVRIxdS7WTrMiyOUgiuQ== X-IronPort-AV: E=Sophos;i="6.24,233,1774335600"; d="scan'208";a="291266929" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 30 Jun 2026 02:37:02 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.58; Tue, 30 Jun 2026 02:37:01 -0700 Received: from che-ll-i67070.microchip.com (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Tue, 30 Jun 2026 02:36:52 -0700 From: Varshini Rajendran To: , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v3 02/13] iio: adc: at91-sama5d2_adc: use cleanup.h for NVMEM buffer Date: Tue, 30 Jun 2026 15:05:52 +0530 Message-ID: <20260630093603.38663-3-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260630093603.38663-1-varshini.rajendran@microchip.com> References: <20260630093603.38663-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Use __free(kfree) cleanup helper for the NVMEM data buffer in at91_adc_temp_sensor_init() to simplify error handling paths. Since __free(kfree) requires a valid kfree-able pointer (not an ERR_PTR), store nvmem_cell_read() result in a temporary void pointer first, check for errors, then assign to the managed buffer. Signed-off-by: Varshini Rajendran Reviewed-by: Andy Shevchenko --- drivers/iio/adc/at91-sama5d2_adc.c | 21 +++++++++++---------- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/drivers/iio/adc/at91-sama5d2_adc.c b/drivers/iio/adc/at91-sama= 5d2_adc.c index 255970b2e747..5015c234289e 100644 --- a/drivers/iio/adc/at91-sama5d2_adc.c +++ b/drivers/iio/adc/at91-sama5d2_adc.c @@ -2251,9 +2251,10 @@ static int at91_adc_temp_sensor_init(struct at91_adc= _state *st, { struct at91_adc_temp_sensor_clb *clb =3D &st->soc_info.temp_sensor_clb; struct nvmem_cell *temp_calib; - u32 *buf; + u32 *buf __free(kfree) =3D NULL; + void *cell_data; size_t len; - int ret =3D 0; + int ret; =20 if (!st->soc_info.platform->temp_sensor) return 0; @@ -2267,16 +2268,18 @@ static int at91_adc_temp_sensor_init(struct at91_ad= c_state *st, return ret; } =20 - buf =3D nvmem_cell_read(temp_calib, &len); + cell_data =3D nvmem_cell_read(temp_calib, &len); nvmem_cell_put(temp_calib); - if (IS_ERR(buf)) { + if (IS_ERR(cell_data)) { dev_err(dev, "Failed to read calibration data!\n"); - return PTR_ERR(buf); + return PTR_ERR(cell_data); } + + buf =3D cell_data; + if (len < AT91_ADC_TS_CLB_IDX_MAX * 4) { dev_err(dev, "Invalid calibration data!\n"); - ret =3D -EINVAL; - goto free_buf; + return -EINVAL; } =20 /* Store calibration data for later use. */ @@ -2289,9 +2292,7 @@ static int at91_adc_temp_sensor_init(struct at91_adc_= state *st, */ clb->p1 =3D clb->p1 * 1000; =20 -free_buf: - kfree(buf); - return ret; + return 0; } =20 static int at91_adc_probe(struct platform_device *pdev) --=20 2.34.1 From nobody Sat Jul 11 18:16:52 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DA5C940D580; Tue, 30 Jun 2026 09:37:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782812233; cv=none; b=hj6LntFvJdEtSsD3N8AbbUCk9rMNsmOgr3x72lwVUSgoi93qGHWqE/AIy6YlZK0mn+6LKr8SfQ0bZ74RFPPMqDFqIk43Jm+9bxJrpU/y8TZFbkQSIe4/784VOMTqkhZnzCGhs8YDwuqWD1oElzfv9bpEk+XAi/5mDsmKmqGewyE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782812233; c=relaxed/simple; bh=HWjobEVV/DWB+4/iozjTvLRIIlCBYW8DxiEGCxnBV0o=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=T+sEttbJOaxnCGVKOWtwFii0S+S80zIQYOFQ3UHARbp8+I4b1dBBcGAu9xiEeNh7vcFf1iOJxQ3tQuJ13mK19iuKFZSes7BEBGoigKlGl42ZcNLdM70CS9ninHgwvA3SXTG6Cp5gg/HVZV7t75WM9yAxA8qodtZlbP9KxdIfNms= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=hFBZAE+W; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="hFBZAE+W" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1782812231; x=1814348231; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=HWjobEVV/DWB+4/iozjTvLRIIlCBYW8DxiEGCxnBV0o=; b=hFBZAE+WjRvrZJru+6CyXNXjiMZfWmHzk6SlhCpcsiqzyLgBNYRsgtdQ KzcKg2WaK0xuu2Ouq9JYOY01/PAmjbC49hTDsVy9wj5QrqAN1BE8h3cVO Mg+/Ct+b1/AfmFu2TZcDe+oG5BhNNG8t5I7z+PeQzRFaG9AaB2wP8JzIW 2hB8XFihy14iVqoXYpf2zpfsrf/2epSAaQ1k3b02We8su9P28HMVbTjMe WFpxb8ls9lRXfUeLGfl/KqidtuQUz4qBIu3G9NWyht04t47xe4MvgRRgr 67rqHspf4/S6nt8+Qs/hZ+vxmQcbhoKKI+8Q4pPiLTqkd71QEW7ClBXvS g==; X-CSE-ConnectionGUID: mOt5XWgTSauewdfaDrJZsg== X-CSE-MsgGUID: YU5tEAK9RcKIeSfUHSQw1g== X-IronPort-AV: E=Sophos;i="6.24,233,1774335600"; d="scan'208";a="59032660" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 30 Jun 2026 02:37:10 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.58; Tue, 30 Jun 2026 02:37:10 -0700 Received: from che-ll-i67070.microchip.com (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Tue, 30 Jun 2026 02:37:01 -0700 From: Varshini Rajendran To: , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v3 03/13] iio: adc: at91-sama5d2_adc: rework temp calibration layout handling Date: Tue, 30 Jun 2026 15:05:53 +0530 Message-ID: <20260630093603.38663-4-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260630093603.38663-1-varshini.rajendran@microchip.com> References: <20260630093603.38663-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Extend support to handle different temperature calibration layouts. Add a temperature calibration data layout structure to describe indexes of the factors P1, P4, P6, tag, minimum length of the packet and the scaling factors for P1 (mul, div) which are SoC-specific instead of the older non scalable id structure. This helps handle the differences in the same function flow and prepare the calibration data to be applied. Add additional condition to validate the calibration data read from the NVMEM cell using the TAG of the packet. Signed-off-by: Varshini Rajendran --- drivers/iio/adc/at91-sama5d2_adc.c | 67 ++++++++++++++++++++++-------- 1 file changed, 49 insertions(+), 18 deletions(-) diff --git a/drivers/iio/adc/at91-sama5d2_adc.c b/drivers/iio/adc/at91-sama= 5d2_adc.c index 5015c234289e..2a25165bc874 100644 --- a/drivers/iio/adc/at91-sama5d2_adc.c +++ b/drivers/iio/adc/at91-sama5d2_adc.c @@ -445,6 +445,29 @@ static const struct at91_adc_reg_layout sama7g5_layout= =3D { #define at91_adc_writel(st, reg, val) \ writel_relaxed(val, (st)->base + (st)->soc_info.platform->layout->reg) =20 +/* Temperature calibration tag "ACST" in ASCII */ +#define AT91_TEMP_CALIB_TAG_ACST 0x41435354 + +/** + * struct at91_adc_temp_calib_layout - temperature calibration packet layo= ut + * @tag_idx: index of Packet tag in the NVMEM cell buffer + * @p1_idx: index of FT1_TEMP, equivalent to P1 in the NVMEM cell buffer + * @p4_idx: index of FT1_VPAT, equivalent to P4 in the NVMEM cell buffer + * @p6_idx: index of FT2_VBG, equivalent to P6 in the NVMEM cell buffer + * @min_len: minimum number of u32 words expected in the NVMEM cell buffer + * @p1_mul: multiplier applied to P1 to convert to millicelcius + * @p1_div: divider applied to P1 to convert to millicelcius + */ +struct at91_adc_temp_calib_layout { + unsigned int tag_idx; + unsigned int p1_idx; + unsigned int p4_idx; + unsigned int p6_idx; + unsigned int min_len; + unsigned int p1_mul; + unsigned int p1_div; +}; + /** * struct at91_adc_platform - at91-sama5d2 platform information struct * @layout: pointer to the reg layout struct @@ -463,6 +486,7 @@ static const struct at91_adc_reg_layout sama7g5_layout = =3D { * @oversampling_avail_no: number of available oversampling values * @chan_realbits: realbits for registered channels * @temp_chan: temperature channel index + * @temp_calib_layout: temperature calibration packet layout * @temp_sensor: temperature sensor supported */ struct at91_adc_platform { @@ -480,6 +504,7 @@ struct at91_adc_platform { unsigned int oversampling_avail_no; unsigned int chan_realbits; unsigned int temp_chan; + const struct at91_adc_temp_calib_layout *temp_calib_layout; bool temp_sensor; }; =20 @@ -496,18 +521,14 @@ struct at91_adc_temp_sensor_clb { u32 p6; }; =20 -/** - * enum at91_adc_ts_clb_idx - calibration indexes in NVMEM buffer - * @AT91_ADC_TS_CLB_IDX_P1: index for P1 - * @AT91_ADC_TS_CLB_IDX_P4: index for P4 - * @AT91_ADC_TS_CLB_IDX_P6: index for P6 - * @AT91_ADC_TS_CLB_IDX_MAX: max index for temperature calibration packet = in OTP - */ -enum at91_adc_ts_clb_idx { - AT91_ADC_TS_CLB_IDX_P1 =3D 2, - AT91_ADC_TS_CLB_IDX_P4 =3D 5, - AT91_ADC_TS_CLB_IDX_P6 =3D 7, - AT91_ADC_TS_CLB_IDX_MAX =3D 19, +static const struct at91_adc_temp_calib_layout sama7g5_temp_calib =3D { + .tag_idx =3D 1, + .p1_idx =3D 2, + .p4_idx =3D 5, + .p6_idx =3D 7, + .min_len =3D 19, + .p1_mul =3D 1000, + .p1_div =3D 1, }; =20 /* Temperature sensor calibration - Vtemp voltage sensitivity to temperatu= re. */ @@ -745,6 +766,7 @@ static const struct at91_adc_platform sama7g5_platform = =3D { .chan_realbits =3D 16, .temp_sensor =3D true, .temp_chan =3D AT91_SAMA7G5_ADC_TEMP_CHANNEL, + .temp_calib_layout =3D &sama7g5_temp_calib, }; =20 static int at91_adc_chan_xlate(struct iio_dev *indio_dev, int chan) @@ -2250,6 +2272,7 @@ static int at91_adc_temp_sensor_init(struct at91_adc_= state *st, struct device *dev) { struct at91_adc_temp_sensor_clb *clb =3D &st->soc_info.temp_sensor_clb; + const struct at91_adc_temp_calib_layout *layout; struct nvmem_cell *temp_calib; u32 *buf __free(kfree) =3D NULL; void *cell_data; @@ -2259,6 +2282,10 @@ static int at91_adc_temp_sensor_init(struct at91_adc= _state *st, if (!st->soc_info.platform->temp_sensor) return 0; =20 + layout =3D st->soc_info.platform->temp_calib_layout; + if (!layout || !layout->p1_div) + return -EINVAL; + /* Get the calibration data from NVMEM. */ temp_calib =3D nvmem_cell_get(dev, "temperature_calib"); if (IS_ERR(temp_calib)) { @@ -2277,20 +2304,24 @@ static int at91_adc_temp_sensor_init(struct at91_ad= c_state *st, =20 buf =3D cell_data; =20 - if (len < AT91_ADC_TS_CLB_IDX_MAX * 4) { + if (len < layout->min_len * sizeof(*buf) || + buf[layout->tag_idx] !=3D AT91_TEMP_CALIB_TAG_ACST) { dev_err(dev, "Invalid calibration data!\n"); return -EINVAL; } =20 /* Store calibration data for later use. */ - clb->p1 =3D buf[AT91_ADC_TS_CLB_IDX_P1]; - clb->p4 =3D buf[AT91_ADC_TS_CLB_IDX_P4]; - clb->p6 =3D buf[AT91_ADC_TS_CLB_IDX_P6]; + clb->p1 =3D buf[layout->p1_idx]; + clb->p4 =3D buf[layout->p4_idx]; + clb->p6 =3D buf[layout->p6_idx]; =20 /* - * We prepare here the conversion to milli to avoid doing it on hotpath. + * Here we prepare the conversion to milli to avoid doing it on hotpath. + * The p1 value is multiplied and divided with a scaling factor as per + * the SoC storage format described by per-platform calibration layout. */ - clb->p1 =3D clb->p1 * 1000; + clb->p1 *=3D layout->p1_mul; + clb->p1 /=3D layout->p1_div; =20 return 0; } --=20 2.34.1 From nobody Sat Jul 11 18:16:52 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A5088382290; Tue, 30 Jun 2026 09:37:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782812241; cv=none; b=tp76SkWpPRVyJt4fBdwY6oGVgwShIbY/zdPBprKoz94WKIN5sKbCMEeOwev9sbOQy6zaA0GAYWrBs7xMsQ79Tb4RZUgWdUVfMNvfqqssXH+t4WMzwVPYMplByfrReymMNOi/SMYJ+4aeQd30NbOtPj0p0BZPIshrJLmUmW9Eqvk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782812241; c=relaxed/simple; bh=14iKVjIbPt4BXpZNPCTRWlVVhuV9b7Zz5uk1BB4yLSM=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=QwWUfrPDbIQMJoNursV9tZdyjx9mRd7+YopkWICZTkVWud/fliSp3tPh+Xv5L9krk12wsRVQggUNXPt2b44OSPophBsns22MWcpA/j6mJSbDVX+SLFgS1YDsxzUuZxmKmeHnsuLVyNI+TkRBtvVys9+qeY90HrKTk4gkEo9hLBA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=LeYg0r6o; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="LeYg0r6o" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1782812240; x=1814348240; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=14iKVjIbPt4BXpZNPCTRWlVVhuV9b7Zz5uk1BB4yLSM=; b=LeYg0r6o6J7pnoBntb07v5w6jovKmwhk3WbeuSe/WOGKitRzPrUxyG4K ZFrDudHFz9ImX8uxLF1DwFUBeZqT2pGZZMXBetPWATNqCpfNaZdLkpvsv kdnRLZPE9oCqotcPkUgWqR9JKNTqFxLj9AKg+lohdSmkQez08t1PEpue/ TQcbXqGDcgT0GU/uogf15tm3b45a8aUcMIDmFeuYMnpQCFjj3+tCMl060 fNbljJVDBOlySNu+zmIFZvVwMx/mR9q14GkCbI6gzmE0ro2ZfX+liQh5I gaGhebZ/t9aAw2uaVvltAdTJQKxRYhmlfZYCBI9aKW5k0gRZXolCuj2gu g==; X-CSE-ConnectionGUID: RYdOZI3+SAqAgq9+5DMc4A== X-CSE-MsgGUID: vt6FXm27SiOmsmupIS4Fkg== X-IronPort-AV: E=Sophos;i="6.24,233,1774335600"; d="scan'208";a="69114899" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Jun 2026 02:37:19 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.87.72) by chn-vm-ex3.mchp-main.com (10.10.87.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.2.2562.43; Tue, 30 Jun 2026 02:37:19 -0700 Received: from che-ll-i67070.microchip.com (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Tue, 30 Jun 2026 02:37:10 -0700 From: Varshini Rajendran To: , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v3 04/13] iio: adc: at91-sama5d2_adc: adapt the driver for sama7d65 Date: Tue, 30 Jun 2026 15:05:54 +0530 Message-ID: <20260630093603.38663-5-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260630093603.38663-1-varshini.rajendran@microchip.com> References: <20260630093603.38663-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for sama7d65 ADC. The differences are highlighted with the compatible. The calibration data layout is the main difference. Update Kconfig help text to mention SAMA7 SoC family support. Signed-off-by: Varshini Rajendran --- drivers/iio/adc/Kconfig | 2 +- drivers/iio/adc/at91-sama5d2_adc.c | 31 ++++++++++++++++++++++++++++++ 2 files changed, 32 insertions(+), 1 deletion(-) diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index a9dedbb8eb46..cf28755a6109 100644 --- a/drivers/iio/adc/Kconfig +++ b/drivers/iio/adc/Kconfig @@ -626,7 +626,7 @@ config AT91_SAMA5D2_ADC select IIO_TRIGGERED_BUFFER help Say yes here to build support for Atmel SAMA5D2 ADC which is - available on SAMA5D2 SoC family. + available on SAMA5D2 and SAMA7 SoC families. =20 To compile this driver as a module, choose M here: the module will be called at91-sama5d2_adc. diff --git a/drivers/iio/adc/at91-sama5d2_adc.c b/drivers/iio/adc/at91-sama= 5d2_adc.c index 2a25165bc874..7e3e347bb6a5 100644 --- a/drivers/iio/adc/at91-sama5d2_adc.c +++ b/drivers/iio/adc/at91-sama5d2_adc.c @@ -531,6 +531,16 @@ static const struct at91_adc_temp_calib_layout sama7g5= _temp_calib =3D { .p1_div =3D 1, }; =20 +static const struct at91_adc_temp_calib_layout sama7d65_temp_calib =3D { + .tag_idx =3D 1, + .p1_idx =3D 3, + .p4_idx =3D 2, + .p6_idx =3D 5, + .min_len =3D 11, + .p1_mul =3D 1, + .p1_div =3D 1000, +}; + /* Temperature sensor calibration - Vtemp voltage sensitivity to temperatu= re. */ #define AT91_ADC_TS_VTEMP_DT (2080U) =20 @@ -769,6 +779,24 @@ static const struct at91_adc_platform sama7g5_platform= =3D { .temp_calib_layout =3D &sama7g5_temp_calib, }; =20 +static const struct at91_adc_platform sama7d65_platform =3D { + .layout =3D &sama7g5_layout, + .adc_channels =3D &at91_sama7g5_adc_channels, + .nr_channels =3D AT91_SAMA7G5_SINGLE_CHAN_CNT + + AT91_SAMA7G5_DIFF_CHAN_CNT + + AT91_SAMA7G5_TEMP_CHAN_CNT, + .max_channels =3D ARRAY_SIZE(at91_sama7g5_adc_channels), + .max_index =3D AT91_SAMA7G5_MAX_CHAN_IDX, + .hw_trig_cnt =3D AT91_SAMA7G5_HW_TRIG_CNT, + .osr_mask =3D GENMASK(18, 16), + .oversampling_avail =3D { 1, 4, 16, 64, 256, }, + .oversampling_avail_no =3D 5, + .chan_realbits =3D 16, + .temp_sensor =3D true, + .temp_chan =3D AT91_SAMA7G5_ADC_TEMP_CHANNEL, + .temp_calib_layout =3D &sama7d65_temp_calib, +}; + static int at91_adc_chan_xlate(struct iio_dev *indio_dev, int chan) { int i; @@ -2639,6 +2667,9 @@ static const struct of_device_id at91_adc_dt_match[] = =3D { }, { .compatible =3D "microchip,sama7g5-adc", .data =3D (const void *)&sama7g5_platform, + }, { + .compatible =3D "microchip,sama7d65-adc", + .data =3D (const void *)&sama7d65_platform, }, { /* sentinel */ } --=20 2.34.1 From nobody Sat Jul 11 18:16:52 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AEE4A38B12B; Tue, 30 Jun 2026 09:37:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782812251; cv=none; b=WRrrTe/gIsESt2oFbLcdMZbihVwlmc/iQrKEGY4TPLQCkKh4oOmqWkb+i1FrBO4vK4tMzxhJKpKW1/p8uH60EWnQvwtsKFnAnRpnox5rc0nmSLHeYapSUZ0fDLhM4GTWAKAXogFztAXX+5CEmMWVUZPutN3ph5VBIKXhabWSnvg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782812251; c=relaxed/simple; bh=bCA8BUnUCacAeM9L4GkNBcOulMHRN3ZMV7gjy96hcXs=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=XFwvE2NaV5LYcyHkE64laAX9whd46oagt4fVl28XWkcnICGPRbyqkQC53lM4pNpqHWKnaNoWVhpvQTTjm0PjCzHb8cJ2GZNsLudR+VOoNjWxpeTN+fJ6s2ScIium+Get8cnUfCye0zWFaGh8kQFsJ7030FalkkeAroG1bopallc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=EPeVVrkx; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="EPeVVrkx" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1782812249; x=1814348249; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=bCA8BUnUCacAeM9L4GkNBcOulMHRN3ZMV7gjy96hcXs=; b=EPeVVrkxQ7bV++FYjKZeLGCchcbEVAgzn7rVkPyFh0QvMixpL0PtnGT2 P3FwAqE4oBIujfy9ZOSMgR2dk/fysDbPyLaLOjgfmbEgwWq7EiO66jc4r M8mPzeXTQVqR15trIYMrmbLBqUwQrc+pBfcfnmCNHInmcryRok4T6xDSS woOZIRZh0obZKFudXumJ7Tz5+bBWim9apCXid4vzcCptJOLKL9Fle6VvP NYOnr0MdIwVm5wlmBm1faYKBT3SicEXHGDuxMyIAK+SRp9mJ11R9uz87r B4LtiBLqaMwV7cZnKSoXxV5m0jKSycUIHeO00BJohOeWG4mIR8gq/GRd4 w==; X-CSE-ConnectionGUID: sN5DjNmgRiOIswaiaE7jxw== X-CSE-MsgGUID: 5cCVH5nJSvWr1o7IT9ZkwA== X-IronPort-AV: E=Sophos;i="6.24,233,1774335600"; d="scan'208";a="59032675" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 30 Jun 2026 02:37:28 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.58; Tue, 30 Jun 2026 02:37:28 -0700 Received: from che-ll-i67070.microchip.com (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Tue, 30 Jun 2026 02:37:19 -0700 From: Varshini Rajendran To: , , , , , , , , , , , , , , , , , , , , , , , CC: Conor Dooley Subject: [PATCH v3 05/13] dt-bindings: nvmem: microchip,sama7g5-otpc: add sama7d65 and dt node example Date: Tue, 30 Jun 2026 15:05:55 +0530 Message-ID: <20260630093603.38663-6-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260630093603.38663-1-varshini.rajendran@microchip.com> References: <20260630093603.38663-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for sama7d65 and a dt node example that shows tag can be used to reference a packet stored in the OTP memory. Signed-off-by: Varshini Rajendran Acked-by: Conor Dooley --- .../nvmem/microchip,sama7g5-otpc.yaml | 28 +++++++++++++++++-- 1 file changed, 25 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/nvmem/microchip,sama7g5-otpc= .yaml b/Documentation/devicetree/bindings/nvmem/microchip,sama7g5-otpc.yaml index cc25f2927682..04b44660554e 100644 --- a/Documentation/devicetree/bindings/nvmem/microchip,sama7g5-otpc.yaml +++ b/Documentation/devicetree/bindings/nvmem/microchip,sama7g5-otpc.yaml @@ -20,9 +20,15 @@ allOf: =20 properties: compatible: - items: - - const: microchip,sama7g5-otpc - - const: syscon + oneOf: + - items: + - const: microchip,sama7g5-otpc + - const: syscon + - items: + - enum: + - microchip,sama7d65-otpc + - const: microchip,sama7g5-otpc + - const: syscon =20 reg: maxItems: 1 @@ -48,4 +54,20 @@ examples: }; }; =20 + - | + efuse@e8c00000 { + compatible =3D "microchip,sama7d65-otpc", "microchip,sama7g5-otpc"= , "syscon"; + reg =3D <0xe8c00000 0x100>; + + nvmem-layout { + compatible =3D "fixed-layout"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + calib@41435354 { + reg =3D <0x41435354 0x2c>; /* Temp calib data packet TA= G */ + }; + }; + }; + ... --=20 2.34.1 From nobody Sat Jul 11 18:16:52 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 50C8735C190; Tue, 30 Jun 2026 09:37:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782812259; cv=none; b=Kyy3xoCT5aRj1motEgEk3fhss4IjIZ3BRnhCuGiIrg7cuY++UDaEtLMH9QJB6wuDtiE5lXTJYmPpsDzxvQeeLwX6ro2xZNMKnlSIVaAvdOWc4AejJDlF8OPtVITH/zgwvzjQAFHTVZ9Yp5xkxj87tYHUGdk1q//g6fw5w+LShVo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782812259; c=relaxed/simple; bh=o7wv8iNpD0SrjN1YDK0Po2BIvdzTGQE50pX3AAbBwEU=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=MpOZxNajdEq5VAC+J/s6RahU9kGROviUAx6jHE2AuYGjWRRDxeSNIqAFo0aNgnMcPpJ13dGKpFCkNYVMl3yPnPt9QOslYcUimgQxln+jwPq6Y3pVnXVQJp1sxNwESQU06E2Dh9oLfwDhCd2SxxtsHl0u48fRuot95ux/KMC3vOk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=lf4VqCfw; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="lf4VqCfw" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1782812258; x=1814348258; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=o7wv8iNpD0SrjN1YDK0Po2BIvdzTGQE50pX3AAbBwEU=; b=lf4VqCfwXfZAjWs3wGm8S3SCVtcITy7hjdDJ5ecwbYpJysczb0Itij1B 1fv3MYMfHH39bJ5BpHAb6PlekN3NeAzpObiuKxsVU2lVBQaDOINzsQixL VnjLX+JJSyA0U0bND5zL2tiAA25D61EiY+HoE9hXzy9i7Se0AGBkTRhzF fWoGjcAVbzBXzHpaQwnhCUTfvTczUc9ZrtoLw0EQiLwm93S7CiPc4JAOQ kpkhNc9q7WtnPhyFpHiR9Tddrd8VaJnXa+ApGNkR1Aoqr+7pnrK+jiVo9 p7zpZv5kvkewe61JuQ6thuNX3DFG7TEObTvhv7pXtK45hqvI40/ahz3CU w==; X-CSE-ConnectionGUID: rJT7i00AStqBvu9gGiugIw== X-CSE-MsgGUID: MNjLtfyGQ+yOIElKU1h07g== X-IronPort-AV: E=Sophos;i="6.24,233,1774335600"; d="scan'208";a="59880480" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 30 Jun 2026 02:37:37 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.58; Tue, 30 Jun 2026 02:37:37 -0700 Received: from che-ll-i67070.microchip.com (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Tue, 30 Jun 2026 02:37:28 -0700 From: Varshini Rajendran To: , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v3 06/13] nvmem: microchip-otpc: add tag-based packet lookup Date: Tue, 30 Jun 2026 15:05:56 +0530 Message-ID: <20260630093603.38663-7-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260630093603.38663-1-varshini.rajendran@microchip.com> References: <20260630093603.38663-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for accessing OTP packets by their 4-byte ASCII tag while preserving backward compatibility with the existing ID-based lookup. The OTP memory layout can vary across devices and may change over time, making the packet ID approach unreliable when the memory map is not known in advance. The packet tag provides a reliable way to identify and access packets without prior knowledge of the OTP memory layout. Two offset encoding are now supported: 1. Legacy ID-based: offset =3D OTP_PKT(id) =3D id * 4 Used in DT as: reg =3D ; 2. TAG-based: offset =3D 4-byte ASCII packet tag Used in DT as: reg =3D <0x41435354 0x4c>; (tag "ACST") The driver resolves offsets matching valid legacy selectors (multiples of 4 within the packet count) through ID lookup, falling back to tag lookup for other values. This ensures existing device trees continue to work while enabling new tag-based access. During probe, packet meta data including the tag is read and cached. The driver also validates OTP memory accessibility and emulation mode status. When the boot packet is not configured, emulation mode allows access to the other packets. When both are not available an informational message is logged. The stride of the nvmem memory is set to 1 in order to support tag based offsets, comment in the header file is updated accordingly. Signed-off-by: Varshini Rajendran --- drivers/nvmem/microchip-otpc.c | 143 ++++++++++++++++-- .../nvmem/microchip,sama7g5-otpc.h | 4 +- 2 files changed, 136 insertions(+), 11 deletions(-) diff --git a/drivers/nvmem/microchip-otpc.c b/drivers/nvmem/microchip-otpc.c index df979e8549fd..bf8589048e17 100644 --- a/drivers/nvmem/microchip-otpc.c +++ b/drivers/nvmem/microchip-otpc.c @@ -18,16 +18,20 @@ #define MCHP_OTPC_CR_READ BIT(6) #define MCHP_OTPC_MR (0x4) #define MCHP_OTPC_MR_ADDR GENMASK(31, 16) +#define MCHP_OTPC_MR_EMUL BIT(7) #define MCHP_OTPC_AR (0x8) #define MCHP_OTPC_SR (0xc) #define MCHP_OTPC_SR_READ BIT(6) #define MCHP_OTPC_HR (0x20) #define MCHP_OTPC_HR_SIZE GENMASK(15, 8) +#define MCHP_OTPC_HR_PACKET_TYPE GENMASK(2, 0) #define MCHP_OTPC_DR (0x24) =20 #define MCHP_OTPC_NAME "mchp-otpc" #define MCHP_OTPC_SIZE (11 * 1024) =20 +#define PACKET_TYPE_REGULAR 1 + /** * struct mchp_otpc - OTPC private data structure * @base: base address @@ -47,11 +51,15 @@ struct mchp_otpc { * @list: list head * @id: packet ID * @offset: packet offset (in words) in OTP memory + * @type: type of the packet + * @tag: 4-byte ASCII tag of the packet */ struct mchp_otpc_packet { struct list_head list; u32 id; u32 offset; + u32 type; + u32 tag; }; =20 static struct mchp_otpc_packet *mchp_otpc_id_to_packet(struct mchp_otpc *o= tpc, @@ -70,6 +78,56 @@ static struct mchp_otpc_packet *mchp_otpc_id_to_packet(s= truct mchp_otpc *otpc, return NULL; } =20 +/** + * mchp_otpc_tag_to_packet() - find packet by tag + * @otpc: OTPC private data + * @tag: 4-byte ASCII tag to search for + * + * Return: pointer to packet if found, NULL otherwise + */ +static struct mchp_otpc_packet *mchp_otpc_tag_to_packet(struct mchp_otpc *= otpc, + u32 tag) +{ + struct mchp_otpc_packet *packet; + + list_for_each_entry(packet, &otpc->packets, list) { + if (packet->tag =3D=3D tag) + return packet; + } + + return NULL; +} + +/** + * mchp_otpc_resolve_packet() - resolve offset to packet + * @otpc: OTPC private data + * @off: NVMEM offset (legacy ID-based or TAG-based) + * + * Legacy offsets (multiples of 4 within valid ID range) are resolved + * through ID lookup. Other offsets are treated as 4-byte ASCII tags. + * + * Return: pointer to packet if found, NULL otherwise + */ +static struct mchp_otpc_packet *mchp_otpc_resolve_packet(struct mchp_otpc = *otpc, + u32 off) +{ + /* + * Legacy id based packet access: offset =3D id * 4 + * Inside the driver we use continuous unsigned integer numbers + * for packet id, thus divide off by 4 before passing it to + * mchp_otpc_id_to_packet(). + */ + u32 id =3D off / 4; + + if (!(off % 4) && id < otpc->npackets) + return mchp_otpc_id_to_packet(otpc, id); + + /* + * TAG-based packet access: offset is a 4-byte ASCII tag + */ + return mchp_otpc_tag_to_packet(otpc, off); +} + static int mchp_otpc_prepare_read(struct mchp_otpc *otpc, unsigned int offset) { @@ -140,8 +198,29 @@ static int mchp_otpc_prepare_read(struct mchp_otpc *ot= pc, * offset returned by hardware. * * For this, the read function will return the first requested bytes in the - * packet. The user will have to be aware of the memory footprint before d= oing - * the read request. + * packet. + * + * Two offset encoding are supported: + * + * 1. Legacy ID-based: offset =3D OTP_PKT(id) =3D id * 4 + * Used in DT as: reg =3D ; + * 2. TAG-based: offset =3D 4-byte ASCII packet tag + * Used in DT as: reg =3D <0x41435354 0x4c>; (tag "ACST") + * + * To use the legacy ID based packet lookup the user will have to be aware= of + * the memory footprint before doing the read request. + * + * But by using the TAG based packet lookup, the user won't have to be awa= re + * of the memory footprint before doing the read request since this driver= has + * it abstracted and taken care of. + * + * Practically, there is no way of knowing the mapping of the OTP memory t= able + * in advance for every device. But by using the packet tag - the identifi= er + * ASCII value, the packets can be recognized without being aware of the + * flashed OTP memory map table and the payload can be acquired reliably. + * + * While the legacy ID based lookup is still supported, TAG based approach= is + * recommended. */ static int mchp_otpc_read(void *priv, unsigned int off, void *val, size_t bytes) @@ -154,12 +233,11 @@ static int mchp_otpc_read(void *priv, unsigned int of= f, void *val, int ret, payload_size; =20 /* - * We reach this point with off being multiple of stride =3D 4 to - * be able to cross the subsystem. Inside the driver we use continuous - * unsigned integer numbers for packet id, thus divide off by 4 - * before passing it to mchp_otpc_id_to_packet(). + * From this point the offset has to be translated into the actual + * packet. For this we traverse the table of contents stored in a list + * "packet" based on the access type - packet id or tag. */ - packet =3D mchp_otpc_id_to_packet(otpc, off / 4); + packet =3D mchp_otpc_resolve_packet(otpc, off); if (!packet) return -EINVAL; offset =3D packet->offset; @@ -190,6 +268,29 @@ static int mchp_otpc_read(void *priv, unsigned int off= , void *val, return 0; } =20 +/** + * mchp_otpc_read_packet_tag() - read tag from packet payload + * @otpc: OTPC private data + * @offset: packet offset in OTP memory + * @val: pointer to store the tag value + * + * Return: 0 on success, negative errno on failure + */ +static int mchp_otpc_read_packet_tag(struct mchp_otpc *otpc, unsigned int = offset, + unsigned int *val) +{ + int ret; + + ret =3D mchp_otpc_prepare_read(otpc, offset); + if (ret) + return ret; + + writel_relaxed(0, otpc->base + MCHP_OTPC_AR); + *val =3D readl_relaxed(otpc->base + MCHP_OTPC_DR); + + return 0; +} + static int mchp_otpc_init_packets_list(struct mchp_otpc *otpc, u32 *size) { struct mchp_otpc_packet *packet; @@ -215,6 +316,17 @@ static int mchp_otpc_init_packets_list(struct mchp_otp= c *otpc, u32 *size) =20 packet->id =3D id++; packet->offset =3D word_pos; + packet->type =3D FIELD_GET(MCHP_OTPC_HR_PACKET_TYPE, word); + + if (packet->type =3D=3D PACKET_TYPE_REGULAR) { + ret =3D mchp_otpc_read_packet_tag(otpc, packet->offset, + &packet->tag); + if (ret) + return ret; + } else { + packet->tag =3D 0; + } + INIT_LIST_HEAD(&packet->list); list_add_tail(&packet->list, &otpc->packets); =20 @@ -236,7 +348,7 @@ static struct nvmem_config mchp_nvmem_config =3D { .type =3D NVMEM_TYPE_OTP, .read_only =3D true, .word_size =3D 4, - .stride =3D 4, + .stride =3D 1, .reg_read =3D mchp_otpc_read, }; =20 @@ -244,7 +356,8 @@ static int mchp_otpc_probe(struct platform_device *pdev) { struct nvmem_device *nvmem; struct mchp_otpc *otpc; - u32 size; + bool emul_enable; + u32 size, tmp; int ret; =20 otpc =3D devm_kzalloc(&pdev->dev, sizeof(*otpc), GFP_KERNEL); @@ -256,10 +369,22 @@ static int mchp_otpc_probe(struct platform_device *pd= ev) return PTR_ERR(otpc->base); =20 otpc->dev =3D &pdev->dev; + + tmp =3D readl_relaxed(otpc->base + MCHP_OTPC_MR); + emul_enable =3D tmp & MCHP_OTPC_MR_EMUL; + if (emul_enable) + dev_info(otpc->dev, "Emulation mode enabled\n"); + ret =3D mchp_otpc_init_packets_list(otpc, &size); if (ret) return ret; =20 + if (!size) { + dev_warn(otpc->dev, "Cannot access OTP memory\n"); + if (!emul_enable) + dev_info(otpc->dev, "Boot packet not programmed and emulation mode disa= bled\n"); + } + mchp_nvmem_config.dev =3D otpc->dev; mchp_nvmem_config.add_legacy_fixed_of_cells =3D true; mchp_nvmem_config.size =3D size; diff --git a/include/dt-bindings/nvmem/microchip,sama7g5-otpc.h b/include/d= t-bindings/nvmem/microchip,sama7g5-otpc.h index f570b23165a2..5f72e75ad091 100644 --- a/include/dt-bindings/nvmem/microchip,sama7g5-otpc.h +++ b/include/dt-bindings/nvmem/microchip,sama7g5-otpc.h @@ -4,8 +4,8 @@ #define _DT_BINDINGS_NVMEM_MICROCHIP_OTPC_H =20 /* - * Need to have it as a multiple of 4 as NVMEM memory is registered with - * stride =3D 4. + * Need to have it as a multiple of 4 for the legacy id based packet + * access. */ #define OTP_PKT(id) ((id) * 4) =20 --=20 2.34.1 From nobody Sat Jul 11 18:16:52 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A0D9B3955EB; Tue, 30 Jun 2026 09:37:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782812268; cv=none; b=IWy48V9BcTiisNYXylAxnIoxXj3qQe2DQV0ijgjcJEykzVjFagj0blWswtQ05npH/+sbK1xNDOxK/4DmiQtOGRpiQmQuAhxGj+cgxvSWDVzJsM4TVdSNrLWGjlRWCl3eL11as7bKq38BetPmCXCHkADyIlUKt4kYrqL5eGZO3CU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782812268; c=relaxed/simple; bh=xo5iwXFK0E9pHQdJ+Y5ZSzvvpbR4uPF2/cc1u7E9VuE=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=NARK7kVUFN5ub8/EGSS2uxmvXaWPqYPTCpHq19DGjoOMWYuebiI3oqduWqmkjxSD0C0K+tGwQewfAReAxqCyAFMEHPnYWdYvzy9auX58+yEOphCKrQyRS1zDsmg5w/zQsRjDxau5FCW5zIB+uYfpSQJZ7i4ott6vqqQSAvqZezE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=1zsTCZal; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="1zsTCZal" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1782812267; x=1814348267; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=xo5iwXFK0E9pHQdJ+Y5ZSzvvpbR4uPF2/cc1u7E9VuE=; b=1zsTCZalU2sZ0H+l/e4QU5JIkYk4IIk/h3s+yHTu6MGsxp1eaw/vAw6g 80chB6ptqwG4T27sdCfagB91sBo/ISyvLC9m+KMWkAIgNyJWabLS64dxw BPQIDNhbkK+oZ2bDefZRNbJ/0HxYbTdfKpkXUMXZeci7GP5TlLbl6D0V1 5QwNVwMrUoknWjagCWsQT1uZyAFoUALyuTaUmIpuUPCUaVWWqGG4WBVsK ypad192JMnJleuu5Dd7QWQwqwz6hH0S1wF1iO75yivmaxkiwKtMH9vUJJ SKlESpefDd3X8r6WHawtOp+ZM/kRr7hnNFwD8z63dg52ZYMHhiFLiYgyq A==; X-CSE-ConnectionGUID: 5NSbx0ugQlGUH4HUi6SY8Q== X-CSE-MsgGUID: +jhzn51+QtmI8wL9vHWJMg== X-IronPort-AV: E=Sophos;i="6.24,233,1774335600"; d="scan'208";a="60234280" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Jun 2026 02:37:47 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.87.72) by chn-vm-ex4.mchp-main.com (10.10.87.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.2.2562.43; Tue, 30 Jun 2026 02:37:46 -0700 Received: from che-ll-i67070.microchip.com (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Tue, 30 Jun 2026 02:37:37 -0700 From: Varshini Rajendran To: , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v3 07/13] ARM: dts: microchip: sama7d65: add cpu opps Date: Tue, 30 Jun 2026 15:05:57 +0530 Message-ID: <20260630093603.38663-8-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260630093603.38663-1-varshini.rajendran@microchip.com> References: <20260630093603.38663-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add CPU OPPs table for SAMA7D65. Signed-off-by: Varshini Rajendran --- arch/arm/boot/dts/microchip/sama7d65.dtsi | 36 +++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/= microchip/sama7d65.dtsi index 67253bbc08df..94d49e20dc79 100644 --- a/arch/arm/boot/dts/microchip/sama7d65.dtsi +++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi @@ -35,6 +35,7 @@ cpu0: cpu@0 { d-cache-size =3D <0x8000>; // L1, 32 KB i-cache-size =3D <0x8000>; // L1, 32 KB next-level-cache =3D <&L2>; + operating-points-v2 =3D <&cpu_opp_table>; =20 L2: l2-cache { compatible =3D "cache"; @@ -45,6 +46,41 @@ L2: l2-cache { }; }; =20 + cpu_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-90000000 { + opp-hz =3D /bits/ 64 <90000000>; + opp-microvolt =3D <1050000 1050000 1225000>; + clock-latency-ns =3D <320000>; + }; + + opp-250000000 { + opp-hz =3D /bits/ 64 <250000000>; + opp-microvolt =3D <1050000 1050000 1225000>; + clock-latency-ns =3D <320000>; + }; + + opp-600000000 { + opp-hz =3D /bits/ 64 <600000000>; + opp-microvolt =3D <1050000 1050000 1225000>; + clock-latency-ns =3D <320000>; + opp-suspend; + }; + + opp-800000000 { + opp-hz =3D /bits/ 64 <800000000>; + opp-microvolt =3D <1150000 1125000 1225000>; + clock-latency-ns =3D <320000>; + }; + + opp-1000000002 { + opp-hz =3D /bits/ 64 <1000000002>; + opp-microvolt =3D <1250000 1225000 1300000>; + clock-latency-ns =3D <320000>; + }; + }; + clocks { main_xtal: clock-mainxtal { compatible =3D "fixed-clock"; --=20 2.34.1 From nobody Sat Jul 11 18:16:52 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A081A3839B8; Tue, 30 Jun 2026 09:37:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782812277; cv=none; b=EXYJFWhS5yVpp1SaDHOEjo48NTRt0VuOwu36MnXd309ie9EDFdWcm6hv3WQ5ZU3eVRfrTXH6566RJJ30VE2gdo7DilWydyarNnskd95NfTK25VBG9p/oTyzR7iPlhFDXKf4WdLytjLhwTbipiWuOmiPgJzPuU50XF/4tA2MGdm0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782812277; c=relaxed/simple; bh=VYa8ctdp7N3lTNfwD0/Ow13u6f6KsP6v25kYxxUXsQU=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=GmQ5/1i5XZNFnxUZTiKK6oAaNVUeQ/D2gxOU4kdnm9M3y4r7UkNavLCxeikK4a0C9cgCT8aqZRa5lyOtUSKjge4lDqSAsK+znvzfBxuu/P8SJqEzoVpvA2OxJMmnhBeFBndvqgJlD2DAbpFyl1yfaND/lMofC6vGIyXw7w0lV5U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=pt6OTVoU; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="pt6OTVoU" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1782812276; x=1814348276; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=VYa8ctdp7N3lTNfwD0/Ow13u6f6KsP6v25kYxxUXsQU=; b=pt6OTVoUCoboe0wHFnLBM+Iuqv78I5o+DsM+B5faaUWOMBblKYyxCIkW rCMzjGZYmW8HK0KCDqFlreM5hQebMUCCX6+m/+QTrXNyiw0g5F/EsLnwJ NEAUu3aMY6xXVdHRG394KyK7KfSFhluug+fPac3vJAzV0PiuHUBR74f+a Ezer0Xud3kZeJk1dhThKuOouHszsXU8fAVbxNthtESKVTlZvL+vB9/nCC 2Je8AM0dqwxOXlbgNKs3x9xsDMN00AaT+xvdJIpM4W6rwBkUEqAvwe8Ke 4qnPp5QAWwK1PL5E7p3HzEqRDYcvs7at08AC2lK6TWSn/awsOxjNEXnHs A==; X-CSE-ConnectionGUID: r7IxPp4ATMyUQX/fgWZgwQ== X-CSE-MsgGUID: mG5scDYFQJCBfGSDZZww/w== X-IronPort-AV: E=Sophos;i="6.24,233,1774335600"; d="scan'208";a="59032695" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Jun 2026 02:37:55 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.87.72) by chn-vm-ex4.mchp-main.com (10.10.87.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.2.2562.43; Tue, 30 Jun 2026 02:37:55 -0700 Received: from che-ll-i67070.microchip.com (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Tue, 30 Jun 2026 02:37:46 -0700 From: Varshini Rajendran To: , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v3 08/13] ARM: dts: microchip: sama7d65: Add ADC node Date: Tue, 30 Jun 2026 15:05:58 +0530 Message-ID: <20260630093603.38663-9-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260630093603.38663-1-varshini.rajendran@microchip.com> References: <20260630093603.38663-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add node for the ADC controller in sama7d65 SoC. Add the vddout25 fixed regulator node which provides the 2.5V reference voltage for the ADC. Signed-off-by: Varshini Rajendran --- arch/arm/boot/dts/microchip/sama7d65.dtsi | 29 +++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/= microchip/sama7d65.dtsi index 94d49e20dc79..ba775459a816 100644 --- a/arch/arm/boot/dts/microchip/sama7d65.dtsi +++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -95,6 +96,16 @@ slow_xtal: clock-slowxtal { }; }; =20 + vddout25: fixed-regulator-vddout25 { + compatible =3D "regulator-fixed"; + + regulator-name =3D "VDDOUT25"; + regulator-min-microvolt =3D <2500000>; + regulator-max-microvolt =3D <2500000>; + regulator-boot-on; + status =3D "disabled"; + }; + ns_sram: sram@100000 { compatible =3D "mmio-sram"; reg =3D <0x100000 0x20000>; @@ -296,6 +307,24 @@ can4: can@e0838000 { status =3D "disabled"; }; =20 + adc: adc@e1000000 { + compatible =3D "microchip,sama7d65-adc"; + reg =3D <0xe1000000 0x200>; + interrupts =3D ; + clocks =3D <&pmc PMC_TYPE_GCK 25>; + assigned-clocks =3D <&pmc PMC_TYPE_GCK 25>; + assigned-clock-rates =3D <100000000>; + clock-names =3D "adc_clk"; + dmas =3D <&dma0 AT91_XDMAC_DT_PERID(0)>; + dma-names =3D "rx"; + atmel,min-sample-rate-hz =3D <200000>; + atmel,max-sample-rate-hz =3D <20000000>; + atmel,trigger-edge-type =3D ; + atmel,startup-time-ms =3D <4>; + #io-channel-cells =3D <1>; + status =3D "disabled"; + }; + dma2: dma-controller@e1200000 { compatible =3D "microchip,sama7d65-dma", "microchip,sama7g5-dma"; reg =3D <0xe1200000 0x1000>; --=20 2.34.1 From nobody Sat Jul 11 18:16:52 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F278D3B42D1; Tue, 30 Jun 2026 09:38:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782812286; cv=none; b=nJwbdrpWfT7FDc7LmmYhgvhKUlhzlYlGaEEy55WjW1vHfiB6ks3gtu/FlMSP1xqel9FJ3AxhRwikEYGywoRDaO7wvR2XarsGhrcCJrSGqpqyt+FvkOCkVwJlyL3+RM+p4khbmaG7Ac912Tx9SP8x1BSraWV5HjdBY6wc3MsWFgE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782812286; c=relaxed/simple; bh=vyyTTSbuj5h3Q9OgBsXCtnnt+Yw0U/fLWgoQLk2IQLk=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=NiCeCp//I7Jf5y+NmAv7kMgHfLeFbCORnNO99o2pBnasEa9mhUrR7PeTaRRr0eFdCRZx4IO0uEhLHS1KpedM5xiTJgaQeNo4yOcy9/NwpyfJyyldsFxlvpiWnCIf+todL3V5i8YlqOC4fI/NFsiAUn/hiM0mis7t5zb+ZmddBSo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=shgLOXZE; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="shgLOXZE" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1782812284; x=1814348284; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=vyyTTSbuj5h3Q9OgBsXCtnnt+Yw0U/fLWgoQLk2IQLk=; b=shgLOXZEZxI9ybM/8X/VoOE7dECSoQgkR9PDUXej0SxhpAkIQIkcle1u 28rpG1Z7yIC4R0jurzotaRR0LeQHTW/xqUcUE3/9ZcESEixaCpcTSs8rv Ub0FswnEzApJ8wtpQvzovwDrc+WSs5Gbd1dLJqepdzawZgHFeDDXDzCas EjzHbABuLNYjVRctQXLGlIBk9+TfQxM/VK7/z30pyvGIPUhTtHh6QYQFZ UR3ewxULhe73VW6I70IP4cCCWY0ArNNPPdIj8npxf9dfHmB5AiYZGr4ea dzjag7neG9Uk//bR4X7wt5GlrBUAZwIKV2BYcwS0huSP1K8B0p5MaKAmj Q==; X-CSE-ConnectionGUID: lmxtWMPfT9qZ8eisWbDhNg== X-CSE-MsgGUID: 4ZgRZ3I9Sl2FVcUhaLvleA== X-IronPort-AV: E=Sophos;i="6.24,233,1774335600"; d="scan'208";a="227053725" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Jun 2026 02:38:03 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.87.72) by chn-vm-ex4.mchp-main.com (10.10.87.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.2.2562.43; Tue, 30 Jun 2026 02:38:03 -0700 Received: from che-ll-i67070.microchip.com (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Tue, 30 Jun 2026 02:37:55 -0700 From: Varshini Rajendran To: , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v3 09/13] ARM: dts: microchip: sama7d65_curiosity: Enable ADC, DVFS Date: Tue, 30 Jun 2026 15:05:59 +0530 Message-ID: <20260630093603.38663-10-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260630093603.38663-1-varshini.rajendran@microchip.com> References: <20260630093603.38663-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add regulator, pinmux and enable ADC for sama7d65 curiosity. Add cpu-supply regulator for DVFS. Signed-off-by: Varshini Rajendran --- .../dts/microchip/at91-sama7d65_curiosity.dts | 27 +++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts b/arch= /arm/boot/dts/microchip/at91-sama7d65_curiosity.dts index 927c27260b6c..c2d1e5308170 100644 --- a/arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts +++ b/arch/arm/boot/dts/microchip/at91-sama7d65_curiosity.dts @@ -79,6 +79,14 @@ reg_5v: regulator-5v { }; }; =20 +&adc { + vddana-supply =3D <&vddout25>; + vref-supply =3D <&vddout25>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_adc_default &pinctrl_adtrg_default>; + status =3D "okay"; +}; + &can1 { pinctrl-names =3D "default"; pinctrl-0 =3D <&pinctrl_can1_default>; @@ -97,6 +105,10 @@ &can3 { status =3D "okay"; }; =20 +&cpu0 { + cpu-supply =3D <&vddcpu>; +}; + &dma0 { status =3D "okay"; }; @@ -334,6 +346,16 @@ &main_xtal { }; =20 &pioa { + pinctrl_adc_default: adc-default { + pinmux =3D ; + bias-disable; + }; + + pinctrl_adtrg_default: adtrg-default { + pinmux =3D ; + bias-pull-up; + }; + pinctrl_can1_default: can1-default { pinmux =3D , ; @@ -457,3 +479,8 @@ input@0 { &slow_xtal { clock-frequency =3D <32768>; }; + +&vddout25 { + vin-supply =3D <&vdd_3v3>; + status =3D "okay"; +}; --=20 2.34.1 From nobody Sat Jul 11 18:16:52 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4A6FF38E8B4; Tue, 30 Jun 2026 09:38:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782812294; cv=none; b=EBmue8cW30x96BH0FjtZNFKEw8TaQDo/XLr/sVWmif6DLxjQ641h/LsDAiqZensn3Q8/6eU/2eUnYfXfT1RWIkzoCmD9BreBKPibZW5xe45Ctdxi1L25rMAKvvB/Q/EBpu3OvuVDb2plS5UJDkAOr+NY5hs1wH37qFY9zBNtOLo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782812294; c=relaxed/simple; bh=kCkIkCkZ+wCnKYcp7lkrWemwFvAzwzkCoeW6zMFBkzc=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=J9zahbrsOIVHwMYnPvmNFaDUw3kj8wR0I6VQnqpFEuxxWO0C/ZaBzuze8rBeFATQ2DtBmS6br6LgNYPf3bEnEfmhrKB08X97TxZc8vvEQ3V7mA/MICmYJmRLVaEhXERJ9yhwnI9sL67impismrD+YnfrX9L2ibOMEZ74Ppe3TuU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=Slq1sb6p; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="Slq1sb6p" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1782812293; x=1814348293; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=kCkIkCkZ+wCnKYcp7lkrWemwFvAzwzkCoeW6zMFBkzc=; b=Slq1sb6pWke0YkhKeg42RzLVbUASsexIzpxd2QxM1swoGi+5aWr8Rpzr QSNLw8+52YrDG8+rVouT82Dm8tB4sp2dt6Zyr5EmFAskzfJmJsq5fECO1 Aa1gSXqcPOOFqPGQNXbBrHXGNSHEhgVKtk1TJnuVAcnD7ZiUJWJO+/OGZ MeEKTb4Z2GazFzWkqMOSFpv7rzTgNKbdfiEJ+MGxzgyIRcrAiXLdEgcgN fkc/hq9TOZOOZ2t5xrYW5Eap/ETUsbOhxVrkBwTmnflPurmMNlxNu9i62 MMzL+eK0D5VdHFtKaJ5evLXmJ/BDNZFCRnHnnOfLQvMa4jegsLUq3nRUo A==; X-CSE-ConnectionGUID: WW0lzzyIQZet4I2N9Xwflg== X-CSE-MsgGUID: hi9iZs0MQQG4lIBpdiRfdA== X-IronPort-AV: E=Sophos;i="6.24,233,1774335600"; d="scan'208";a="227053731" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 30 Jun 2026 02:38:12 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.58; Tue, 30 Jun 2026 02:38:12 -0700 Received: from che-ll-i67070.microchip.com (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Tue, 30 Jun 2026 02:38:04 -0700 From: Varshini Rajendran To: , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v3 10/13] ARM: dts: microchip: sama7d65: add otpc node Date: Tue, 30 Jun 2026 15:06:00 +0530 Message-ID: <20260630093603.38663-11-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260630093603.38663-1-varshini.rajendran@microchip.com> References: <20260630093603.38663-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add OTPC node along with temperature calibration cell. Signed-off-by: Varshini Rajendran --- arch/arm/boot/dts/microchip/sama7d65.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/= microchip/sama7d65.dtsi index ba775459a816..5867fda378b1 100644 --- a/arch/arm/boot/dts/microchip/sama7d65.dtsi +++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi @@ -15,6 +15,7 @@ #include #include #include +#include =20 / { model =3D "Microchip SAMA7D65 family SoC"; @@ -1112,6 +1113,21 @@ ddr3phy: ddr3phy@e3804000 { reg =3D <0xe3804000 0x1000>; }; =20 + otpc: efuse@e8c00000 { + compatible =3D "microchip,sama7d65-otpc", "microchip,sama7g5-otpc", "sy= scon"; + reg =3D <0xe8c00000 0x100>; + + nvmem-layout { + compatible =3D "fixed-layout"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + temperature_calib: calib@41435354 { + reg =3D <0x41435354 0x2c>; /* Temp calib data packet TAG */ + }; + }; + }; + gic: interrupt-controller@e8c11000 { compatible =3D "arm,cortex-a7-gic"; reg =3D <0xe8c11000 0x1000>, --=20 2.34.1 From nobody Sat Jul 11 18:16:52 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C2510399357; Tue, 30 Jun 2026 09:38:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782812303; cv=none; b=p+sgkadGRRcBorbgpKb1x3sKEpktxHnrisDUA0hsfCCXybKtlnXDLBx4TU0i7Nlh+Mz7bTyWCh8X9/GtSOmuJlYLQTV9BUhq4/VDrpmrHOgklEuxTRYzPu82E41CHG36X7XIORKvxzoqLWGUjqC7xVNHgYkvmajNAkqYResGFlA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782812303; c=relaxed/simple; bh=qPxtI+f+BE5aWVid8LOQEajXcJY4oSXCvUiv/NY6ixY=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=OHeOZMyF9oLPqH6l/cjgDghUXC8omr2CahKLka5ZsmkHrD0dIijpgKIi5LuyVQhSHXnd7QdY6nvhRJ1fw4ID7TJ3nJK0/z8W2O4zkDLhv3i513CoyxhSl+VVuKvH253rueAQ9PkJEytuqJRF1QUWIWpTCpYAcpTAS7IKvxuAgSQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=EGKMhbw1; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="EGKMhbw1" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1782812301; x=1814348301; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=qPxtI+f+BE5aWVid8LOQEajXcJY4oSXCvUiv/NY6ixY=; b=EGKMhbw1DqyQ0g4WNq5jNCEL+1g9wc7nQeL+g2zOYsBce7L4WV1Qi7Dj aKxVNWtavPqdZPMfh2+at5W4nAJ5l23eIsIf/jXnczv3XeXioyn/Sqjeq toOiCNF+3n8cWbzHCJTs+KczP2kISk9Id5T3JVuV0o488261dQNbHv2qu o71/Q4vHRHoV452QNxwoDHKNyGZ1IzATNE9qUoEKFckJu864DbzDNv1h0 nmhzOGyjlDtdBVkBXKSaiMqMbu7i6A2OwdnIGZ8Qihfd3Y/cXrI6ayjM4 Ak2S5NwVy0q7CmxE52x16KCm9VW7+UIBw0jOyxeNro7TVVm8FGSj1auaN Q==; X-CSE-ConnectionGUID: DMe9/CRHQ/yCFfdCFRbxVQ== X-CSE-MsgGUID: P4Zsrn08TZebKbn4DPHosg== X-IronPort-AV: E=Sophos;i="6.24,233,1774335600"; d="scan'208";a="59032715" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Jun 2026 02:38:21 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.87.72) by chn-vm-ex4.mchp-main.com (10.10.87.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.2.2562.43; Tue, 30 Jun 2026 02:38:20 -0700 Received: from che-ll-i67070.microchip.com (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Tue, 30 Jun 2026 02:38:12 -0700 From: Varshini Rajendran To: , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v3 11/13] ARM: dts: microchip: sama7d65: add cells for temperature calibration Date: Tue, 30 Jun 2026 15:06:01 +0530 Message-ID: <20260630093603.38663-12-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260630093603.38663-1-varshini.rajendran@microchip.com> References: <20260630093603.38663-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add NVMEM cell to ADC for temperature calibration data. Signed-off-by: Varshini Rajendran --- arch/arm/boot/dts/microchip/sama7d65.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/= microchip/sama7d65.dtsi index 5867fda378b1..c336f863406d 100644 --- a/arch/arm/boot/dts/microchip/sama7d65.dtsi +++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi @@ -323,6 +323,8 @@ adc: adc@e1000000 { atmel,trigger-edge-type =3D ; atmel,startup-time-ms =3D <4>; #io-channel-cells =3D <1>; + nvmem-cells =3D <&temperature_calib>; + nvmem-cell-names =3D "temperature_calib"; status =3D "disabled"; }; =20 --=20 2.34.1 From nobody Sat Jul 11 18:16:52 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 63FA038C407; Tue, 30 Jun 2026 09:38:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782812312; cv=none; b=keYmItzJda3ZfYDWVajmnhhEObFG8n7bL/61WA7DKL1h4Q7IH4RxNqQMeGz5GJigFEDynI/ajhc3ThdYGF4jQqT6xvzidq3zmAK8SAQ98PWJKpCbpgVclWCuDWjVd3J0NVx2cRFQdwGsYX49dKgSX8b5thVB/OQ4VcDZNC4Yvqo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782812312; c=relaxed/simple; bh=+JAI97nnRrQjRgPPWdsBYZeYFHJ400kcB7mRR/guJPY=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=HUOjNZKXG60fXr3O7s4CPgraDvcTjRyvreLW1wIsYUaVu9iudGUn9kFWPm/uhaBTS66ga6geCcAuhc2U9r0jTfRyr4I+9BeymTOUhnxoXTGVY0uQhDHpS+pb6SgxjFrIxMLa9inULOB+HCCKn6xJ6CRmEEhD1QY9WV+b2S3ZffM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=sP9kVJxJ; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="sP9kVJxJ" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1782812311; x=1814348311; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=+JAI97nnRrQjRgPPWdsBYZeYFHJ400kcB7mRR/guJPY=; b=sP9kVJxJ8fcK76W5ZVrWriWoWyrWsdu55jlyd+gV7HlVhWWSPhJxCQzp 68v67lhKPzRGRWgx9bJpHlWUgSY2+z/46//eLy691ie6dBGvCPVDeNYVK Lc7p9HzXpLhor5q9gTQn0LpLOHRUhKIqaRnUvbj5oduDiKd4b/E5OpZxu zw28783VOuzZcJgo2MxFbyR/QsbpAdvMV3hXnsM/NLqmS15S3z7wT/4gH bNxlFuB6nnnuDkKxikwmvnQ7UNdcK99SbYxtaRtJhth1ztwyyZoKCYVjR mrRf7gOo88T3Wer6Z5PQkka+8RzyuLWhE5MzmeRi3YX8VDQETUyMbidQr Q==; X-CSE-ConnectionGUID: DUuy9YIyS4m07SSKsCxMVQ== X-CSE-MsgGUID: FbaOAge8Qref46MdaSyAmg== X-IronPort-AV: E=Sophos;i="6.24,233,1774335600"; d="scan'208";a="59032722" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Jun 2026 02:38:30 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.87.72) by chn-vm-ex4.mchp-main.com (10.10.87.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.2.2562.43; Tue, 30 Jun 2026 02:38:30 -0700 Received: from che-ll-i67070.microchip.com (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Tue, 30 Jun 2026 02:38:21 -0700 From: Varshini Rajendran To: , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v3 12/13] ARM: dts: microchip: sama7d65: add temperature sensor Date: Tue, 30 Jun 2026 15:06:02 +0530 Message-ID: <20260630093603.38663-13-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260630093603.38663-1-varshini.rajendran@microchip.com> References: <20260630093603.38663-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add temperature sensor node. Signed-off-by: Varshini Rajendran --- arch/arm/boot/dts/microchip/sama7d65.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/= microchip/sama7d65.dtsi index c336f863406d..89904397d021 100644 --- a/arch/arm/boot/dts/microchip/sama7d65.dtsi +++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi @@ -120,6 +120,13 @@ pmu { interrupts =3D ; }; =20 + thermal_sensor: thermal-sensor { + compatible =3D "generic-adc-thermal"; + #thermal-sensor-cells =3D <0>; + io-channels =3D <&adc AT91_SAMA7G5_ADC_TEMP_CHANNEL>; + io-channel-names =3D "sensor-channel"; + }; + soc { compatible =3D "simple-bus"; ranges; --=20 2.34.1 From nobody Sat Jul 11 18:16:52 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F06DA3D6493; Tue, 30 Jun 2026 09:38:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782812321; cv=none; b=DKDPbAufRuFX5fUJ2SNz//17Xj0qP2MPTXNY/wGKH2eHOqjQxTP6cPzQ5dKOQL3EkeEFZNru1N3pEWdaNBRC4XvoMuY++4iZFNg91P/t8E1iXV1DH/28/PURaB2wzd9mAW083PtE1R/XiNDhMw2nrb+vgIlrlfvwHMdzNCGmmL8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782812321; c=relaxed/simple; bh=5xYA55UOhzIXToSE5GZpeE9CT0EHf953ZhVrNg1L6YA=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=MXfsgh2sU3kJmYpaoR32QZoKEk7fNjmapd1awGf2dFRw9MUaiqoLTexY9udRe6CLZRhMlVMMdH/HqEXGZzRQ79dQhutXinHVb1yfP8DUTYlV9DkcMz7ypUyiNcXYrwtGT8iDFVA3I6zwLtF11nceugTzK62jyONMi/6VM6MGUrc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=nggM+Frq; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="nggM+Frq" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1782812319; x=1814348319; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=5xYA55UOhzIXToSE5GZpeE9CT0EHf953ZhVrNg1L6YA=; b=nggM+Frq6VlAtxRv+Fc+sRaOw0dhxN+tXpyJUCarwbUNI5ytrPFHFsFp xGRsLab0A6DgzN81nG2IvLdoUAvoZ6WhMRx5cGymOy/YRs0OFKgvQhRdV Uch1pfCyTLAvzAWWc1HiKTEFzmeEoRddf1wlnDAU8ZLUuKj4snHTAZ9v3 inW6NUtlbzgPbu2H/akaUsCGoqaRFdE6yWmCm+yE0uy2Yc43M9RyGy+EJ iQnAxvmU7YUruOrlh4u+wg/7lf7xvK7GNaOP/W/IX20DvO5gRD5tEsb3X oQHvE4tcCBYE/nrPQBPLRvR2tJVckJfZGZu0V40MjE9oxDWFY0QBcmKrn g==; X-CSE-ConnectionGUID: SUqO/kxASaKWBXK1VeZsfw== X-CSE-MsgGUID: Bg9g48AeTziF9k/8sH2P2A== X-IronPort-AV: E=Sophos;i="6.24,233,1774335600"; d="scan'208";a="227053760" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Jun 2026 02:38:39 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.87.72) by chn-vm-ex4.mchp-main.com (10.10.87.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.2.2562.43; Tue, 30 Jun 2026 02:38:38 -0700 Received: from che-ll-i67070.microchip.com (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Tue, 30 Jun 2026 02:38:30 -0700 From: Varshini Rajendran To: , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v3 13/13] ARM: dts: microchip: sama7d65: add thermal zones node Date: Tue, 30 Jun 2026 15:06:03 +0530 Message-ID: <20260630093603.38663-14-varshini.rajendran@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260630093603.38663-1-varshini.rajendran@microchip.com> References: <20260630093603.38663-1-varshini.rajendran@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add thermal zones node with its associated trips and cooling-maps. It uses CPUFreq as cooling device for temperatures in the interval [90, 100) degrees Celsius and describe the temperature of 100 degrees Celsius as critical temperature. System will shut down when reaching critical temperature. Signed-off-by: Varshini Rajendran --- arch/arm/boot/dts/microchip/sama7d65.dtsi | 42 +++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/= microchip/sama7d65.dtsi index 89904397d021..f2140010d337 100644 --- a/arch/arm/boot/dts/microchip/sama7d65.dtsi +++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi @@ -16,6 +16,7 @@ #include #include #include +#include =20 / { model =3D "Microchip SAMA7D65 family SoC"; @@ -38,6 +39,7 @@ cpu0: cpu@0 { i-cache-size =3D <0x8000>; // L1, 32 KB next-level-cache =3D <&L2>; operating-points-v2 =3D <&cpu_opp_table>; + #cooling-cells =3D <2>; /* min followed by max */ =20 L2: l2-cache { compatible =3D "cache"; @@ -127,6 +129,46 @@ thermal_sensor: thermal-sensor { io-channel-names =3D "sensor-channel"; }; =20 + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive =3D <1000>; + polling-delay =3D <5000>; + thermal-sensors =3D <&thermal_sensor>; + + trips { + cpu_normal: cpu-alert0 { + temperature =3D <90000>; + hysteresis =3D <0>; + type =3D "passive"; + }; + + cpu_hot: cpu-alert1 { + temperature =3D <95000>; + hysteresis =3D <0>; + type =3D "passive"; + }; + + cpu_critical: cpu-critical { + temperature =3D <100000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + + cooling-maps { + map0 { + trip =3D <&cpu_normal>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + + map1 { + trip =3D <&cpu_hot>; + cooling-device =3D <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; + soc { compatible =3D "simple-bus"; ranges; --=20 2.34.1