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Tue, 30 Jun 2026 02:02:53 -0700 (PDT) Received: from hu-guptap-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-30ee3264f52sm6022612eec.28.2026.06.30.02.02.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Jun 2026 02:02:53 -0700 (PDT) From: Prakash Gupta Date: Tue, 30 Jun 2026 14:32:46 +0530 Subject: [PATCH v3] iommu/arm-smmu: Use pm_runtime in fault handlers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260630-smmu-rpm-v3-1-f69874a580fa@oss.qualcomm.com> X-B4-Tracking: v=1; b=H4sIADaGQ2oC/22Myw7CIBBFf6VhLQ0MfaAr/8O4KI9aEpHKWKJp+ u/SburCzSRncs+ZCdroLJJTMZNok0MXHhnEoSB66B43S53JTIBBzYFJit5PNI6eSmWa1qijMLo jeT5G27v3lrpcMw8OXyF+tnLi63eNNIxDu0cSp5yC7aGvtKwFq88BsXxO3V0H78t8yNpKsPuCi x8fsi81gGhUxUCxP/6yLF+i5uQI5wAAAA== X-Change-ID: 20251208-smmu-rpm-8bd67db93dca To: Will Deacon , Robin Murphy , Joerg Roedel , Rob Clark , Connor Abbott Cc: linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org, Akhil P Oommen , Pranjal Shrivastava , Pratyush Brahma , Prakash Gupta X-Mailer: b4 0.15-dev-47773 X-Proofpoint-Spam-Info: AW1haW4tMjYwNjMwMDA4MCBTYWx0ZWRfXw9wXFUbpywUi SNNrbwaeR5177lAh15go/NlSG2EfW8Xa/g8PF6n9E+kyLnSQgnPyCg686XDAljZMmzlkBxH3z0b vRx3R2OWZv1cTM71bAoOaHQg+0yZXw4= X-Authority-Analysis: v=2.4 cv=KfDidwYD c=1 sm=1 tr=0 ts=6a43863f cx=c_pps a=wEP8DlPgTf/vqF+yE6f9lg==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=bC-a23v3AAAA:8 a=EUspDBNiAAAA:8 a=44HM8yHCulYeUOODjvgA:9 a=QEXdDO2ut3YA:10 a=bBxd6f-gb0O0v-kibOvt:22 a=FO4_E8m0qiDe52t0p3_H:22 X-Proofpoint-GUID: w5nIpsp0dBv4MCZhLXWfqGbTyKoMO0uo X-Proofpoint-ORIG-GUID: w5nIpsp0dBv4MCZhLXWfqGbTyKoMO0uo X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjMwMDA4MCBTYWx0ZWRfX5k8RFjcwpWHc 6XBuOhVpnr/9toofqrCM+BZVghJQ7rt0aaAdwT5JvXfinliEFdf+r8RLPPk4jJ96iGvpnvZE2PT 0JQnsW3n0LI1FWvZxeZs1GqKmrHFTQbsVHLkheOcQQsQMCyvwheTY+i3jsPpdrOlYQ+tRrJwe5W yyB5jZJpU1pN8pWs5RP4QMpaJuCT9SAq1Zq9VNSrpNsaBUKU2VXaABXwETYXnEhd2x4gHVRfSPE oWHSWE7YEa9m+w26q+j8FZO1Y7s3UkD1XJ7qbB7MdvuSr6YLYmVInJKLQsyx8TVqx+KbqV9C766 3ogpitjDZtUodHyd9ioBDUH0N0glOd+Sq0hjtxb64KqC1EeKMfnF+/Kr/RTSAxMiAvXZ8hblz/L +h4wH3KWidPyEw8dBc7BGS/XSGseaKzafHhFCz9zykxVKiVPLIDQn4QEtyxgvwFRlJHbCkKC9/c 8AE8yixhzQj/5arucWA== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-30_02,2026-06-26_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 phishscore=0 impostorscore=0 bulkscore=0 clxscore=1015 spamscore=0 priorityscore=1501 lowpriorityscore=0 malwarescore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2606300080 Commit d4a44f0750bb ("iommu/arm-smmu: Invoke pm_runtime across the driver") enabled pm_runtime for the arm-smmu device. On systems where the SMMU sits in a power domain, all register accesses must be done while the device is runtime active to avoid unclocked register reads and potential NoC errors. So far, this has not been an issue for most SMMU clients because stall-on-fault is enabled by default. While a translation fault is being handled, the SMMU stalls further translations for that context bank, so the fault handler would not race with a powered-down SMMU. Adreno SMMU now disables stall-on-fault in the presence of fault storms to avoid saturating SMMU resources and hanging the GMU. With stall-on-fault disabled, the SMMU can generate faults while its power domain may no longer be enabled, which makes unclocked accesses to fault-status registers in the SMMU fault handlers possible. Guard the context and global fault handlers with arm_smmu_rpm_get_if_active() and arm_smmu_rpm_put() so that all SMMU fault register accesses are done with the SMMU powered. If the SMMU is not runtime active, the fault can be safely ignored as arm_smmu_device_reset() clears fault registers on resume. Additionally, disable fault reporting in arm_smmu_runtime_suspend() before powering down. pm_runtime_get_if_active() returns 0 during RPM_SUSPENDING, so without this, level-triggered fault interrupts would cause an interrupt storm while the device is being suspended. arm_smmu_device_reset() re-enables fault reporting on resume. Fixes: b13044092c1e ("drm/msm: Temporarily disable stall-on-fault after a p= age fault") Co-developed-by: Pratyush Brahma Signed-off-by: Pratyush Brahma Signed-off-by: Prakash Gupta --- Changes in v3: - Add arm_smmu_rpm_get_if_active() wrapper that returns 1 when pm_runtime is disabled, ensuring fault handlers work on non-pm_runtime systems - Disable fault reporting in arm_smmu_runtime_suspend() before powering down to prevent interrupt storms during RPM_SUSPENDING state - Use pm_runtime_put_autosuspend() in arm_smmu_rpm_put() instead of private __pm_runtime_put_autosuspend() - Link to v2: https://patch.msgid.link/20260313-smmu-rpm-v2-1-8c2236b402b0@= oss.qualcomm.com Changes in v2: - Switched from arm_smmu_rpm_get()/arm_smmu_rpm_put() wrappers to pm_runtime_get_if_active()/pm_runtime_put_autosuspend() APIs - Added support for smmu->impl->global_fault callback in global fault handl= er - Remove threaded irq context fault restriction to allow modifying stall mode for adreno smmu - Link to v1: https://patch.msgid.link/20260127-smmu-rpm-v1-1-2ef2f4c85305@= oss.qualcomm.com --- drivers/iommu/arm/arm-smmu/arm-smmu.c | 92 +++++++++++++++++++++++++------= ---- 1 file changed, 67 insertions(+), 25 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/arm-= smmu/arm-smmu.c index 0bd21d206eb3..045389e89484 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c @@ -79,11 +79,16 @@ static inline int arm_smmu_rpm_get(struct arm_smmu_devi= ce *smmu) =20 static inline void arm_smmu_rpm_put(struct arm_smmu_device *smmu) { - if (pm_runtime_enabled(smmu->dev)) { - pm_runtime_mark_last_busy(smmu->dev); - __pm_runtime_put_autosuspend(smmu->dev); + if (pm_runtime_enabled(smmu->dev)) + pm_runtime_put_autosuspend(smmu->dev); +} =20 - } +static inline int arm_smmu_rpm_get_if_active(struct arm_smmu_device *smmu) +{ + if (!pm_runtime_enabled(smmu->dev)) + return 1; + + return pm_runtime_get_if_active(smmu->dev); } =20 static void arm_smmu_rpm_use_autosuspend(struct arm_smmu_device *smmu) @@ -462,10 +467,20 @@ static irqreturn_t arm_smmu_context_fault(int irq, vo= id *dev) int idx =3D smmu_domain->cfg.cbndx; int ret; =20 + if (!arm_smmu_rpm_get_if_active(smmu)) + return IRQ_NONE; + + if (smmu->impl && smmu->impl->context_fault) { + ret =3D smmu->impl->context_fault(irq, dev); + goto out_power_off; + } + arm_smmu_read_context_fault_info(smmu, idx, &cfi); =20 - if (!(cfi.fsr & ARM_SMMU_CB_FSR_FAULT)) - return IRQ_NONE; + if (!(cfi.fsr & ARM_SMMU_CB_FSR_FAULT)) { + ret =3D IRQ_NONE; + goto out_power_off; + } =20 ret =3D report_iommu_fault(&smmu_domain->domain, NULL, cfi.iova, cfi.fsynr & ARM_SMMU_CB_FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_REA= D); @@ -480,7 +495,12 @@ static irqreturn_t arm_smmu_context_fault(int irq, voi= d *dev) ret =3D=3D -EAGAIN ? 0 : ARM_SMMU_RESUME_TERMINATE); } =20 - return IRQ_HANDLED; + ret =3D IRQ_HANDLED; + +out_power_off: + arm_smmu_rpm_put(smmu); + + return ret; } =20 static irqreturn_t arm_smmu_global_fault(int irq, void *dev) @@ -489,14 +509,25 @@ static irqreturn_t arm_smmu_global_fault(int irq, voi= d *dev) struct arm_smmu_device *smmu =3D dev; static DEFINE_RATELIMIT_STATE(rs, DEFAULT_RATELIMIT_INTERVAL, DEFAULT_RATELIMIT_BURST); + int ret; + + if (!arm_smmu_rpm_get_if_active(smmu)) + return IRQ_NONE; + + if (smmu->impl && smmu->impl->global_fault) { + ret =3D smmu->impl->global_fault(irq, dev); + goto out_power_off; + } =20 gfsr =3D arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_sGFSR); gfsynr0 =3D arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_sGFSYNR0); gfsynr1 =3D arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_sGFSYNR1); gfsynr2 =3D arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_sGFSYNR2); =20 - if (!gfsr) - return IRQ_NONE; + if (!gfsr) { + ret =3D IRQ_NONE; + goto out_power_off; + } =20 if (__ratelimit(&rs)) { if (IS_ENABLED(CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT) && @@ -513,7 +544,11 @@ static irqreturn_t arm_smmu_global_fault(int irq, void= *dev) } =20 arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_sGFSR, gfsr); - return IRQ_HANDLED; + ret =3D IRQ_HANDLED; + +out_power_off: + arm_smmu_rpm_put(smmu); + return ret; } =20 static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain, @@ -683,7 +718,6 @@ static int arm_smmu_init_domain_context(struct arm_smmu= _domain *smmu_domain, enum io_pgtable_fmt fmt; struct iommu_domain *domain =3D &smmu_domain->domain; struct arm_smmu_cfg *cfg =3D &smmu_domain->cfg; - irqreturn_t (*context_fault)(int irq, void *dev); =20 mutex_lock(&smmu_domain->init_mutex); if (smmu_domain->smmu) @@ -850,19 +884,14 @@ static int arm_smmu_init_domain_context(struct arm_sm= mu_domain *smmu_domain, */ irq =3D smmu->irqs[cfg->irptndx]; =20 - if (smmu->impl && smmu->impl->context_fault) - context_fault =3D smmu->impl->context_fault; - else - context_fault =3D arm_smmu_context_fault; - if (smmu->impl && smmu->impl->context_fault_needs_threaded_irq) ret =3D devm_request_threaded_irq(smmu->dev, irq, NULL, - context_fault, + arm_smmu_context_fault, IRQF_ONESHOT | IRQF_SHARED, "arm-smmu-context-fault", smmu_domain); else - ret =3D devm_request_irq(smmu->dev, irq, context_fault, IRQF_SHARED, + ret =3D devm_request_irq(smmu->dev, irq, arm_smmu_context_fault, IRQF_SH= ARED, "arm-smmu-context-fault", smmu_domain); =20 if (ret < 0) { @@ -2125,7 +2154,6 @@ static int arm_smmu_device_probe(struct platform_devi= ce *pdev) struct device *dev =3D &pdev->dev; int num_irqs, i, err; u32 global_irqs, pmu_irqs; - irqreturn_t (*global_fault)(int irq, void *dev); =20 smmu =3D devm_kzalloc(dev, sizeof(*smmu), GFP_KERNEL); if (!smmu) { @@ -2205,18 +2233,13 @@ static int arm_smmu_device_probe(struct platform_de= vice *pdev) smmu->num_context_irqs =3D smmu->num_context_banks; } =20 - if (smmu->impl && smmu->impl->global_fault) - global_fault =3D smmu->impl->global_fault; - else - global_fault =3D arm_smmu_global_fault; - for (i =3D 0; i < global_irqs; i++) { int irq =3D platform_get_irq(pdev, i); =20 if (irq < 0) return irq; =20 - err =3D devm_request_irq(dev, irq, global_fault, IRQF_SHARED, + err =3D devm_request_irq(dev, irq, arm_smmu_global_fault, IRQF_SHARED, "arm-smmu global fault", smmu); if (err) return dev_err_probe(dev, err, @@ -2306,6 +2329,25 @@ static int __maybe_unused arm_smmu_runtime_resume(st= ruct device *dev) static int __maybe_unused arm_smmu_runtime_suspend(struct device *dev) { struct arm_smmu_device *smmu =3D dev_get_drvdata(dev); + int i; + u32 reg; + + /* + * Disable fault reporting before powering down to prevent unclocked + * register accesses in the fault handlers if an interrupt races with + * the suspend callback (e.g. device in RPM_SUSPENDING state). + * arm_smmu_device_reset() re-enables fault reporting on resume. + */ + reg =3D arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_sCR0); + reg &=3D ~(ARM_SMMU_sCR0_GFRE | ARM_SMMU_sCR0_GFIE | + ARM_SMMU_sCR0_GCFGFRE | ARM_SMMU_sCR0_GCFGFIE); + arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_sCR0, reg); + + for (i =3D 0; i < smmu->num_context_banks; i++) { + reg =3D arm_smmu_cb_read(smmu, i, ARM_SMMU_CB_SCTLR); + reg &=3D ~(ARM_SMMU_SCTLR_CFIE | ARM_SMMU_SCTLR_CFRE); + arm_smmu_cb_write(smmu, i, ARM_SMMU_CB_SCTLR, reg); + } =20 clk_bulk_disable(smmu->num_clks, smmu->clks); =20 --- base-commit: ba3e43a9e601636f5edb54e259a74f96ca3b8fd8 change-id: 20251208-smmu-rpm-8bd67db93dca Best regards, -- =20 Prakash Gupta