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Peter Anvin" Subject: [PATCH v4 01/18] x86/alternative: Support alt_replace_call() with instructions after call Date: Mon, 29 Jun 2026 08:55:27 +0200 Message-ID: <20260629065544.3643253-2-jgross@suse.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260629065544.3643253-1-jgross@suse.com> References: <20260629065544.3643253-1-jgross@suse.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Spam-Flag: NO X-Spam-Score: -6.80 X-Spamd-Result: default: False [-6.80 / 50.00]; REPLY(-4.00)[]; BAYES_HAM(-3.00)[100.00%]; MID_CONTAINS_FROM(1.00)[]; NEURAL_HAM_LONG(-1.00)[-1.000]; R_MISSING_CHARSET(0.50)[]; NEURAL_HAM_SHORT(-0.20)[-1.000]; MIME_GOOD(-0.10)[text/plain]; TO_MATCH_ENVRCPT_ALL(0.00)[]; DKIM_SIGNED(0.00)[suse.com:s=susede1]; MIME_TRACE(0.00)[0:+]; FUZZY_RATELIMITED(0.00)[rspamd.com]; ARC_NA(0.00)[]; RCVD_TLS_ALL(0.00)[]; R_RATELIMIT(0.00)[to_ip_from(RLfdszjqhz8kzzb9uwpzdm8png)]; FROM_EQ_ENVFROM(0.00)[]; FROM_HAS_DN(0.00)[]; TO_DN_SOME(0.00)[]; RCVD_COUNT_TWO(0.00)[2]; RCVD_VIA_SMTP_AUTH(0.00)[]; RCPT_COUNT_SEVEN(0.00)[8]; DBL_BLOCKED_OPENRESOLVER(0.00)[suse.com:email,suse.com:mid,imap1.dmz-prg2.suse.org:helo] X-Spam-Level: Content-Type: text/plain; charset="utf-8" Today alt_replace_call() requires the initial indirect call not to be followed by any further instructions, including padding NOPs. In case any replacement is longer than 6 bytes, a subsequent replacement of the indirect call with a direct one will result in a crash. Fix that by crashing only if the original instruction is less than 6 bytes long or not a known indirect call. Signed-off-by: Juergen Gross --- arch/x86/kernel/alternative.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/alternative.c b/arch/x86/kernel/alternative.c index 62936a3bde19..2f24c3e9c0c0 100644 --- a/arch/x86/kernel/alternative.c +++ b/arch/x86/kernel/alternative.c @@ -534,6 +534,7 @@ noinstr void BUG_func(void) } EXPORT_SYMBOL(BUG_func); =20 +#define CALL_RIP_INSTRLEN 6 #define CALL_RIP_REL_OPCODE 0xff #define CALL_RIP_REL_MODRM 0x15 =20 @@ -551,7 +552,7 @@ static unsigned int alt_replace_call(u8 *instr, u8 *ins= n_buff, struct alt_instr BUG(); } =20 - if (a->instrlen !=3D 6 || + if (a->instrlen < CALL_RIP_INSTRLEN || instr[0] !=3D CALL_RIP_REL_OPCODE || instr[1] !=3D CALL_RIP_REL_MODRM) { pr_err("ALT_FLAG_DIRECT_CALL set for unrecognized indirect call\n"); @@ -563,7 +564,7 @@ static unsigned int alt_replace_call(u8 *instr, u8 *ins= n_buff, struct alt_instr #ifdef CONFIG_X86_64 /* ff 15 00 00 00 00 call *0x0(%rip) */ /* target address is stored at "next instruction + disp". */ - target =3D *(void **)(instr + a->instrlen + disp); + target =3D *(void **)(instr + CALL_RIP_INSTRLEN + disp); #else /* ff 15 00 00 00 00 call *0x0 */ /* target address is stored at disp. */ --=20 2.54.0 From nobody Tue Jun 30 05:35:18 2026 Received: from smtp-out1.suse.de (smtp-out1.suse.de [195.135.223.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 260B03B388A for ; Mon, 29 Jun 2026 06:56:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=195.135.223.130 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782716167; cv=none; b=Dx8ZVoVN5MkmQ3/CoSeNhK5wVpMQPrIgZjIf0te4Y/YPG/28N2hFTnRwL76JGBnOgNUeb5GeWKxrRKEbMO/jnSD54yzvbwfRAhHzPNMhgCGnAbkSQ0p3lpxClFQ9kN1BTt8r9M4d+KiLdTQIJeFPgt6GCRsuH/K2QXRT6iS3DYY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782716167; c=relaxed/simple; bh=GraXAf7tc04adQQBFmyLhWVjf7YXHiydpYpgLn0bWkU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=YAhctckeSMyUQkmdJuXuXskjERU16a+2kNxM++d80xLuIDcBQ2/5FTFYABvECafKx3lug4lSd3q/FeOddKpcNC9zVOUEFQSkFzVWtSbRFzRm2wO8mRHpVFJKVle9c5Nk4A55gQbLj06MfIZvHLdwQskwgkwI0Sqvh+Qri4M8uaw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=suse.com; spf=pass smtp.mailfrom=suse.com; arc=none smtp.client-ip=195.135.223.130 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=suse.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=suse.com Received: from imap1.dmz-prg2.suse.org (imap1.dmz-prg2.suse.org [IPv6:2a07:de40:b281:104:10:150:64:97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by smtp-out1.suse.de (Postfix) with ESMTPS id 6374672F36; Mon, 29 Jun 2026 06:55:58 +0000 (UTC) Authentication-Results: smtp-out1.suse.de; none Received: from imap1.dmz-prg2.suse.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by imap1.dmz-prg2.suse.org (Postfix) with ESMTPS id 0AC31779A8; Mon, 29 Jun 2026 06:55:58 +0000 (UTC) Received: from dovecot-director2.suse.de ([2a07:de40:b281:106:10:150:64:167]) by imap1.dmz-prg2.suse.org with ESMTPSA id jeQlAf4WQmqbQQAAD6G6ig (envelope-from ); Mon, 29 Jun 2026 06:55:58 +0000 From: Juergen Gross To: linux-kernel@vger.kernel.org, x86@kernel.org, linux-coco@lists.linux.dev, kvm@vger.kernel.org Cc: Juergen Gross , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Kiryl Shutsemau , Rick Edgecombe Subject: [PATCH v4 02/18] coco/tdx: Rename MSR access helpers Date: Mon, 29 Jun 2026 08:55:28 +0200 Message-ID: <20260629065544.3643253-3-jgross@suse.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260629065544.3643253-1-jgross@suse.com> References: <20260629065544.3643253-1-jgross@suse.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Rspamd-Pre-Result: action=no action; module=replies; Message is reply to one we originated X-Rspamd-Pre-Result: action=no action; module=replies; Message is reply to one we originated X-Spam-Flag: NO X-Spam-Score: -4.00 X-Spam-Level: X-Rspamd-Server: rspamd2.dmz-prg2.suse.org X-Spamd-Result: default: False [-4.00 / 50.00]; REPLY(-4.00)[] X-Rspamd-Queue-Id: 6374672F36 X-Rspamd-Action: no action Content-Type: text/plain; charset="utf-8" In order to avoid a name clash with some general MSR access helpers after a future MSR infrastructure rework, rename the TDX specific helpers. Signed-off-by: Juergen Gross Reviewed-by: Kiryl Shutsemau Reviewed-by: H. Peter Anvin (Intel) Reviewed-by: Rick Edgecombe --- arch/x86/coco/tdx/tdx.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/x86/coco/tdx/tdx.c b/arch/x86/coco/tdx/tdx.c index 29b6f1ed59ec..24379affb90d 100644 --- a/arch/x86/coco/tdx/tdx.c +++ b/arch/x86/coco/tdx/tdx.c @@ -469,7 +469,7 @@ static void __cpuidle tdx_safe_halt(void) raw_local_irq_enable(); } =20 -static int read_msr(struct pt_regs *regs, struct ve_info *ve) +static int tdx_read_msr(struct pt_regs *regs, struct ve_info *ve) { struct tdx_module_args args =3D { .r10 =3D TDX_HYPERCALL_STANDARD, @@ -490,7 +490,7 @@ static int read_msr(struct pt_regs *regs, struct ve_inf= o *ve) return ve_instr_len(ve); } =20 -static int write_msr(struct pt_regs *regs, struct ve_info *ve) +static int tdx_write_msr(struct pt_regs *regs, struct ve_info *ve) { struct tdx_module_args args =3D { .r10 =3D TDX_HYPERCALL_STANDARD, @@ -843,9 +843,9 @@ static int virt_exception_kernel(struct pt_regs *regs, = struct ve_info *ve) case EXIT_REASON_HLT: return handle_halt(ve); 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Peter Anvin" , Kiryl Shutsemau , Rick Edgecombe Subject: [PATCH v4 03/18] KVM: x86: Remove the KVM private read_msr() function Date: Mon, 29 Jun 2026 08:55:29 +0200 Message-ID: <20260629065544.3643253-4-jgross@suse.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260629065544.3643253-1-jgross@suse.com> References: <20260629065544.3643253-1-jgross@suse.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Spam-Flag: NO X-Spam-Score: -6.80 X-Spamd-Result: default: False [-6.80 / 50.00]; REPLY(-4.00)[]; BAYES_HAM(-3.00)[100.00%]; MID_CONTAINS_FROM(1.00)[]; NEURAL_HAM_LONG(-1.00)[-1.000]; R_MISSING_CHARSET(0.50)[]; NEURAL_HAM_SHORT(-0.20)[-1.000]; MIME_GOOD(-0.10)[text/plain]; DBL_BLOCKED_OPENRESOLVER(0.00)[imap1.dmz-prg2.suse.org:helo,suse.com:email,suse.com:mid]; ARC_NA(0.00)[]; MIME_TRACE(0.00)[0:+]; TO_DN_SOME(0.00)[]; RCPT_COUNT_TWELVE(0.00)[14]; RCVD_VIA_SMTP_AUTH(0.00)[]; FUZZY_RATELIMITED(0.00)[rspamd.com]; FROM_HAS_DN(0.00)[]; TO_MATCH_ENVRCPT_ALL(0.00)[]; FROM_EQ_ENVFROM(0.00)[]; RCVD_COUNT_TWO(0.00)[2]; R_RATELIMIT(0.00)[to_ip_from(RLfdszjqhz8kzzb9uwpzdm8png)]; DKIM_SIGNED(0.00)[suse.com:s=susede1]; RCVD_TLS_ALL(0.00)[] X-Spam-Level: Content-Type: text/plain; charset="utf-8" Instead of having a KVM private read_msr() function, just use rdmsrq(). Signed-off-by: Juergen Gross Reviewed-by: H. Peter Anvin (Intel) Reviewed-by: Rick Edgecombe Acked-by: Sean Christopherson --- V2: - remove the helper and use rdmsrq() directly (Sean Christopherson) --- arch/x86/include/asm/kvm_host.h | 7 ------- arch/x86/kvm/vmx/tdx.c | 2 +- arch/x86/kvm/vmx/vmx.c | 6 +++--- 3 files changed, 4 insertions(+), 11 deletions(-) diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_hos= t.h index c87545070347..b4473c4428cf 100644 --- a/arch/x86/include/asm/kvm_host.h +++ b/arch/x86/include/asm/kvm_host.h @@ -2412,13 +2412,6 @@ static inline void kvm_load_ldt(u16 sel) asm("lldt %0" : : "rm"(sel)); } =20 -#ifdef CONFIG_X86_64 -static inline unsigned long read_msr(unsigned long msr) -{ - return rdmsrq(msr); -} -#endif - static inline void kvm_inject_gp(struct kvm_vcpu *vcpu, u32 error_code) { kvm_queue_exception_e(vcpu, GP_VECTOR, error_code); diff --git a/arch/x86/kvm/vmx/tdx.c b/arch/x86/kvm/vmx/tdx.c index 989ab29b8c6f..cf4efca81fd4 100644 --- a/arch/x86/kvm/vmx/tdx.c +++ b/arch/x86/kvm/vmx/tdx.c @@ -793,7 +793,7 @@ void tdx_prepare_switch_to_guest(struct kvm_vcpu *vcpu) if (likely(is_64bit_mm(current->mm))) vt->msr_host_kernel_gs_base =3D current->thread.gsbase; else - vt->msr_host_kernel_gs_base =3D read_msr(MSR_KERNEL_GS_BASE); + vt->msr_host_kernel_gs_base =3D rdmsrq(MSR_KERNEL_GS_BASE); =20 vt->guest_state_loaded =3D true; =20 diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index 3d53b5bb6914..729d4a0d0beb 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -1375,8 +1375,8 @@ void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcp= u) } else { savesegment(fs, fs_sel); savesegment(gs, gs_sel); - fs_base =3D read_msr(MSR_FS_BASE); - vt->msr_host_kernel_gs_base =3D read_msr(MSR_KERNEL_GS_BASE); + fs_base =3D rdmsrq(MSR_FS_BASE); + vt->msr_host_kernel_gs_base =3D rdmsrq(MSR_KERNEL_GS_BASE); } =20 wrmsrq(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base); @@ -1435,7 +1435,7 @@ static u64 vmx_read_guest_host_msr(struct vcpu_vmx *v= mx, u32 msr, u64 *cache) { preempt_disable(); if (vmx->vt.guest_state_loaded) - *cache =3D read_msr(msr); + *cache =3D rdmsrq(msr); preempt_enable(); return *cache; } --=20 2.54.0 From nobody Tue Jun 30 05:35:18 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; 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Y. Srinivasan" , Haiyang Zhang , Wei Liu , Dexuan Cui , Long Li , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Paolo Bonzini , Vitaly Kuznetsov , Sean Christopherson , Boris Ostrovsky , xen-devel@lists.xenproject.org Subject: [PATCH v4 04/18] x86/msr: Minimize usage of native_*() msr access functions Date: Mon, 29 Jun 2026 08:55:30 +0200 Message-ID: <20260629065544.3643253-5-jgross@suse.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260629065544.3643253-1-jgross@suse.com> References: <20260629065544.3643253-1-jgross@suse.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Spam-Flag: NO X-Spamd-Result: default: False [-6.80 / 50.00]; REPLY(-4.00)[]; BAYES_HAM(-3.00)[100.00%]; MID_CONTAINS_FROM(1.00)[]; NEURAL_HAM_LONG(-1.00)[-1.000]; R_MISSING_CHARSET(0.50)[]; NEURAL_HAM_SHORT(-0.20)[-1.000]; MIME_GOOD(-0.10)[text/plain]; DBL_BLOCKED_OPENRESOLVER(0.00)[suse.com:email,suse.com:mid,imap1.dmz-prg2.suse.org:helo]; ARC_NA(0.00)[]; MIME_TRACE(0.00)[0:+]; TO_DN_SOME(0.00)[]; RCPT_COUNT_TWELVE(0.00)[20]; RCVD_VIA_SMTP_AUTH(0.00)[]; FUZZY_RATELIMITED(0.00)[rspamd.com]; FROM_HAS_DN(0.00)[]; TO_MATCH_ENVRCPT_ALL(0.00)[]; FROM_EQ_ENVFROM(0.00)[]; RCVD_COUNT_TWO(0.00)[2]; R_RATELIMIT(0.00)[to_ip_from(RLfdszjqhz8kzzb9uwpzdm8png)]; DKIM_SIGNED(0.00)[suse.com:s=susede1]; RCVD_TLS_ALL(0.00)[] X-Spam-Level: X-Spam-Score: -6.80 X-purgate-ID: tlsNG-d25034/1782716170-9072FD51-8382D86B/0/0 X-purgate-type: clean X-purgate-size: 5326 X-ZohoMail-DKIM: pass (identity @suse.com) X-ZM-MESSAGEID: 1782716186666158500 Content-Type: text/plain; charset="utf-8" In order to prepare for some MSR access function reorg work, switch most users of native_{read|write}_msr[_safe]() to the more generic rdmsr*()/wrmsr*() variants. For now this will have some intermediate performance impact with paravirtualization configured when running on bare metal, but this is a prereq change for the planned direct inlining of the rdmsr/wrmsr instructions with this configuration. The main reason for this switch is the planned move of the MSR trace function invocation from the native_*() functions to the generic rdmsr*()/wrmsr*() variants. Without this switch the users of the native_*() functions would lose the related tracing entries. Note that the Xen related MSR access functions will not be switched, as these will be handled after the move of the trace hooks. Signed-off-by: Juergen Gross Acked-by: Sean Christopherson Acked-by: Wei Liu Reviewed-by: H. Peter Anvin (Intel) --- arch/x86/hyperv/ivm.c | 2 +- arch/x86/kernel/cpu/mshyperv.c | 4 ++-- arch/x86/kernel/kvmclock.c | 2 +- arch/x86/kvm/svm/svm.c | 16 ++++++++-------- arch/x86/xen/pmu.c | 4 ++-- 5 files changed, 14 insertions(+), 14 deletions(-) diff --git a/arch/x86/hyperv/ivm.c b/arch/x86/hyperv/ivm.c index 2ce4dfe53472..a74f121f2a02 100644 --- a/arch/x86/hyperv/ivm.c +++ b/arch/x86/hyperv/ivm.c @@ -328,7 +328,7 @@ int hv_snp_boot_ap(u32 apic_id, unsigned long start_ip,= unsigned int cpu) savesegment(ds, vmsa->ds.selector); hv_populate_vmcb_seg(vmsa->ds, vmsa->gdtr.base); =20 - vmsa->efer =3D native_read_msr(MSR_EFER); + vmsa->efer =3D rdmsrq(MSR_EFER); =20 vmsa->cr4 =3D native_read_cr4(); vmsa->cr3 =3D __native_read_cr3(); diff --git a/arch/x86/kernel/cpu/mshyperv.c b/arch/x86/kernel/cpu/mshyperv.c index 65ad235ef5c6..69c7cbae7a8e 100644 --- a/arch/x86/kernel/cpu/mshyperv.c +++ b/arch/x86/kernel/cpu/mshyperv.c @@ -114,7 +114,7 @@ u64 hv_para_get_synic_register(unsigned int reg) { if (WARN_ON(!ms_hyperv.paravisor_present || !hv_is_synic_msr(reg))) return ~0ULL; - return native_read_msr(reg); + return rdmsrq(reg); } =20 /* @@ -124,7 +124,7 @@ void hv_para_set_synic_register(unsigned int reg, u64 v= al) { if (WARN_ON(!ms_hyperv.paravisor_present || !hv_is_synic_msr(reg))) return; - native_write_msr(reg, val); + wrmsrq(reg, val); } =20 u64 hv_get_msr(unsigned int reg) diff --git a/arch/x86/kernel/kvmclock.c b/arch/x86/kernel/kvmclock.c index cb3d0ca1fa22..6ddef8b5426a 100644 --- a/arch/x86/kernel/kvmclock.c +++ b/arch/x86/kernel/kvmclock.c @@ -219,7 +219,7 @@ static void kvm_setup_secondary_clock(void) void kvmclock_disable(void) { if (msr_kvm_system_time) - native_write_msr(msr_kvm_system_time, 0); + wrmsrq(msr_kvm_system_time, 0); } =20 static void __init kvmclock_init_mem(void) diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index 977112d8713c..604f3ca3c1e3 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -413,12 +413,12 @@ static void svm_init_erratum_383(void) return; =20 /* Use _safe variants to not break nested virtualization */ - if (native_read_msr_safe(MSR_AMD64_DC_CFG, &val)) + if (rdmsrq_safe(MSR_AMD64_DC_CFG, &val)) return; =20 val |=3D (1ULL << 47); =20 - native_write_msr_safe(MSR_AMD64_DC_CFG, val); + wrmsrq_safe(MSR_AMD64_DC_CFG, val); =20 erratum_383_found =3D true; } @@ -471,8 +471,8 @@ static void svm_init_os_visible_workarounds(void) return; =20 if (!this_cpu_has(X86_FEATURE_OSVW) || - native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &len) || - native_read_msr_safe(MSR_AMD64_OSVW_STATUS, &status)) + rdmsrq_safe(MSR_AMD64_OSVW_ID_LENGTH, &len) || + rdmsrq_safe(MSR_AMD64_OSVW_STATUS, &status)) len =3D status =3D 0; =20 if (status =3D=3D READ_ONCE(osvw_status) && len >=3D READ_ONCE(osvw_len)) @@ -2096,7 +2096,7 @@ static bool is_erratum_383(void) if (!erratum_383_found) return false; =20 - if (native_read_msr_safe(MSR_IA32_MC0_STATUS, &value)) + if (rdmsrq_safe(MSR_IA32_MC0_STATUS, &value)) return false; =20 /* Bit 62 may or may not be set for this mce */ @@ -2107,11 +2107,11 @@ static bool is_erratum_383(void) =20 /* Clear MCi_STATUS registers */ for (i =3D 0; i < 6; ++i) - native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0); + wrmsrq_safe(MSR_IA32_MCx_STATUS(i), 0); =20 - if (!native_read_msr_safe(MSR_IA32_MCG_STATUS, &value)) { + if (!rdmsrq_safe(MSR_IA32_MCG_STATUS, &value)) { value &=3D ~(1ULL << 2); - native_write_msr_safe(MSR_IA32_MCG_STATUS, value); + wrmsrq_safe(MSR_IA32_MCG_STATUS, value); } =20 /* Flush tlb to evict multi-match entries */ diff --git a/arch/x86/xen/pmu.c b/arch/x86/xen/pmu.c index 5f50a3ee08f5..37512df8b8f2 100644 --- a/arch/x86/xen/pmu.c +++ b/arch/x86/xen/pmu.c @@ -324,7 +324,7 @@ static u64 xen_amd_read_pmc(int counter) u64 val; =20 msr =3D amd_counters_base + (counter * amd_msr_step); - native_read_msr_safe(msr, &val); + rdmsrq_safe(msr, &val); return val; } =20 @@ -350,7 +350,7 @@ static u64 xen_intel_read_pmc(int counter) else msr =3D MSR_IA32_PERFCTR0 + counter; =20 - native_read_msr_safe(msr, &val); + rdmsrq_safe(msr, &val); return val; } =20 --=20 2.54.0 From nobody Tue Jun 30 05:35:18 2026 Received: from smtp-out1.suse.de (smtp-out1.suse.de [195.135.223.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7456C3BBFC4 for ; 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Mon, 29 Jun 2026 06:56:15 +0000 From: Juergen Gross To: linux-kernel@vger.kernel.org, x86@kernel.org, virtualization@lists.linux.dev Cc: Juergen Gross , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Ajay Kaher , Alexey Makhalov , Broadcom internal kernel review list Subject: [PATCH v4 05/18] x86/msr: Move MSR trace calls one function level up Date: Mon, 29 Jun 2026 08:55:31 +0200 Message-ID: <20260629065544.3643253-6-jgross@suse.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260629065544.3643253-1-jgross@suse.com> References: <20260629065544.3643253-1-jgross@suse.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Rspamd-Pre-Result: action=no action; module=replies; Message is reply to one we originated X-Rspamd-Pre-Result: action=no action; module=replies; Message is reply to one we originated X-Spam-Flag: NO X-Spam-Score: -4.00 X-Spam-Level: X-Rspamd-Server: rspamd2.dmz-prg2.suse.org X-Spamd-Result: default: False [-4.00 / 50.00]; REPLY(-4.00)[] X-Rspamd-Queue-Id: E228E71266 X-Rspamd-Action: no action Content-Type: text/plain; charset="utf-8" In order to prepare paravirt inlining of the MSR access instructions move the calls of MSR trace functions one function level up. Introduce {read|write}_msr[_safe]() helpers allowing to have common definitions in msr.h doing the trace calls. Signed-off-by: Juergen Gross Reviewed-by: H. Peter Anvin (Intel) --- V4: - some modifications removed due to rebase --- arch/x86/include/asm/msr.h | 79 ++++++++++++++++++++++----------- arch/x86/include/asm/paravirt.h | 8 ++-- 2 files changed, 57 insertions(+), 30 deletions(-) diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h index 3b33d432bc24..266298b3d201 100644 --- a/arch/x86/include/asm/msr.h +++ b/arch/x86/include/asm/msr.h @@ -95,14 +95,7 @@ static __always_inline void native_wrmsrq(u32 msr, u64 v= al) =20 static inline u64 native_read_msr(u32 msr) { - u64 val; - - val =3D __rdmsr(msr); - - if (tracepoint_enabled(read_msr)) - do_trace_read_msr(msr, val, 0); - - return val; + return __rdmsr(msr); } =20 static inline int native_read_msr_safe(u32 msr, u64 *p) @@ -115,8 +108,6 @@ static inline int native_read_msr_safe(u32 msr, u64 *p) _ASM_EXTABLE_TYPE_REG(1b, 2b, EX_TYPE_RDMSR_SAFE, %[err]) : [err] "=3Dr" (err), EAX_EDX_RET(val, low, high) : "c" (msr)); - if (tracepoint_enabled(read_msr)) - do_trace_read_msr(msr, EAX_EDX_VAL(val, low, high), err); =20 *p =3D EAX_EDX_VAL(val, low, high); =20 @@ -127,9 +118,6 @@ static inline int native_read_msr_safe(u32 msr, u64 *p) static inline void notrace native_write_msr(u32 msr, u64 val) { native_wrmsrq(msr, val); - - if (tracepoint_enabled(write_msr)) - do_trace_write_msr(msr, val, 0); } =20 /* Can be uninlined because referenced by paravirt */ @@ -143,8 +131,6 @@ static inline int notrace native_write_msr_safe(u32 msr= , u64 val) : [err] "=3Da" (err) : "c" (msr), "0" ((u32)val), "d" ((u32)(val >> 32)) : "memory"); - if (tracepoint_enabled(write_msr)) - do_trace_write_msr(msr, val, err); return err; } =20 @@ -165,36 +151,77 @@ static inline u64 native_read_pmc(int counter) #include #else #include - -/* Access to machine-specific registers (available on 586 and better only)= */ - -static __always_inline u64 rdmsrq(u32 msr) +static __always_inline u64 read_msr(u32 msr) { return native_read_msr(msr); } =20 -static inline void wrmsrq(u32 msr, u64 val) +static __always_inline int read_msr_safe(u32 msr, u64 *p) +{ + return native_read_msr_safe(msr, p); +} + +static __always_inline void write_msr(u32 msr, u64 val) { native_write_msr(msr, val); } =20 -/* wrmsr with exception handling */ -static inline int wrmsrq_safe(u32 msr, u64 val) +static __always_inline int write_msr_safe(u32 msr, u64 val) { return native_write_msr_safe(msr, val); } =20 +static __always_inline u64 rdpmc(int counter) +{ + return native_read_pmc(counter); +} +#endif /* !CONFIG_PARAVIRT_XXL */ + +/* Access to machine-specific registers (available on 586 and better only)= */ + +static __always_inline u64 rdmsrq(u32 msr) +{ + u64 val =3D read_msr(msr); + + if (tracepoint_enabled(read_msr)) + do_trace_read_msr(msr, val, 0); + + return val; +} + +/* rdmsr with exception handling */ static inline int rdmsrq_safe(u32 msr, u64 *p) { - return native_read_msr_safe(msr, p); + int err; + + err =3D read_msr_safe(msr, p); + + if (tracepoint_enabled(read_msr)) + do_trace_read_msr(msr, *p, err); + + return err; } =20 -static __always_inline u64 rdpmc(int counter) +static inline void wrmsrq(u32 msr, u64 val) { - return native_read_pmc(counter); + write_msr(msr, val); + + if (tracepoint_enabled(write_msr)) + do_trace_write_msr(msr, val, 0); } =20 -#endif /* !CONFIG_PARAVIRT_XXL */ +/* wrmsr with exception handling */ +static inline int wrmsrq_safe(u32 msr, u64 val) +{ + int err; + + err =3D write_msr_safe(msr, val); + + if (tracepoint_enabled(write_msr)) + do_trace_write_msr(msr, val, err); + + return err; +} =20 /* Instruction opcode for WRMSRNS supported in binutils >=3D 2.40 */ #define ASM_WRMSRNS _ASM_BYTES(0x0f,0x01,0xc6) diff --git a/arch/x86/include/asm/paravirt.h b/arch/x86/include/asm/paravir= t.h index 19442bc3af37..a5a1fc4c88d1 100644 --- a/arch/x86/include/asm/paravirt.h +++ b/arch/x86/include/asm/paravirt.h @@ -150,22 +150,22 @@ static inline int paravirt_write_msr_safe(u32 msr, u6= 4 val) return PVOP_CALL2(int, pv_ops, cpu.write_msr_safe, msr, val); } =20 -static __always_inline u64 rdmsrq(u32 msr) +static __always_inline u64 read_msr(u32 msr) { return paravirt_read_msr(msr); } =20 -static inline void wrmsrq(u32 msr, u64 val) +static inline void write_msr(u32 msr, u64 val) { paravirt_write_msr(msr, val); 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Y. Srinivasan" , Haiyang Zhang , Wei Liu , Dexuan Cui , Long Li , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , kernel test robot Subject: [PATCH v4 06/18] x86/hyperv: Switch from __rdmsr() to native_rdmsrq() Date: Mon, 29 Jun 2026 08:55:32 +0200 Message-ID: <20260629065544.3643253-7-jgross@suse.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260629065544.3643253-1-jgross@suse.com> References: <20260629065544.3643253-1-jgross@suse.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Spam-Flag: NO X-Spamd-Result: default: False [-6.80 / 50.00]; REPLY(-4.00)[]; BAYES_HAM(-3.00)[99.99%]; MID_CONTAINS_FROM(1.00)[]; NEURAL_HAM_LONG(-1.00)[-1.000]; R_MISSING_CHARSET(0.50)[]; NEURAL_HAM_SHORT(-0.20)[-1.000]; MIME_GOOD(-0.10)[text/plain]; DBL_BLOCKED_OPENRESOLVER(0.00)[suse.com:email,suse.com:mid,imap1.dmz-prg2.suse.org:helo]; ARC_NA(0.00)[]; MIME_TRACE(0.00)[0:+]; TO_DN_SOME(0.00)[]; RCPT_COUNT_TWELVE(0.00)[15]; RCVD_VIA_SMTP_AUTH(0.00)[]; FUZZY_RATELIMITED(0.00)[rspamd.com]; FROM_HAS_DN(0.00)[]; TO_MATCH_ENVRCPT_ALL(0.00)[]; FROM_EQ_ENVFROM(0.00)[]; RCVD_COUNT_TWO(0.00)[2]; R_RATELIMIT(0.00)[to_ip_from(RLfdszjqhz8kzzb9uwpzdm8png)]; DKIM_SIGNED(0.00)[suse.com:s=susede1]; RCVD_TLS_ALL(0.00)[] X-Spam-Level: X-Spam-Score: -6.80 Content-Type: text/plain; charset="utf-8" The __rdmsr() helper will be changed soon, so don't use it directly outside of msr.h. Switch to native_rdmsrq() in HyperV related code. Reported-by: kernel test robot Closes: https://lore.kernel.org/oe-kbuild-all/202602182222.WEBLSQRj-lkp@int= el.com/ Signed-off-by: Juergen Gross --- V4: - new patch (kernel test robot) --- arch/x86/hyperv/hv_crash.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/x86/hyperv/hv_crash.c b/arch/x86/hyperv/hv_crash.c index 5ffcc23255de..28ee76e18d9b 100644 --- a/arch/x86/hyperv/hv_crash.c +++ b/arch/x86/hyperv/hv_crash.c @@ -217,9 +217,9 @@ static void hv_hvcrash_ctxt_save(void) native_store_gdt(&ctxt->gdtr); store_idt(&ctxt->idtr); =20 - ctxt->gsbase =3D __rdmsr(MSR_GS_BASE); - ctxt->efer =3D __rdmsr(MSR_EFER); - ctxt->pat =3D __rdmsr(MSR_IA32_CR_PAT); + ctxt->gsbase =3D native_rdmsrq(MSR_GS_BASE); + ctxt->efer =3D native_rdmsrq(MSR_EFER); + ctxt->pat =3D native_rdmsrq(MSR_IA32_CR_PAT); } =20 /* Add trampoline page to the kernel pagetable for transition to kernel PT= */ --=20 2.54.0 From nobody Tue Jun 30 05:35:18 2026 Received: from smtp-out2.suse.de (smtp-out2.suse.de [195.135.223.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5A1393B2FE9 for ; Mon, 29 Jun 2026 06:56:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=195.135.223.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782716197; cv=none; b=sml6iBIFv8GI0yjN0OL85yeRLZ0rpL0pwUW8WduTuV088yorQPLs6SKdff8t1VOG3HGpCjW+qmFx1HWyIHV1BYtsUo6jvE2qQbZlBq+EouJG5TQnv6WXXpJOnec1T/6L4XXtL8m4HkJ2KgLThF+Y9Tei/KxewRMDMkmQsmirUrM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782716197; c=relaxed/simple; bh=hr7GAukJD5fqcRcDv6REQBBMZcTokY4Pyi0UBxZ1Z+A=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=FPHCPac2XL4JSn51oFqaqzRhgh+j1aCl+RDEh1GP7vwYksfkG3fdAHTNyu6sNpPWanrmTuhByeY+aiERbt0x84u3ylDbcJmHWjyIWHiaP50HinzWWwKZ87hiWz9m0blfzwm0xdLWiviBWztC77syEbOKkubS3psQ5qfeuqXXq1Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=suse.com; spf=pass smtp.mailfrom=suse.com; arc=none smtp.client-ip=195.135.223.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=suse.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=suse.com Received: from imap1.dmz-prg2.suse.org (imap1.dmz-prg2.suse.org [IPv6:2a07:de40:b281:104:10:150:64:97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by smtp-out2.suse.de (Postfix) with ESMTPS id 6310C75ADB; Mon, 29 Jun 2026 06:56:27 +0000 (UTC) Authentication-Results: smtp-out2.suse.de; none Received: from imap1.dmz-prg2.suse.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by imap1.dmz-prg2.suse.org (Postfix) with ESMTPS id 1B460779A8; Mon, 29 Jun 2026 06:56:27 +0000 (UTC) Received: from dovecot-director2.suse.de ([2a07:de40:b281:106:10:150:64:167]) by imap1.dmz-prg2.suse.org with ESMTPSA id isIaBRsXQmrOQQAAD6G6ig (envelope-from ); Mon, 29 Jun 2026 06:56:27 +0000 From: Juergen Gross To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: Juergen Gross , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , "Xin Li (Intel)" Subject: [PATCH v4 07/18] x86/opcode: Add immediate form MSR instructions Date: Mon, 29 Jun 2026 08:55:33 +0200 Message-ID: <20260629065544.3643253-8-jgross@suse.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260629065544.3643253-1-jgross@suse.com> References: <20260629065544.3643253-1-jgross@suse.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Rspamd-Pre-Result: action=no action; module=replies; Message is reply to one we originated X-Rspamd-Queue-Id: 6310C75ADB X-Spam-Flag: NO X-Spam-Score: -4.00 X-Spam-Level: X-Rspamd-Action: no action X-Rspamd-Server: rspamd1.dmz-prg2.suse.org X-Rspamd-Pre-Result: action=no action; module=replies; Message is reply to one we originated X-Spamd-Result: default: False [-4.00 / 50.00]; REPLY(-4.00)[] Content-Type: text/plain; charset="utf-8" Add the instruction opcodes used by the immediate form WRMSRNS/RDMSR to x86-opcode-map. Signed-off-by: Xin Li (Intel) Signed-off-by: Juergen Gross Reviewed-by: H. Peter Anvin (Intel) --- V2: - new patch, taken from the RFC v2 MSR refactor series by Xin Li --- arch/x86/lib/x86-opcode-map.txt | 5 +++-- tools/arch/x86/lib/x86-opcode-map.txt | 5 +++-- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/arch/x86/lib/x86-opcode-map.txt b/arch/x86/lib/x86-opcode-map.= txt index 2a4e69ecc2de..62f7c90b9a83 100644 --- a/arch/x86/lib/x86-opcode-map.txt +++ b/arch/x86/lib/x86-opcode-map.txt @@ -844,7 +844,7 @@ f1: MOVBE My,Gy | MOVBE Mw,Gw (66) | CRC32 Gd,Ey (F2) |= CRC32 Gd,Ew (66&F2) f2: ANDN Gy,By,Ey (v) f3: Grp17 (1A) f5: BZHI Gy,Ey,By (v) | PEXT Gy,By,Ey (F3),(v) | PDEP Gy,By,Ey (F2),(v) | = WRUSSD/Q My,Gy (66) -f6: ADCX Gy,Ey (66) | ADOX Gy,Ey (F3) | MULX By,Gy,rDX,Ey (F2),(v) | WRSSD= /Q My,Gy +f6: ADCX Gy,Ey (66) | ADOX Gy,Ey (F3) | MULX By,Gy,rDX,Ey (F2),(v) | WRSSD= /Q My,Gy | RDMSR Rq,Gq (F2),(11B) | WRMSRNS Gq,Rq (F3),(11B) f7: BEXTR Gy,Ey,By (v) | SHLX Gy,Ey,By (66),(v) | SARX Gy,Ey,By (F3),(v) |= SHRX Gy,Ey,By (F2),(v) f8: MOVDIR64B Gv,Mdqq (66) | ENQCMD Gv,Mdqq (F2) | ENQCMDS Gv,Mdqq (F3) | = URDMSR Rq,Gq (F2),(11B) | UWRMSR Gq,Rq (F3),(11B) f9: MOVDIRI My,Gy @@ -1019,7 +1019,7 @@ f1: CRC32 Gy,Ey (es) | CRC32 Gy,Ey (66),(es) | INVVPI= D Gy,Mdq (F3),(ev) f2: INVPCID Gy,Mdq (F3),(ev) f4: TZCNT Gv,Ev (es) | TZCNT Gv,Ev (66),(es) f5: LZCNT Gv,Ev (es) | LZCNT Gv,Ev (66),(es) -f6: Grp3_1 Eb (1A),(ev) +f6: Grp3_1 Eb (1A),(ev) | RDMSR Rq,Gq (F2),(11B),(ev) | WRMSRNS Gq,Rq (F3)= ,(11B),(ev) f7: Grp3_2 Ev (1A),(es) f8: MOVDIR64B Gv,Mdqq (66),(ev) | ENQCMD Gv,Mdqq (F2),(ev) | ENQCMDS Gv,Md= qq (F3),(ev) | URDMSR Rq,Gq (F2),(11B),(ev) | UWRMSR Gq,Rq (F3),(11B),(ev) f9: MOVDIRI My,Gy (ev) @@ -1108,6 +1108,7 @@ EndTable Table: VEX map 7 Referrer: AVXcode: 7 +f6: RDMSR Rq,Id (F2),(v1),(11B) | WRMSRNS Id,Rq (F3),(v1),(11B) f8: URDMSR Rq,Id (F2),(v1),(11B) | UWRMSR Id,Rq (F3),(v1),(11B) EndTable =20 diff --git a/tools/arch/x86/lib/x86-opcode-map.txt b/tools/arch/x86/lib/x86= -opcode-map.txt index 2a4e69ecc2de..62f7c90b9a83 100644 --- a/tools/arch/x86/lib/x86-opcode-map.txt +++ b/tools/arch/x86/lib/x86-opcode-map.txt @@ -844,7 +844,7 @@ f1: MOVBE My,Gy | MOVBE Mw,Gw (66) | CRC32 Gd,Ey (F2) |= CRC32 Gd,Ew (66&F2) f2: ANDN Gy,By,Ey (v) f3: Grp17 (1A) f5: BZHI Gy,Ey,By (v) | PEXT Gy,By,Ey (F3),(v) | PDEP Gy,By,Ey (F2),(v) | = WRUSSD/Q My,Gy (66) -f6: ADCX Gy,Ey (66) | ADOX Gy,Ey (F3) | MULX By,Gy,rDX,Ey (F2),(v) | WRSSD= /Q My,Gy +f6: ADCX Gy,Ey (66) | ADOX Gy,Ey (F3) | MULX By,Gy,rDX,Ey (F2),(v) | WRSSD= /Q My,Gy | RDMSR Rq,Gq (F2),(11B) | WRMSRNS Gq,Rq (F3),(11B) f7: BEXTR Gy,Ey,By (v) | SHLX Gy,Ey,By (66),(v) | SARX Gy,Ey,By (F3),(v) |= SHRX Gy,Ey,By (F2),(v) f8: MOVDIR64B Gv,Mdqq (66) | ENQCMD Gv,Mdqq (F2) | ENQCMDS Gv,Mdqq (F3) | = URDMSR Rq,Gq (F2),(11B) | UWRMSR Gq,Rq (F3),(11B) f9: MOVDIRI My,Gy @@ -1019,7 +1019,7 @@ f1: CRC32 Gy,Ey (es) | CRC32 Gy,Ey (66),(es) | INVVPI= D Gy,Mdq (F3),(ev) f2: INVPCID Gy,Mdq (F3),(ev) f4: TZCNT Gv,Ev (es) | TZCNT Gv,Ev (66),(es) f5: LZCNT Gv,Ev (es) | LZCNT Gv,Ev (66),(es) -f6: Grp3_1 Eb (1A),(ev) +f6: Grp3_1 Eb (1A),(ev) | RDMSR Rq,Gq (F2),(11B),(ev) | WRMSRNS Gq,Rq (F3)= ,(11B),(ev) f7: Grp3_2 Ev (1A),(es) f8: MOVDIR64B Gv,Mdqq (66),(ev) | ENQCMD Gv,Mdqq (F2),(ev) | ENQCMDS Gv,Md= qq (F3),(ev) | URDMSR Rq,Gq (F2),(11B),(ev) | UWRMSR Gq,Rq (F3),(11B),(ev) f9: MOVDIRI My,Gy (ev) @@ -1108,6 +1108,7 @@ EndTable Table: VEX map 7 Referrer: AVXcode: 7 +f6: RDMSR Rq,Id (F2),(v1),(11B) | WRMSRNS Id,Rq (F3),(v1),(11B) f8: URDMSR Rq,Id (F2),(v1),(11B) | UWRMSR Id,Rq (F3),(v1),(11B) EndTable =20 --=20 2.54.0 From nobody Tue Jun 30 05:35:18 2026 Received: from smtp-out1.suse.de (smtp-out1.suse.de [195.135.223.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 214F63B4E9A for ; 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Peter Anvin" , "Xin Li (Intel)" Subject: [PATCH v4 08/18] x86/extable: Add support for immediate form MSR instructions Date: Mon, 29 Jun 2026 08:55:34 +0200 Message-ID: <20260629065544.3643253-9-jgross@suse.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260629065544.3643253-1-jgross@suse.com> References: <20260629065544.3643253-1-jgross@suse.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Spam-Flag: NO X-Spam-Score: -6.80 X-Spamd-Result: default: False [-6.80 / 50.00]; REPLY(-4.00)[]; BAYES_HAM(-3.00)[100.00%]; MID_CONTAINS_FROM(1.00)[]; NEURAL_HAM_LONG(-1.00)[-1.000]; R_MISSING_CHARSET(0.50)[]; NEURAL_HAM_SHORT(-0.20)[-1.000]; MIME_GOOD(-0.10)[text/plain]; MIME_TRACE(0.00)[0:+]; FUZZY_RATELIMITED(0.00)[rspamd.com]; ARC_NA(0.00)[]; RCVD_VIA_SMTP_AUTH(0.00)[]; TO_DN_SOME(0.00)[]; RCPT_COUNT_SEVEN(0.00)[11]; DKIM_SIGNED(0.00)[suse.com:s=susede1]; FROM_EQ_ENVFROM(0.00)[]; FROM_HAS_DN(0.00)[]; R_RATELIMIT(0.00)[to_ip_from(RLfdszjqhz8kzzb9uwpzdm8png)]; DBL_BLOCKED_OPENRESOLVER(0.00)[imap1.dmz-prg2.suse.org:helo,suse.com:email,suse.com:mid,zytor.com:email]; RCVD_COUNT_TWO(0.00)[2]; TO_MATCH_ENVRCPT_ALL(0.00)[]; RCVD_TLS_ALL(0.00)[] X-Spam-Level: Content-Type: text/plain; charset="utf-8" Signed-off-by: Xin Li (Intel) Signed-off-by: Juergen Gross --- V2: - new patch, taken from the RFC v2 MSR refactor series by Xin Li V3: - use instruction decoder (Peter Zijlstra) V4: - don't assume %rax for immediate form (Andrew Cooper) --- arch/x86/mm/extable.c | 46 +++++++++++++++++++++++++++++++++++++------ 1 file changed, 40 insertions(+), 6 deletions(-) diff --git a/arch/x86/mm/extable.c b/arch/x86/mm/extable.c index ceb8d03191ab..9974785c8968 100644 --- a/arch/x86/mm/extable.c +++ b/arch/x86/mm/extable.c @@ -166,25 +166,59 @@ static bool ex_handler_uaccess(const struct exception= _table_entry *fixup, static bool ex_handler_msr(const struct exception_table_entry *fixup, struct pt_regs *regs, bool wrmsr, bool safe, int reg) { + unsigned long *regptr; + struct insn insn; + bool imm_insn; + u32 msr; + + imm_insn =3D insn_decode_kernel(&insn, (void *)regs->ip) && + insn.vex_prefix.nbytes; + msr =3D imm_insn ? insn.immediate.value : (u32)regs->cx; + regptr =3D imm_insn ? insn_get_modrm_reg_ptr(&insn, regs) : ®s->ax; + if (unlikely(!regptr)) { + pr_err("Inconsistent %sMSR access instruction data at rIP: 0x%lx (%pS)!\= n", + wrmsr ? "WR" : "RD", regs->ip, (void *)regs->ip); + show_stack_regs(regs); + goto out; + } + if (__ONCE_LITE_IF(!safe && wrmsr)) { - pr_warn("unchecked MSR access error: WRMSR to 0x%x (tried to write 0x%08= x%08x) at rIP: 0x%lx (%pS)\n", - (unsigned int)regs->cx, (unsigned int)regs->dx, - (unsigned int)regs->ax, regs->ip, (void *)regs->ip); + /* + * To maintain consistency with existing RDMSR and WRMSR(NS) instruction= s, + * the register operand for immediate form MSR instructions is ALWAYS + * encoded as RAX in for reading or writing the MSR value. + */ + u64 msr_val =3D *regptr; + + if (!imm_insn) { + /* + * On processors that support the Intel 64 architecture, the + * high-order 32 bits of each of RAX and RDX are ignored. + */ + msr_val &=3D 0xffffffff; + msr_val |=3D (u64)regs->dx << 32; + } + + pr_warn("unchecked MSR access error: WRMSR to 0x%x (tried to write 0x%01= 6llx) at rIP: 0x%lx (%pS)\n", + msr, msr_val, regs->ip, (void *)regs->ip); show_stack_regs(regs); } =20 if (__ONCE_LITE_IF(!safe && !wrmsr)) { pr_warn("unchecked MSR access error: RDMSR from 0x%x at rIP: 0x%lx (%pS)= \n", - (unsigned int)regs->cx, regs->ip, (void *)regs->ip); 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Peter Anvin" , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , Ajay Kaher , Alexey Makhalov , Broadcom internal kernel review list , Nathan Chancellor , Nick Desaulniers , Bill Wendling , Justin Stitt Subject: [PATCH v4 09/18] x86/msr: Make wrmsrns() a first class citizen Date: Mon, 29 Jun 2026 08:55:35 +0200 Message-ID: <20260629065544.3643253-10-jgross@suse.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260629065544.3643253-1-jgross@suse.com> References: <20260629065544.3643253-1-jgross@suse.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Spam-Flag: NO X-Spamd-Result: default: False [-5.30 / 50.00]; REPLY(-4.00)[]; BAYES_HAM(-3.00)[100.00%]; SUSPICIOUS_RECIPS(1.50)[]; MID_CONTAINS_FROM(1.00)[]; NEURAL_HAM_LONG(-1.00)[-1.000]; R_MISSING_CHARSET(0.50)[]; NEURAL_HAM_SHORT(-0.20)[-1.000]; MIME_GOOD(-0.10)[text/plain]; ARC_NA(0.00)[]; RCVD_VIA_SMTP_AUTH(0.00)[]; FUZZY_RATELIMITED(0.00)[rspamd.com]; TO_MATCH_ENVRCPT_ALL(0.00)[]; RCPT_COUNT_TWELVE(0.00)[18]; MIME_TRACE(0.00)[0:+]; TO_DN_SOME(0.00)[]; FROM_EQ_ENVFROM(0.00)[]; TAGGED_RCPT(0.00)[lkml]; RCVD_TLS_ALL(0.00)[]; DBL_BLOCKED_OPENRESOLVER(0.00)[zytor.com:email,suse.com:email,suse.com:mid,imap1.dmz-prg2.suse.org:helo]; RCVD_COUNT_TWO(0.00)[2]; FREEMAIL_CC(0.00)[suse.com,zytor.com,kernel.org,redhat.com,alien8.de,linux.intel.com,broadcom.com,gmail.com,google.com]; DKIM_SIGNED(0.00)[suse.com:s=susede1]; R_RATELIMIT(0.00)[to_ip_from(RLfdszjqhz8kzzb9uwpzdm8png)]; FROM_HAS_DN(0.00)[]; FREEMAIL_ENVRCPT(0.00)[gmail.com] X-Spam-Level: X-Spam-Score: -5.30 Content-Type: text/plain; charset="utf-8" Today wrmsrns() is - apart from the potential use of the wrmsrns instruction - equivalent to __wrmsrq(). Change that by supporting MSR write trace entries and a safe variant. wrmsrns() and wrmsrns_safe() will be the "normal" interfaces like wrmsrq() and wrmsrq_safe(). They will call write_msrns[_safe]() and conditionally create trace entries via do_trace_write_msr(). write_msrns[_safe]() are different between paravirt and non-paravirt cases. For the paravirt case they will (for now) only use the wrmsr paravirt functions, while for non-paravirt they call native_wrmsrns() and native_wrmsrns_safe(). native_wrmsrns() is like wrmsrns() today, native_wrmsrns_safe() is just the safe variant of it. The both rely on __wrmsrns(), which will use the ALTERNATIVE*() macros for selecting WRMSR or WRMSRNS (with or without an immediate operand specifying the MSR register) depending on availability. Switch the wrmsrns() call in fred_update_rsp0() to native_wrmsrns() in order to avoid a change of functionality. The wrmsrns() call in vmx_write_guest_host_msr() can be kept, as it has replaced a wrmsrq() call, so eventually creating a trace entry is obviously fine here. Originally-by: Xin Li (Intel) Signed-off-by: Juergen Gross --- V2: - new patch, partially taken from "[RFC PATCH v2 21/34] x86/msr: Utilize the alternatives mechanism to write MSR" by Xin Li. V4: - don't modify __wrmsrq(), but create __wrmsrns(). --- arch/x86/include/asm/fred.h | 2 +- arch/x86/include/asm/msr.h | 150 +++++++++++++++++++++++++++++--- arch/x86/include/asm/paravirt.h | 10 +++ 3 files changed, 148 insertions(+), 14 deletions(-) diff --git a/arch/x86/include/asm/fred.h b/arch/x86/include/asm/fred.h index 18a2f811c358..0a6773b76968 100644 --- a/arch/x86/include/asm/fred.h +++ b/arch/x86/include/asm/fred.h @@ -101,7 +101,7 @@ static __always_inline void fred_update_rsp0(void) unsigned long rsp0 =3D (unsigned long) task_stack_page(current) + THREAD_= SIZE; =20 if (cpu_feature_enabled(X86_FEATURE_FRED) && (__this_cpu_read(fred_rsp0) = !=3D rsp0)) { - wrmsrns(MSR_IA32_FRED_RSP0, rsp0); + native_wrmsrns(MSR_IA32_FRED_RSP0, rsp0); __this_cpu_write(fred_rsp0, rsp0); } } diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h index 266298b3d201..91d6f481732b 100644 --- a/arch/x86/include/asm/msr.h +++ b/arch/x86/include/asm/msr.h @@ -7,11 +7,11 @@ #ifndef __ASSEMBLER__ =20 #include -#include #include #include #include =20 +#include #include #include =20 @@ -56,6 +56,36 @@ static inline void do_trace_read_msr(u32 msr, u64 val, i= nt failed) {} static inline void do_trace_rdpmc(u32 msr, u64 val, int failed) {} #endif =20 +/* The GNU Assembler (Gas) with Binutils 2.40 adds WRMSRNS support */ +#if defined(CONFIG_AS_IS_GNU) && CONFIG_AS_VERSION >=3D 24000 +#define ASM_WRMSRNS "wrmsrns\n\t" +#else +#define ASM_WRMSRNS _ASM_BYTES(0x0f,0x01,0xc6) +#endif + +/* The GNU Assembler (Gas) with Binutils 2.41 adds the .insn directive sup= port */ +#if defined(CONFIG_AS_IS_GNU) && CONFIG_AS_VERSION >=3D 24100 +#define ASM_WRMSRNS_IMM \ + " .insn VEX.128.F3.M7.W0 0xf6 /0, %[val], %[msr]%{:u32}\n\t" +#else +/* + * Note, clang also doesn't support the .insn directive. + * + * The register operand is encoded as %rax because all uses of the immedia= te + * form MSR access instructions reference %rax as the register operand. + */ +#define ASM_WRMSRNS_IMM \ + " .byte 0xc4,0xe7,0x7a,0xf6,0xc0; .long %c[msr]" +#endif + +#define PREPARE_RDX_FOR_WRMSR \ + "mov %%rax, %%rdx\n\t" \ + "shr $0x20, %%rdx\n\t" + +#define PREPARE_RCX_RDX_FOR_WRMSR \ + "mov %[msr], %%ecx\n\t" \ + PREPARE_RDX_FOR_WRMSR + /* * __rdmsr() and __wrmsr() are the two primitives which are the bare minim= um MSR * accessors and should not have any tracing or other functionality piggyb= acking @@ -83,6 +113,78 @@ static __always_inline void __wrmsrq(u32 msr, u64 val) : : "c" (msr), "a" ((u32)val), "d" ((u32)(val >> 32)) : "memory"); } =20 +static __always_inline bool __wrmsrns_variable(u32 msr, u64 val, int type) +{ +#ifdef CONFIG_X86_64 + BUILD_BUG_ON(__builtin_constant_p(msr)); +#endif + + /* + * WRMSR is 2 bytes. WRMSRNS is 3 bytes. Pad WRMSR with a redundant + * DS prefix to avoid a trailing NOP. + */ + asm_inline volatile goto( + "1:\n" + ALTERNATIVE("ds wrmsr", + ASM_WRMSRNS, + X86_FEATURE_WRMSRNS) + _ASM_EXTABLE_TYPE(1b, %l[badmsr], %c[type]) + + : + : "c" (msr), "a" ((u32)val), "d" ((u32)(val >> 32)), [type] "i" (type) + : "memory" + : badmsr); + + return false; + +badmsr: + return true; +} + +#ifdef CONFIG_X86_64 +/* + * Non-serializing WRMSR or its immediate form, when available. + * + * Otherwise, it falls back to a serializing WRMSR. + */ +static __always_inline bool __wrmsrns_constant(u32 msr, u64 val, int type) +{ + BUILD_BUG_ON(!__builtin_constant_p(msr)); + + asm_inline volatile goto( + "1:\n" + ALTERNATIVE_2(PREPARE_RCX_RDX_FOR_WRMSR + "2: ds wrmsr", + PREPARE_RCX_RDX_FOR_WRMSR + ASM_WRMSRNS, + X86_FEATURE_WRMSRNS, + ASM_WRMSRNS_IMM, + X86_FEATURE_MSR_IMM) + _ASM_EXTABLE_TYPE(1b, %l[badmsr], %c[type]) /* For WRMSRNS immediate */ + _ASM_EXTABLE_TYPE(2b, %l[badmsr], %c[type]) /* For WRMSR(NS) */ + + : + : [val] "a" (val), [msr] "i" (msr), [type] "i" (type) + : "memory", "ecx", "rdx" + : badmsr); + + return false; + +badmsr: + return true; +} +#endif + +static __always_inline bool __wrmsrns(u32 msr, u64 val, int type) +{ +#ifdef CONFIG_X86_64 + if (__builtin_constant_p(msr)) + return __wrmsrns_constant(msr, val, type); +#endif + + return __wrmsrns_variable(msr, val, type); +} + static __always_inline u64 native_rdmsrq(u32 msr) { return __rdmsr(msr); @@ -134,6 +236,16 @@ static inline int notrace native_write_msr_safe(u32 ms= r, u64 val) return err; } =20 +static __always_inline void native_wrmsrns(u32 msr, u64 val) +{ + __wrmsrns(msr, val, EX_TYPE_WRMSR); +} + +static __always_inline int native_wrmsrns_safe(u32 msr, u64 val) +{ + return __wrmsrns(msr, val, EX_TYPE_WRMSR_SAFE) ? -EIO : 0; +} + extern int rdmsr_safe_regs(u32 regs[8]); extern int wrmsr_safe_regs(u32 regs[8]); =20 @@ -150,7 +262,6 @@ static inline u64 native_read_pmc(int counter) #ifdef CONFIG_PARAVIRT_XXL #include #else -#include static __always_inline u64 read_msr(u32 msr) { return native_read_msr(msr); @@ -171,6 +282,16 @@ static __always_inline int write_msr_safe(u32 msr, u64= val) return native_write_msr_safe(msr, val); } =20 +static __always_inline void write_msrns(u32 msr, u64 val) +{ + native_wrmsrns(msr, val); +} + +static __always_inline int write_msrns_safe(u32 msr, u64 val) +{ + return native_wrmsrns_safe(msr, val); +} + static __always_inline u64 rdpmc(int counter) { return native_read_pmc(counter); @@ -223,19 +344,22 @@ static inline int wrmsrq_safe(u32 msr, u64 val) return err; } =20 -/* Instruction opcode for WRMSRNS supported in binutils >=3D 2.40 */ -#define ASM_WRMSRNS _ASM_BYTES(0x0f,0x01,0xc6) - -/* Non-serializing WRMSR, when available. Falls back to a serializing WRM= SR. */ static __always_inline void wrmsrns(u32 msr, u64 val) { - /* - * WRMSR is 2 bytes. WRMSRNS is 3 bytes. Pad WRMSR with a redundant - * DS prefix to avoid a trailing NOP. - */ - asm volatile("1: " ALTERNATIVE("ds wrmsr", ASM_WRMSRNS, X86_FEATURE_WRMSR= NS) - "2: " _ASM_EXTABLE_TYPE(1b, 2b, EX_TYPE_WRMSR) - : : "c" (msr), "a" ((u32)val), "d" ((u32)(val >> 32))); + write_msrns(msr, val); + + if (tracepoint_enabled(write_msr)) + do_trace_write_msr(msr, val, 0); +} + +static __always_inline int wrmsrns_safe(u32 msr, u64 val) +{ + int err =3D write_msrns_safe(msr, val); + + if (tracepoint_enabled(write_msr)) + do_trace_write_msr(msr, val, err); + + return err; } =20 struct msr __percpu *msrs_alloc(void); diff --git a/arch/x86/include/asm/paravirt.h b/arch/x86/include/asm/paravir= t.h index a5a1fc4c88d1..b0c740316cf7 100644 --- a/arch/x86/include/asm/paravirt.h +++ b/arch/x86/include/asm/paravirt.h @@ -160,11 +160,21 @@ static inline void write_msr(u32 msr, u64 val) paravirt_write_msr(msr, val); } =20 +static __always_inline void write_msrns(u32 msr, u64 val) +{ + paravirt_write_msr(msr, val); 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Peter Anvin" Subject: [PATCH v4 10/18] x86/msr: Introduce sync_cpu_after_wrmsrns() Date: Mon, 29 Jun 2026 08:55:36 +0200 Message-ID: <20260629065544.3643253-11-jgross@suse.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260629065544.3643253-1-jgross@suse.com> References: <20260629065544.3643253-1-jgross@suse.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Spam-Flag: NO X-Spamd-Result: default: False [-6.80 / 50.00]; REPLY(-4.00)[]; BAYES_HAM(-3.00)[100.00%]; MID_CONTAINS_FROM(1.00)[]; NEURAL_HAM_LONG(-1.00)[-1.000]; R_MISSING_CHARSET(0.50)[]; NEURAL_HAM_SHORT(-0.20)[-1.000]; MIME_GOOD(-0.10)[text/plain]; MIME_TRACE(0.00)[0:+]; FUZZY_RATELIMITED(0.00)[rspamd.com]; ARC_NA(0.00)[]; RCVD_VIA_SMTP_AUTH(0.00)[]; TO_DN_SOME(0.00)[]; RCPT_COUNT_SEVEN(0.00)[8]; DKIM_SIGNED(0.00)[suse.com:s=susede1]; FROM_EQ_ENVFROM(0.00)[]; FROM_HAS_DN(0.00)[]; R_RATELIMIT(0.00)[to_ip_from(RLfdszjqhz8kzzb9uwpzdm8png)]; DBL_BLOCKED_OPENRESOLVER(0.00)[zytor.com:email,suse.com:email,suse.com:mid,imap1.dmz-prg2.suse.org:helo]; RCVD_COUNT_TWO(0.00)[2]; TO_MATCH_ENVRCPT_ALL(0.00)[]; RCVD_TLS_ALL(0.00)[] X-Spam-Level: X-Spam-Score: -6.80 Content-Type: text/plain; charset="utf-8" In order to allow using wrmsrns() for multiple MSR register writes introduce sync_cpu_after_wrmsrns() which will then do a CPU serialize operation, if the hardware does support the WRMSRNS instruction. In case the hardware doesn't support WRMSRNS, sync_cpu_after_wrmsrns() will be a NOP. Suggested-by: H. Peter Anvin Signed-off-by: Juergen Gross --- V4: - new patch --- arch/x86/include/asm/msr.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h index 91d6f481732b..40bb03df162c 100644 --- a/arch/x86/include/asm/msr.h +++ b/arch/x86/include/asm/msr.h @@ -14,6 +14,7 @@ #include #include #include +#include =20 struct msr_info { u32 msr_no; @@ -362,6 +363,12 @@ static __always_inline int wrmsrns_safe(u32 msr, u64 v= al) return err; } =20 +static __always_inline void sync_cpu_after_wrmsrns(void) +{ + if (static_cpu_has(X86_FEATURE_WRMSRNS)) + serialize(); +} + struct msr __percpu *msrs_alloc(void); void msrs_free(struct msr __percpu *msrs); int msr_set_bit(u32 msr, u8 bit); --=20 2.54.0 From nobody Tue Jun 30 05:35:18 2026 Received: from smtp-out2.suse.de (smtp-out2.suse.de [195.135.223.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8D21EE54B for ; Mon, 29 Jun 2026 06:56:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=195.135.223.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782716220; cv=none; b=Xs+ki2W7OG4d/Gq5+WKjWYTA8QohjUWbZlK3X/+dIJixq9AbZT1xx9BjT3KVad3EOwncSko8ANXq0spaXvceKWGBCP+r1LhiMw+uOaPCH2WaNQ+//U8Ex3KUVDmloXzVusUed8WqXoFzyfU+0EmqX4GrNPiKRzSwNSXujp8UWkY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782716220; c=relaxed/simple; bh=bu5DRfzzUEyuO2Lo+UleBY4Lbk0IQhvPFaRBoiQ4cmo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=qq99diWKpeUipUJujjL0AKss6IZrTDbzoxMpSnHqcZGZlRlyX1I6BHd3HPwPELNj1Fc9MCkK/8ElNgVCwBPoRj91n9O6O07Se8YoxqyW4hDOv7jfglDDiIomCvsH/ZI1/WrQ6goM/zlRA9lDeymQ9fqSTeXC0fGzSIcZG4BH0fQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=suse.com; spf=pass smtp.mailfrom=suse.com; arc=none smtp.client-ip=195.135.223.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=suse.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=suse.com Received: from imap1.dmz-prg2.suse.org (imap1.dmz-prg2.suse.org [IPv6:2a07:de40:b281:104:10:150:64:97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by smtp-out2.suse.de (Postfix) with ESMTPS id 622D875ADB; Mon, 29 Jun 2026 06:56:50 +0000 (UTC) Authentication-Results: smtp-out2.suse.de; none Received: from imap1.dmz-prg2.suse.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by imap1.dmz-prg2.suse.org (Postfix) with ESMTPS id 1A699779A8; Mon, 29 Jun 2026 06:56:50 +0000 (UTC) Received: from dovecot-director2.suse.de ([2a07:de40:b281:106:10:150:64:167]) by imap1.dmz-prg2.suse.org with ESMTPSA id zy/6BDIXQmpuQgAAD6G6ig (envelope-from ); Mon, 29 Jun 2026 06:56:50 +0000 From: Juergen Gross To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: Juergen Gross , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , "Xin Li (Intel)" Subject: [PATCH v4 11/18] x86/msr: Use the alternatives mechanism for RDMSR Date: Mon, 29 Jun 2026 08:55:37 +0200 Message-ID: <20260629065544.3643253-12-jgross@suse.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260629065544.3643253-1-jgross@suse.com> References: <20260629065544.3643253-1-jgross@suse.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Rspamd-Pre-Result: action=no action; module=replies; Message is reply to one we originated X-Rspamd-Pre-Result: action=no action; module=replies; Message is reply to one we originated X-Spam-Flag: NO X-Spam-Score: -4.00 X-Spam-Level: X-Rspamd-Server: rspamd2.dmz-prg2.suse.org X-Spamd-Result: default: False [-4.00 / 50.00]; REPLY(-4.00)[] X-Rspamd-Queue-Id: 622D875ADB X-Rspamd-Action: no action Content-Type: text/plain; charset="utf-8" When available use the immediate variant of RDMSR in __rdmsr(). For the safe/unsafe variants make __rdmsr() to be a common base function instead of duplicating the ALTERNATIVE*() macros. Modify native_rdmsr() and native_read_msr() to use native_rdmsrq(). The paravirt case will be handled later. Originally-by: Xin Li (Intel) Signed-off-by: Juergen Gross --- V2: - new patch, partially taken from "[RFC PATCH v2 22/34] x86/msr: Utilize the alternatives mechanism to read MSR" by Xin Li --- arch/x86/include/asm/msr.h | 106 +++++++++++++++++++++++++++++-------- 1 file changed, 84 insertions(+), 22 deletions(-) diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h index 40bb03df162c..6a8af80305d1 100644 --- a/arch/x86/include/asm/msr.h +++ b/arch/x86/include/asm/msr.h @@ -66,6 +66,8 @@ static inline void do_trace_rdpmc(u32 msr, u64 val, int f= ailed) {} =20 /* The GNU Assembler (Gas) with Binutils 2.41 adds the .insn directive sup= port */ #if defined(CONFIG_AS_IS_GNU) && CONFIG_AS_VERSION >=3D 24100 +#define ASM_RDMSR_IMM \ + " .insn VEX.128.F2.M7.W0 0xf6 /0, %[msr]%{:u32}, %[val]\n\t" #define ASM_WRMSRNS_IMM \ " .insn VEX.128.F3.M7.W0 0xf6 /0, %[val], %[msr]%{:u32}\n\t" #else @@ -75,10 +77,17 @@ static inline void do_trace_rdpmc(u32 msr, u64 val, int= failed) {} * The register operand is encoded as %rax because all uses of the immedia= te * form MSR access instructions reference %rax as the register operand. */ +#define ASM_RDMSR_IMM \ + " .byte 0xc4,0xe7,0x7b,0xf6,0xc0; .long %c[msr]" #define ASM_WRMSRNS_IMM \ " .byte 0xc4,0xe7,0x7a,0xf6,0xc0; .long %c[msr]" #endif =20 +#define RDMSR_AND_SAVE_RESULT \ + "rdmsr\n\t" \ + "shl $0x20, %%rdx\n\t" \ + "or %%rdx, %%rax\n\t" + #define PREPARE_RDX_FOR_WRMSR \ "mov %%rax, %%rdx\n\t" \ "shr $0x20, %%rdx\n\t" @@ -94,16 +103,76 @@ static inline void do_trace_rdpmc(u32 msr, u64 val, in= t failed) {} * think of extending them - you will be slapped with a stinking trout or = a frozen * shark will reach you, wherever you are! You've been warned. */ -static __always_inline u64 __rdmsr(u32 msr) +static __always_inline bool __rdmsrq_variable(u32 msr, u64 *val, int type) + { +#ifdef CONFIG_X86_64 + BUILD_BUG_ON(__builtin_constant_p(msr)); + + asm_inline volatile goto( + "1:\n" + RDMSR_AND_SAVE_RESULT + _ASM_EXTABLE_TYPE(1b, %l[badmsr], %c[type]) /* For RDMSR */ + + : [val] "=3Da" (*val) + : "c" (msr), [type] "i" (type) + : "rdx" + : badmsr); +#else + asm_inline volatile goto( + "1: rdmsr\n\t" + _ASM_EXTABLE_TYPE(1b, %l[badmsr], %c[type]) /* For RDMSR */ + + : "=3DA" (*val) + : "c" (msr), [type] "i" (type) + : + : badmsr); +#endif + + return false; + +badmsr: + *val =3D 0; + + return true; +} + +#ifdef CONFIG_X86_64 +static __always_inline bool __rdmsrq_constant(u32 msr, u64 *val, int type) { - EAX_EDX_DECLARE_ARGS(val, low, high); + BUILD_BUG_ON(!__builtin_constant_p(msr)); =20 - asm volatile("1: rdmsr\n" - "2:\n" - _ASM_EXTABLE_TYPE(1b, 2b, EX_TYPE_RDMSR) - : EAX_EDX_RET(val, low, high) : "c" (msr)); + asm_inline volatile goto( + "1:\n" + ALTERNATIVE("mov %[msr], %%ecx\n\t" + "2:\n" + RDMSR_AND_SAVE_RESULT, + ASM_RDMSR_IMM, + X86_FEATURE_MSR_IMM) + _ASM_EXTABLE_TYPE(1b, %l[badmsr], %c[type]) /* For RDMSR immediate */ + _ASM_EXTABLE_TYPE(2b, %l[badmsr], %c[type]) /* For RDMSR */ + + : [val] "=3Da" (*val) + : [msr] "i" (msr), [type] "i" (type) + : "ecx", "rdx" + : badmsr); =20 - return EAX_EDX_VAL(val, low, high); + return false; + +badmsr: + *val =3D 0; + + return true; +} +#endif + +static __always_inline bool __rdmsr(u32 msr, u64 *val, int type) +{ +#ifdef CONFIG_X86_64 + if (__builtin_constant_p(msr)) + return __rdmsrq_constant(msr, val, type); +#endif + + return __rdmsrq_variable(msr, val, type); } =20 static __always_inline void __wrmsrq(u32 msr, u64 val) @@ -188,7 +257,11 @@ static __always_inline bool __wrmsrns(u32 msr, u64 val= , int type) =20 static __always_inline u64 native_rdmsrq(u32 msr) { - return __rdmsr(msr); + u64 val; + + __rdmsr(msr, &val, EX_TYPE_RDMSR); + + return val; } =20 static __always_inline void native_wrmsrq(u32 msr, u64 val) @@ -198,23 +271,12 @@ static __always_inline void native_wrmsrq(u32 msr, u6= 4 val) =20 static inline u64 native_read_msr(u32 msr) { - return __rdmsr(msr); + return native_rdmsrq(msr); } =20 -static inline int native_read_msr_safe(u32 msr, u64 *p) +static inline int native_read_msr_safe(u32 msr, u64 *val) { - int err; - EAX_EDX_DECLARE_ARGS(val, low, high); - - asm volatile("1: rdmsr ; xor %[err],%[err]\n" - "2:\n\t" - _ASM_EXTABLE_TYPE_REG(1b, 2b, EX_TYPE_RDMSR_SAFE, %[err]) - : [err] "=3Dr" (err), EAX_EDX_RET(val, low, high) - : "c" (msr)); - - *p =3D EAX_EDX_VAL(val, low, high); - - return err; + return __rdmsr(msr, val, EX_TYPE_RDMSR_SAFE) ? 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Peter Anvin" Subject: [PATCH v4 12/18] x86/alternatives: Add ALTERNATIVE_4() Date: Mon, 29 Jun 2026 08:55:38 +0200 Message-ID: <20260629065544.3643253-13-jgross@suse.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260629065544.3643253-1-jgross@suse.com> References: <20260629065544.3643253-1-jgross@suse.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Spam-Flag: NO X-Spamd-Result: default: False [-6.80 / 50.00]; REPLY(-4.00)[]; BAYES_HAM(-3.00)[99.99%]; MID_CONTAINS_FROM(1.00)[]; NEURAL_HAM_LONG(-1.00)[-1.000]; R_MISSING_CHARSET(0.50)[]; NEURAL_HAM_SHORT(-0.20)[-1.000]; MIME_GOOD(-0.10)[text/plain]; MIME_TRACE(0.00)[0:+]; FUZZY_RATELIMITED(0.00)[rspamd.com]; ARC_NA(0.00)[]; RCVD_VIA_SMTP_AUTH(0.00)[]; TO_DN_SOME(0.00)[]; RCPT_COUNT_SEVEN(0.00)[8]; DKIM_SIGNED(0.00)[suse.com:s=susede1]; FROM_EQ_ENVFROM(0.00)[]; FROM_HAS_DN(0.00)[]; R_RATELIMIT(0.00)[to_ip_from(RLfdszjqhz8kzzb9uwpzdm8png)]; DBL_BLOCKED_OPENRESOLVER(0.00)[imap1.dmz-prg2.suse.org:helo,suse.com:email,suse.com:mid]; RCVD_COUNT_TWO(0.00)[2]; TO_MATCH_ENVRCPT_ALL(0.00)[]; RCVD_TLS_ALL(0.00)[] X-Spam-Level: X-Spam-Score: -6.80 Content-Type: text/plain; charset="utf-8" For supporting WRMSR with CONFIG_PARAVIRT_XXL using direct instruction replacement, ALTERNATIVE_4() is needed. Signed-off-by: Juergen Gross --- V3: - new patch --- arch/x86/include/asm/alternative.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/x86/include/asm/alternative.h b/arch/x86/include/asm/alte= rnative.h index 03364510d5fe..119634eb3361 100644 --- a/arch/x86/include/asm/alternative.h +++ b/arch/x86/include/asm/alternative.h @@ -231,6 +231,12 @@ static inline int alternatives_text_reserved(void *sta= rt, void *end) ALTERNATIVE(ALTERNATIVE_2(oldinstr, newinstr1, ft_flags1, newinstr2, ft_f= lags2), \ newinstr3, ft_flags3) =20 +#define ALTERNATIVE_4(oldinstr, newinstr1, ft_flags1, newinstr2, ft_flags2= , \ + newinstr3, ft_flags3, newinstr4, ft_flags4) \ + ALTERNATIVE(ALTERNATIVE_3(oldinstr, newinstr1, ft_flags1, \ + newinstr2, ft_flags2, newinstr3, ft_flags3),\ + newinstr4, ft_flags4) + /* * Alternative instructions for different CPU types or capabilities. * --=20 2.54.0 From nobody Tue Jun 30 05:35:18 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail(p=quarantine dis=quarantine) header.from=suse.com Return-Path: Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) by mx.zohomail.com with SMTPS id 17827162454741010.7958049244673; Sun, 28 Jun 2026 23:57:25 -0700 (PDT) Received: from list by lists.xenproject.org with outflank-mailman.1347188.1605059 (Exim 4.92) (envelope-from ) id 1we5vX-0005s2-Rv; Mon, 29 Jun 2026 06:57:07 +0000 Received: by outflank-mailman (output) from mailman id 1347188.1605059; Mon, 29 Jun 2026 06:57:07 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1we5vX-0005rv-Oq; Mon, 29 Jun 2026 06:57:07 +0000 Received: by outflank-mailman (input) for mailman id 1347188; Mon, 29 Jun 2026 06:57:06 +0000 Received: from mx.expurgate.net ([194.145.224.20]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1we5vW-0005qY-2X for xen-devel@lists.xenproject.org; Mon, 29 Jun 2026 06:57:06 +0000 Received: from mx.expurgate.net (helo=localhost) by mx.expurgate.net with esmtp id 1we5vV-00BYi9-Fb for xen-devel@lists.xenproject.org; Mon, 29 Jun 2026 08:57:05 +0200 Received: from [10.42.69.11] (helo=localhost) by localhost with ESMTP (eXpurgate MTA 0.9.1) (envelope-from ) id 6a421737-5cb7-0a2a0a5109dd-0a2a450bd058-32 for ; Mon, 29 Jun 2026 08:57:05 +0200 Received: from [195.135.223.130] (helo=smtp-out1.suse.de) by tlsNG-42698a.mxtls.expurgate.net with ESMTPS (eXpurgate 4.57.1) (envelope-from ) id 6a42173d-ac48-0a2a450b0019-c387df82ae6c-3 for ; Mon, 29 Jun 2026 08:57:02 +0200 Received: from imap1.dmz-prg2.suse.org (imap1.dmz-prg2.suse.org [IPv6:2a07:de40:b281:104:10:150:64:97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by smtp-out1.suse.de (Postfix) with ESMTPS id E042271266; Mon, 29 Jun 2026 06:57:01 +0000 (UTC) Received: from imap1.dmz-prg2.suse.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by imap1.dmz-prg2.suse.org (Postfix) with ESMTPS id 6F47E779A8; Mon, 29 Jun 2026 06:57:01 +0000 (UTC) Received: from dovecot-director2.suse.de ([2a07:de40:b281:106:10:150:64:167]) by imap1.dmz-prg2.suse.org with ESMTPSA id ktawGT0XQmp3QgAAD6G6ig (envelope-from ); Mon, 29 Jun 2026 06:57:01 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" Authentication-Results: eu.smtp.expurgate.cloud; none Authentication-Results: smtp-out1.suse.de; none From: Juergen Gross To: linux-kernel@vger.kernel.org, x86@kernel.org, virtualization@lists.linux.dev Cc: Juergen Gross , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Ajay Kaher , Alexey Makhalov , Broadcom internal kernel review list , Boris Ostrovsky , Josh Poimboeuf , Peter Zijlstra , xen-devel@lists.xenproject.org Subject: [PATCH v4 13/18] x86/paravirt: Split off MSR related hooks into new header Date: Mon, 29 Jun 2026 08:55:39 +0200 Message-ID: <20260629065544.3643253-14-jgross@suse.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260629065544.3643253-1-jgross@suse.com> References: <20260629065544.3643253-1-jgross@suse.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Rspamd-Pre-Result: action=no action; module=replies; Message is reply to one we originated X-Rspamd-Queue-Id: E042271266 X-Spam-Flag: NO X-Spam-Score: -4.00 X-Spam-Level: X-Rspamd-Action: no action X-Rspamd-Server: rspamd1.dmz-prg2.suse.org X-Rspamd-Pre-Result: action=no action; module=replies; Message is reply to one we originated X-Spamd-Result: default: False [-4.00 / 50.00]; REPLY(-4.00)[] X-purgate-ID: tlsNG-42698a/1782716222-4054C220-1AC45F42/0/0 X-purgate-type: clean X-purgate-size: 8115 X-ZM-MESSAGEID: 1782716247307158500 Content-Type: text/plain; charset="utf-8" Move the WRMSR, RDMSR and RDPMC related parts of paravirt.h and paravirt_types.h into a new header file paravirt-msr.h. Switch all moved helper functions to __always_inline. Signed-off-by: Juergen Gross --- V3: - new patch V4: - always use __always_inline --- arch/x86/include/asm/msr.h | 2 +- arch/x86/include/asm/paravirt-msr.h | 56 +++++++++++++++++++++++++++ arch/x86/include/asm/paravirt.h | 55 -------------------------- arch/x86/include/asm/paravirt_types.h | 13 ------- arch/x86/kernel/paravirt.c | 14 ++++--- arch/x86/xen/enlighten_pv.c | 11 +++--- tools/objtool/check.c | 1 + 7 files changed, 73 insertions(+), 79 deletions(-) create mode 100644 arch/x86/include/asm/paravirt-msr.h diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h index 6a8af80305d1..b13b4a93673e 100644 --- a/arch/x86/include/asm/msr.h +++ b/arch/x86/include/asm/msr.h @@ -323,7 +323,7 @@ static inline u64 native_read_pmc(int counter) } =20 #ifdef CONFIG_PARAVIRT_XXL -#include +#include #else static __always_inline u64 read_msr(u32 msr) { diff --git a/arch/x86/include/asm/paravirt-msr.h b/arch/x86/include/asm/par= avirt-msr.h new file mode 100644 index 000000000000..3e31648316a8 --- /dev/null +++ b/arch/x86/include/asm/paravirt-msr.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef _ASM_X86_PARAVIRT_MSR_H +#define _ASM_X86_PARAVIRT_MSR_H + +#include + +struct pv_msr_ops { + /* Unsafe MSR operations. These will warn or panic on failure. */ + u64 (*read_msr)(u32 msr); + void (*write_msr)(u32 msr, u64 val); + + /* Safe MSR operations. Returns 0 or -EIO. */ + int (*read_msr_safe)(u32 msr, u64 *val); + int (*write_msr_safe)(u32 msr, u64 val); + + u64 (*read_pmc)(int counter); +} __no_randomize_layout; + +extern struct pv_msr_ops pv_ops_msr; + +static __always_inline u64 read_msr(u32 msr) +{ + return PVOP_CALL1(u64, pv_ops_msr, read_msr, msr); +} + +static __always_inline void write_msr(u32 msr, u64 val) +{ + PVOP_VCALL2(pv_ops_msr, write_msr, msr, val); +} + +static __always_inline void write_msrns(u32 msr, u64 val) +{ + PVOP_VCALL2(pv_ops_msr, write_msr, msr, val); +} + +static __always_inline int read_msr_safe(u32 msr, u64 *val) +{ + return PVOP_CALL2(int, pv_ops_msr, read_msr_safe, msr, val); +} + +static __always_inline int write_msr_safe(u32 msr, u64 val) +{ + return PVOP_CALL2(int, pv_ops_msr, write_msr_safe, msr, val); +} + +static __always_inline int write_msrns_safe(u32 msr, u64 val) +{ + return PVOP_CALL2(int, pv_ops_msr, write_msr_safe, msr, val); +} + +static __always_inline u64 rdpmc(int counter) +{ + return PVOP_CALL1(u64, pv_ops_msr, read_pmc, counter); +} + +#endif /* _ASM_X86_PARAVIRT_MSR_H */ diff --git a/arch/x86/include/asm/paravirt.h b/arch/x86/include/asm/paravir= t.h index b0c740316cf7..eb16d55f94d3 100644 --- a/arch/x86/include/asm/paravirt.h +++ b/arch/x86/include/asm/paravirt.h @@ -130,61 +130,6 @@ static inline void __write_cr4(unsigned long x) PVOP_VCALL1(pv_ops, cpu.write_cr4, x); } =20 -static inline u64 paravirt_read_msr(u32 msr) -{ - return PVOP_CALL1(u64, pv_ops, cpu.read_msr, msr); -} - -static inline void paravirt_write_msr(u32 msr, u64 val) -{ - PVOP_VCALL2(pv_ops, cpu.write_msr, msr, val); -} - -static inline int paravirt_read_msr_safe(u32 msr, u64 *val) -{ - return PVOP_CALL2(int, pv_ops, cpu.read_msr_safe, msr, val); -} - -static inline int paravirt_write_msr_safe(u32 msr, u64 val) -{ - return PVOP_CALL2(int, pv_ops, cpu.write_msr_safe, msr, val); -} - -static __always_inline u64 read_msr(u32 msr) -{ - return paravirt_read_msr(msr); -} - -static inline void write_msr(u32 msr, u64 val) -{ - paravirt_write_msr(msr, val); -} - -static __always_inline void write_msrns(u32 msr, u64 val) -{ - paravirt_write_msr(msr, val); -} - -static inline int write_msr_safe(u32 msr, u64 val) -{ - return paravirt_write_msr_safe(msr, val); -} - -static __always_inline int write_msrns_safe(u32 msr, u64 val) -{ - return paravirt_write_msr_safe(msr, val); -} - -static __always_inline int read_msr_safe(u32 msr, u64 *p) -{ - return paravirt_read_msr_safe(msr, p); -} - -static __always_inline u64 rdpmc(int counter) -{ - return PVOP_CALL1(u64, pv_ops, cpu.read_pmc, counter); -} - static inline void paravirt_alloc_ldt(struct desc_struct *ldt, unsigned en= tries) { PVOP_VCALL2(pv_ops, cpu.alloc_ldt, ldt, entries); diff --git a/arch/x86/include/asm/paravirt_types.h b/arch/x86/include/asm/p= aravirt_types.h index b4c4a23e77a1..2459163fa196 100644 --- a/arch/x86/include/asm/paravirt_types.h +++ b/arch/x86/include/asm/paravirt_types.h @@ -58,19 +58,6 @@ struct pv_cpu_ops { void (*cpuid)(unsigned int *eax, unsigned int *ebx, unsigned int *ecx, unsigned int *edx); =20 - /* Unsafe MSR operations. These will warn or panic on failure. */ - u64 (*read_msr)(u32 msr); - void (*write_msr)(u32 msr, u64 val); - - /* - * Safe MSR operations. - * Returns 0 or -EIO. - */ - int (*read_msr_safe)(u32 msr, u64 *val); - int (*write_msr_safe)(u32 msr, u64 val); - - u64 (*read_pmc)(int counter); - void (*start_context_switch)(struct task_struct *prev); void (*end_context_switch)(struct task_struct *next); #endif diff --git a/arch/x86/kernel/paravirt.c b/arch/x86/kernel/paravirt.c index 00b59d774389..739dbfd8aadf 100644 --- a/arch/x86/kernel/paravirt.c +++ b/arch/x86/kernel/paravirt.c @@ -110,11 +110,6 @@ struct paravirt_patch_template pv_ops =3D { .cpu.read_cr0 =3D native_read_cr0, .cpu.write_cr0 =3D native_write_cr0, .cpu.write_cr4 =3D native_write_cr4, - .cpu.read_msr =3D native_read_msr, - .cpu.write_msr =3D native_write_msr, - .cpu.read_msr_safe =3D native_read_msr_safe, - .cpu.write_msr_safe =3D native_write_msr_safe, - .cpu.read_pmc =3D native_read_pmc, .cpu.load_tr_desc =3D native_load_tr_desc, .cpu.set_ldt =3D native_set_ldt, .cpu.load_gdt =3D native_load_gdt, @@ -212,6 +207,15 @@ struct paravirt_patch_template pv_ops =3D { }; =20 #ifdef CONFIG_PARAVIRT_XXL +struct pv_msr_ops pv_ops_msr =3D { + .read_msr =3D native_read_msr, + .write_msr =3D native_write_msr, + .read_msr_safe =3D native_read_msr_safe, + .write_msr_safe =3D native_write_msr_safe, + .read_pmc =3D native_read_pmc, +}; +EXPORT_SYMBOL(pv_ops_msr); + NOKPROBE_SYMBOL(native_load_idt); #endif =20 diff --git a/arch/x86/xen/enlighten_pv.c b/arch/x86/xen/enlighten_pv.c index 2c64b388f616..bf81e84ff261 100644 --- a/arch/x86/xen/enlighten_pv.c +++ b/arch/x86/xen/enlighten_pv.c @@ -1360,11 +1360,6 @@ asmlinkage __visible void __init xen_start_kernel(st= ruct start_info *si) pv_ops.cpu.read_cr0 =3D xen_read_cr0; pv_ops.cpu.write_cr0 =3D xen_write_cr0; pv_ops.cpu.write_cr4 =3D xen_write_cr4; - pv_ops.cpu.read_msr =3D xen_read_msr; - pv_ops.cpu.write_msr =3D xen_write_msr; - pv_ops.cpu.read_msr_safe =3D xen_read_msr_safe; - pv_ops.cpu.write_msr_safe =3D xen_write_msr_safe; - pv_ops.cpu.read_pmc =3D xen_read_pmc; pv_ops.cpu.load_tr_desc =3D paravirt_nop; pv_ops.cpu.set_ldt =3D xen_set_ldt; pv_ops.cpu.load_gdt =3D xen_load_gdt; @@ -1385,6 +1380,12 @@ asmlinkage __visible void __init xen_start_kernel(st= ruct start_info *si) pv_ops.cpu.start_context_switch =3D xen_start_context_switch; pv_ops.cpu.end_context_switch =3D xen_end_context_switch; =20 + pv_ops_msr.read_msr =3D xen_read_msr; + pv_ops_msr.write_msr =3D xen_write_msr; + pv_ops_msr.read_msr_safe =3D xen_read_msr_safe; + pv_ops_msr.write_msr_safe =3D xen_write_msr_safe; + pv_ops_msr.read_pmc =3D xen_read_pmc; + xen_init_irq_ops(); =20 /* diff --git a/tools/objtool/check.c b/tools/objtool/check.c index 10b18cf9c360..2c91fcff77f4 100644 --- a/tools/objtool/check.c +++ b/tools/objtool/check.c @@ -525,6 +525,7 @@ static struct { } pv_ops_tables[] =3D { { .name =3D "pv_ops", }, { .name =3D "pv_ops_lock", }, + { .name =3D "pv_ops_msr", }, { .name =3D NULL, .idx_off =3D -1 } }; =20 --=20 2.54.0 From nobody Tue Jun 30 05:35:19 2026 Received: from smtp-out2.suse.de (smtp-out2.suse.de [195.135.223.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 169243BB69E for ; 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Peter Anvin" Subject: [PATCH v4 14/18] x86/paravirt: Prepare support of MSR instruction interfaces Date: Mon, 29 Jun 2026 08:55:40 +0200 Message-ID: <20260629065544.3643253-15-jgross@suse.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260629065544.3643253-1-jgross@suse.com> References: <20260629065544.3643253-1-jgross@suse.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Spam-Flag: NO X-Spam-Score: -6.80 X-Spamd-Result: default: False [-6.80 / 50.00]; REPLY(-4.00)[]; BAYES_HAM(-3.00)[100.00%]; MID_CONTAINS_FROM(1.00)[]; NEURAL_HAM_LONG(-1.00)[-1.000]; R_MISSING_CHARSET(0.50)[]; NEURAL_HAM_SHORT(-0.20)[-1.000]; MIME_GOOD(-0.10)[text/plain]; FUZZY_RATELIMITED(0.00)[rspamd.com]; ARC_NA(0.00)[]; MIME_TRACE(0.00)[0:+]; RCPT_COUNT_TWELVE(0.00)[12]; DKIM_SIGNED(0.00)[suse.com:s=susede1]; TO_MATCH_ENVRCPT_ALL(0.00)[]; FROM_HAS_DN(0.00)[]; FROM_EQ_ENVFROM(0.00)[]; RCVD_VIA_SMTP_AUTH(0.00)[]; RCVD_COUNT_TWO(0.00)[2]; R_RATELIMIT(0.00)[to_ip_from(RLfdszjqhz8kzzb9uwpzdm8png)]; TO_DN_SOME(0.00)[]; RCVD_TLS_ALL(0.00)[]; DBL_BLOCKED_OPENRESOLVER(0.00)[suse.com:email,suse.com:mid,imap1.dmz-prg2.suse.org:helo] X-Spam-Level: Content-Type: text/plain; charset="utf-8" Make the paravirt callee-save infrastructure more generic by allowing arbitrary register interfaces via prologue and epilogue helper macros. Signed-off-by: Juergen Gross --- V3: - carved out from patch 5 of V1 --- arch/x86/include/asm/paravirt_types.h | 43 ++++++++++++++--------- arch/x86/include/asm/qspinlock_paravirt.h | 4 +-- 2 files changed, 29 insertions(+), 18 deletions(-) diff --git a/arch/x86/include/asm/paravirt_types.h b/arch/x86/include/asm/p= aravirt_types.h index 2459163fa196..740ea819bbab 100644 --- a/arch/x86/include/asm/paravirt_types.h +++ b/arch/x86/include/asm/paravirt_types.h @@ -448,27 +448,38 @@ extern struct paravirt_patch_template pv_ops; #define PV_SAVE_ALL_CALLER_REGS "pushl %ecx;" #define PV_RESTORE_ALL_CALLER_REGS "popl %ecx;" #else +/* Save and restore caller-save registers, except %rax, %rcx and %rdx. */ +#define PV_SAVE_COMMON_CALLER_REGS \ + "push %rsi;" \ + "push %rdi;" \ + "push %r8;" \ + "push %r9;" \ + "push %r10;" \ + "push %r11;" + +#define PV_RESTORE_COMMON_CALLER_REGS \ + "pop %r11;" \ + "pop %r10;" \ + "pop %r9;" \ + "pop %r8;" \ + "pop %rdi;" \ + "pop %rsi;" + /* save and restore all caller-save registers, except return value */ #define PV_SAVE_ALL_CALLER_REGS \ "push %rcx;" \ "push %rdx;" \ - "push %rsi;" \ - "push %rdi;" \ - "push %r8;" \ - "push %r9;" \ - "push %r10;" \ - "push %r11;" + PV_SAVE_COMMON_CALLER_REGS + #define PV_RESTORE_ALL_CALLER_REGS \ - "pop %r11;" \ - "pop %r10;" \ - "pop %r9;" \ - "pop %r8;" \ - "pop %rdi;" \ - "pop %rsi;" \ + PV_RESTORE_COMMON_CALLER_REGS \ "pop %rdx;" \ "pop %rcx;" #endif =20 +#define PV_PROLOGUE_ALL(func) PV_SAVE_ALL_CALLER_REGS +#define PV_EPILOGUE_ALL(func) PV_RESTORE_ALL_CALLER_REGS + /* * Generate a thunk around a function which saves all caller-save * registers except for the return value. This allows C functions to @@ -482,7 +493,7 @@ extern struct paravirt_patch_template pv_ops; * functions. */ #define PV_THUNK_NAME(func) "__raw_callee_save_" #func -#define __PV_CALLEE_SAVE_REGS_THUNK(func, section) \ +#define __PV_CALLEE_SAVE_REGS_THUNK(func, section, helper) \ extern typeof(func) __raw_callee_save_##func; \ \ asm(".pushsection " section ", \"ax\";" \ @@ -492,16 +503,16 @@ extern struct paravirt_patch_template pv_ops; PV_THUNK_NAME(func) ":" \ ASM_ENDBR \ FRAME_BEGIN \ - PV_SAVE_ALL_CALLER_REGS \ + PV_PROLOGUE_##helper(func) \ "call " #func ";" \ - PV_RESTORE_ALL_CALLER_REGS \ + PV_EPILOGUE_##helper(func) \ FRAME_END \ ASM_RET \ ".size " PV_THUNK_NAME(func) ", .-" PV_THUNK_NAME(func) ";" \ ".popsection") =20 #define PV_CALLEE_SAVE_REGS_THUNK(func) \ - __PV_CALLEE_SAVE_REGS_THUNK(func, ".text") + __PV_CALLEE_SAVE_REGS_THUNK(func, ".text", ALL) =20 /* Get a reference to a callee-save function */ #define PV_CALLEE_SAVE(func) \ diff --git a/arch/x86/include/asm/qspinlock_paravirt.h b/arch/x86/include/a= sm/qspinlock_paravirt.h index 0a985784be9b..002b17f0735e 100644 --- a/arch/x86/include/asm/qspinlock_paravirt.h +++ b/arch/x86/include/asm/qspinlock_paravirt.h @@ -14,7 +14,7 @@ void __lockfunc __pv_queued_spin_unlock_slowpath(struct q= spinlock *lock, u8 lock */ #ifdef CONFIG_64BIT =20 -__PV_CALLEE_SAVE_REGS_THUNK(__pv_queued_spin_unlock_slowpath, ".spinlock.t= ext"); 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Peter Anvin" , Boris Ostrovsky , xen-devel@lists.xenproject.org Subject: [PATCH v4 15/18] x86/paravirt: Switch MSR access pv_ops functions to instruction interfaces Date: Mon, 29 Jun 2026 08:55:41 +0200 Message-ID: <20260629065544.3643253-16-jgross@suse.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260629065544.3643253-1-jgross@suse.com> References: <20260629065544.3643253-1-jgross@suse.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Spam-Flag: NO X-Spamd-Result: default: False [-6.80 / 50.00]; REPLY(-4.00)[]; BAYES_HAM(-3.00)[100.00%]; MID_CONTAINS_FROM(1.00)[]; NEURAL_HAM_LONG(-1.00)[-1.000]; R_MISSING_CHARSET(0.50)[]; NEURAL_HAM_SHORT(-0.20)[-1.000]; MIME_GOOD(-0.10)[text/plain]; FUZZY_RATELIMITED(0.00)[rspamd.com]; ARC_NA(0.00)[]; MIME_TRACE(0.00)[0:+]; RCPT_COUNT_TWELVE(0.00)[14]; DKIM_SIGNED(0.00)[suse.com:s=susede1]; TO_MATCH_ENVRCPT_ALL(0.00)[]; FROM_HAS_DN(0.00)[]; FROM_EQ_ENVFROM(0.00)[]; RCVD_VIA_SMTP_AUTH(0.00)[]; RCVD_COUNT_TWO(0.00)[2]; R_RATELIMIT(0.00)[to_ip_from(RLfdszjqhz8kzzb9uwpzdm8png)]; TO_DN_SOME(0.00)[]; RCVD_TLS_ALL(0.00)[]; DBL_BLOCKED_OPENRESOLVER(0.00)[suse.com:email,suse.com:mid,imap1.dmz-prg2.suse.org:helo] X-Spam-Level: X-Spam-Score: -6.80 X-purgate-ID: tlsNG-33051d/1782716233-B7D235D1-C20D4451/0/0 X-purgate-type: clean X-purgate-size: 8932 X-ZohoMail-DKIM: pass (identity @suse.com) X-ZM-MESSAGEID: 1782716251242158500 Content-Type: text/plain; charset="utf-8" In order to prepare for inlining RDMSR/WRMSR instructions via alternatives directly when running not in a Xen PV guest, switch the interfaces of the MSR related pvops callbacks to ones similar of the related instructions. In order to prepare for supporting the immediate variants of RDMSR/WRMSR use a 64-bit interface instead of the 32-bit one of RDMSR/WRMSR. Signed-off-by: Juergen Gross --- V3: - former patch 5 of V1 has been split - use 64-bit interface (Xin Li) --- arch/x86/include/asm/paravirt-msr.h | 64 ++++++++++++++++++++++++----- arch/x86/kernel/paravirt.c | 36 ++++++++++++++-- arch/x86/xen/enlighten_pv.c | 45 +++++++++++++++----- 3 files changed, 120 insertions(+), 25 deletions(-) diff --git a/arch/x86/include/asm/paravirt-msr.h b/arch/x86/include/asm/par= avirt-msr.h index 3e31648316a8..4b71a1cd780c 100644 --- a/arch/x86/include/asm/paravirt-msr.h +++ b/arch/x86/include/asm/paravirt-msr.h @@ -6,46 +6,90 @@ =20 struct pv_msr_ops { /* Unsafe MSR operations. These will warn or panic on failure. */ - u64 (*read_msr)(u32 msr); - void (*write_msr)(u32 msr, u64 val); + struct paravirt_callee_save read_msr; + struct paravirt_callee_save write_msr; =20 /* Safe MSR operations. Returns 0 or -EIO. */ - int (*read_msr_safe)(u32 msr, u64 *val); - int (*write_msr_safe)(u32 msr, u64 val); + struct paravirt_callee_save read_msr_safe; + struct paravirt_callee_save write_msr_safe; =20 u64 (*read_pmc)(int counter); } __no_randomize_layout; =20 extern struct pv_msr_ops pv_ops_msr; =20 +#define PV_PROLOGUE_MSR(func) \ + PV_SAVE_COMMON_CALLER_REGS \ + PV_PROLOGUE_MSR_##func + +#define PV_EPILOGUE_MSR(func) PV_RESTORE_COMMON_CALLER_REGS + +#define PV_CALLEE_SAVE_REGS_MSR_THUNK(func) \ + __PV_CALLEE_SAVE_REGS_THUNK(func, ".text", MSR) + static __always_inline u64 read_msr(u32 msr) { - return PVOP_CALL1(u64, pv_ops_msr, read_msr, msr); + u64 val; + + asm volatile(PARAVIRT_CALL + : "=3Da" (val), ASM_CALL_CONSTRAINT + : paravirt_ptr(pv_ops_msr, read_msr), "c" (msr) + : "rdx"); + + return val; } =20 static __always_inline void write_msr(u32 msr, u64 val) { - PVOP_VCALL2(pv_ops_msr, write_msr, msr, val); + asm volatile(PARAVIRT_CALL + : ASM_CALL_CONSTRAINT + : paravirt_ptr(pv_ops_msr, write_msr), "c" (msr), "a" (val) + : "memory", "rdx"); } =20 static __always_inline void write_msrns(u32 msr, u64 val) { - PVOP_VCALL2(pv_ops_msr, write_msr, msr, val); + asm volatile(PARAVIRT_CALL + : ASM_CALL_CONSTRAINT + : paravirt_ptr(pv_ops_msr, write_msr), "c" (msr), "a" (val) + : "memory", "rdx"); } =20 static __always_inline int read_msr_safe(u32 msr, u64 *val) { - return PVOP_CALL2(int, pv_ops_msr, read_msr_safe, msr, val); + int err; + + asm volatile(PARAVIRT_CALL + : [err] "=3Dd" (err), "=3Da" (*val), ASM_CALL_CONSTRAINT + : paravirt_ptr(pv_ops_msr, read_msr_safe), "c" (msr)); + + return err ? -EIO : 0; } =20 static __always_inline int write_msr_safe(u32 msr, u64 val) { - return PVOP_CALL2(int, pv_ops_msr, write_msr_safe, msr, val); + int err; + + asm volatile(PARAVIRT_CALL + : [err] "=3Da" (err), ASM_CALL_CONSTRAINT + : paravirt_ptr(pv_ops_msr, write_msr_safe), + "c" (msr), "a" (val) + : "memory", "rdx"); + + return err ? -EIO : 0; } =20 static __always_inline int write_msrns_safe(u32 msr, u64 val) { - return PVOP_CALL2(int, pv_ops_msr, write_msr_safe, msr, val); + int err; + + asm volatile(PARAVIRT_CALL + : [err] "=3Da" (err), ASM_CALL_CONSTRAINT + : paravirt_ptr(pv_ops_msr, write_msr_safe), + "c" (msr), "a" (val) + : "memory", "rdx"); + + return err ? -EIO : 0; } =20 static __always_inline u64 rdpmc(int counter) diff --git a/arch/x86/kernel/paravirt.c b/arch/x86/kernel/paravirt.c index 739dbfd8aadf..66c0d6b5423c 100644 --- a/arch/x86/kernel/paravirt.c +++ b/arch/x86/kernel/paravirt.c @@ -50,12 +50,40 @@ unsigned long pv_native_save_fl(void); void pv_native_irq_disable(void); void pv_native_irq_enable(void); unsigned long pv_native_read_cr2(void); +void pv_native_rdmsr(void); +void pv_native_wrmsr(void); +void pv_native_rdmsr_safe(void); +void pv_native_wrmsr_safe(void); =20 DEFINE_ASM_FUNC(_paravirt_ident_64, "mov %rdi, %rax", .text); DEFINE_ASM_FUNC(pv_native_save_fl, "pushf; pop %rax", .noinstr.text); DEFINE_ASM_FUNC(pv_native_irq_disable, "cli", .noinstr.text); DEFINE_ASM_FUNC(pv_native_irq_enable, "sti", .noinstr.text); DEFINE_ASM_FUNC(pv_native_read_cr2, "mov %cr2, %rax", .noinstr.text); +DEFINE_ASM_FUNC(pv_native_rdmsr, + "1: rdmsr\n" + "shl $32, %rdx; or %rdx, %rax\n" + "2:\n" + _ASM_EXTABLE_TYPE(1b, 2b, EX_TYPE_RDMSR), .noinstr.text); +DEFINE_ASM_FUNC(pv_native_wrmsr, + "mov %rax, %rdx; shr $32, %rdx\n" + "1: wrmsr\n" + "2:\n" + _ASM_EXTABLE_TYPE(1b, 2b, EX_TYPE_WRMSR), .noinstr.text); +DEFINE_ASM_FUNC(pv_native_rdmsr_safe, + "1: rdmsr\n" + "shl $32, %rdx; or %rdx, %rax\n" + "xor %edx, %edx\n" + "2:\n" + _ASM_EXTABLE_TYPE_REG(1b, 2b, EX_TYPE_RDMSR_SAFE, %%edx), + .noinstr.text); +DEFINE_ASM_FUNC(pv_native_wrmsr_safe, + "mov %rax, %rdx; shr $32, %rdx\n" + "1: wrmsr\n" + "xor %eax, %eax\n" + "2:\n" + _ASM_EXTABLE_TYPE_REG(1b, 2b, EX_TYPE_WRMSR_SAFE, %%eax), + .noinstr.text); #endif =20 static noinstr void pv_native_safe_halt(void) @@ -208,10 +236,10 @@ struct paravirt_patch_template pv_ops =3D { =20 #ifdef CONFIG_PARAVIRT_XXL struct pv_msr_ops pv_ops_msr =3D { - .read_msr =3D native_read_msr, - .write_msr =3D native_write_msr, - .read_msr_safe =3D native_read_msr_safe, - .write_msr_safe =3D native_write_msr_safe, + .read_msr =3D __PV_IS_CALLEE_SAVE(pv_native_rdmsr), + .write_msr =3D __PV_IS_CALLEE_SAVE(pv_native_wrmsr), + .read_msr_safe =3D __PV_IS_CALLEE_SAVE(pv_native_rdmsr_safe), + .write_msr_safe =3D __PV_IS_CALLEE_SAVE(pv_native_wrmsr_safe), .read_pmc =3D native_read_pmc, }; EXPORT_SYMBOL(pv_ops_msr); diff --git a/arch/x86/xen/enlighten_pv.c b/arch/x86/xen/enlighten_pv.c index bf81e84ff261..505a85c3869e 100644 --- a/arch/x86/xen/enlighten_pv.c +++ b/arch/x86/xen/enlighten_pv.c @@ -1148,15 +1148,32 @@ static void xen_do_write_msr(u32 msr, u64 val, int = *err) } } =20 -static int xen_read_msr_safe(u32 msr, u64 *val) +/* + * Prototypes for functions called via PV_CALLEE_SAVE_REGS_THUNK() in order + * to avoid warnings with "-Wmissing-prototypes". + */ +struct xen_rdmsr_safe_ret { + u64 val; + int err; +}; +struct xen_rdmsr_safe_ret xen_read_msr_safe(u32 msr); +int xen_write_msr_safe(u32 msr, u64 val); +u64 xen_read_msr(u32 msr); +void xen_write_msr(u32 msr, u64 val); +#define PV_PROLOGUE_RDMSR "mov %ecx, %edi;" +#define PV_PROLOGUE_WRMSR "mov %ecx, %edi; mov %rax, %rsi;" + +__visible struct xen_rdmsr_safe_ret xen_read_msr_safe(u32 msr) { - int err =3D 0; + struct xen_rdmsr_safe_ret ret =3D { 0, 0 }; =20 - *val =3D xen_do_read_msr(msr, &err); - return err; + ret.val =3D xen_do_read_msr(msr, &ret.err); + return ret; } +#define PV_PROLOGUE_MSR_xen_read_msr_safe PV_PROLOGUE_RDMSR +PV_CALLEE_SAVE_REGS_MSR_THUNK(xen_read_msr_safe); =20 -static int xen_write_msr_safe(u32 msr, u64 val) +__visible int xen_write_msr_safe(u32 msr, u64 val) { int err =3D 0; =20 @@ -1164,20 +1181,26 @@ static int xen_write_msr_safe(u32 msr, u64 val) =20 return err; } +#define PV_PROLOGUE_MSR_xen_write_msr_safe PV_PROLOGUE_WRMSR +PV_CALLEE_SAVE_REGS_MSR_THUNK(xen_write_msr_safe); =20 -static u64 xen_read_msr(u32 msr) +__visible u64 xen_read_msr(u32 msr) { int err =3D 0; =20 return xen_do_read_msr(msr, xen_msr_safe ? &err : NULL); } +#define PV_PROLOGUE_MSR_xen_read_msr PV_PROLOGUE_RDMSR +PV_CALLEE_SAVE_REGS_MSR_THUNK(xen_read_msr); =20 -static void xen_write_msr(u32 msr, u64 val) +__visible void xen_write_msr(u32 msr, u64 val) { int err; =20 xen_do_write_msr(msr, val, xen_msr_safe ? &err : NULL); } +#define PV_PROLOGUE_MSR_xen_write_msr PV_PROLOGUE_WRMSR +PV_CALLEE_SAVE_REGS_MSR_THUNK(xen_write_msr); =20 /* This is called once we have the cpu_possible_mask */ void __init xen_setup_vcpu_info_placement(void) @@ -1380,10 +1403,10 @@ asmlinkage __visible void __init xen_start_kernel(s= truct start_info *si) pv_ops.cpu.start_context_switch =3D xen_start_context_switch; pv_ops.cpu.end_context_switch =3D xen_end_context_switch; =20 - pv_ops_msr.read_msr =3D xen_read_msr; - pv_ops_msr.write_msr =3D xen_write_msr; - pv_ops_msr.read_msr_safe =3D xen_read_msr_safe; - pv_ops_msr.write_msr_safe =3D xen_write_msr_safe; + pv_ops_msr.read_msr =3D PV_CALLEE_SAVE(xen_read_msr); + pv_ops_msr.write_msr =3D PV_CALLEE_SAVE(xen_write_msr); + pv_ops_msr.read_msr_safe =3D PV_CALLEE_SAVE(xen_read_msr_safe); + pv_ops_msr.write_msr_safe =3D PV_CALLEE_SAVE(xen_write_msr_safe); pv_ops_msr.read_pmc =3D xen_read_pmc; =20 xen_init_irq_ops(); --=20 2.54.0 From nobody Tue Jun 30 05:35:19 2026 Received: from smtp-out2.suse.de (smtp-out2.suse.de [195.135.223.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C6CC93C2B82 for ; Mon, 29 Jun 2026 06:57:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=195.135.223.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782716242; cv=none; b=EncnK8UJfsuchjUg6O/uf3+zmeZpt4KoP59rb/Kq57BW357fkm+0YR3eKD7RH5PVY9vPTVIzIUZ8mjWBn+h+S7jJDAnGd+xfmB8p0PwS3Gmrs9kzHu+yYOVrDR60aC/fBx5u++X2SySZiEIrHpdhQgOPXHNN9NNTAOFYh865oMM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782716242; c=relaxed/simple; bh=/SkIgLbuypieCDjz+RCrJV/IMl1sV0FddN4+mIBvQT8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=OSFWqcJ97NRw5QY7ekk5JOEMjOtjPCxH5GDvMVsKBtPv5y3Gdta3WiDAiaFRQcUIcUSdNdByGDQ815h4z+1lxtNKyWG0eHwZ3OHwc9LqKDr/ORXustC13TfXUzVFM0G9FzmX76g5Ljns+IB0Bi7Ojuu2x5Kri6kZHWxO6+CIMA8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=suse.com; spf=pass smtp.mailfrom=suse.com; arc=none smtp.client-ip=195.135.223.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=suse.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=suse.com Received: from imap1.dmz-prg2.suse.org (imap1.dmz-prg2.suse.org [IPv6:2a07:de40:b281:104:10:150:64:97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by smtp-out2.suse.de (Postfix) with ESMTPS id 2FE9F75D0F; Mon, 29 Jun 2026 06:57:19 +0000 (UTC) Authentication-Results: smtp-out2.suse.de; none Received: from imap1.dmz-prg2.suse.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by imap1.dmz-prg2.suse.org (Postfix) with ESMTPS id D482F779A8; Mon, 29 Jun 2026 06:57:18 +0000 (UTC) Received: from dovecot-director2.suse.de ([2a07:de40:b281:106:10:150:64:167]) by imap1.dmz-prg2.suse.org with ESMTPSA id DuZvMk4XQmqQQgAAD6G6ig (envelope-from ); Mon, 29 Jun 2026 06:57:18 +0000 From: Juergen Gross To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: Juergen Gross , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Boris Ostrovsky , xen-devel@lists.xenproject.org Subject: [PATCH v4 16/18] x86/msr: Reduce number of low level MSR access helpers Date: Mon, 29 Jun 2026 08:55:42 +0200 Message-ID: <20260629065544.3643253-17-jgross@suse.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260629065544.3643253-1-jgross@suse.com> References: <20260629065544.3643253-1-jgross@suse.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Rspamd-Pre-Result: action=no action; module=replies; Message is reply to one we originated X-Rspamd-Queue-Id: 2FE9F75D0F X-Spam-Flag: NO X-Spam-Score: -4.00 X-Spam-Level: X-Rspamd-Action: no action X-Rspamd-Server: rspamd1.dmz-prg2.suse.org X-Rspamd-Pre-Result: action=no action; module=replies; Message is reply to one we originated X-Spamd-Result: default: False [-4.00 / 50.00]; REPLY(-4.00)[] Content-Type: text/plain; charset="utf-8" Some MSR access helpers are redundant now, so remove the no longer needed ones. Signed-off-by: Juergen Gross --- arch/x86/include/asm/msr.h | 15 ++------------- arch/x86/xen/enlighten_pv.c | 4 ++-- 2 files changed, 4 insertions(+), 15 deletions(-) diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h index b13b4a93673e..74defb414931 100644 --- a/arch/x86/include/asm/msr.h +++ b/arch/x86/include/asm/msr.h @@ -269,22 +269,11 @@ static __always_inline void native_wrmsrq(u32 msr, u6= 4 val) __wrmsrq(msr, val); } =20 -static inline u64 native_read_msr(u32 msr) -{ - return native_rdmsrq(msr); -} - static inline int native_read_msr_safe(u32 msr, u64 *val) { return __rdmsr(msr, val, EX_TYPE_RDMSR_SAFE) ? -EIO : 0; } =20 -/* Can be uninlined because referenced by paravirt */ -static inline void notrace native_write_msr(u32 msr, u64 val) -{ - native_wrmsrq(msr, val); -} - /* Can be uninlined because referenced by paravirt */ static inline int notrace native_write_msr_safe(u32 msr, u64 val) { @@ -327,7 +316,7 @@ static inline u64 native_read_pmc(int counter) #else static __always_inline u64 read_msr(u32 msr) { - return native_read_msr(msr); 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Peter Anvin" , Nathan Chancellor , Nick Desaulniers , Bill Wendling , Justin Stitt Subject: [PATCH v4 17/18] x86/paravirt: Use alternatives for MSR access with paravirt Date: Mon, 29 Jun 2026 08:55:43 +0200 Message-ID: <20260629065544.3643253-18-jgross@suse.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260629065544.3643253-1-jgross@suse.com> References: <20260629065544.3643253-1-jgross@suse.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Spam-Flag: NO X-Spamd-Result: default: False [-5.30 / 50.00]; REPLY(-4.00)[]; BAYES_HAM(-3.00)[100.00%]; SUSPICIOUS_RECIPS(1.50)[]; MID_CONTAINS_FROM(1.00)[]; NEURAL_HAM_LONG(-1.00)[-1.000]; R_MISSING_CHARSET(0.50)[]; NEURAL_HAM_SHORT(-0.20)[-1.000]; MIME_GOOD(-0.10)[text/plain]; MIME_TRACE(0.00)[0:+]; RCPT_COUNT_TWELVE(0.00)[17]; DKIM_SIGNED(0.00)[suse.com:s=susede1]; TO_MATCH_ENVRCPT_ALL(0.00)[]; FUZZY_RATELIMITED(0.00)[rspamd.com]; ARC_NA(0.00)[]; FREEMAIL_CC(0.00)[suse.com,broadcom.com,kernel.org,redhat.com,alien8.de,linux.intel.com,zytor.com,gmail.com,google.com]; RCVD_TLS_ALL(0.00)[]; RCVD_COUNT_TWO(0.00)[2]; FROM_EQ_ENVFROM(0.00)[]; FROM_HAS_DN(0.00)[]; TO_DN_SOME(0.00)[]; DBL_BLOCKED_OPENRESOLVER(0.00)[suse.com:email,suse.com:mid,imap1.dmz-prg2.suse.org:helo]; RCVD_VIA_SMTP_AUTH(0.00)[]; TAGGED_RCPT(0.00)[lkml]; R_RATELIMIT(0.00)[to_ip_from(RLfdszjqhz8kzzb9uwpzdm8png)]; FREEMAIL_ENVRCPT(0.00)[gmail.com] X-Spam-Level: X-Spam-Score: -5.30 Content-Type: text/plain; charset="utf-8" When not running as Xen PV guest, patch in the optimal MSR instructions via alternative and use direct calls otherwise. This will especially have positive effects for performance when not running as a Xen PV guest with paravirtualization enabled, as there will be no call overhead for MSR access functions any longer. Signed-off-by: Juergen Gross --- V3: - new patch V4: - fix build error with clang (kernel test robot) --- arch/x86/include/asm/paravirt-msr.h | 136 ++++++++++++++++++++------ arch/x86/include/asm/paravirt_types.h | 1 + 2 files changed, 109 insertions(+), 28 deletions(-) diff --git a/arch/x86/include/asm/paravirt-msr.h b/arch/x86/include/asm/par= avirt-msr.h index 4b71a1cd780c..ba3ee64446db 100644 --- a/arch/x86/include/asm/paravirt-msr.h +++ b/arch/x86/include/asm/paravirt-msr.h @@ -27,67 +27,147 @@ extern struct pv_msr_ops pv_ops_msr; #define PV_CALLEE_SAVE_REGS_MSR_THUNK(func) \ __PV_CALLEE_SAVE_REGS_THUNK(func, ".text", MSR) =20 +#define ASM_CLRERR "xor %[err],%[err]\n" + +#define PV_RDMSR_VAR(__msr, __val, __type, __func, __err) \ + asm volatile( \ + "1:\n" \ + ALTERNATIVE_2(PARAVIRT_CALL, \ + RDMSR_AND_SAVE_RESULT ASM_CLRERR, X86_FEATURE_ALWAYS, \ + ALT_CALL_INSTR, ALT_XEN_CALL) \ + "2:\n" \ + _ASM_EXTABLE_TYPE_REG(1b, 2b, __type, %[err]) \ + : [err] "=3Dd" (__err), [val] "=3Da" (__val), \ + ASM_CALL_CONSTRAINT \ + : paravirt_ptr(pv_ops_msr, __func), "c" (__msr) \ + : "cc") + +#define PV_RDMSR_CONST(__msr, __val, __type, __func, __err) \ + asm volatile( \ + "1:\n" \ + ALTERNATIVE_3(PARAVIRT_CALL, \ + RDMSR_AND_SAVE_RESULT ASM_CLRERR, X86_FEATURE_ALWAYS, \ + ASM_RDMSR_IMM ASM_CLRERR, X86_FEATURE_MSR_IMM, \ + ALT_CALL_INSTR, ALT_XEN_CALL) \ + "2:\n" \ + _ASM_EXTABLE_TYPE_REG(1b, 2b, __type, %[err]) \ + : [err] "=3Dd" (__err), [val] "=3Da" (__val), \ + ASM_CALL_CONSTRAINT \ + : paravirt_ptr(pv_ops_msr, __func), \ + "c" (__msr), [msr] "i" (__msr) \ + : "cc") + +#define PV_WRMSR(__msr, __val, __type, __func, __err) \ +({ \ + unsigned long rdx =3D rdx; \ + asm volatile( \ + "1:\n" \ + ALTERNATIVE_2(PARAVIRT_CALL, \ + "wrmsr;" ASM_CLRERR, X86_FEATURE_ALWAYS, \ + ALT_CALL_INSTR, ALT_XEN_CALL) \ + "2:\n" \ + _ASM_EXTABLE_TYPE_REG(1b, 2b, __type, %[err]) \ + : [err] "=3Da" (__err), "=3Dd" (rdx), ASM_CALL_CONSTRAINT \ + : paravirt_ptr(pv_ops_msr, __func), \ + "0" (__val), "1" ((__val) >> 32), "c" (__msr) \ + : "memory", "cc"); \ +}) + +#define PV_WRMSRNS_VAR(__msr, __val, __type, __func, __err) \ +({ \ + unsigned long rdx =3D rdx; \ + asm volatile( \ + "1:\n" \ + ALTERNATIVE_3(PARAVIRT_CALL, \ + "wrmsr;" ASM_CLRERR, X86_FEATURE_ALWAYS, \ + ASM_WRMSRNS ASM_CLRERR, X86_FEATURE_WRMSRNS, \ + ALT_CALL_INSTR, ALT_XEN_CALL) \ + "2:\n" \ + _ASM_EXTABLE_TYPE_REG(1b, 2b, __type, %[err]) \ + : [err] "=3Da" (__err), "=3Dd" (rdx), ASM_CALL_CONSTRAINT \ + : paravirt_ptr(pv_ops_msr, __func), \ + "0" (__val), "1" ((__val) >> 32), "c" (__msr) \ + : "memory", "cc"); \ +}) + +#define PV_WRMSRNS_CONST(__msr, __val, __type, __func, __err) \ +({ \ + unsigned long rdx =3D rdx; \ + asm volatile( \ + "1:\n" \ + ALTERNATIVE_4(PARAVIRT_CALL, \ + "wrmsr;" ASM_CLRERR, X86_FEATURE_ALWAYS, \ + ASM_WRMSRNS ASM_CLRERR, X86_FEATURE_WRMSRNS, \ + ASM_WRMSRNS_IMM ASM_CLRERR, X86_FEATURE_MSR_IMM,\ + ALT_CALL_INSTR, ALT_XEN_CALL) \ + "2:\n" \ + _ASM_EXTABLE_TYPE_REG(1b, 2b, __type, %[err]) \ + : [err] "=3Da" (__err), "=3Dd" (rdx), ASM_CALL_CONSTRAINT \ + : paravirt_ptr(pv_ops_msr, __func), \ + [val] "0" (__val), "1" ((__val) >> 32), \ + "c" (__msr), [msr] "i" (__msr) \ + : "memory", "cc"); \ +}) + static __always_inline u64 read_msr(u32 msr) { u64 val; + u64 err; =20 - asm volatile(PARAVIRT_CALL - : "=3Da" (val), ASM_CALL_CONSTRAINT - : paravirt_ptr(pv_ops_msr, read_msr), "c" (msr) - : "rdx"); + if (__builtin_constant_p(msr)) + PV_RDMSR_CONST(msr, val, EX_TYPE_RDMSR, read_msr, err); + else + PV_RDMSR_VAR(msr, val, EX_TYPE_RDMSR, read_msr, err); =20 return val; } =20 static __always_inline void write_msr(u32 msr, u64 val) { - asm volatile(PARAVIRT_CALL - : ASM_CALL_CONSTRAINT - : paravirt_ptr(pv_ops_msr, write_msr), "c" (msr), "a" (val) - : "memory", "rdx"); + u64 err; + + PV_WRMSR(msr, val, EX_TYPE_WRMSR, write_msr, err); } =20 static __always_inline void write_msrns(u32 msr, u64 val) { - asm volatile(PARAVIRT_CALL - : ASM_CALL_CONSTRAINT - : paravirt_ptr(pv_ops_msr, write_msr), "c" (msr), "a" (val) - : "memory", "rdx"); + u64 err; + + if (__builtin_constant_p(msr)) + PV_WRMSRNS_CONST(msr, val, EX_TYPE_WRMSR, write_msr, err); + else + PV_WRMSRNS_VAR(msr, val, EX_TYPE_WRMSR, write_msr, err); } =20 static __always_inline int read_msr_safe(u32 msr, u64 *val) { - int err; + u64 err; =20 - asm volatile(PARAVIRT_CALL - : [err] "=3Dd" (err), "=3Da" (*val), ASM_CALL_CONSTRAINT - : paravirt_ptr(pv_ops_msr, read_msr_safe), "c" (msr)); + if (__builtin_constant_p(msr)) + PV_RDMSR_CONST(msr, *val, EX_TYPE_RDMSR_SAFE, read_msr_safe, err); + else + PV_RDMSR_VAR(msr, *val, EX_TYPE_RDMSR_SAFE, read_msr_safe, err); =20 return err ? -EIO : 0; } =20 static __always_inline int write_msr_safe(u32 msr, u64 val) { - int err; + u64 err; =20 - asm volatile(PARAVIRT_CALL - : [err] "=3Da" (err), ASM_CALL_CONSTRAINT - : paravirt_ptr(pv_ops_msr, write_msr_safe), - "c" (msr), "a" (val) - : "memory", "rdx"); + PV_WRMSR(msr, val, EX_TYPE_WRMSR_SAFE, write_msr_safe, err); =20 return err ? -EIO : 0; } =20 static __always_inline int write_msrns_safe(u32 msr, u64 val) { - int err; + u64 err; =20 - asm volatile(PARAVIRT_CALL - : [err] "=3Da" (err), ASM_CALL_CONSTRAINT - : paravirt_ptr(pv_ops_msr, write_msr_safe), - "c" (msr), "a" (val) - : "memory", "rdx"); + if (__builtin_constant_p(msr)) + PV_WRMSRNS_CONST(msr, val, EX_TYPE_WRMSR_SAFE, write_msr_safe, err); + else + PV_WRMSRNS_VAR(msr, val, EX_TYPE_WRMSR_SAFE, write_msr_safe, err); =20 return err ? -EIO : 0; } diff --git a/arch/x86/include/asm/paravirt_types.h b/arch/x86/include/asm/p= aravirt_types.h index 740ea819bbab..54f7c3d8fadf 100644 --- a/arch/x86/include/asm/paravirt_types.h +++ b/arch/x86/include/asm/paravirt_types.h @@ -442,6 +442,7 @@ extern struct paravirt_patch_template pv_ops; #endif /* __ASSEMBLER__ */ =20 #define ALT_NOT_XEN ALT_NOT(X86_FEATURE_XENPV) +#define ALT_XEN_CALL ALT_DIRECT_CALL(X86_FEATURE_XENPV) =20 #ifdef CONFIG_X86_32 /* save and restore all caller-save registers, except return value */ --=20 2.54.0 From nobody Tue Jun 30 05:35:19 2026 Received: from smtp-out1.suse.de (smtp-out1.suse.de [195.135.223.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A81AA3BC687 for ; Mon, 29 Jun 2026 06:57:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=195.135.223.130 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782716253; cv=none; b=igIM0gJH6QEVYrvFS1IcTH5ya9RXJ8pDDMvPgvn98rS+36z1W+khsatcBmrosxR7agrv/xGYReOygj2l/sn4CweXvTIDfuLgpYlTa3DPe62iPBCiRtRCIRiERsFxbMRTfBwl0+IDSzZaEqNeTE2HGvThTyIHEqgIVzpVDkO9Z3U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782716253; c=relaxed/simple; bh=7SofCqHlXZHsGywWIbJLRunzHijONIUHedv8Xrx1yGY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=WNDCDBKGxtuvOghadpstuE5oRuE58tOud3+Y7SWu1L/vGLerSKU2Hf7nwfUwDp30mBWD85T1C037sP/kGOT2Hr5o80RWenGf18H/0o7VGN4MtsTomIPUOSmy0cHRZLd26cH9Eaq1qdoqFxaqtV5X8n2lcRgVUtCY64yjJdSfA/Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=suse.com; spf=pass smtp.mailfrom=suse.com; arc=none smtp.client-ip=195.135.223.130 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=suse.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=suse.com Received: from imap1.dmz-prg2.suse.org (imap1.dmz-prg2.suse.org [IPv6:2a07:de40:b281:104:10:150:64:97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by smtp-out1.suse.de (Postfix) with ESMTPS id A6AA072F34; Mon, 29 Jun 2026 06:57:30 +0000 (UTC) Authentication-Results: smtp-out1.suse.de; none Received: from imap1.dmz-prg2.suse.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by imap1.dmz-prg2.suse.org (Postfix) with ESMTPS id 66990779A8; Mon, 29 Jun 2026 06:57:30 +0000 (UTC) Received: from dovecot-director2.suse.de ([2a07:de40:b281:106:10:150:64:167]) by imap1.dmz-prg2.suse.org with ESMTPSA id 8EudF1oXQmqsQgAAD6G6ig (envelope-from ); Mon, 29 Jun 2026 06:57:30 +0000 From: Juergen Gross To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: Juergen Gross , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" Subject: [PATCH v4 18/18] x86/msr: Make all MSR access functions __always_inline Date: Mon, 29 Jun 2026 08:55:44 +0200 Message-ID: <20260629065544.3643253-19-jgross@suse.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260629065544.3643253-1-jgross@suse.com> References: <20260629065544.3643253-1-jgross@suse.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Rspamd-Pre-Result: action=no action; module=replies; Message is reply to one we originated X-Rspamd-Queue-Id: A6AA072F34 X-Spam-Flag: NO X-Spam-Score: -4.00 X-Spam-Level: X-Rspamd-Action: no action X-Rspamd-Server: rspamd1.dmz-prg2.suse.org X-Rspamd-Pre-Result: action=no action; module=replies; Message is reply to one we originated X-Spamd-Result: default: False [-4.00 / 50.00]; REPLY(-4.00)[] Content-Type: text/plain; charset="utf-8" There are a few MSR access functions left which are not yet marked as __always_inline. Do the conversion. Remove a leftover comment no longer being true related to this. Signed-off-by: Juergen Gross --- V4: - new patch --- arch/x86/include/asm/msr.h | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h index 74defb414931..a8cfed32d9a3 100644 --- a/arch/x86/include/asm/msr.h +++ b/arch/x86/include/asm/msr.h @@ -269,13 +269,12 @@ static __always_inline void native_wrmsrq(u32 msr, u6= 4 val) __wrmsrq(msr, val); } =20 -static inline int native_read_msr_safe(u32 msr, u64 *val) +static __always_inline int native_read_msr_safe(u32 msr, u64 *val) { return __rdmsr(msr, val, EX_TYPE_RDMSR_SAFE) ? -EIO : 0; } =20 -/* Can be uninlined because referenced by paravirt */ -static inline int notrace native_write_msr_safe(u32 msr, u64 val) +static __always_inline int notrace native_write_msr_safe(u32 msr, u64 val) { int err; =20 @@ -301,7 +300,7 @@ static __always_inline int native_wrmsrns_safe(u32 msr,= u64 val) extern int rdmsr_safe_regs(u32 regs[8]); extern int wrmsr_safe_regs(u32 regs[8]); =20 -static inline u64 native_read_pmc(int counter) +static __always_inline u64 native_read_pmc(int counter) { EAX_EDX_DECLARE_ARGS(val, low, high); =20 @@ -363,7 +362,7 @@ static __always_inline u64 rdmsrq(u32 msr) } =20 /* rdmsr with exception handling */ -static inline int rdmsrq_safe(u32 msr, u64 *p) +static __always_inline int rdmsrq_safe(u32 msr, u64 *p) { int err; =20 @@ -375,7 +374,7 @@ static inline int rdmsrq_safe(u32 msr, u64 *p) return err; } =20 -static inline void wrmsrq(u32 msr, u64 val) +static __always_inline void wrmsrq(u32 msr, u64 val) { write_msr(msr, val); =20 @@ -384,7 +383,7 @@ static inline void wrmsrq(u32 msr, u64 val) } =20 /* wrmsr with exception handling */ -static inline int wrmsrq_safe(u32 msr, u64 val) +static __always_inline int wrmsrq_safe(u32 msr, u64 val) { int err; =20 --=20 2.54.0