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charset="utf-8" Fix a race condition in AXIDMA and MCDMA irq handlers where the channel could be incorrectly marked as idle and attempt spurious transfers when descriptors are still being processed. The issue occurs when: 1. Multiple descriptors are queued and active. 2. An interrupt fires after completing some descriptors. 3. xilinx_dma_complete_descriptor() moves completed descriptors to done_list. 4. Channel is marked idle and start_transfer() is called even though active_list still contains unprocessed descriptors. 5. This leads to premature transfer attempts and potential descriptor corruption or missed completions. Only mark the channel as idle and start new transfers when the active list is actually empty, ensuring proper channel state management and avoiding spurious transfer attempts. Fixes: c0bba3a99f07 ("dmaengine: vdma: Add Support for Xilinx AXI Direct Me= mory Access Engine") Tested-by: Folker Schwesinger Signed-off-by: Suraj Gupta Co-developed-by: Srinivas Neeli Signed-off-by: Srinivas Neeli Reviewed-by: Radhey Shyam Pandey --- drivers/dma/xilinx/xilinx_dma.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dm= a.c index 404235c17353..ca396b709742 100644 --- a/drivers/dma/xilinx/xilinx_dma.c +++ b/drivers/dma/xilinx/xilinx_dma.c @@ -1893,8 +1893,10 @@ static irqreturn_t xilinx_mcdma_irq_handler(int irq,= void *data) if (status & XILINX_MCDMA_IRQ_IOC_MASK) { spin_lock(&chan->lock); xilinx_dma_complete_descriptor(chan); - chan->idle =3D true; - chan->start_transfer(chan); + if (list_empty(&chan->active_list)) { + chan->idle =3D true; + chan->start_transfer(chan); + } spin_unlock(&chan->lock); } =20 @@ -1950,8 +1952,10 @@ static irqreturn_t xilinx_dma_irq_handler(int irq, v= oid *data) XILINX_DMA_DMASR_DLY_CNT_IRQ)) { spin_lock(&chan->lock); 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charset="utf-8" Relax the idle check in xilinx_dma_start_transfer() and xilinx_mcdma_start_transfer() that prevented new transfers from being queued when the channel was busy, so scatter-gather transfers can be chained onto an in-flight transfer. In scatter-gather mode, only update the CURDESC register when the active list is empty to avoid interfering with transfers already in progress. When the active list contains transfers, the hardware tail pointer extension mechanism handles chaining automatically via the descriptor next pointer chain, which is set up at channel allocation and preserved across descriptor recycling. Direct (non-SG) mode has no descriptor queue: writing the BTT register launches a transfer immediately, so a new transfer must not be programmed while one is in flight. Keep those transfers serialized by retaining the idle check on the non-SG path. MCDMA always operates in scatter-gather mode, so it is unaffected. Signed-off-by: Suraj Gupta Co-developed-by: Srinivas Neeli Signed-off-by: Srinivas Neeli Reviewed-by: Radhey Shyam Pandey Tested-by: Folker Schwesinger --- drivers/dma/xilinx/xilinx_dma.c | 19 ++++++++++++------- 1 file changed, 12 insertions(+), 7 deletions(-) diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dm= a.c index ca396b709742..6e7b183cb499 100644 --- a/drivers/dma/xilinx/xilinx_dma.c +++ b/drivers/dma/xilinx/xilinx_dma.c @@ -1580,7 +1580,14 @@ static void xilinx_dma_start_transfer(struct xilinx_= dma_chan *chan) return; } =20 - if (!chan->idle) + /* + * Direct (non-SG) mode has no descriptor queue: writing the BTT + * register launches a transfer immediately, so a new transfer must + * not be programmed while one is in flight. Keep such transfers + * serialized. SG mode supports chaining onto a running transfer via + * tail-pointer extension, so it is allowed to proceed when busy. + */ + if (!chan->has_sg && !chan->idle) return; =20 head_desc =3D list_first_entry(&chan->pending_list, @@ -1599,7 +1606,7 @@ static void xilinx_dma_start_transfer(struct xilinx_d= ma_chan *chan) dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg); } =20 - if (chan->has_sg) + if (chan->has_sg && list_empty(&chan->active_list)) xilinx_write(chan, XILINX_DMA_REG_CURDESC, head_desc->async_tx.phys); reg &=3D ~XILINX_DMA_CR_DELAY_MAX; @@ -1660,9 +1667,6 @@ static void xilinx_mcdma_start_transfer(struct xilinx= _dma_chan *chan) if (chan->err) return; =20 - if (!chan->idle) - return; - if (list_empty(&chan->pending_list)) return; =20 @@ -1685,8 +1689,9 @@ static void xilinx_mcdma_start_transfer(struct xilinx= _dma_chan *chan) dma_ctrl_write(chan, XILINX_MCDMA_CHAN_CR_OFFSET(chan->tdest), reg); =20 /* Program current descriptor */ - xilinx_write(chan, XILINX_MCDMA_CHAN_CDESC_OFFSET(chan->tdest), - head_desc->async_tx.phys); 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charset="utf-8" Optimize AXI DMA control register programming by consolidating coalesce count and delay configuration into a single register write. Previously, the coalesce count was written separately from the delay configuration, resulting in two register writes. Combine these into one write operation to reduce bus overhead. Additionally, avoid redundant channel starts in xilinx_dma_start_transfer() and xilinx_mcdma_start_transfer() by only calling xilinx_dma_start() when the channel is actually idle. Tested-by: Folker Schwesinger Signed-off-by: Suraj Gupta Co-developed-by: Srinivas Neeli Signed-off-by: Srinivas Neeli Reviewed-by: Radhey Shyam Pandey --- drivers/dma/xilinx/xilinx_dma.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dm= a.c index 6e7b183cb499..829601d8a16f 100644 --- a/drivers/dma/xilinx/xilinx_dma.c +++ b/drivers/dma/xilinx/xilinx_dma.c @@ -1603,7 +1603,6 @@ static void xilinx_dma_start_transfer(struct xilinx_d= ma_chan *chan) reg &=3D ~XILINX_DMA_CR_COALESCE_MAX; reg |=3D chan->desc_pendingcount << XILINX_DMA_CR_COALESCE_SHIFT; - dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg); } =20 if (chan->has_sg && list_empty(&chan->active_list)) @@ -1614,7 +1613,8 @@ static void xilinx_dma_start_transfer(struct xilinx_d= ma_chan *chan) reg |=3D XILINX_DMA_DMAXR_ALL_IRQ_MASK; dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg); =20 - xilinx_dma_start(chan); + if (chan->idle) + xilinx_dma_start(chan); =20 if (chan->err) return; @@ -1703,7 +1703,8 @@ static void xilinx_mcdma_start_transfer(struct xilinx= _dma_chan *chan) reg |=3D XILINX_MCDMA_CR_RUNSTOP_MASK; dma_ctrl_write(chan, XILINX_MCDMA_CHAN_CR_OFFSET(chan->tdest), reg); =20 - xilinx_dma_start(chan); + if (chan->idle) + xilinx_dma_start(chan); =20 if (chan->err) return; --=20 2.25.1