From nobody Sun Jun 28 12:42:54 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0108C1CAA78; Thu, 25 Jun 2026 03:54:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.20 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782359695; cv=none; b=V0lMKZ4RRmrsivs+UynmF1uZd+16ruSj8RclK0fqt2AxDHqd4P+mp0IvuWkRcYPJsfaqAhdcTMmJ0E9kCJ4Z4WTpJyvjgnF15WpukKOKvQf1JlYGbXuO3enUNKlTN1qVs62XCKdVB41y8nR8R6SdaErMmxAf/cHsoPnmyEHWBUY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782359695; c=relaxed/simple; bh=cnIcwmbbTbzD78xzTfIyMXwnIfQGt6qigGgffUtGN5I=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=KCadYDlzygmeplloQGmwjHbkSR/NNNWUZcpysPz71Ep2+ktxjV+vOV2/e5efmN1jLt6+KbpR+1VP4Te/EFzPtRARYoPuXg0Ux1wC89huLFXjML390U1g45qkOZUEVBTjjzwybZHxsa/Kcd3n/Txg/rfNioS3/pMzcOhzn6JoAdk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Brjzcpys; arc=none smtp.client-ip=198.175.65.20 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Brjzcpys" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1782359694; x=1813895694; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=cnIcwmbbTbzD78xzTfIyMXwnIfQGt6qigGgffUtGN5I=; b=Brjzcpysuo1qEu3Pg/S97e0UliME7FnzKMBKAqurghyKbQksgFGstyVy jBLa9+1oPdYmo8MX/vKOEKQYG7Panlk/GFbitrMOnJv7EsS6Qjt5Vo4VG MNJW8tMGWPzgXP9VHx41I7bb5vDqOp+dPgktwRCQX6G2SyTmdDjhfKy2/ 8XJBgbhRpD3hTgqBvXw7g/BCpRvTAIHPQTgEOq0mOSt2DCwlFio6jHaX9 uvrF7ubRHdBc+fzbDID+F932A1PgDUw9n5q0iuouuRwUv+6yYaxf5PODw Ybxt1h0kI+cxLVV77ZQ9/cdZavEPtwifTMc1PESYOuA5yiubEuo96JL4i A==; X-CSE-ConnectionGUID: uiwnvD9CTNyo4ZTm9m1oSg== X-CSE-MsgGUID: +5MxV9oxTb65uX8au3Qs7Q== X-IronPort-AV: E=McAfee;i="6800,10657,11827"; a="82901454" X-IronPort-AV: E=Sophos;i="6.24,223,1774335600"; d="scan'208";a="82901454" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by orvoesa112.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Jun 2026 20:54:53 -0700 X-CSE-ConnectionGUID: WjNZjeZOS2CgZSU4rIHgRg== X-CSE-MsgGUID: Kj5sEOfhS+KqaVgoD0Y9Lg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,223,1774335600"; d="scan'208";a="288396615" Received: from 9cc2c43eec6b.jf.intel.com ([10.54.77.29]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Jun 2026 20:54:52 -0700 From: Zide Chen To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Jim Mattson , Mingwei Zhang , Zide Chen , Das Sandipan , Shukla Manali , Dapeng Mi , Falcon Thomas , Xudong Hao Subject: [PATCH V5 1/7] KVM: x86/pmu: Do not map fixed counters >= 3 to generic perf events Date: Wed, 24 Jun 2026 20:45:49 -0700 Message-ID: <20260625034555.141453-2-zide.chen@intel.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260625034555.141453-1-zide.chen@intel.com> References: <20260625034555.141453-1-zide.chen@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Only fixed counters 0..2 have matching generic cross-platform hardware perf events (INSTRUCTIONS, CPU_CYCLES, REF_CPU_CYCLES). Therefore, perf_get_hw_event_config() is only applicable to these counters. KVM does not intend to emulate fixed counters >=3D 3 on legacy (non-mediated) vPMU, while for mediated vPMU, KVM does not care what the fixed counter event mappings are. Therefore, return 0 for their eventsel. Also remove __always_inline as BUILD_BUG_ON() is no longer needed. Signed-off-by: Zide Chen --- v2: - Replace 3 in "if (index < 3)" with ARRAY_SIZE(fixed_pmc_perf_ids). --- arch/x86/kvm/vmx/pmu_intel.c | 26 ++++++++++++++------------ 1 file changed, 14 insertions(+), 12 deletions(-) diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c index a73a9515d96c..60b6b83c7ced 100644 --- a/arch/x86/kvm/vmx/pmu_intel.c +++ b/arch/x86/kvm/vmx/pmu_intel.c @@ -464,28 +464,30 @@ static int intel_pmu_set_msr(struct kvm_vcpu *vcpu, s= truct msr_data *msr_info) * different perf_event is already utilizing the requested counter, but th= e end * result is the same (ignoring the fact that using a general purpose coun= ter * will likely exacerbate counter contention). - * - * Forcibly inlined to allow asserting on @index at build time, and there = should - * never be more than one user. */ -static __always_inline u64 intel_get_fixed_pmc_eventsel(unsigned int index) +static u64 intel_get_fixed_pmc_eventsel(unsigned int index) { const enum perf_hw_id fixed_pmc_perf_ids[] =3D { [0] =3D PERF_COUNT_HW_INSTRUCTIONS, [1] =3D PERF_COUNT_HW_CPU_CYCLES, [2] =3D PERF_COUNT_HW_REF_CPU_CYCLES, }; - u64 eventsel; - - BUILD_BUG_ON(ARRAY_SIZE(fixed_pmc_perf_ids) !=3D KVM_MAX_NR_INTEL_FIXED_C= OUNTERS); - BUILD_BUG_ON(index >=3D KVM_MAX_NR_INTEL_FIXED_COUNTERS); + u64 eventsel =3D 0; =20 /* - * Yell if perf reports support for a fixed counter but perf doesn't - * have a known encoding for the associated general purpose event. + * Fixed counters 3 and above don't have a corresponding generic + * hardware perf event, and KVM does not intend to emulate them on + * non-mediated vPMU. */ - eventsel =3D perf_get_hw_event_config(fixed_pmc_perf_ids[index]); - WARN_ON_ONCE(!eventsel && index < kvm_pmu_cap.num_counters_fixed); + if (index < ARRAY_SIZE(fixed_pmc_perf_ids)) { + /* + * Yell if perf reports support for a fixed counter but perf + * doesn't have a known encoding for the associated general + * purpose event. + */ + eventsel =3D perf_get_hw_event_config(fixed_pmc_perf_ids[index]); + WARN_ON_ONCE(!eventsel && index < kvm_pmu_cap.num_counters_fixed); + } return eventsel; } =20 --=20 2.54.0 From nobody Sun Jun 28 12:42:54 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4CC4A3009E2; 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a="82901461" X-IronPort-AV: E=Sophos;i="6.24,223,1774335600"; d="scan'208";a="82901461" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by orvoesa112.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Jun 2026 20:54:53 -0700 X-CSE-ConnectionGUID: QkIM1vTERzuC99JthBmkNw== X-CSE-MsgGUID: vCs2VBUdTcyc8JrbwxeN8A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,223,1774335600"; d="scan'208";a="288396618" Received: from 9cc2c43eec6b.jf.intel.com ([10.54.77.29]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Jun 2026 20:54:52 -0700 From: Zide Chen To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Jim Mattson , Mingwei Zhang , Zide Chen , Das Sandipan , Shukla Manali , Dapeng Mi , Falcon Thomas , Xudong Hao Subject: [PATCH V5 2/7] KVM: x86/pmu: Support Intel fixed counter 3 on mediated vPMU Date: Wed, 24 Jun 2026 20:45:50 -0700 Message-ID: <20260625034555.141453-3-zide.chen@intel.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260625034555.141453-1-zide.chen@intel.com> References: <20260625034555.141453-1-zide.chen@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Dapeng Mi Starting with Ice Lake, Intel introduced fixed counter 3, which counts TOPDOWN.SLOTS - the number of available slots for an unhalted logical processor. It serves as the denominator for top-level metrics in the Top-down Microarchitecture Analysis method. Emulating this counter on legacy vPMU would require introducing a new generic perf encoding for the Intel-specific TOPDOWN.SLOTS event in order to call perf_get_hw_event_config(). This is undesirable as it would pollute the generic perf event encoding. Moreover, KVM does not intend to emulate IA32_PERF_METRICS in the legacy vPMU model, and without IA32_PERF_METRICS, emulating this counter has little practical value. Therefore, expose fixed counter 3 to guests only when mediated vPMU is enabled. Signed-off-by: Dapeng Mi Co-developed-by: Zide Chen Signed-off-by: Zide Chen --- v3: - Move the non-contiguous counter filter code to pmu.c v2: - Don't advertise fixed counter 3 to userspace if the host doesn't support it. --- arch/x86/include/asm/kvm_host.h | 2 +- arch/x86/kvm/pmu.c | 18 ++++++++++++++++++ arch/x86/kvm/x86.c | 4 ++-- 3 files changed, 21 insertions(+), 3 deletions(-) diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_hos= t.h index eee473717c0e..edd414f8ee95 100644 --- a/arch/x86/include/asm/kvm_host.h +++ b/arch/x86/include/asm/kvm_host.h @@ -574,7 +574,7 @@ struct kvm_pmc { #define KVM_MAX_NR_GP_COUNTERS KVM_MAX(KVM_MAX_NR_INTEL_GP_COUNTERS, \ KVM_MAX_NR_AMD_GP_COUNTERS) =20 -#define KVM_MAX_NR_INTEL_FIXED_COUNTERS 3 +#define KVM_MAX_NR_INTEL_FIXED_COUNTERS 4 #define KVM_MAX_NR_AMD_FIXED_COUNTERS 0 #define KVM_MAX_NR_FIXED_COUNTERS KVM_MAX(KVM_MAX_NR_INTEL_FIXED_COUNTERS,= \ KVM_MAX_NR_AMD_FIXED_COUNTERS) diff --git a/arch/x86/kvm/pmu.c b/arch/x86/kvm/pmu.c index b92dd2e58335..7aafc5db1346 100644 --- a/arch/x86/kvm/pmu.c +++ b/arch/x86/kvm/pmu.c @@ -122,6 +122,8 @@ void kvm_init_pmu_capability(struct kvm_pmu_ops *pmu_op= s) { bool is_intel =3D boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_INTEL; int min_nr_gp_ctrs =3D pmu_ops->MIN_NR_GP_COUNTERS; + union cpuid10_edx edx; + u32 eax, ebx, ecx; =20 /* * Hybrid PMUs don't play nice with virtualization without careful @@ -169,6 +171,22 @@ void kvm_init_pmu_capability(struct kvm_pmu_ops *pmu_o= ps) kvm_pmu_cap.num_counters_fixed =3D min(kvm_pmu_cap.num_counters_fixed, KVM_MAX_NR_FIXED_COUNTERS); =20 + /* + * Intel platforms may support non-contiguous fixed counters, e.g., some + * E-core based server processors don't implement fixed counter 3. + * + * Before KVM supports non-contiguous fixed counters, make sure only + * contiguous ones are retained in kvm_pmu_cap. + */ + if (kvm_host_pmu.version >=3D 5) { + cpuid(0xa, &eax, &ebx, &ecx, &edx.full); + if (kvm_pmu_cap.num_counters_fixed > edx.split.num_counters_fixed) + kvm_pmu_cap.num_counters_fixed =3D edx.split.num_counters_fixed; + } + + if (!enable_mediated_pmu && kvm_pmu_cap.num_counters_fixed > 3) + kvm_pmu_cap.num_counters_fixed =3D 3; + kvm_pmu_eventsel.INSTRUCTIONS_RETIRED =3D perf_get_hw_event_config(PERF_COUNT_HW_INSTRUCTIONS); kvm_pmu_eventsel.BRANCH_INSTRUCTIONS_RETIRED =3D diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index d9d51803b7b2..e872398c12fc 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -350,7 +350,7 @@ static const u32 msrs_to_save_base[] =3D { =20 static const u32 msrs_to_save_pmu[] =3D { MSR_ARCH_PERFMON_FIXED_CTR0, MSR_ARCH_PERFMON_FIXED_CTR1, - MSR_ARCH_PERFMON_FIXED_CTR0 + 2, + MSR_ARCH_PERFMON_FIXED_CTR2, MSR_ARCH_PERFMON_FIXED_CTR3, MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_CORE_PERF_GLOBAL_STATUS, MSR_CORE_PERF_GLOBAL_CTRL, MSR_IA32_PEBS_ENABLE, MSR_IA32_DS_AREA, MSR_PEBS_DATA_CFG, @@ -7742,7 +7742,7 @@ static void kvm_init_msr_lists(void) { unsigned i; =20 - BUILD_BUG_ON_MSG(KVM_MAX_NR_FIXED_COUNTERS !=3D 3, + BUILD_BUG_ON_MSG(KVM_MAX_NR_FIXED_COUNTERS !=3D 4, "Please update the fixed PMCs in msrs_to_save_pmu[]"); =20 num_msrs_to_save =3D 0; --=20 2.54.0 From nobody Sun Jun 28 12:42:54 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CF6FA2F6565; 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a="82901457" X-IronPort-AV: E=Sophos;i="6.24,223,1774335600"; d="scan'208";a="82901457" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by orvoesa112.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Jun 2026 20:54:53 -0700 X-CSE-ConnectionGUID: T99teRCOQDCI6+XQqrZbug== X-CSE-MsgGUID: 52AmVRv9TCKSFZKD4Ql1vg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,223,1774335600"; d="scan'208";a="288396620" Received: from 9cc2c43eec6b.jf.intel.com ([10.54.77.29]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Jun 2026 20:54:52 -0700 From: Zide Chen To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Jim Mattson , Mingwei Zhang , Zide Chen , Das Sandipan , Shukla Manali , Dapeng Mi , Falcon Thomas , Xudong Hao Subject: [PATCH V5 3/7] KVM: x86/pmu: Rename and move vcpu_get_perf_capabilities() to pmu.h Date: Wed, 24 Jun 2026 20:45:51 -0700 Message-ID: <20260625034555.141453-4-zide.chen@intel.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260625034555.141453-1-zide.chen@intel.com> References: <20260625034555.141453-1-zide.chen@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This is in preparation for it to be called from common x86 code, for example kvm_need_rdpmc_intercept(), to check the guest's PERF_METRICS capability. Rename it to kvm_vcpu_get_perf_caps() to indicate that it's part of the common API, and shorten _capabilities to _caps. No functional change intended. Signed-off-by: Zide Chen --- v5: new patch. --- arch/x86/kvm/pmu.h | 8 ++++++++ arch/x86/kvm/vmx/pmu_intel.c | 6 +++--- arch/x86/kvm/vmx/pmu_intel.h | 10 +--------- 3 files changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/x86/kvm/pmu.h b/arch/x86/kvm/pmu.h index a5821d7c87f9..1b2f66a2e915 100644 --- a/arch/x86/kvm/pmu.h +++ b/arch/x86/kvm/pmu.h @@ -271,6 +271,14 @@ static inline bool kvm_pmu_is_fastpath_emulation_allow= ed(struct kvm_vcpu *vcpu) X86_PMC_IDX_MAX); } =20 +static inline u64 kvm_vcpu_get_perf_caps(struct kvm_vcpu *vcpu) +{ + if (!guest_cpu_cap_has(vcpu, X86_FEATURE_PDCM)) + return 0; + + return vcpu->arch.perf_capabilities; +} + void kvm_pmu_deliver_pmi(struct kvm_vcpu *vcpu); int kvm_pmu_rdpmc(struct kvm_vcpu *vcpu, unsigned pmc, u64 *data); int kvm_pmu_check_rdpmc_early(struct kvm_vcpu *vcpu, unsigned int idx); diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c index 60b6b83c7ced..8171265df684 100644 --- a/arch/x86/kvm/vmx/pmu_intel.c +++ b/arch/x86/kvm/vmx/pmu_intel.c @@ -189,13 +189,13 @@ static bool intel_is_valid_msr(struct kvm_vcpu *vcpu,= u32 msr) case MSR_CORE_PERF_FIXED_CTR_CTRL: return kvm_pmu_has_perf_global_ctrl(pmu); case MSR_IA32_PEBS_ENABLE: - ret =3D vcpu_get_perf_capabilities(vcpu) & PERF_CAP_PEBS_FORMAT; + ret =3D kvm_vcpu_get_perf_caps(vcpu) & PERF_CAP_PEBS_FORMAT; break; case MSR_IA32_DS_AREA: ret =3D guest_cpu_cap_has(vcpu, X86_FEATURE_DS); break; case MSR_PEBS_DATA_CFG: - perf_capabilities =3D vcpu_get_perf_capabilities(vcpu); + perf_capabilities =3D kvm_vcpu_get_perf_caps(vcpu); ret =3D (perf_capabilities & PERF_CAP_PEBS_BASELINE) && ((perf_capabilities & PERF_CAP_PEBS_FORMAT) > 3); break; @@ -550,7 +550,7 @@ static void intel_pmu_refresh(struct kvm_vcpu *vcpu) pmu->raw_event_mask |=3D (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED); } =20 - perf_capabilities =3D vcpu_get_perf_capabilities(vcpu); + perf_capabilities =3D kvm_vcpu_get_perf_caps(vcpu); if (intel_pmu_lbr_is_compatible(vcpu) && (perf_capabilities & PERF_CAP_LBR_FMT)) memcpy(&lbr_desc->records, &vmx_lbr_caps, sizeof(vmx_lbr_caps)); diff --git a/arch/x86/kvm/vmx/pmu_intel.h b/arch/x86/kvm/vmx/pmu_intel.h index 5d9357640aa1..afdbbc9991d6 100644 --- a/arch/x86/kvm/vmx/pmu_intel.h +++ b/arch/x86/kvm/vmx/pmu_intel.h @@ -6,17 +6,9 @@ =20 #include "cpuid.h" =20 -static inline u64 vcpu_get_perf_capabilities(struct kvm_vcpu *vcpu) -{ - if (!guest_cpu_cap_has(vcpu, X86_FEATURE_PDCM)) - return 0; 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d="scan'208";a="288396623" Received: from 9cc2c43eec6b.jf.intel.com ([10.54.77.29]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Jun 2026 20:54:52 -0700 From: Zide Chen To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Jim Mattson , Mingwei Zhang , Zide Chen , Das Sandipan , Shukla Manali , Dapeng Mi , Falcon Thomas , Xudong Hao Subject: [PATCH V5 4/7] KVM: x86/pmu: Support PERF_METRICS MSR in mediated vPMU Date: Wed, 24 Jun 2026 20:45:52 -0700 Message-ID: <20260625034555.141453-5-zide.chen@intel.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260625034555.141453-1-zide.chen@intel.com> References: <20260625034555.141453-1-zide.chen@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Dapeng Mi Bit 15 in IA32_PERF_CAPABILITIES indicates that the CPU provides built-in support for Topdown Microarchitecture Analysis (TMA) L1 metrics via the IA32_PERF_METRICS MSR. Expose this capability only when mediated vPMU is enabled, as emulating IA32_PERF_METRICS in the legacy vPMU model is impractical. Pass IA32_PERF_METRICS through to the guest only when mediated vPMU is enabled and bit 15 is set in guest IA32_PERF_CAPABILITIES. Allow kvm_pmu_{get,set}_msr() to handle this MSR for host accesses. Save and restore this MSR on host/guest PMU context switches so that host PMU activity does not clobber the guest value, and guest state is not leaked into the host. Signed-off-by: Dapeng Mi Signed-off-by: Zide Chen --- v5: - Remove host_initiated check in set/get MSR handlers. v4: - Remove WARN_ON_ONCE() and simply reject the guest accesses by checking host_initiated. (Sashiko) - Passthru MSR_PERF_METRICS only if has_mediated_pmu is true. (Sashiko) - Remove the redundant !! in vcpu_has_perf_metrics(). v3: - Replace WARN_ON() with WARN_ON_ONCE(). (Dapeng) - Add comments to explain why we don't validate writes on PERF_METRICS. --- arch/x86/include/asm/kvm_host.h | 1 + arch/x86/include/asm/msr-index.h | 1 + arch/x86/include/asm/perf_event.h | 1 + arch/x86/kvm/pmu.h | 5 +++++ arch/x86/kvm/vmx/pmu_intel.c | 29 +++++++++++++++++++++++++++++ arch/x86/kvm/vmx/vmx.c | 7 +++++++ arch/x86/kvm/x86.c | 6 +++++- 7 files changed, 49 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_hos= t.h index edd414f8ee95..4f549ef012d2 100644 --- a/arch/x86/include/asm/kvm_host.h +++ b/arch/x86/include/asm/kvm_host.h @@ -594,6 +594,7 @@ struct kvm_pmu { u64 global_status_rsvd; u64 reserved_bits; u64 raw_event_mask; + u64 perf_metrics; struct kvm_pmc gp_counters[KVM_MAX_NR_GP_COUNTERS]; struct kvm_pmc fixed_counters[KVM_MAX_NR_FIXED_COUNTERS]; =20 diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-in= dex.h index 18c4be75e927..fdcaeb6c8352 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -331,6 +331,7 @@ #define PERF_CAP_PEBS_FORMAT 0xf00 #define PERF_CAP_FW_WRITES BIT_ULL(13) #define PERF_CAP_PEBS_BASELINE BIT_ULL(14) +#define PERF_CAP_PERF_METRICS BIT_ULL(15) #define PERF_CAP_PEBS_TIMING_INFO BIT_ULL(17) #define PERF_CAP_PEBS_MASK (PERF_CAP_PEBS_TRAP | PERF_CAP_ARCH_REG | \ PERF_CAP_PEBS_FORMAT | PERF_CAP_PEBS_BASELINE | \ diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_= event.h index 1eb13673e889..bc2e1cbcd9b9 100644 --- a/arch/x86/include/asm/perf_event.h +++ b/arch/x86/include/asm/perf_event.h @@ -447,6 +447,7 @@ static inline bool is_topdown_idx(int idx) #define GLOBAL_STATUS_ARCH_PEBS_THRESHOLD_BIT 54 #define GLOBAL_STATUS_ARCH_PEBS_THRESHOLD BIT_ULL(GLOBAL_STATUS_ARCH_PEBS_= THRESHOLD_BIT) #define GLOBAL_STATUS_PERF_METRICS_OVF_BIT 48 +#define GLOBAL_STATUS_PERF_METRICS_OVF BIT_ULL(GLOBAL_STATUS_PERF_METRICS= _OVF_BIT) =20 #define GLOBAL_CTRL_EN_PERF_METRICS BIT_ULL(48) /* diff --git a/arch/x86/kvm/pmu.h b/arch/x86/kvm/pmu.h index 1b2f66a2e915..3066cade5790 100644 --- a/arch/x86/kvm/pmu.h +++ b/arch/x86/kvm/pmu.h @@ -279,6 +279,11 @@ static inline u64 kvm_vcpu_get_perf_caps(struct kvm_vc= pu *vcpu) return vcpu->arch.perf_capabilities; } =20 +static inline bool kvm_vcpu_has_perf_metrics(struct kvm_vcpu *vcpu) +{ + return kvm_vcpu_get_perf_caps(vcpu) & PERF_CAP_PERF_METRICS; +} + void kvm_pmu_deliver_pmi(struct kvm_vcpu *vcpu); int kvm_pmu_rdpmc(struct kvm_vcpu *vcpu, unsigned pmc, u64 *data); int kvm_pmu_check_rdpmc_early(struct kvm_vcpu *vcpu, unsigned int idx); diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c index 8171265df684..f54d1610df76 100644 --- a/arch/x86/kvm/vmx/pmu_intel.c +++ b/arch/x86/kvm/vmx/pmu_intel.c @@ -188,6 +188,8 @@ static bool intel_is_valid_msr(struct kvm_vcpu *vcpu, u= 32 msr) switch (msr) { case MSR_CORE_PERF_FIXED_CTR_CTRL: return kvm_pmu_has_perf_global_ctrl(pmu); + case MSR_PERF_METRICS: + return kvm_vcpu_has_perf_metrics(vcpu); case MSR_IA32_PEBS_ENABLE: ret =3D kvm_vcpu_get_perf_caps(vcpu) & PERF_CAP_PEBS_FORMAT; break; @@ -345,6 +347,9 @@ static int intel_pmu_get_msr(struct kvm_vcpu *vcpu, str= uct msr_data *msr_info) case MSR_CORE_PERF_FIXED_CTR_CTRL: msr_info->data =3D pmu->fixed_ctr_ctrl; break; + case MSR_PERF_METRICS: + msr_info->data =3D pmu->perf_metrics; + break; case MSR_IA32_PEBS_ENABLE: msr_info->data =3D pmu->pebs_enable; break; @@ -394,6 +399,13 @@ static int intel_pmu_set_msr(struct kvm_vcpu *vcpu, st= ruct msr_data *msr_info) if (pmu->fixed_ctr_ctrl !=3D data) reprogram_fixed_counters(pmu, data); break; + case MSR_PERF_METRICS: + /* + * If TMA level 2 is not supported, bits [63:32] are reserved + * and ignored on write, so no validation is needed here. + */ + pmu->perf_metrics =3D data; + break; case MSR_IA32_PEBS_ENABLE: if (data & pmu->pebs_enable_rsvd) return 1; @@ -589,6 +601,11 @@ static void intel_pmu_refresh(struct kvm_vcpu *vcpu) pmu->global_status_rsvd &=3D ~MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI; =20 + if (perf_capabilities & PERF_CAP_PERF_METRICS) { + pmu->global_ctrl_rsvd &=3D ~GLOBAL_CTRL_EN_PERF_METRICS; + pmu->global_status_rsvd &=3D ~GLOBAL_STATUS_PERF_METRICS_OVF; + } + if (perf_capabilities & PERF_CAP_PEBS_FORMAT) { if (perf_capabilities & PERF_CAP_PEBS_BASELINE) { pmu->pebs_enable_rsvd =3D counter_rsvd; @@ -632,6 +649,9 @@ static void intel_pmu_init(struct kvm_vcpu *vcpu) =20 static void intel_pmu_reset(struct kvm_vcpu *vcpu) { + struct kvm_pmu *pmu =3D vcpu_to_pmu(vcpu); + + pmu->perf_metrics =3D 0; intel_pmu_release_guest_lbr_event(vcpu); } =20 @@ -803,6 +823,9 @@ static void intel_mediated_pmu_load(struct kvm_vcpu *vc= pu) struct kvm_pmu *pmu =3D vcpu_to_pmu(vcpu); u64 global_status, toggle; =20 + if (kvm_vcpu_has_perf_metrics(vcpu)) + wrmsrq(MSR_PERF_METRICS, pmu->perf_metrics); + rdmsrq(MSR_CORE_PERF_GLOBAL_STATUS, global_status); toggle =3D pmu->global_status ^ global_status; if (global_status & toggle) @@ -831,6 +854,12 @@ static void intel_mediated_pmu_put(struct kvm_vcpu *vc= pu) */ if (pmu->fixed_ctr_ctrl_hw) wrmsrq(MSR_CORE_PERF_FIXED_CTR_CTRL, 0); + + if (kvm_vcpu_has_perf_metrics(vcpu)) { + pmu->perf_metrics =3D rdpmc(INTEL_PMC_FIXED_RDPMC_METRICS); + if (pmu->perf_metrics) + wrmsrq(MSR_PERF_METRICS, 0); + } } =20 struct kvm_pmu_ops intel_pmu_ops __initdata =3D { diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index a1a5edb39a7e..82df75f91e46 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -4260,6 +4260,10 @@ static void vmx_recalc_pmu_msr_intercepts(struct kvm= _vcpu *vcpu) MSR_TYPE_RW, intercept); vmx_set_intercept_for_msr(vcpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, MSR_TYPE_RW, intercept); + + intercept =3D !has_mediated_pmu || !kvm_vcpu_has_perf_metrics(vcpu); + vmx_set_intercept_for_msr(vcpu, MSR_PERF_METRICS, + MSR_TYPE_RW, intercept); } =20 static void vmx_recalc_msr_intercepts(struct kvm_vcpu *vcpu) @@ -8084,6 +8088,9 @@ static __init u64 vmx_get_perf_capabilities(void) perf_cap &=3D ~PERF_CAP_PEBS_BASELINE; } =20 + if (enable_mediated_pmu) + perf_cap |=3D kvm_host.perf_capabilities & PERF_CAP_PERF_METRICS; + return perf_cap; } =20 diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index e872398c12fc..9623f558f359 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -352,7 +352,7 @@ static const u32 msrs_to_save_pmu[] =3D { MSR_ARCH_PERFMON_FIXED_CTR0, MSR_ARCH_PERFMON_FIXED_CTR1, MSR_ARCH_PERFMON_FIXED_CTR2, MSR_ARCH_PERFMON_FIXED_CTR3, MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_CORE_PERF_GLOBAL_STATUS, - MSR_CORE_PERF_GLOBAL_CTRL, + MSR_CORE_PERF_GLOBAL_CTRL, MSR_PERF_METRICS, MSR_IA32_PEBS_ENABLE, MSR_IA32_DS_AREA, MSR_PEBS_DATA_CFG, =20 /* This part of MSRs should match KVM_MAX_NR_INTEL_GP_COUNTERS. */ @@ -7679,6 +7679,10 @@ static void kvm_probe_msr_to_save(u32 msr_index) intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2)) return; break; + case MSR_PERF_METRICS: + if (!(kvm_caps.supported_perf_cap & PERF_CAP_PERF_METRICS)) + return; + break; case MSR_ARCH_PERFMON_PERFCTR0 ... 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For example, if the host supports PERF_METRICS but it is not configured to the guest, KVM can use it to determine that RDPMC accesses must be intercepted. Signed-off-by: Mingwei Zhang Signed-off-by: Zide Chen --- v5: new patch. --- arch/x86/kvm/vmx/vmx.c | 8 ++------ arch/x86/kvm/x86.c | 4 ++++ arch/x86/kvm/x86.h | 1 + 3 files changed, 7 insertions(+), 6 deletions(-) diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index 82df75f91e46..40d41c83ca42 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -8039,14 +8039,10 @@ void vmx_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu) static __init u64 vmx_get_perf_capabilities(void) { u64 perf_cap =3D PERF_CAP_FW_WRITES; - u64 host_perf_cap =3D 0; =20 if (!enable_pmu) return 0; =20 - if (boot_cpu_has(X86_FEATURE_PDCM)) - rdmsrq(MSR_IA32_PERF_CAPABILITIES, host_perf_cap); - if (!cpu_feature_enabled(X86_FEATURE_ARCH_LBR) && !enable_mediated_pmu) { x86_perf_get_lbr(&vmx_lbr_caps); @@ -8059,11 +8055,11 @@ static __init u64 vmx_get_perf_capabilities(void) if (!vmx_lbr_caps.has_callstack) memset(&vmx_lbr_caps, 0, sizeof(vmx_lbr_caps)); else if (vmx_lbr_caps.nr) - perf_cap |=3D host_perf_cap & PERF_CAP_LBR_FMT; + perf_cap |=3D kvm_host.perf_capabilities & PERF_CAP_LBR_FMT; } =20 if (vmx_pebs_supported()) { - perf_cap |=3D host_perf_cap & PERF_CAP_PEBS_MASK; + perf_cap |=3D kvm_host.perf_capabilities & PERF_CAP_PEBS_MASK; =20 /* * Disallow adaptive PEBS as it is functionally broken, can be diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 9623f558f359..18afbf00d17b 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -10148,6 +10148,10 @@ int kvm_x86_vendor_init(struct kvm_x86_init_ops *o= ps) if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) rdmsrq(MSR_IA32_ARCH_CAPABILITIES, kvm_host.arch_capabilities); =20 + if (boot_cpu_has(X86_FEATURE_PDCM)) + rdmsrq_safe(MSR_IA32_PERF_CAPABILITIES, + &kvm_host.perf_capabilities); + WARN_ON_ONCE(kvm_nr_uret_msrs); =20 r =3D ops->hardware_setup(); diff --git a/arch/x86/kvm/x86.h b/arch/x86/kvm/x86.h index 9de577ef9c97..74487f36d099 100644 --- a/arch/x86/kvm/x86.h +++ b/arch/x86/kvm/x86.h @@ -52,6 +52,7 @@ struct kvm_host_values { u64 xss; u64 s_cet; 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24 Jun 2026 20:54:52 -0700 From: Zide Chen To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Jim Mattson , Mingwei Zhang , Zide Chen , Das Sandipan , Shukla Manali , Dapeng Mi , Falcon Thomas , Xudong Hao Subject: [PATCH V5 6/7] KVM: x86/pmu: Emulate RDPMC on performance metrics Date: Wed, 24 Jun 2026 20:45:54 -0700 Message-ID: <20260625034555.141453-7-zide.chen@intel.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260625034555.141453-1-zide.chen@intel.com> References: <20260625034555.141453-1-zide.chen@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" If the host has the PERF_METRICS capability but it's not present on the guest, RDPMC interception must be enabled and KVM should inject an #GP when the guest attempts to read it. If the guest has PERF_METRICS, but RDPMC interception is enabled for other reasons, KVM needs to emulate RDPMC with type 2000H. For simplicity, Metrics Clear Mode is not supported. Signed-off-by: Zide Chen --- v5: new patch. --- arch/x86/kvm/pmu.c | 30 ++++++++++++++++++++++++++---- 1 file changed, 26 insertions(+), 4 deletions(-) diff --git a/arch/x86/kvm/pmu.c b/arch/x86/kvm/pmu.c index 7aafc5db1346..af5b14f44e4b 100644 --- a/arch/x86/kvm/pmu.c +++ b/arch/x86/kvm/pmu.c @@ -755,6 +755,16 @@ static int kvm_pmu_rdpmc_vmware(struct kvm_vcpu *vcpu,= unsigned idx, u64 *data) return 0; } =20 +static int kvm_pmu_rdpmc_metrics(struct kvm_vcpu *vcpu, + unsigned idx, u64 *data) +{ + if (!kvm_vcpu_has_perf_metrics(vcpu)) + return 1; + + *data =3D vcpu_to_pmu(vcpu)->perf_metrics; + return 0; +} + int kvm_pmu_rdpmc(struct kvm_vcpu *vcpu, unsigned idx, u64 *data) { struct kvm_pmu *pmu =3D vcpu_to_pmu(vcpu); @@ -767,15 +777,18 @@ int kvm_pmu_rdpmc(struct kvm_vcpu *vcpu, unsigned idx= , u64 *data) if (is_vmware_backdoor_pmc(idx)) return kvm_pmu_rdpmc_vmware(vcpu, idx, data); =20 - pmc =3D kvm_pmu_call(rdpmc_ecx_to_pmc)(vcpu, idx, &mask); - if (!pmc) - return 1; - if (!kvm_is_cr4_bit_set(vcpu, X86_CR4_PCE) && (kvm_x86_call(get_cpl)(vcpu) !=3D 0) && kvm_is_cr0_bit_set(vcpu, X86_CR0_PE)) return 1; =20 + if (idx & INTEL_PMC_FIXED_RDPMC_METRICS) + return kvm_pmu_rdpmc_metrics(vcpu, idx, data); + + pmc =3D kvm_pmu_call(rdpmc_ecx_to_pmc)(vcpu, idx, &mask); + if (!pmc) + return 1; + *data =3D pmc_read_counter(pmc) & mask; return 0; } @@ -803,6 +816,14 @@ bool kvm_need_perf_global_ctrl_intercept(struct kvm_vc= pu *vcpu) } EXPORT_SYMBOL_FOR_KVM_INTERNAL(kvm_need_perf_global_ctrl_intercept); =20 +static bool kvm_need_perf_metrics_intercept(struct kvm_vcpu *vcpu) +{ + if (!(kvm_host.perf_capabilities & PERF_CAP_PERF_METRICS)) + return false; + + return !kvm_vcpu_has_perf_metrics(vcpu); +} + bool kvm_need_rdpmc_intercept(struct kvm_vcpu *vcpu) { struct kvm_pmu *pmu =3D vcpu_to_pmu(vcpu); @@ -815,6 +836,7 @@ bool kvm_need_rdpmc_intercept(struct kvm_vcpu *vcpu) return true; =20 return kvm_need_any_pmc_intercept(vcpu) || + kvm_need_perf_metrics_intercept(vcpu) || pmu->counter_bitmask[KVM_PMC_GP] !=3D (BIT_ULL(kvm_host_pmu.bit_wi= dth_gp) - 1) || pmu->counter_bitmask[KVM_PMC_FIXED] !=3D (BIT_ULL(kvm_host_pmu.bit= _width_fixed) - 1); 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X-CSE-ConnectionGUID: Co/GPT4LSUGZViotyucCFA== X-CSE-MsgGUID: KuJ8nAKYTlCBZdOz1PHA7g== X-IronPort-AV: E=McAfee;i="6800,10657,11827"; a="82901477" X-IronPort-AV: E=Sophos;i="6.24,223,1774335600"; d="scan'208";a="82901477" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by orvoesa112.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Jun 2026 20:54:53 -0700 X-CSE-ConnectionGUID: WvbFgzDYQq2Ov4Aw9o3LSw== X-CSE-MsgGUID: 4t+NZs6WRj25Ra2sI5zm1w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,223,1774335600"; d="scan'208";a="288396632" Received: from 9cc2c43eec6b.jf.intel.com ([10.54.77.29]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Jun 2026 20:54:52 -0700 From: Zide Chen To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Jim Mattson , Mingwei Zhang , Zide Chen , Das Sandipan , Shukla Manali , Dapeng Mi , Falcon Thomas , Xudong Hao Subject: [PATCH V5 7/7] KVM: selftests: Add perf_metrics and fixed counter 3 tests Date: Wed, 24 Jun 2026 20:45:55 -0700 Message-ID: <20260625034555.141453-8-zide.chen@intel.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260625034555.141453-1-zide.chen@intel.com> References: <20260625034555.141453-1-zide.chen@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a test case to exercise IA32_PERF_METRICS, i.e. architectural support for Topdown (TMA) Level 1 metrics, enumerated by IA32_PERF_CAPABILITIES[15]. Only check for non-zero metrics, as they are derived and depend on the workload, CPU model, and host scheduling, making precise expectations fragile. Extend the PMU selftest to cover Intel fixed counter 3 by bumping MAX_NR_FIXED_COUNTERS to 4 and validating basic functionality. Signed-off-by: Zide Chen --- v3: - Slightly reword comment to explain the sum of topdown metrics is close to 100%. - Change abs() with explicit bounds (sum >=3D 0xfd && sum <=3D 0x102) for better readability. v2: - New patch. --- --- tools/arch/x86/include/asm/msr-index.h | 1 + tools/testing/selftests/kvm/include/x86/pmu.h | 3 + .../selftests/kvm/x86/pmu_counters_test.c | 72 +++++++++++++++++-- 3 files changed, 71 insertions(+), 5 deletions(-) diff --git a/tools/arch/x86/include/asm/msr-index.h b/tools/arch/x86/includ= e/asm/msr-index.h index eff29645719b..e7745e2cd543 100644 --- a/tools/arch/x86/include/asm/msr-index.h +++ b/tools/arch/x86/include/asm/msr-index.h @@ -331,6 +331,7 @@ #define PERF_CAP_PEBS_FORMAT 0xf00 #define PERF_CAP_FW_WRITES BIT_ULL(13) #define PERF_CAP_PEBS_BASELINE BIT_ULL(14) +#define PERF_CAP_PERF_METRICS BIT_ULL(15) #define PERF_CAP_PEBS_TIMING_INFO BIT_ULL(17) #define PERF_CAP_PEBS_MASK (PERF_CAP_PEBS_TRAP | PERF_CAP_ARCH_REG | \ PERF_CAP_PEBS_FORMAT | PERF_CAP_PEBS_BASELINE | \ diff --git a/tools/testing/selftests/kvm/include/x86/pmu.h b/tools/testing/= selftests/kvm/include/x86/pmu.h index 608ed83d7c6a..6c19503e0bb7 100644 --- a/tools/testing/selftests/kvm/include/x86/pmu.h +++ b/tools/testing/selftests/kvm/include/x86/pmu.h @@ -52,6 +52,9 @@ /* Fixed PMC controls, Intel only. */ #define FIXED_PMC_GLOBAL_CTRL_ENABLE(_idx) BIT_ULL((32 + (_idx))) =20 +/* PERF_METRICS enable, Intel only. */ +#define PERF_METRICS_GLOBAL_CTRL_ENABLE BIT_ULL(48) + #define FIXED_PMC_KERNEL BIT_ULL(0) #define FIXED_PMC_USER BIT_ULL(1) #define FIXED_PMC_ANYTHREAD BIT_ULL(2) diff --git a/tools/testing/selftests/kvm/x86/pmu_counters_test.c b/tools/te= sting/selftests/kvm/x86/pmu_counters_test.c index dc6afac3aa91..db5ec222ef9e 100644 --- a/tools/testing/selftests/kvm/x86/pmu_counters_test.c +++ b/tools/testing/selftests/kvm/x86/pmu_counters_test.c @@ -6,6 +6,7 @@ =20 #include "pmu.h" #include "processor.h" +#include =20 /* Number of iterations of the loop for the guest measurement payload. */ #define NUM_LOOPS 10 @@ -241,17 +242,20 @@ do { \ ); \ } while (0) =20 -#define GUEST_TEST_EVENT(_idx, _pmc, _pmc_msr, _ctrl_msr, _value, FEP) \ +#define GUEST_RUN_PAYLOAD(_ctrl_msr, _value, FEP) \ do { \ - wrmsr(_pmc_msr, 0); \ - \ if (this_cpu_has(X86_FEATURE_CLFLUSHOPT)) \ GUEST_MEASURE_EVENT(_ctrl_msr, _value, "clflushopt %[m]", FEP); \ else if (this_cpu_has(X86_FEATURE_CLFLUSH)) \ GUEST_MEASURE_EVENT(_ctrl_msr, _value, "clflush %[m]", FEP); \ else \ GUEST_MEASURE_EVENT(_ctrl_msr, _value, "nop", FEP); \ - \ +} while (0) + +#define GUEST_TEST_EVENT(_idx, _pmc, _pmc_msr, _ctrl_msr, _value, FEP) \ +do { \ + wrmsr(_pmc_msr, 0); \ + GUEST_RUN_PAYLOAD(_ctrl_msr, _value, FEP); \ guest_assert_event_count(_idx, _pmc, _pmc_msr); \ } while (0) =20 @@ -318,6 +322,56 @@ static void guest_test_arch_event(u8 idx) FIXED_PMC_GLOBAL_CTRL_ENABLE(i)); } =20 +static void guest_test_perf_metrics(void) +{ + int retiring, bad_spec, fe_bound, be_bound, sum; + u64 global_ctrl, metrics; + + if ((guest_get_pmu_version() < 2) || /* Does guest have GLOBAL_CTRL? */ + !this_cpu_has(X86_FEATURE_PDCM) || + !(rdmsr(MSR_IA32_PERF_CAPABILITIES) & PERF_CAP_PERF_METRICS)) + return; + + wrmsr(MSR_CORE_PERF_GLOBAL_CTRL, 0); + wrmsr(MSR_CORE_PERF_FIXED_CTR3, 0); + wrmsr(MSR_PERF_METRICS, 0); + + /* Enable fixed ctr3 (TOPDOWN.SLOTS) and PERF_METRICS. */ + wrmsr(MSR_CORE_PERF_FIXED_CTR_CTRL, FIXED_PMC_CTRL(3, FIXED_PMC_KERNEL)); + global_ctrl =3D FIXED_PMC_GLOBAL_CTRL_ENABLE(3) | + PERF_METRICS_GLOBAL_CTRL_ENABLE; + + GUEST_RUN_PAYLOAD(MSR_CORE_PERF_GLOBAL_CTRL, global_ctrl, ""); + + /* Check test results. */ + metrics =3D rdmsr(MSR_PERF_METRICS); + retiring =3D FIELD_GET(GENMASK_ULL(7, 0), metrics); + bad_spec =3D FIELD_GET(GENMASK_ULL(15, 8), metrics); + fe_bound =3D FIELD_GET(GENMASK_ULL(23, 16), metrics); + be_bound =3D FIELD_GET(GENMASK_ULL(31, 24), metrics); + + /* + * Be conservative: the measured payload definitely retires work, so + * Retiring should be non-zero. + */ + GUEST_ASSERT_NE(metrics, 0ULL); + GUEST_ASSERT_NE(retiring, 0ULL); + + /* + * The sum of the 4 level-1 topdown metrics should be close to 100%. + * 3 is chosen as a loose sanity check. + */ + sum =3D retiring + bad_spec + fe_bound + be_bound; + GUEST_ASSERT(sum >=3D 0xfd && sum <=3D 0x101); + + /* Sanity check after PERF_METRICS disabled. */ + __asm__ __volatile__("loop ." : "+c"((int){NUM_LOOPS})); + GUEST_ASSERT_EQ(rdmsr(MSR_PERF_METRICS), metrics); + wrmsr(MSR_PERF_METRICS, 0xdeaddead); + + GUEST_ASSERT_EQ(rdmsr(MSR_PERF_METRICS), 0xdeaddead); +} + static void guest_test_arch_events(void) { u8 i; @@ -325,6 +379,8 @@ static void guest_test_arch_events(void) for (i =3D 0; i < NR_INTEL_ARCH_EVENTS; i++) guest_test_arch_event(i); =20 + guest_test_perf_metrics(); + GUEST_DONE(); } =20 @@ -361,7 +417,7 @@ static void test_arch_events(u8 pmu_version, u64 perf_c= apabilities, * other than PMCs in the future. */ #define MAX_NR_GP_COUNTERS 8 -#define MAX_NR_FIXED_COUNTERS 3 +#define MAX_NR_FIXED_COUNTERS 4 =20 #define GUEST_ASSERT_PMC_MSR_ACCESS(insn, msr, expect_gp, vector) \ __GUEST_ASSERT(expect_gp ? vector =3D=3D GP_VECTOR : !vector, \ @@ -585,6 +641,7 @@ static void test_intel_counters(void) u8 nr_fixed_counters =3D kvm_cpu_property(X86_PROPERTY_PMU_NR_FIXED_COUNT= ERS); u8 nr_gp_counters =3D kvm_cpu_property(X86_PROPERTY_PMU_NR_GP_COUNTERS); u8 pmu_version =3D kvm_cpu_property(X86_PROPERTY_PMU_VERSION); + u64 advertised_perf_caps =3D kvm_get_feature_msr(MSR_IA32_PERF_CAPABILITI= ES); unsigned int i; u8 v, j; u32 k; @@ -592,6 +649,7 @@ static void test_intel_counters(void) const u64 perf_caps[] =3D { 0, PMU_CAP_FW_WRITES, + PERF_CAP_PERF_METRICS, }; =20 /* @@ -649,6 +707,10 @@ static void test_intel_counters(void) if (!kvm_has_perf_caps && perf_caps[i]) continue; =20 + /* Ignore unsupported features. */ + if (perf_caps[i] & ~advertised_perf_caps) + continue; + pr_info("Testing arch events, PMU version %u, perf_caps =3D %lx\n", v, perf_caps[i]); =20 --=20 2.54.0