From nobody Sun Jun 28 10:37:02 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6FF0B346E5D for ; Thu, 25 Jun 2026 10:46:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782384389; cv=none; b=LGpEop/u5TXgghaWZWNaBKOz+8PQnyIU6RPyL6WwxliFxpVqxpZrME6YAj2JOK0iVRlTkYuTz7tiK1ggfvfcWB0y4h5mVgdjk7YMwPfGrUlTLPKeGj9BRv9S98Os7MD4Brntuzi2vIKKAUXCf38qWWjgIJ/FIfmfPiOlnrN7LL0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782384389; c=relaxed/simple; bh=2qv5ewq1ayMiwA7pIPcW1bE63RIRPVWk501yvyFDS5Y=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=LlHJFGqVVVysLB8c5cTZ8u6rk1CrN2015JtqlKa1NwQ4pEqfkMrFaHLP3grdmh0OfNxy8EVjBjWqkImtyLmUpek1WeHHMiPv/GCRzSjXL34ltURHoItzvvMSRmOU0UvzSsJ2smx7403zYE8Fx+ae5u5rfQtNz19c2jYqPT9BTj4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=p2vlIuEF; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=ce5PXpFn; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="p2vlIuEF"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="ce5PXpFn" Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 65P9jucg1753859 for ; Thu, 25 Jun 2026 10:46:27 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= Og8dUuxYfUI8iPCT4BbZaBKBzGWQaRRs4BGixtCQHqI=; b=p2vlIuEFK//7zrsL WruckMQiBkDEmLxwbQzmmfXGIGL5YOMMjWUSo+i+xpaX91ShoIoUGVXvevgXGeLD cIXFyN66VSv22T4lID2FK94VHbBkoJhf10M9BIbcrJcqiVXS9lJxUTPzebq3BwSi hCqycZ7QJy/cTuk15n/eoNiBUV5l24kQf+IcD5fQ4ILiSZmvuwx8XyfbBLpMqCT1 WXlhrLNGD6I0RF/534OGWzZ49z0KfeaA8hsNK36vvdxh3gjpRAMv+1XIIe/GCzA5 Uvl4+4BBns9OuUe/jHGFHQg1JfC6ySV8R5GlXwnYnd/qkNSMVpPDvwhrHIGDR+3i nJQmjw== Received: from mail-pl1-f199.google.com (mail-pl1-f199.google.com [209.85.214.199]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4f0w0q1duv-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Thu, 25 Jun 2026 10:46:27 +0000 (GMT) Received: by mail-pl1-f199.google.com with SMTP id d9443c01a7336-2c7e921550fso18401645ad.1 for ; Thu, 25 Jun 2026 03:46:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1782384386; x=1782989186; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=Og8dUuxYfUI8iPCT4BbZaBKBzGWQaRRs4BGixtCQHqI=; b=ce5PXpFnhxJv1iEDZNeYKvvWWCFo1QwKpoupPnK3SCPbNCZp+0vrvWJgiVk/xnQiIP qh23IIaSWKiuGyWA35BRQMCMy6m/tDQIbhb+ZNLloDsEkKoQcx/8ikCj4dJIdbeBGPb+ XT+7TXo+DKaOVoQMpnUrzzTF1MQ0RXycY25f3OPsAmneKDisasE34AusSmCMQULgnDKW 2pg35xxZJmtdPtrtorA4WP4j0N05r/wiTe1JuttAGolvIMCKBxZ5+aS4XIg4/ybfv3Pn sBPemVhaMS6wZscHI3OmcFlvWFNakH5W/MuoQ0lQ11KhdDAtyUN/ypBzK/wdml/6F9XE 0fdQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1782384386; x=1782989186; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=Og8dUuxYfUI8iPCT4BbZaBKBzGWQaRRs4BGixtCQHqI=; b=C/VG1MYjOG7wNS+LGxqUAIc8XhKsJguLonXqMP09gJW03snvBCCalsJqiqs0zRv3rA SV317srvCrPFFVx6sEFlGSssNlWH7Pf9r5DK1gJit8qxoHFlw9r974DGd0FGz871Mub0 LAl594mx7nMbDBYELyJSUddZLS4Ze9dXLrOQOuofyswVxHLO2aU7ZV37KFjFbMhYio8i 0W9npRsFlXg/18FGQvalGySFA2lN02KKqbEUeicmO+e0h3yKsvFZMBg6NI7Yv0CP7lzu 4aQUhUVFUskZkE/wT+HoxGPX0nQWeLLxMBHeYx7hAt0qapYotypEWY35irLrTG0pg3SZ p7Xg== X-Forwarded-Encrypted: i=1; AHgh+RrJkhxrB+c4/ZO/d9mQDV2DehIIbgZ2yq2I33HWG++pMpx5ZRFQ3y6yAOpRaQydJyHa+EJNeYF3tRGyjRU=@vger.kernel.org X-Gm-Message-State: AOJu0Yz9aM19aYS7yggxdGVoxCIitmBV9WoccvA08GSfkm7eyMhDHBtj qEsOTd7NMV8BMM876cevrwOIcnbQ7dv2/PmLW9Ka2UxOQJFDdcIjdplOkWiMqsB6j4uuGVmEpe/ nsJll8wtTmuFPub1taBVY5lEL2w+H9eqI/Ddka29yvIII7jDblXPJ+1aXjLZmBFO/92CsNT3xHU +JJQ== X-Gm-Gg: AfdE7ckH5YUcj1RQDFFdh9vAkSC2qxF13KpoWQxjLTR0PYBCRp6ImFTMzrVGV6V+4zH LvsQGvEUWLymoTmgfeMqkZ4V5ptXMEr4RH3MF75qVONL5MgxMwV/40W09tH4TQ4KaQiiDFOp4V+ aTLZMWs0+pTBNi3jaUxGx2Sl1a7ybdRMDZ1h6Svip5X9w8SBsW+oxYlCBzAP6KZhv6kxQGGAk5e zAD4AEZFz70AZ2UT3dNU8tXokeeMVyvT6QA/WYWI9+cdonoKwQjC7LUk9QZH8k/5PL0IjRHKRMW PufgfeOvidyWiMC95I0HdxzsCSGIz0Vdk57UpbFVIiUqkP5I6Ukbw5q1DroAbVyFNBfiLAC/JH8 +OgulVw+4Pvm3SGbp80o0VX/6OrKycCSzKbDS0jN+qqKuuerqe2k291ucl+Z+kyJw53EEVFx1IA == X-Received: by 2002:a17:903:2cb:b0:2c2:33a4:aaa2 with SMTP id d9443c01a7336-2c7fc9b9eeamr21454975ad.35.1782384386264; Thu, 25 Jun 2026 03:46:26 -0700 (PDT) X-Received: by 2002:a17:903:2cb:b0:2c2:33a4:aaa2 with SMTP id d9443c01a7336-2c7fc9b9eeamr21454685ad.35.1782384385785; Thu, 25 Jun 2026 03:46:25 -0700 (PDT) Received: from jiegan-gv.ap.qualcomm.com (tpe-colo-wan-fw-bordernet.qualcomm.com. [103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2c7f63d58e9sm17114035ad.60.2026.06.25.03.46.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Jun 2026 03:46:25 -0700 (PDT) From: Jie Gan Date: Thu, 25 Jun 2026 18:45:51 +0800 Subject: [PATCH v19 1/7] coresight: core: refactor ctcu_get_active_port and make it generic Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260625-enable-byte-cntr-for-ctcu-v19-1-8fbbf22e8381@oss.qualcomm.com> References: <20260625-enable-byte-cntr-for-ctcu-v19-0-8fbbf22e8381@oss.qualcomm.com> In-Reply-To: <20260625-enable-byte-cntr-for-ctcu-v19-0-8fbbf22e8381@oss.qualcomm.com> To: Suzuki K Poulose , Mike Leach , James Clark , Leo Yan , Alexander Shishkin , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Tingwei Zhang , Jie Gan , Bjorn Andersson , Konrad Dybcio , Yuanfang Zhang , Mao Jinlong Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Mike Leach X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1782384372; l=3815; i=jie.gan@oss.qualcomm.com; s=20250909; h=from:subject:message-id; bh=2qv5ewq1ayMiwA7pIPcW1bE63RIRPVWk501yvyFDS5Y=; b=3vlrcWFnAHSdC4q4HVI5kWl0yLxPjWU5FuOyiBV2dpVW3NmwTup+szP/owlmFgK2Y9EGCu8LL 0YhWZr56BubDg2VIYoeooe2EAPBVOOCGz3bihyEpTHrkLSe0+ocJyDB X-Developer-Key: i=jie.gan@oss.qualcomm.com; a=ed25519; pk=3LxxUZRPCNkvPDlWOvXfJNqNO4SfGdy3eghMb8puHuk= X-Proofpoint-ORIG-GUID: JYGd6Rm0H4xHk1F6wrHFl9Ly5BQLqrZR X-Proofpoint-Spam-Info: AW1haW4tMjYwNjI1MDA5MiBTYWx0ZWRfX4jzQy4IzO7a1 omUfVWZpa1Beoh9N+EXoqV1zK4FkGxUPi5zKbWUjnHgaE1jl4fxwZDQxtWSntiRwWLr/4BxsLYv vJYGubLuryASVcEhwg8xXRbx0asb/XU= X-Proofpoint-GUID: JYGd6Rm0H4xHk1F6wrHFl9Ly5BQLqrZR X-Authority-Analysis: v=2.4 cv=R6Ez39RX c=1 sm=1 tr=0 ts=6a3d0703 cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=KKAkSRfTAAAA:8 a=EUspDBNiAAAA:8 a=lyq7_Muqgj1vGRpOYO0A:9 a=QEXdDO2ut3YA:10 a=324X-CrmTo6CU4MGRt3R:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjI1MDA5MiBTYWx0ZWRfXz99GY5hi9czJ NfMDxqIFjSTTut8iMtncjixjdqejL5wz1fuacJq+DHoODwrTOMWiOMHEfz2Su/pa0X/g1XZ+5Lm Pcqy8Cc/fEKZb8R2GMrVhxxqc1d6LGoboW/SBF5Kb+C9pgiVUcVFxCNSGBMEGz07WYD63Kw41tO LdU09IlgQsPuke3LLcHFvVB+3/HbYL29z0a//GHDsCM/KL4q2JJhRsqbu3+08/+AMFFYF+TK2XU iK1EgHzWbwypjjYM0fWTw6waTT6RadKZ4pEhyWDAOBXcmKtwGAB38teiGKVxruCqYY5VsQSQ41o 1eWyIo0VVzH2yIGWA7nrDpnbxknpqmBd1Wjpo5ueisGcNRbfTJCOl1lzJf7RgePmyyGZf7m00t6 P75hFeR+/3/dPhL46LQZhKBYeJkKoG5Go/I+Bk2iPJBKT0RXlxc+L7+EV5nvpBSdgMMFPJeb8r6 68z9NnOK0ZfEZ/XXNQw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-25_01,2026-06-24_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 clxscore=1015 malwarescore=0 priorityscore=1501 adultscore=0 suspectscore=0 impostorscore=0 spamscore=0 lowpriorityscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2606250092 Remove ctcu_get_active_port from CTCU module and add it to the core framework. The port number is crucial for the CTCU device to identify which ETR it serves. With the port number we can correctly get required parameters of the CTCU device in TMC module. Reviewed-by: Mike Leach Signed-off-by: Jie Gan --- drivers/hwtracing/coresight/coresight-core.c | 27 +++++++++++++++++++= ++++ drivers/hwtracing/coresight/coresight-ctcu-core.c | 19 +--------------- drivers/hwtracing/coresight/coresight-priv.h | 2 ++ 3 files changed, 30 insertions(+), 18 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtraci= ng/coresight/coresight-core.c index 6d65c43d574f..7a7a85acdca0 100644 --- a/drivers/hwtracing/coresight/coresight-core.c +++ b/drivers/hwtracing/coresight/coresight-core.c @@ -773,6 +773,33 @@ struct coresight_device *coresight_get_sink(struct cor= esight_path *path) } EXPORT_SYMBOL_GPL(coresight_get_sink); =20 +/** + * coresight_get_in_port: Find the input port number at @remote where the = @csdev + * device is connected to. + * + * @csdev: csdev of the device. + * @remote: csdev of the remote device which is connected to @csdev. + * + * Return: port number upon success or -EINVAL for fail. + */ +int coresight_get_in_port(struct coresight_device *csdev, + struct coresight_device *remote) +{ + struct coresight_platform_data *pdata =3D remote->pdata; + int i; + + for (i =3D 0; i < pdata->nr_inconns; ++i) { + if (!pdata->in_conns[i]) + continue; + + if (pdata->in_conns[i]->src_dev =3D=3D csdev) + return pdata->in_conns[i]->dest_port; + } + + return -EINVAL; +} +EXPORT_SYMBOL_GPL(coresight_get_in_port); + u32 coresight_get_sink_id(struct coresight_device *csdev) { if (!csdev->ea) diff --git a/drivers/hwtracing/coresight/coresight-ctcu-core.c b/drivers/hw= tracing/coresight/coresight-ctcu-core.c index 9043cad42f01..e8720026c9e3 100644 --- a/drivers/hwtracing/coresight/coresight-ctcu-core.c +++ b/drivers/hwtracing/coresight/coresight-ctcu-core.c @@ -116,23 +116,6 @@ static int __ctcu_set_etr_traceid(struct coresight_dev= ice *csdev, u8 traceid, in return 0; } =20 -/* - * Searching the sink device from helper's view in case there are multiple= helper devices - * connected to the sink device. - */ -static int ctcu_get_active_port(struct coresight_device *sink, struct core= sight_device *helper) -{ - struct coresight_platform_data *pdata =3D helper->pdata; - int i; - - for (i =3D 0; i < pdata->nr_inconns; ++i) { - if (pdata->in_conns[i]->src_dev =3D=3D sink) - return pdata->in_conns[i]->dest_port; - } - - return -EINVAL; -} - static int ctcu_set_etr_traceid(struct coresight_device *csdev, struct cor= esight_path *path, bool enable) { @@ -145,7 +128,7 @@ static int ctcu_set_etr_traceid(struct coresight_device= *csdev, struct coresight return -EINVAL; } =20 - port_num =3D ctcu_get_active_port(sink, csdev); + port_num =3D coresight_get_in_port(sink, csdev); if (port_num < 0) return -EINVAL; =20 diff --git a/drivers/hwtracing/coresight/coresight-priv.h b/drivers/hwtraci= ng/coresight/coresight-priv.h index dddac946659f..854c0a3cb080 100644 --- a/drivers/hwtracing/coresight/coresight-priv.h +++ b/drivers/hwtracing/coresight/coresight-priv.h @@ -155,6 +155,8 @@ void coresight_remove_links(struct coresight_device *or= ig, u32 coresight_get_sink_id(struct coresight_device *csdev); int coresight_path_assign_trace_id(struct coresight_path *path, enum cs_mode mode); +int coresight_get_in_port(struct coresight_device *csdev, + struct coresight_device *remote); =20 #if IS_ENABLED(CONFIG_CORESIGHT_SOURCE_ETM3X) int etm_readl_cp14(u32 off, unsigned int *val); --=20 2.34.1 From nobody Sun Jun 28 10:37:02 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3F3C430F816 for ; Thu, 25 Jun 2026 10:46:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782384395; cv=none; b=Wds5TJ4b7IfVtH39WmU/l5CiwCz+n4BWgk/g4ITva+CCd3HXRvK4SUNQ+4L/w+iSJNJK7KMrVF2mFcEdxPWwAo1wk0oi522POS6sT/pulR5Q9TmLDPWhyO6ylOWkBTTc7R4wcta9ia9FxJazDK4QWgjSTaLYYoPDZPwsDidkVUQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782384395; c=relaxed/simple; bh=9EezabmICKllxnPSTbMv0/+FBj6ysKrEUMz0dUQTQTI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=oxZDwVmYTDJYndmSCqyCEsICSE5Y5S/3fA9xemBWHirnp15Kcn6pgJIfqEfsX3YpwYRxv34NPu1cQV6JmJ9OlGJI8PdqrOMqC8MImeWPmF1ijZKCHFLAgxxprQO9Szbm8Wff/aDWQ9VNkpM1LHuv0EcbBP3GRgYwqXyzAJYdqCg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=UpahMKRB; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=gEI6MQvx; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="UpahMKRB"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="gEI6MQvx" Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 65P9juPX1723340 for ; Thu, 25 Jun 2026 10:46:33 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= qkjyld+701iCJkcBnuuBcYNMLRsu6rC1sbHUZIe+tYI=; b=UpahMKRBhKE0Jbk7 7iFFbDjh6eck7v0y0FOKyFvfcv0LFtpAWw8G9Ue2SrV8JCoRARH6C7HdR2XRDAo/ Z4EaX0YLc33H9iO3dLY9jypQ8d9+w2iZtqBjsKMQZBvPkiDTCH/qCB+qNSGBSuUm HHzIjnHH+jkd5zzixMyJ/OVKCyrQIalWIWXK2lXtvvRmwEy/N/iW+KaS+duJF4Oc CElZkRVmSk8mW3or4FSB0nuqlL0xH3NaBsVW9cqzKfZHE3B+iiXnHcOeV49b/k44 QZllIckG17fQlRS4wtTVV5+rVIE6Wt8bmfk6FHshpXEIBBtgRf3aC8iaRXcyEGuW Rkmq6Q== Received: from mail-pl1-f199.google.com (mail-pl1-f199.google.com [209.85.214.199]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4f0j7duwjj-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Thu, 25 Jun 2026 10:46:33 +0000 (GMT) Received: by mail-pl1-f199.google.com with SMTP id d9443c01a7336-2c7fae22808so9189035ad.2 for ; Thu, 25 Jun 2026 03:46:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1782384392; x=1782989192; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=qkjyld+701iCJkcBnuuBcYNMLRsu6rC1sbHUZIe+tYI=; b=gEI6MQvx4zXirfS/vRCCd9/t3jlAV8N8e99UrPaB0o7eeaYD10mpx2viF40PKihDBT AMAlgv6unOOLSeVI0PjWQe2tXMitdpRDPT97PlS1aB6VA6Rjp7Deoe+sYpWG2uaE5d/T f1tiTSFx8U6klgmkK/d89CbdaIqCjdNftwhjI7nM9TTjdB3KW1pFDU5EvHMpvjTMSYJR wCTzjgSnVrYgalKR8bjwaqz//bWxI552mGhdYIvOM7GltkabNjWK0bis6QXD19Qyf6XL mzFIpT8sGpkXIXiUl2v5IBRmDeEqGSE23L3/eokMM77kRPNfsuqSU3k6HMXSVlqPiqWG X2lA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1782384392; x=1782989192; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=qkjyld+701iCJkcBnuuBcYNMLRsu6rC1sbHUZIe+tYI=; b=C70BZ8WXNJMTem7E2ZP4x7diJj/6UeZYz4tGOL6fxBhxwxH2UzhM0Yl7J3KtD8Re+9 nSCU+OS1lkTMyoZagxQNeVVHx/We25Jkdt+CA+AzN+cieCIKOltMaPubq36P0nCxThra jfGKxqoOpAUnZnQE6lKJtaH3xT7VfTeHy1Z+oRognEHhleogKyCckQZVCObjR2ZlQjhu gp3WE9GTgQzG8klbBLmMznG3uLG+E/22Ggzei/6ccG76lnWMitdX0Ixp3BCtv5QaJ0Hb 9LCF+/fEHT1yNnkcyMz+GRWR+2PC2xb2a98W/dn1LvzP03HI1HpN9HPYzPZZTo07LA1O ONyw== X-Forwarded-Encrypted: i=1; AHgh+RrqpAUi2Eu+JAWMJgzCp42pW+mnGb7TdofS7qj/jU9iJL3tnz7V0e6Eoptu4hyVZboqpMDTH2GXro4oZ9Y=@vger.kernel.org X-Gm-Message-State: AOJu0YzLATF5p2tlUT5Mo+n7fmvacGHCUuZfzkpZf9UsXlNy1GjY67d7 D8ASh29JgPXCrbuPYz/sOXxZg29t20e7bQHOfuqTMCuDL7QDTMkU0bWZdNdhXm0qB6cGTHFyStr rDBJ6Ao0ctHnEO8ALNmabzsnMrnvoHrqanI6n2OgjiNrhM5ar2cPDemjqvQaIm5TxmFvBNHoQIX CnPw== X-Gm-Gg: AfdE7ckelvbyf3kOsfo5btLP7b6RTsHrUXMlceVvMFIkX1fvg2RD3S44oMqQJa1LLxP 83UoH62c4dRDaVtS/t7A+kdjg4lpJmPzTP//yR+400GIfpEoG8bkhbD4VrqzgAVOjvnpZbzetmy ivDgxrdmhUxBKBX3qhH1FsfAHPJGQJUJYVAHCY9yagytH9ycQQJBHagjLwbDafEbChgwBci2bHP LNowq+acK5nDTJ3CRHAM+guvuNtOy6ZgsEcUYPfBdLRF5A+6pFVuTfIzltzETQEo7nYiVjeHuNW f7yGr0XcBwmggt51P+O/OaTu/m2tqNQM7DXUr9VVXKqD5R3uNqwYqIj+mnSrVvrRGti/aIIArQX k8AONE+j0NaZcQWKCqfyALNRkSTSK8Wx+KMfVB5ey1RzvSqJZAeqTYuFl0+c6ynpu+sQSrflIeA == X-Received: by 2002:a17:902:f681:b0:2c0:cb90:1dfc with SMTP id d9443c01a7336-2c7fc9eedf1mr20851685ad.12.1782384391915; Thu, 25 Jun 2026 03:46:31 -0700 (PDT) X-Received: by 2002:a17:902:f681:b0:2c0:cb90:1dfc with SMTP id d9443c01a7336-2c7fc9eedf1mr20851325ad.12.1782384391397; Thu, 25 Jun 2026 03:46:31 -0700 (PDT) Received: from jiegan-gv.ap.qualcomm.com (tpe-colo-wan-fw-bordernet.qualcomm.com. [103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2c7f63d58e9sm17114035ad.60.2026.06.25.03.46.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Jun 2026 03:46:31 -0700 (PDT) From: Jie Gan Date: Thu, 25 Jun 2026 18:45:52 +0800 Subject: [PATCH v19 2/7] coresight: tmc: add create/clean functions for etr_buf_list Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260625-enable-byte-cntr-for-ctcu-v19-2-8fbbf22e8381@oss.qualcomm.com> References: <20260625-enable-byte-cntr-for-ctcu-v19-0-8fbbf22e8381@oss.qualcomm.com> In-Reply-To: <20260625-enable-byte-cntr-for-ctcu-v19-0-8fbbf22e8381@oss.qualcomm.com> To: Suzuki K Poulose , Mike Leach , James Clark , Leo Yan , Alexander Shishkin , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Tingwei Zhang , Jie Gan , Bjorn Andersson , Konrad Dybcio , Yuanfang Zhang , Mao Jinlong Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Mike Leach X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1782384372; l=7649; i=jie.gan@oss.qualcomm.com; s=20250909; h=from:subject:message-id; bh=9EezabmICKllxnPSTbMv0/+FBj6ysKrEUMz0dUQTQTI=; b=1LmRdhr8uVlX7Vc805ZdGTqNtrE1gUymPtTdzVqNYrHsQqInykK2P0mFfoWdInF7GLHmDKilU xmtu+0reVpRAOJ5WCriGuc/gSdL/d95AECqwpWXsxuOOEud1ANPHZaM X-Developer-Key: i=jie.gan@oss.qualcomm.com; a=ed25519; pk=3LxxUZRPCNkvPDlWOvXfJNqNO4SfGdy3eghMb8puHuk= X-Proofpoint-GUID: -byH0N88uQjkurwV7C7pWcDZHOd3vO3p X-Authority-Analysis: v=2.4 cv=NvHhtcdJ c=1 sm=1 tr=0 ts=6a3d0709 cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=KKAkSRfTAAAA:8 a=EUspDBNiAAAA:8 a=wY6pATnJNnZAKtYNhpEA:9 a=QEXdDO2ut3YA:10 a=324X-CrmTo6CU4MGRt3R:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwNjI1MDA5MiBTYWx0ZWRfX92aXBWyDhfMx OOetDu9NYBKXMdwld28BaMSkW3X2cuW5cRNgAZBc1zF78YoWJEKN0VuA4y3vBsDybc3U9dgjaA7 UoJtSj64ZaOOJzDuhiu+58F7jIInIKI= X-Proofpoint-ORIG-GUID: -byH0N88uQjkurwV7C7pWcDZHOd3vO3p X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjI1MDA5MiBTYWx0ZWRfXzQcWLb4nDKfZ g/cWp1WaYDP+R4B2IbmjJ09YFh+B8yWZypOr2LA0vqad6210SuPHacWI2HyKfc9vLFzhD9IADeQ bIsncq5oWfM1nxUuEs0vdYZuBNYmeFuSKAe1U3Gu2yj+wLZIQlmgmU23HsiE9ljiDsX7aCnxVty 3C3nlrYMKouEhJzQOgMfcii85HxdTi2hfxwUh0uZgDUJm4r3xbSMd3l5VC76YqyWPn4ST0Ogb3k PGSOIm/13o+cfgT9u+CiCv+h8xV02fssfMlK9YTh8vDumTS1XyMLkA6Av4ALa4MJnGM8vmzLUxs mTFhCZK0DkxNYiVztCl1FtkOnsegPl93s96sydlMw+FAnXvepYyScOVreGmWZF4mGEYPKXR+Ldf xd8Ws1CvY7TxPqJym/WhwmrsTvXStEmoAV2yOct8G0yRvx6FEXIjkwAePdozBhHOP+NeX+D05UG FobMT8aJ4BgnHbqgqCA== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-25_01,2026-06-24_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 priorityscore=1501 suspectscore=0 adultscore=0 impostorscore=0 phishscore=0 spamscore=0 bulkscore=0 lowpriorityscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2606250092 Introduce functions for creating and inserting or removing the etr_buf_node to/from the etr_buf_list. The byte-cntr functionality requires two etr_buf to receive trace data. The active etr_buf collects the trace data from source device, while the byte-cntr reading function accesses the deactivated etr_buf after is has been filled and synced, transferring data to the userspace. Reviewed-by: Mike Leach Signed-off-by: Jie Gan --- drivers/hwtracing/coresight/coresight-tmc-core.c | 1 + drivers/hwtracing/coresight/coresight-tmc-etr.c | 126 +++++++++++++++++++= ++++ drivers/hwtracing/coresight/coresight-tmc.h | 17 +++ 3 files changed, 144 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwt= racing/coresight/coresight-tmc-core.c index bc5a133ada3e..bc7dd676da47 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-core.c +++ b/drivers/hwtracing/coresight/coresight-tmc-core.c @@ -835,6 +835,7 @@ static int __tmc_probe(struct device *dev, struct resou= rce *res) idr_init(&drvdata->idr); mutex_init(&drvdata->idr_mutex); dev_list =3D "tmc_etr"; + INIT_LIST_HEAD(&drvdata->etr_buf_list); break; case TMC_CONFIG_TYPE_ETF: desc.groups =3D coresight_etf_groups; diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtr= acing/coresight/coresight-tmc-etr.c index 361a433e6f0c..9b3ef73e9cf2 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -1918,6 +1918,132 @@ const struct coresight_ops tmc_etr_cs_ops =3D { .panic_ops =3D &tmc_etr_sync_ops, }; =20 +/** + * tmc_clean_etr_buf_list - clean the etr_buf_list. + * @drvdata: driver data of the TMC device. + * + * Remove all nodes from @drvdata->etr_buf_list and free their buffers. + * If a node holds the live sysfs_buf and the device is active, the node is + * removed but the buffer is not freed; ownership stays with drvdata->sysf= s_buf. + * + * Locking: callers must guarantee exclusive access to @drvdata->etr_buf_l= ist + * and must not hold @drvdata->spinlock. The spinlock is taken internally = only + * to serialise the @drvdata->sysfs_buf accesses against the ETR sink + * enable/disable paths. Must be called from process context: buffers are = freed + * with the lock released. + */ +void tmc_clean_etr_buf_list(struct tmc_drvdata *drvdata) +{ + struct etr_buf_node *nd, *next; + unsigned long flags; + + list_for_each_entry_safe(nd, next, &drvdata->etr_buf_list, link) { + raw_spin_lock_irqsave(&drvdata->spinlock, flags); + if (nd->sysfs_buf =3D=3D drvdata->sysfs_buf) { + if (coresight_get_mode(drvdata->csdev) !=3D CS_MODE_DISABLED) + /* + * The device is still active. Keep the live + * buffer owned by drvdata->sysfs_buf and only + * drop the list's reference to it. + */ + nd->sysfs_buf =3D NULL; + else + /* Free the buffer below through nd->sysfs_buf */ + drvdata->sysfs_buf =3D NULL; + } + raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); + + /* Free the buffer (NULL is ignored) and the node out of the lock */ + tmc_etr_free_sysfs_buf(nd->sysfs_buf); + list_del(&nd->link); + kfree(nd); + } +} +EXPORT_SYMBOL_GPL(tmc_clean_etr_buf_list); + +/** + * tmc_create_etr_buf_list - create a list to manage the etr_buf_node. + * @drvdata: driver data of the TMC device. + * @num_nodes: number of nodes want to create with the list. + * + * Locking: callers must guarantee exclusive access to @drvdata->etr_buf_l= ist + * and must not hold @drvdata->spinlock. The spinlock is taken internally = only + * to serialise the @drvdata->sysfs_buf accesses against the ETR sink + * enable/disable paths. Must be called from process context: buffers and = nodes + * are allocated with the lock released. + * + * Return 0 upon success and return the error number if fail. + */ +int tmc_create_etr_buf_list(struct tmc_drvdata *drvdata, int num_nodes) +{ + struct etr_buf_node *new_node; + struct etr_buf *sysfs_buf; + unsigned long flags; + int i =3D 0, ret =3D 0; + + /* We don't need a list if there is only one node */ + if (num_nodes < 2) + return -EINVAL; + + /* + * We expect that sysfs_buf in drvdata has already been allocated. + * Wrap the live sysfs_buf into the first node so the captured trace + * data is preserved. The list is owned by the caller, so no lock is + * needed to read sysfs_buf or to add the node here. + */ + if (drvdata->sysfs_buf) { + new_node =3D kzalloc_obj(*new_node, GFP_KERNEL); + if (!new_node) + return -ENOMEM; + + new_node->sysfs_buf =3D drvdata->sysfs_buf; + new_node->is_free =3D false; + list_add(&new_node->link, &drvdata->etr_buf_list); + i++; + } + + while (i < num_nodes) { + new_node =3D kzalloc_obj(*new_node, GFP_KERNEL); + if (!new_node) { + ret =3D -ENOMEM; + break; + } + + /* Allocate the buffer with the lock released */ + sysfs_buf =3D tmc_alloc_etr_buf(drvdata, drvdata->size, 0, cpu_to_node(0= ), NULL); + if (IS_ERR(sysfs_buf)) { + kfree(new_node); + ret =3D PTR_ERR(sysfs_buf); + break; + } + + new_node->sysfs_buf =3D sysfs_buf; + /* + * Only the drvdata->sysfs_buf write needs the spinlock, to + * serialise against the ETR sink enable/disable paths. + */ + raw_spin_lock_irqsave(&drvdata->spinlock, flags); + /* We don't have an available sysfs_buf in drvdata, set one up */ + if (!drvdata->sysfs_buf) { + drvdata->sysfs_buf =3D sysfs_buf; + new_node->is_free =3D false; + } else { + new_node->is_free =3D true; + } + raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); + + list_add_tail(&new_node->link, &drvdata->etr_buf_list); + i++; + } + + /* Clean the list if there is an error */ + if (ret) + tmc_clean_etr_buf_list(drvdata); + + return ret; +} +EXPORT_SYMBOL_GPL(tmc_create_etr_buf_list); + int tmc_read_prepare_etr(struct tmc_drvdata *drvdata) { int ret =3D 0; diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracin= g/coresight/coresight-tmc.h index 319a354ede9f..6e994678f926 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.h +++ b/drivers/hwtracing/coresight/coresight-tmc.h @@ -208,6 +208,19 @@ struct tmc_resrv_buf { s64 len; }; =20 +/** + * @sysfs_buf: Allocated sysfs_buf. + * @is_free: Indicates whether the buffer is free to choose. + * @pos: Offset to the start of the buffer. + * @link: list_head of the node. + */ +struct etr_buf_node { + struct etr_buf *sysfs_buf; + bool is_free; + loff_t pos; + struct list_head link; +}; + /** * struct tmc_drvdata - specifics associated to an TMC component * @atclk: optional clock for the core parts of the TMC. @@ -245,6 +258,7 @@ struct tmc_resrv_buf { * (after crash) by default. * @crash_mdata: Reserved memory for storing tmc crash metadata. * Used by ETR/ETF. + * @etr_buf_list: List that is used to manage allocated etr_buf. */ struct tmc_drvdata { struct clk *atclk; @@ -275,6 +289,7 @@ struct tmc_drvdata { struct etr_buf *perf_buf; struct tmc_resrv_buf resrv_buf; struct tmc_resrv_buf crash_mdata; + struct list_head etr_buf_list; }; =20 struct etr_buf_operations { @@ -447,5 +462,7 @@ struct etr_buf *tmc_etr_get_buffer(struct coresight_dev= ice *csdev, enum cs_mode mode, struct coresight_path *path); extern const struct attribute_group coresight_etr_group; +void tmc_clean_etr_buf_list(struct tmc_drvdata *drvdata); +int tmc_create_etr_buf_list(struct tmc_drvdata *drvdata, int num_nodes); =20 #endif --=20 2.34.1 From nobody Sun Jun 28 10:37:02 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DC147330675 for ; Thu, 25 Jun 2026 10:46:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782384401; cv=none; b=ElYXbksN6yN6ANhz/qgrjfsYGQ9UYs2NgV2ZLwQto1Ie7UKmcVbeZdB0G+1QCkKI1SEWN4tj4wpGnOTOZ4J+zUnTEOEEqrOtefK+NhqAvdlOGMTjIKyRn3NIbu05P00ptH+gXvQcJMsZkByHzfFyTOc8iAAG0+dhzdltw9tETgU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782384401; c=relaxed/simple; bh=tijaxrXD7Cb53GGSRhRGBOVQmb2AQTa3/Hi3VM9v7z0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=OlenvbqHmUZUtO8oO1Mvcz9hH5w2YmQphlm9WuWd9J9bG+NpyK4mz0+ZTps/8fzfBnbK1PeQCKcUb5Qkuy7WFfrKauBpeEWhwy7IPBRvasMBuS2mGtEkhNANfYnyFm8IN9ghV0VGzirjIyVs+LB1gwemI56deL0Q80WYX4FLC4E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=IAWvewx+; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=fkUPkpo2; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="IAWvewx+"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="fkUPkpo2" Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 65P9k9lG1948022 for ; Thu, 25 Jun 2026 10:46:38 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= C4m/o41K5fL/YEM2+crvUsuSSJz0c2LF9MIABocLHis=; b=IAWvewx+UfFggX59 QOup+8YviA4zd/pUe1HoM5Fhuq/KDSaOgDuQK3BbyKjQINnZD5SkKQt7DcZkf3CW DpzjOVpK7H/JK8Dhz5haHq62lXo5C1uJs17KOZVkjYqgJ18MJx54o2GI94IDLRW8 9L4XU2YPW8E7F0znMLhZ832Y6QAs44OmKjmLBx+Cl1tLSgMLDaUMMX6nkXMNZNWl iTT7I2GyBFvSX0Nk0sgWxN1F1G/XpiNPV6Q95Zmf57cV2jaoEZMZrylR1NNvuS7C WpCsijJYDgtgPk60aB1T/dt8PA7/hnOHH7EZCwqGn6um8U6Bq1c/JPCqwFJbVTX1 LGv4jA== Received: from mail-pl1-f198.google.com (mail-pl1-f198.google.com [209.85.214.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4f0ya8rxb2-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Thu, 25 Jun 2026 10:46:38 +0000 (GMT) Received: by mail-pl1-f198.google.com with SMTP id d9443c01a7336-2c6a9bbcc53so20711125ad.2 for ; Thu, 25 Jun 2026 03:46:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1782384398; x=1782989198; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=C4m/o41K5fL/YEM2+crvUsuSSJz0c2LF9MIABocLHis=; b=fkUPkpo2K2mXN5rUvdtewRoPj3KHl7vHZvgBNDFJKjhRYm9jBCK3lnBmZQO/ex30TD aGBJqNQEzBHHlknA0hfdweTGYf9vKDaqGJxrFJVpWzFRendCKp5BZrtElb9NRj1a+/Kd jvwr0JuPV3fw/6V2VYplroNLFCaLwuoenHgz+DhoRRTqy7h+BV91Ms/2DeWgTWN7VQYm ExDmJbFLLPETaR/imYpQvujvWgzwYmVWo2EpkGepx50TB/+nkughBIoun1m3Un6TBNd4 fMpEn4Mj99JKUGc80yTQoLHff5g+S5yGgRjeEInqKYvnEYrvs/3dULOMS58qB4Mhh9ua JQFg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1782384398; x=1782989198; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=C4m/o41K5fL/YEM2+crvUsuSSJz0c2LF9MIABocLHis=; b=pGI22aPrhk+qmCZdtczVqr/o8nosQlPzp8134pIjipV7aQGpxj8MyuXoaeXJNLzkRH WIS2nswlxEboBzp7voVfnA9nLKtq4ehttngkzjnZVvIIREgPX1QReKfY406uTLCWjpJM qF/AnSVTbsvH8Glebw8xdPnOTloIsyPWCR+Rjw9lR/4eOzAyE9iFzX2CkKOPZtmCEOAg +JAt2q16/w2+2vIwD2LHBJMahBJrGA2i78QXVp9PAQ6XP6S7OHpCpKDtl5jq2a1zXqaI BHeoDLtzBUul5Pnxfw+dOugtJfE5rZhsrim6mG1djEV2CmBWxIUt7Cvm1EDXydJg8Vii W56Q== X-Forwarded-Encrypted: i=1; AHgh+RqSlE2dwMnBf7Zwi6mPa7zm+G64hWKpkhwCuFC8Q6RPS2k4CA7Ut5dvgln9513quhHEnaMzIAgQ4ZgF+K4=@vger.kernel.org X-Gm-Message-State: AOJu0YyQmoT2z4LD/2o3GNR2iCsBY2dU65bz6RMnCOh1pr/abcspSp6i eeyLUf8hizdC8i03LQJSv35olR/BiMwvwshw/ewjYk9qCKkCo/vUdlAYxngkmx061maPIy4nPte H66PaHBcK0n5UOjL5ZfHwFdyJF/9V2F15rfMYS3G84c/239nbAQVHiG3nYRNwa8kVgSfnLGTY+m pOrA== X-Gm-Gg: AfdE7clD7noZafRSiu/w1V32Ml0vylCPXRNg+Zt6IlW1iUyuG1bvzF3+GhnmToYQzJG bFwFmLBHh5EmPXzVn7ZlD/m/1uUqgrA3Bot1bsZlI+EgWU4xQ703Bkb89U8w3jcsH85G7bImoQk 1xyg9361MBAZKFDe0gndPV9ngb5JFStTqfDjHeItvLy4zHaopDA3Gjt77eIFrsafWcnOwnWFXsm LnTL8co8Rz/FLB14xQ8pOQdOMQP1NiSv629AmXtI1HZNZNCuCbwDGaCiwMbrklpZDZQ/4rtfASb r+qiM54h7WVrvLZzTt4zsK2AgQOGC2X4VSEvG6zWOyBuI+hSFPbwxFVxn7HDe6wXFE1R98ukHaz CvspwPQhCbndGYf7q13vrX95RRv/P9iyy7MFnx/qGjFMc76ZVGpQt/e739CznmmFghHCfAQDmbA == X-Received: by 2002:a17:902:ffcb:b0:2c2:245a:3360 with SMTP id d9443c01a7336-2c7fc75a023mr22142855ad.6.1782384397647; Thu, 25 Jun 2026 03:46:37 -0700 (PDT) X-Received: by 2002:a17:902:ffcb:b0:2c2:245a:3360 with SMTP id d9443c01a7336-2c7fc75a023mr22142505ad.6.1782384397066; Thu, 25 Jun 2026 03:46:37 -0700 (PDT) Received: from jiegan-gv.ap.qualcomm.com (tpe-colo-wan-fw-bordernet.qualcomm.com. [103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2c7f63d58e9sm17114035ad.60.2026.06.25.03.46.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Jun 2026 03:46:36 -0700 (PDT) From: Jie Gan Date: Thu, 25 Jun 2026 18:45:53 +0800 Subject: [PATCH v19 3/7] coresight: tmc: introduce tmc_sysfs_ops to wrap sysfs read operations Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260625-enable-byte-cntr-for-ctcu-v19-3-8fbbf22e8381@oss.qualcomm.com> References: <20260625-enable-byte-cntr-for-ctcu-v19-0-8fbbf22e8381@oss.qualcomm.com> In-Reply-To: <20260625-enable-byte-cntr-for-ctcu-v19-0-8fbbf22e8381@oss.qualcomm.com> To: Suzuki K Poulose , Mike Leach , James Clark , Leo Yan , Alexander Shishkin , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Tingwei Zhang , Jie Gan , Bjorn Andersson , Konrad Dybcio , Yuanfang Zhang , Mao Jinlong Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Mike Leach X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1782384372; l=5200; i=jie.gan@oss.qualcomm.com; s=20250909; h=from:subject:message-id; bh=tijaxrXD7Cb53GGSRhRGBOVQmb2AQTa3/Hi3VM9v7z0=; b=mAH0BMPCvVpUPe3fys7XXrZMV0kBBjHQcALCqQixnnQY8J3MudGkw+q7Jh1fOiIi8sQK8Cp9/ AMvYYPUBqEUAsYKHF9x4A/F4a7D8MfQQEHmUBcguH4mjbIrcBpdaSPI X-Developer-Key: i=jie.gan@oss.qualcomm.com; a=ed25519; pk=3LxxUZRPCNkvPDlWOvXfJNqNO4SfGdy3eghMb8puHuk= X-Proofpoint-Spam-Info: AW1haW4tMjYwNjI1MDA5MiBTYWx0ZWRfX0AB0ldKX4s4X 7GrpfLLYzSXzwgwc6R3LUbgegMa4a9MDZz9/Vr8zwKr7lGfzs1zTtq5Pe9KquTAUsjhb80YgYUW XskxLlVBN5xC9Oe1nHeQeDP69Ih3NBk= X-Proofpoint-GUID: B2iAF6odXZmmr7U2HSKKaLh4xaVa5tWe X-Proofpoint-ORIG-GUID: B2iAF6odXZmmr7U2HSKKaLh4xaVa5tWe X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjI1MDA5MiBTYWx0ZWRfX/PtLqZFsr1Dh wVDsfn9tEy2b4LTIDhquOuHhMJ2Q7YFLhY7Q0Nd90YM4PxAiiS5uBNvmJDOtPvLbG4sSnTmSOKk orS5V5RfAki17DfXqsCCeRVOWaEj60XDCw1JcBC+G+rwAHk462h5Mdk6qMSMKs+rt1eUz87Ba+P RbHtiopD5A4kjev5GxlG6Z23gIXfdWHEgugSArBb8qggBjXhJkdifmsS/lwu38KMgUD4IBsuvUC DBZbj2VzaeJ0sT3XZbUweU6aWxOgwDvYSB2M6mbH6AyEuzI1uIjK3wPGcgeSZyO+k8GadjhXdej 7jVbF0Em9d9rj+hHuWDmbsT8TSBmsCyRk2k7H/Pef3OSGR+W20cV6IOcv3EeSFi3uLEF9s1ubMe zADLI6vuAFontab4nmgAXa5ce50o/zO5CigkyYr2jAI5NfIW8AjTvJGmm3ENuIW6MSirQ34+2zQ GK1Xg7St9K6LCkrQWmg== X-Authority-Analysis: v=2.4 cv=Z+Xc2nRA c=1 sm=1 tr=0 ts=6a3d070e cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=KKAkSRfTAAAA:8 a=EUspDBNiAAAA:8 a=ia3uihG--C1vaqsH_ucA:9 a=QEXdDO2ut3YA:10 a=GvdueXVYPmCkWapjIL-Q:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-25_01,2026-06-24_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 malwarescore=0 bulkscore=0 suspectscore=0 phishscore=0 spamscore=0 adultscore=0 lowpriorityscore=0 priorityscore=1501 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2606250092 Introduce tmc_sysfs_ops as a wrapper, wrap sysfs read operations, for reading trace data from the TMC buffer. Reviewed-by: Mike Leach Signed-off-by: Jie Gan --- drivers/hwtracing/coresight/coresight-tmc-core.c | 51 ++++++++++----------= ---- drivers/hwtracing/coresight/coresight-tmc.h | 15 +++++++ 2 files changed, 37 insertions(+), 29 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwt= racing/coresight/coresight-tmc-core.c index bc7dd676da47..4b40b692be4d 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-core.c +++ b/drivers/hwtracing/coresight/coresight-tmc-core.c @@ -228,17 +228,10 @@ static int tmc_read_prepare(struct tmc_drvdata *drvda= ta) { int ret =3D 0; =20 - switch (drvdata->config_type) { - case TMC_CONFIG_TYPE_ETB: - case TMC_CONFIG_TYPE_ETF: - ret =3D tmc_read_prepare_etb(drvdata); - break; - case TMC_CONFIG_TYPE_ETR: - ret =3D tmc_read_prepare_etr(drvdata); - break; - default: + if (drvdata->sysfs_ops) + ret =3D drvdata->sysfs_ops->read_prepare(drvdata); + else ret =3D -EINVAL; - } =20 if (!ret) dev_dbg(&drvdata->csdev->dev, "TMC read start\n"); @@ -250,17 +243,10 @@ static int tmc_read_unprepare(struct tmc_drvdata *drv= data) { int ret =3D 0; =20 - switch (drvdata->config_type) { - case TMC_CONFIG_TYPE_ETB: - case TMC_CONFIG_TYPE_ETF: - ret =3D tmc_read_unprepare_etb(drvdata); - break; - case TMC_CONFIG_TYPE_ETR: - ret =3D tmc_read_unprepare_etr(drvdata); - break; - default: + if (drvdata->sysfs_ops) + ret =3D drvdata->sysfs_ops->read_unprepare(drvdata); + else ret =3D -EINVAL; - } =20 if (!ret) dev_dbg(&drvdata->csdev->dev, "TMC read end\n"); @@ -287,15 +273,7 @@ static int tmc_open(struct inode *inode, struct file *= file) static ssize_t tmc_get_sysfs_trace(struct tmc_drvdata *drvdata, loff_t pos= , size_t len, char **bufpp) { - switch (drvdata->config_type) { - case TMC_CONFIG_TYPE_ETB: - case TMC_CONFIG_TYPE_ETF: - return tmc_etb_get_sysfs_trace(drvdata, pos, len, bufpp); - case TMC_CONFIG_TYPE_ETR: - return tmc_etr_get_sysfs_trace(drvdata, pos, len, bufpp); - } - - return -EINVAL; + return drvdata->sysfs_ops->get_trace_data(drvdata, pos, len, bufpp); } =20 static ssize_t tmc_read(struct file *file, char __user *data, size_t len, @@ -764,6 +742,18 @@ static void register_crash_dev_interface(struct tmc_dr= vdata *drvdata, "Valid crash tracedata found\n"); } =20 +static const struct tmc_sysfs_ops etb_sysfs_ops =3D { + .read_prepare =3D tmc_read_prepare_etb, + .read_unprepare =3D tmc_read_unprepare_etb, + .get_trace_data =3D tmc_etb_get_sysfs_trace, +}; + +static const struct tmc_sysfs_ops etr_sysfs_ops =3D { + .read_prepare =3D tmc_read_prepare_etr, + .read_unprepare =3D tmc_read_unprepare_etr, + .get_trace_data =3D tmc_etr_get_sysfs_trace, +}; + static int __tmc_probe(struct device *dev, struct resource *res) { int ret =3D 0; @@ -823,6 +813,7 @@ static int __tmc_probe(struct device *dev, struct resou= rce *res) desc.subtype.sink_subtype =3D CORESIGHT_DEV_SUBTYPE_SINK_BUFFER; desc.ops =3D &tmc_etb_cs_ops; dev_list =3D "tmc_etb"; + drvdata->sysfs_ops =3D &etb_sysfs_ops; break; case TMC_CONFIG_TYPE_ETR: desc.groups =3D coresight_etr_groups; @@ -835,6 +826,7 @@ static int __tmc_probe(struct device *dev, struct resou= rce *res) idr_init(&drvdata->idr); mutex_init(&drvdata->idr_mutex); dev_list =3D "tmc_etr"; + drvdata->sysfs_ops =3D &etr_sysfs_ops; INIT_LIST_HEAD(&drvdata->etr_buf_list); break; case TMC_CONFIG_TYPE_ETF: @@ -844,6 +836,7 @@ static int __tmc_probe(struct device *dev, struct resou= rce *res) desc.subtype.link_subtype =3D CORESIGHT_DEV_SUBTYPE_LINK_FIFO; desc.ops =3D &tmc_etf_cs_ops; dev_list =3D "tmc_etf"; + drvdata->sysfs_ops =3D &etb_sysfs_ops; break; default: pr_err("%s: Unsupported TMC config\n", desc.name); diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracin= g/coresight/coresight-tmc.h index 6e994678f926..a14645b04624 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.h +++ b/drivers/hwtracing/coresight/coresight-tmc.h @@ -259,6 +259,7 @@ struct etr_buf_node { * @crash_mdata: Reserved memory for storing tmc crash metadata. * Used by ETR/ETF. * @etr_buf_list: List that is used to manage allocated etr_buf. + * @sysfs_ops: Read operations for the sysfs mode. */ struct tmc_drvdata { struct clk *atclk; @@ -290,6 +291,20 @@ struct tmc_drvdata { struct tmc_resrv_buf resrv_buf; struct tmc_resrv_buf crash_mdata; struct list_head etr_buf_list; + const struct tmc_sysfs_ops *sysfs_ops; +}; + +/** + * struct tmc_sysfs_ops - read operations for TMC and its helper devices + * @read_prepare: prepare operation. + * @read_unprepare: unprepare operation. + * @get_trace_data: read operation. + */ +struct tmc_sysfs_ops { + int (*read_prepare)(struct tmc_drvdata *drvdata); + int (*read_unprepare)(struct tmc_drvdata *drvdata); + ssize_t (*get_trace_data)(struct tmc_drvdata *drvdata, loff_t pos, + size_t len, char **bufpp); }; =20 struct etr_buf_operations { --=20 2.34.1 From nobody Sun Jun 28 10:37:02 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 12B7238398B for ; Thu, 25 Jun 2026 10:46:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782384406; cv=none; b=T4yU4AlINDL69fCjlpJ7lV3nbdhn29ftTL0AsvJBdR2bRPZvAy+v4TiqpTeZcjfbCZ4vqo/j8SRamrix7OO7QMRfn/4MdpzDEBV7wOdOV1oRrXC+LzAga7qZpC2Ldt98lMbasIUp83GcNQfWfw+an1Gwvfl8Xy4O/MrOA9emAiI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782384406; c=relaxed/simple; bh=fIhJzaso9N9Xd1IgveByjqgunx3Xh6KSxy4FjeYwCkc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=XZCCA2CRKrPE3pcxpOBnGoZMvHAOdf1Pz8eS8go+sZ4qSK21qCJVKjtwhePxTsbAzqBB2wt+/Q7hoO+/HmvU2CxpRDYYzmiFubMQ7o9/2AVyS6z94JzTpHY0dxKvHPPXlhkRtxA0RCXTUysMou/X/GYMHgsWKzllFZtWcCMjF3A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=nktWvLFF; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=NrVt1OOB; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="nktWvLFF"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="NrVt1OOB" Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 65P9jwoS1371476 for ; Thu, 25 Jun 2026 10:46:44 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= H2gE10b7DqflojsoJUwYlVeY6chdArR8ZAvuFavqtsk=; b=nktWvLFFua3yFrvd 5B6nj7vGsAE6Lr5dZJwt5IA3hJuKA9DKcIxxpr1gYLk/OnGRIsih3W3n39YUVJKi ioA69YxoPwgudCSl7IIvK33sJRokav+1zQ9ZVU0hi15A7kxxi16eXu4lTnHjmjtq oBKoXnTZ4EAIm2UxbibrJbIQ7Vb02PYSImjzW0UgLReajzEgQdxpv/ACh97dPixr Dj3BruedT6b+9nzI0J3bM8ZIgaVhaCG1Hwtm1uvTAiEZdCYFVd5tTysLusvK/QIl qsmF7FDNZum+Rx7PFSoH43uw5ek7/k9K8VwFgrMWG9WSqH41i9s4EfyEmWjDgN56 MaCh6A== Received: from mail-pl1-f200.google.com (mail-pl1-f200.google.com [209.85.214.200]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4f0ymv0tha-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Thu, 25 Jun 2026 10:46:44 +0000 (GMT) Received: by mail-pl1-f200.google.com with SMTP id d9443c01a7336-2c7edb8505dso13060125ad.1 for ; Thu, 25 Jun 2026 03:46:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1782384404; x=1782989204; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=H2gE10b7DqflojsoJUwYlVeY6chdArR8ZAvuFavqtsk=; b=NrVt1OOBJILPxddMbzddgG7qJ2sV23CbQ+JawSCG0L9ThGoVo8nBHqFAQh7ZSmBqM0 uc48RrarXPZvvVkWZq68XJWuc8tRj4oJCiuBzyRmAlZgYlENiRczqqJCNCkdqOu76AD6 Zff+J7idIRMnL7SmTA27967pBxZid2BpCQ59KsEsoPH3wIznrsbJmw4/G2Gp/uWsAFNH 5KF3SSNredT6kGUGU4ypBhYL0IpBsNXdAXiqRhrizM81DXqBC4Bi9AA+GwBJMzO3qBo6 UHCm9yx2Yz5WfbRIeJsEKoe49TyvHVntHRiu2+aDfeCISeQELg4skeZfrdvIqejb/M3i n6NQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1782384404; x=1782989204; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=H2gE10b7DqflojsoJUwYlVeY6chdArR8ZAvuFavqtsk=; b=ExEORQSweJLJ3A16IX8eK2RQEzPfdTVZwanrsqp/3Km2lWrpGXewDek2QlI+BEIEsb ovZRVCPay86j/uYDrb9pMlflF8Nj6023qvp1qFNrmOdQ79CvvbAm3MPC8803H7sU/iik gKzZArpr9fqfIRX2myjYtiAnrkxLyaFE1L6H+LKJ0PLAR6F9OKC+jEO0LST8Pqkz0j0f 02CalxFyhgZ8OeSwbg1Ui1Z0fEkx2VafHMuy9NXcTgbU5k9IzVgBkQKYwpxnOkoi92xS Sv+jbcBGHMEp4NWsMx0ee5/+Rt/oTr0gRisi48d9Ne4JiJU1LgAvCp19gklxs9kxq08z QFbw== X-Forwarded-Encrypted: i=1; AHgh+RpXp4CiJ++XGV4rqx9YYQOBUTtJF04X+jRtIFMMmLiefiPKvqSD31aqY/38PCOdKkto2nZadWcO8wsxPiw=@vger.kernel.org X-Gm-Message-State: AOJu0YzXvYo0bR8nOL7rDZ2jozB06jbn/04Wo6J7ssavCM0+ji5ntWa/ J4y3AYhZKcoKNO7uXIxeNGoW5DXfTZhRDJSEcLeq8iEbIPQUdgokLhMzlsIhdcezY31xvcCjem7 YxVAo4hGmmLNv2LRzeS0Adlw3huUcb/3Vbky8E9hgTOPib0r0zBVGP2BF0XaPYV1NyJfwD9DmdJ xUIw== X-Gm-Gg: AfdE7clAMQMayLNKXG7IncVISHrpggouTrlKYDVRipJn8MHYDrwc4G2jygsAqMxTjBz JVrKkx+mciIMz+3BT0E9prAN9OMdH6/UkhasvnzYm2ZCuuw5bSFH7d2zG3+ohN3Eh9QNxb/4mdM 7PVhw3rJtnSZtocsDLkNBHiTFOacSsb8dOhMpl27Sfsv1UPB4JVvlg8aptShoDxSzbDXffOAokm 1KkPHjMwh9YxoBYA4Utkpr9GCsOu/PzCByELa3jjzmPqG3f7zBnA859WgYX01oVUFG3Zp/JSt64 9FYqkxL6sN/3GCIPKo3ELPDKnp0RwsP+gZixdYazVdd/UMvYV34vcI/jLoY+xcdXVaRT3ZLpJ90 m4bqSTymNCrAOnX6Q1Wzo7DOn3ct6GPSlkDkkIB+NTA/JgA+Qlvqn1N7B/EgGsqCDZWCKWvGX/A == X-Received: by 2002:a17:902:cec1:b0:2c0:c14c:bf38 with SMTP id d9443c01a7336-2c7fc7309b2mr19682065ad.24.1782384403459; Thu, 25 Jun 2026 03:46:43 -0700 (PDT) X-Received: by 2002:a17:902:cec1:b0:2c0:c14c:bf38 with SMTP id d9443c01a7336-2c7fc7309b2mr19681765ad.24.1782384402956; Thu, 25 Jun 2026 03:46:42 -0700 (PDT) Received: from jiegan-gv.ap.qualcomm.com (tpe-colo-wan-fw-bordernet.qualcomm.com. [103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2c7f63d58e9sm17114035ad.60.2026.06.25.03.46.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Jun 2026 03:46:42 -0700 (PDT) From: Jie Gan Date: Thu, 25 Jun 2026 18:45:54 +0800 Subject: [PATCH v19 4/7] coresight: etr: add a new function to retrieve the CTCU device Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260625-enable-byte-cntr-for-ctcu-v19-4-8fbbf22e8381@oss.qualcomm.com> References: <20260625-enable-byte-cntr-for-ctcu-v19-0-8fbbf22e8381@oss.qualcomm.com> In-Reply-To: <20260625-enable-byte-cntr-for-ctcu-v19-0-8fbbf22e8381@oss.qualcomm.com> To: Suzuki K Poulose , Mike Leach , James Clark , Leo Yan , Alexander Shishkin , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Tingwei Zhang , Jie Gan , Bjorn Andersson , Konrad Dybcio , Yuanfang Zhang , Mao Jinlong Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1782384372; l=2348; i=jie.gan@oss.qualcomm.com; s=20250909; h=from:subject:message-id; bh=fIhJzaso9N9Xd1IgveByjqgunx3Xh6KSxy4FjeYwCkc=; b=KxGEjMfdJvyIiidzq8F2ZIosQs0uCJGWkZa5FHiQaLch4Vk5w2VVPtL3MT5jND7sa+axVhvo/ NXNHyXdi6zaBGQNmRG6wcWvxqdFOS8qRrrxEyaqfei1DNGJ1U1Xbtuk X-Developer-Key: i=jie.gan@oss.qualcomm.com; a=ed25519; pk=3LxxUZRPCNkvPDlWOvXfJNqNO4SfGdy3eghMb8puHuk= X-Authority-Analysis: v=2.4 cv=DqBmPm/+ c=1 sm=1 tr=0 ts=6a3d0714 cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=EUspDBNiAAAA:8 a=FuIWbRVyn4pKkvqW11oA:9 a=QEXdDO2ut3YA:10 a=uG9DUKGECoFWVXl0Dc02:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwNjI1MDA5MiBTYWx0ZWRfX3fqPbYN0DxKn VpTge8Qd2HH/nihzqOXD3h2zH5cgE+TdJ7mzHZlIXX3j++x65Yfty5ETuxeBsbFJ2Z14wP17ni5 lu7tibIUQHPNnKzwdo7BKJ15JonJc20= X-Proofpoint-ORIG-GUID: incrYLX-2O_p4F0P4b9Do3witfCb9tRK X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjI1MDA5MiBTYWx0ZWRfXz7Dj1KXgdbbw fKSAOp8L17or/N/o7A2B5P1kd0TsJrox2q/AKH/aPvTFzEunQlsLA0vxDbc4YdizmxiQUti2sye PfdBt5jyJI6jN9APL5rFoL2S9NGU5QN0R5DpKsGK7+Ye9aEbZK5WiR9uCw5ugMxzFB9k/N5NpFa Kn+CPH3yaQwrGI0co4jxXOiYhXa23C1TboLKji1tZZ6IzDBnqwfiuJiWQADyg06SYQnL/H8tWbh JzyEBiTLWbs9BLp973xb5KXU29p22U4RRk0Qsi4rBVun1rN/AxvZ3Oc1Sppt1Ty8SkqWFVzaoBK sapACpwm8Bnejbkvt+jixpzVg00TOKEpaBaKGJom3vYssAO1CM+Wjnhie4RNR0KJGj+mazkPVXr P2r/vrjA6LDReQxZOoLsdZUC63YcAq4cOUbJu4dRbmynMa62dRT1zHqpS22L16jOHuDy2ro+LPf erDED1PrOgoJuBFLOyQ== X-Proofpoint-GUID: incrYLX-2O_p4F0P4b9Do3witfCb9tRK X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-25_01,2026-06-24_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 lowpriorityscore=0 priorityscore=1501 malwarescore=0 suspectscore=0 bulkscore=0 adultscore=0 spamscore=0 impostorscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2606250092 Add tmc_etr_get_ctcu_device function to find the ptr of the coresight_device of the CTCU device if the CTCU device is connected to the TMC ETR device. Signed-off-by: Jie Gan --- drivers/hwtracing/coresight/coresight-tmc-etr.c | 24 +++++++++++++++++++++= +++ drivers/hwtracing/coresight/coresight-tmc.h | 1 + 2 files changed, 25 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtr= acing/coresight/coresight-tmc-etr.c index 9b3ef73e9cf2..2b26ce6455a7 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -865,6 +865,30 @@ tmc_etr_get_catu_device(struct tmc_drvdata *drvdata) } EXPORT_SYMBOL_GPL(tmc_etr_get_catu_device); =20 +/* + * TMC ETR could be connected to a CTCU device, which can provide ATID fil= ter + * and byte-cntr service. This is represented by the output port of the TMC + * (ETR) connected to the input port of the CTCU. + * + * Returns : coresight_device ptr for the CTCU device if a CTCU is found. + * : NULL otherwise. + */ +struct coresight_device * +tmc_etr_get_ctcu_device(struct tmc_drvdata *drvdata) +{ + struct coresight_device *etr =3D drvdata->csdev; + union coresight_dev_subtype ctcu_subtype =3D { + .helper_subtype =3D CORESIGHT_DEV_SUBTYPE_HELPER_CTCU + }; + + if (!IS_ENABLED(CONFIG_CORESIGHT_CTCU)) + return NULL; + + return coresight_find_output_type(etr->pdata, CORESIGHT_DEV_TYPE_HELPER, + ctcu_subtype); +} +EXPORT_SYMBOL_GPL(tmc_etr_get_ctcu_device); + static const struct etr_buf_operations *etr_buf_ops[] =3D { [ETR_MODE_FLAT] =3D &etr_flat_buf_ops, [ETR_MODE_ETR_SG] =3D &etr_sg_buf_ops, diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracin= g/coresight/coresight-tmc.h index a14645b04624..fbb015079872 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.h +++ b/drivers/hwtracing/coresight/coresight-tmc.h @@ -470,6 +470,7 @@ static inline uint32_t find_crash_tracedata_crc(struct = tmc_drvdata *drvdata, } =20 struct coresight_device *tmc_etr_get_catu_device(struct tmc_drvdata *drvda= ta); +struct coresight_device *tmc_etr_get_ctcu_device(struct tmc_drvdata *drvda= ta); =20 void tmc_etr_set_catu_ops(const struct etr_buf_operations *catu); void tmc_etr_remove_catu_ops(void); --=20 2.34.1 From nobody Sun Jun 28 10:37:02 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8AA7770809 for ; Thu, 25 Jun 2026 10:46:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782384411; cv=none; b=bguxc3JrnqMg0Pi/3bvQZJ1Ql1WfILj3U9x3JGxECwoC9iTbPt/NjLazEb9vikGrDopSerHb1Fu2vmM6BOjEl/vqrgVx3m2K8rxfhcPgVdCMpwXtocqzIToRXQAAvghcDFSGOEpLW9zccYycWeqktSmzykliuAJ1R2eegrGQJnQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782384411; c=relaxed/simple; bh=DsL6kcYT3hY1q2jvZSOp/rxfO6RBNAUHqHA9yEMzJAk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=NKxmiLppij46cPhB+6vDhZciKDtA365Gx9rKCQUOckX9JuulPbh+ILnTjBi7iR0uzkWcI/bdwUUTcqRFew1DTDvpypyGR3mgl7+qK9TIW+IwhaaY2a+O+4t+HQYcJM/2ETM/xvM5f1C6zAud/QwtrBrixX/XXV4nKYScHivyCMY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=nRfvZ60R; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=EOsHzkSy; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="nRfvZ60R"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="EOsHzkSy" Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 65P9jxfk1398012 for ; Thu, 25 Jun 2026 10:46:50 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= 5AiUjeizRXgIt0pWaEk9wGXXVAIJo5RCeKWJBfIhvcE=; b=nRfvZ60Rlqp9rNcv oHgd2pHed7vU4J3YzF3pnvOY4Na4PjKZwiF8sYjhElRIBdebz/u5NmlB9Q8ufid+ fmTfC01MewRQS075QIm3VdEKATwOGJfMXyChmrpqW3kw1wXAeO4WC9So0Bz/Jhel ASDiuB2m0fN+De5JhZvrxVdYXTOyC4dBOrldkdgpScabNKAnXo16YuYW++Jucetx N+fPQaCAGWGIqypHj03R8GUrbZAx2enTofHbUwGEpKQwoKfPJiuNpQapqLUAFVln egSOU313amuWxKoxA1Ix8lUdNMhKlLBVqmoyxUQnSrciTpEVc1XW/4Nt/PnEN+Jg 0PssKQ== Received: from mail-pg1-f198.google.com (mail-pg1-f198.google.com [209.85.215.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4f0uudhqr1-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Thu, 25 Jun 2026 10:46:49 +0000 (GMT) Received: by mail-pg1-f198.google.com with SMTP id 41be03b00d2f7-c89956023dbso1232005a12.0 for ; Thu, 25 Jun 2026 03:46:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1782384409; x=1782989209; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=5AiUjeizRXgIt0pWaEk9wGXXVAIJo5RCeKWJBfIhvcE=; b=EOsHzkSy6j0dyabxvdH/PceVxv2QI939HnZZqAMEOe77qJdOJOeRvO5wNwvTq9yw9J rpwuKyw9GVoSUmz/aUz4QOApeezUeDPEx65S1QmT3B9zJPJ4tvbtvBKvMn4YzSoo0+Gl F+22qHAthuaQaHAFY1YqOIEdkViVGkmilDzuLnmkDWmn0WA35cVhWdMTMPm1nsc3sAJl mAr7Ei9jVmA8EukYf4tV13awlGx0PbuTfNmIM1FwIhoG1NSz1Vbwv+aXCHAtZfJe7uck T/AkS78qAig7z+4sgYpSdueiSG1oaWlNb3XHLso/0cTfEw65BHx2frb9xVWb6dS+12Ao xxLg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1782384409; x=1782989209; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=5AiUjeizRXgIt0pWaEk9wGXXVAIJo5RCeKWJBfIhvcE=; b=fDUWj//0cw4+U032RLh3jWLOU+v2ffraOB4rIXc0j7KhkyckHCPngFViylpouQovY7 YxAeczyt1KocA9kTriYPgsWVUWnmJI1q9noVHE7Br/5oHebEeY15o1EDmRZqjeJ6reT6 Sqp7AonUCuCBiSEIrkn58cMbVm0u3QdtfjSvwydY7ZuIgz//X3/uT2V4YlSkHsRV37Sq fz70+AKrkpU1JZSq3scSWD2hFbzB6i7qh5gfsPncm9Syzd7S09a/RM7LfWEpYS2vMn1i JzhpdFHaVcX6Tkh+L5c7ejFAu7Q/+RgizSlm78LsoYmFSiiCbkpMsBiDbG1RqHLC0G5k 5G+A== X-Forwarded-Encrypted: i=1; AHgh+Rq6+0djxo/hRZGXHGQWrbk7lBw0uWRbPq+9arlGHeGcklp5za9nsWU8XnCRT6yvwScsdQWdMGYRTtCCe2I=@vger.kernel.org X-Gm-Message-State: AOJu0YyGa8KeX1ydax+WgUKU9ToOO7C71eBlP7E3iyM8iWo5F/1vwytR mtHcfidnpeB9VLlAxd55QiQzLJbpyDrVWLKFbQ9XQFE+1+qAJ27sm37IQBuQNqA+agPj3Qdw92V v1NSAQUxNm7bzUaTanvZN6lpQujoxEIWbK4qIM+qFFoWSJm+1my2xXC4TVUOdfnbWYXGVtHUIrO Rpow== X-Gm-Gg: AfdE7cllIr9VFN2ffFJzCA03XgsmdaXCpSy/3IAOlb7hwu9uYLSXPqHniEXrJ/B5Ywc Rkjta3061t7wkGggoBMPpUj3L1Elfh7P5Wo9kOQ3FrqnzKBTpRxEj+d4e47jSAxqdSzsHrK7cwO rbZDOkwPpkIQwTWeiGCx5+l0ZJXFKh5b5TBTAh9vRaM//ccKCVoq1cdSr3I4eRLAntMF96kP9y8 CbzcYipi1PQRGAmPGXUEWz7kivYYXXAg5xzA8otGmpI2pVNi5Avn/qMW6/VZwoohWd+fZmeIiKJ zrL0mGae2FNXx5xAOqk9SoZlkHTrtDAz0vDjNe2QoCOt4nXj9xn3r4jXC5c+bLIOW7CPrnuuzMb LSYO0uEyRjN95zE4ITECRYhtXYVstB5pPcNVZiMe1PdXTjJ3a8uOjDS2j1rKscuhEPLbJDmB7Vw == X-Received: by 2002:a17:902:f644:b0:2bf:211c:4980 with SMTP id d9443c01a7336-2c7fc8b106fmr21137695ad.35.1782384409178; Thu, 25 Jun 2026 03:46:49 -0700 (PDT) X-Received: by 2002:a17:902:f644:b0:2bf:211c:4980 with SMTP id d9443c01a7336-2c7fc8b106fmr21137275ad.35.1782384408748; Thu, 25 Jun 2026 03:46:48 -0700 (PDT) Received: from jiegan-gv.ap.qualcomm.com (tpe-colo-wan-fw-bordernet.qualcomm.com. [103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2c7f63d58e9sm17114035ad.60.2026.06.25.03.46.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Jun 2026 03:46:48 -0700 (PDT) From: Jie Gan Date: Thu, 25 Jun 2026 18:45:55 +0800 Subject: [PATCH v19 5/7] dt-bindings: arm: add an interrupt property for Coresight CTCU Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260625-enable-byte-cntr-for-ctcu-v19-5-8fbbf22e8381@oss.qualcomm.com> References: <20260625-enable-byte-cntr-for-ctcu-v19-0-8fbbf22e8381@oss.qualcomm.com> In-Reply-To: <20260625-enable-byte-cntr-for-ctcu-v19-0-8fbbf22e8381@oss.qualcomm.com> To: Suzuki K Poulose , Mike Leach , James Clark , Leo Yan , Alexander Shishkin , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Tingwei Zhang , Jie Gan , Bjorn Andersson , Konrad Dybcio , Yuanfang Zhang , Mao Jinlong Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Krzysztof Kozlowski , Mike Leach X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1782384373; l=1751; i=jie.gan@oss.qualcomm.com; s=20250909; h=from:subject:message-id; bh=DsL6kcYT3hY1q2jvZSOp/rxfO6RBNAUHqHA9yEMzJAk=; b=NzXxSe9YCbXAOvgLAW+bQfAw5hmoUMFjsQl9kHlNLjYZHW1EJko7qSAjLxFK6OuUzJFyZUeKl 4BnzXZlDCyQCs8tj3LgEVmXHRuP7meAdUfgA7U0nC1dnKWo3CftEjyp X-Developer-Key: i=jie.gan@oss.qualcomm.com; a=ed25519; pk=3LxxUZRPCNkvPDlWOvXfJNqNO4SfGdy3eghMb8puHuk= X-Proofpoint-Spam-Info: AW1haW4tMjYwNjI1MDA5MiBTYWx0ZWRfXx9EvbBfk5RwL yz6b57YalP1T1gNvPyxSxSW75lFvlW7myB2M8yLUUL97KgedUC+uDFl3vxhZYkXHp7WRGLBI5Rf 6C5N6dsBxPGAYz5mcqYeSFNM2lYyc+I= X-Proofpoint-ORIG-GUID: YCvW-smveQs9c8DudF91keV_1WBbbR5i X-Proofpoint-GUID: YCvW-smveQs9c8DudF91keV_1WBbbR5i X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjI1MDA5MiBTYWx0ZWRfXwUUAEUROluqI ++dnC6/8nXCew5o7baabyTRQCLG83nxZNDp1Ne5hv6ex3JQIkDPOl9ZYGJNT24RNx9oZzMKH8Nr 5ENfo/BLj9ouWjUt+S9q/E5lYoUjwScTwofkq2/elwHJg75Iz21XVN+PfexdROHk+LsNdllsYMU 5jHBk2T8qWMFe0oU9X6GA9AeuAuKw6mzLNGrEcX5lF/76YzhRrzDQZo6DxstASZj1bzMmlG6pyT SxkWL62PvxEsbTUn2Oqs4Qa0c38ZiGO0K7qVAyap5RSoVZXSg3z/5eKHq0VfAFw0gw+Xr56GCJ/ S7qgnu2FISeZcX9iDS44rgRKGECmBHVWW/uGjCV5jviDGu6NEJUKj6TITx8+mlKJu3hRA1EwRp0 1HTdiWI/SNCHuQMOZI/yElSw1zoJCt+S1/AviisTCiOgrNR+4Pk1yWHhBBEpG042hQ4Pt9U1vgr IDa5s19eS+OVlo5/vPw== X-Authority-Analysis: v=2.4 cv=HdckiCE8 c=1 sm=1 tr=0 ts=6a3d0719 cx=c_pps a=Qgeoaf8Lrialg5Z894R3/Q==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=KKAkSRfTAAAA:8 a=EUspDBNiAAAA:8 a=gSyxy6DGYGa4b6s9XCEA:9 a=QEXdDO2ut3YA:10 a=x9snwWr2DeNwDh03kgHS:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-25_01,2026-06-24_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 lowpriorityscore=0 impostorscore=0 malwarescore=0 phishscore=0 bulkscore=0 spamscore=0 suspectscore=0 clxscore=1015 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2606250092 Add an interrupt property to CTCU device. The interrupt will be triggered when the data size in the ETR buffer exceeds the threshold of the BYTECNTRVAL register. Programming a threshold in the BYTECNTRVAL register of CTCU device will enable the interrupt. Acked-by: Krzysztof Kozlowski Reviewed-by: Mike Leach Signed-off-by: Jie Gan --- Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml | 10 ++++++= ++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml= b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml index e002f87361ad..2981001a7d7f 100644 --- a/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml @@ -44,6 +44,11 @@ properties: items: - const: apb =20 + interrupts: + items: + - description: Interrupt for the ETR device connected to in-port0. + - description: Interrupt for the ETR device connected to in-port1. + label: description: Description of a coresight device. @@ -65,6 +70,8 @@ additionalProperties: false =20 examples: - | + #include + ctcu@1001000 { compatible =3D "qcom,sa8775p-ctcu"; reg =3D <0x1001000 0x1000>; @@ -72,6 +79,9 @@ examples: clocks =3D <&aoss_qmp>; clock-names =3D "apb"; =20 + interrupts =3D , + ; + in-ports { #address-cells =3D <1>; #size-cells =3D <0>; --=20 2.34.1 From nobody Sun Jun 28 10:37:02 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0C41A70809 for ; Thu, 25 Jun 2026 10:46:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782384420; cv=none; b=VmsvJL0fjmjCzjBTazcIZ3f9k+5WoAg/7BToeAQ5TZx7eIFtf/iy9yXhP/7bLIcQfyzaIEGcbFRZYJl26IveUfJ1uKOl1eRZvxH/L1ayzUc+MIg5S6syrSbW54erbrehHrToARiau3+1ezGI+alILzqXK4zv4cEQTC7g6KMQU1o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782384420; c=relaxed/simple; bh=PCwX1iBZJhnZ+HJC7VMP77gmaxnW1thFOp5z4RDwksI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ZGkuCiflanzHbe01EhgL6Yd76WZXn2VlCY0WZK7gInCBjaqrTrOHBhjd8ri7k+YXRp12QgKf0o68FZsZotqbaAJIFtiKLfkBeZCLAnb6Raq0vkO3pcud56PqqCzgD0bNEm2Fpg63d1Z24e8x87ILLXdRzTIjh6hcnctFiV7WNdM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=jxYE+jvr; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=NInHLBNH; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="jxYE+jvr"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="NInHLBNH" Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 65P9k4E42048176 for ; Thu, 25 Jun 2026 10:46:57 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= eHYgqL5qRMOfpJ4Bq7Ch5tatGQPhgkOHru8UKnasYlY=; b=jxYE+jvrw1AdMwNm zj9N7IY/1wZojkAVxiJKTywMyyugtvizDLEeF+gCsQb5/BF+1sqGd+JGHLero67d VHodd/f3J2qXi+FfIXnyJUh6x15Zr1x0e8fvx3s9PFB+eVsCQrYhc8ReqFlxsHbY oiEQC4zDn7H/7U0UAb3NAs47MmYAkPBHlSjnb3hlqn0KkydGxHhoxFPaNe1l4YFR EQIuwtyaLc9CIHOLhnsSrv1yOpw67kqc7N6JnVcLpAcc0f0nWZGwVACG3N0iG2DS 0W2oskAsyHXClszDtn0giuKGcXmx1HnHtOaraZBDD6cJm6IuCkCSzqcKMlNAYxHe dE/hRg== Received: from mail-pl1-f199.google.com (mail-pl1-f199.google.com [209.85.214.199]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4f0uyqhpbh-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Thu, 25 Jun 2026 10:46:56 +0000 (GMT) Received: by mail-pl1-f199.google.com with SMTP id d9443c01a7336-2c6bf305403so16242045ad.2 for ; Thu, 25 Jun 2026 03:46:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1782384416; x=1782989216; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=eHYgqL5qRMOfpJ4Bq7Ch5tatGQPhgkOHru8UKnasYlY=; b=NInHLBNH9sI/ZfFRhBBxtUGLBt9wi4ADetID2wzSnnKQqdBqPLCfT1YpDaRu28mTid HNtoh0w4FnHrDveTH2gsMqoBDONlqV13QFx9ymca6cocyhuk8CUdUwtshSDPbDFRfSjN NhjK6xSKz4/vD9tKJMUXnM/QTBpY6vWvfpdeCZUlPmCz/oHvWGlLOi6FbmW4obhupc0A zFKGH2XfYRjFTSLs/qfiLrjzYAfo878rwAw/GRWgPyTopis3z2R/TSC28MqQRIC6TFXL OWT/qk6txt3cI51tVWF7mnjnQKwi8oidMDbQTucFBvdDcbJVIq7NHZpLwaHM8e1RYh+A q6qA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1782384416; x=1782989216; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=eHYgqL5qRMOfpJ4Bq7Ch5tatGQPhgkOHru8UKnasYlY=; b=Nqedb3ncC5Bu89e6UXrhBRgSyPQRNLYjjJHCO5m/YU9YdARuDsxubcSSPNjnNw301D OnEeVl6XP43pYqcfC5Sm7Dr/pvO+m+5LD1pi85+67kM5xGXBqV+i12QhgAdlJcAdpwYd Vs7rhwCVMA/PMH6evXtZRoFFj+v6WKTnXlDsLgBbKaoswqVDBCX/PM0B3CFxUIyo5lAD hDvGKPoMqUepZX459TkyDeQYT3S2Up2BHTItbUrRBN2iCMMeuxqtmnLxkjRcQ1SkBhx1 Y8ib3n6QnSiAb4OC0zI9ffh40ZCOz8ExzjZZopXKr7NA6cOKoixmZPSxDfR/IfcTP3ba 4Wqw== X-Forwarded-Encrypted: i=1; AHgh+RoPvoRdM8xSkX3pAlTpJt0YjfKia1oa8hn2j8HZFvx5eeyEGf38sfu11/qwcLvHSehl4S/VoQaMWpeTj6A=@vger.kernel.org X-Gm-Message-State: AOJu0Yxs60gvQyNlSylO2MVM6Fp0ZULY/5QcPmSiNAiKnnHj8IzH0tFZ Iu+mV9rLmKzc5ODKGyTuanAdA/xa8ieQz6OpIof+N3lshc7czWHivD+wH/ApVdX2StM080M+L2K BMa2GweF9R0Hi+x16MGlDQO5hLU/WcJDALjvYZqQ5f482zeytTKsRfca9Ntgq/tyA6boEODlMjm y1Jg== X-Gm-Gg: AfdE7cnJp2pBv0S7g8zE+3VsciRpWyzwN7fyx9O5W4dq4jHxdjSTkZ+RVYx0SEAjd/M Dm/TOWvAgJQLYi5qqJ/gMT3OVRX8nHR3kU1ZERaokpRJt//EIjpp5K+6Tc+n2vuFsUhC8wVj2qK IdoieOcYgnM+3X+4YjowDu/uqQjZbabJOuO4kqQQJnpDJ7cSay8cJ204QRVCXwxOabxxz6C++r9 iXcs9hGK6lwWOGtJMrjTINOhtOLAv1ayGGqDIfVG3+fke0P08LqdUwsa39Fl4rouwbtfrOMD+Uc oru/5CLQuvm4Hng0DIfOaGezLRf0A0uyovwzH5+0x/D8TxpqYIUWLo4AbLtHroLatkH46lk/eON gC5VSM3HPfAkMFGPe/mtJa/dsiZ1kHm8f03TewQaFGs7BWyIOqPW8pZBF+MJ3qk5NluKpI7xjBw == X-Received: by 2002:a17:903:35c6:b0:2bf:77b2:8b2d with SMTP id d9443c01a7336-2c7fc8900f5mr21001285ad.30.1782384415486; Thu, 25 Jun 2026 03:46:55 -0700 (PDT) X-Received: by 2002:a17:903:35c6:b0:2bf:77b2:8b2d with SMTP id d9443c01a7336-2c7fc8900f5mr21000715ad.30.1782384414773; Thu, 25 Jun 2026 03:46:54 -0700 (PDT) Received: from jiegan-gv.ap.qualcomm.com (tpe-colo-wan-fw-bordernet.qualcomm.com. [103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2c7f63d58e9sm17114035ad.60.2026.06.25.03.46.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Jun 2026 03:46:54 -0700 (PDT) From: Jie Gan Date: Thu, 25 Jun 2026 18:45:56 +0800 Subject: [PATCH v19 6/7] coresight: ctcu: enable byte-cntr for TMC ETR devices Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260625-enable-byte-cntr-for-ctcu-v19-6-8fbbf22e8381@oss.qualcomm.com> References: <20260625-enable-byte-cntr-for-ctcu-v19-0-8fbbf22e8381@oss.qualcomm.com> In-Reply-To: <20260625-enable-byte-cntr-for-ctcu-v19-0-8fbbf22e8381@oss.qualcomm.com> To: Suzuki K Poulose , Mike Leach , James Clark , Leo Yan , Alexander Shishkin , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Tingwei Zhang , Jie Gan , Bjorn Andersson , Konrad Dybcio , Yuanfang Zhang , Mao Jinlong Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1782384373; l=31528; i=jie.gan@oss.qualcomm.com; s=20250909; h=from:subject:message-id; bh=PCwX1iBZJhnZ+HJC7VMP77gmaxnW1thFOp5z4RDwksI=; b=XMk4VbH2b1ZAeTiMALvR9c4Irtk9g+yrugWCZWLlQIq8Ru96RtAhkfnJqryYsif0rbTPkcg2w ejmcR8vCCHaDilB2f5fUBGXq0ibQeWwSwj9iYdlfNsvLLwJ1Kql9Aej X-Developer-Key: i=jie.gan@oss.qualcomm.com; a=ed25519; pk=3LxxUZRPCNkvPDlWOvXfJNqNO4SfGdy3eghMb8puHuk= X-Proofpoint-GUID: oCOZ26wKb_Ha56p2VuzKnhYYb_vFs_CB X-Proofpoint-ORIG-GUID: oCOZ26wKb_Ha56p2VuzKnhYYb_vFs_CB X-Proofpoint-Spam-Info: AW1haW4tMjYwNjI1MDA5MiBTYWx0ZWRfX81dFlU63T7Zy QCkuz6gbaq1LG3ZfBwJG6jdYaUFMYPoON93KQtad4xkszEWv5AIDKUMwLJNFN+pRVZu3P9Q1rtG 86dpQlQve0C3p83S9c2yZtrrJy2aC0g= X-Authority-Analysis: v=2.4 cv=EsLiaycA c=1 sm=1 tr=0 ts=6a3d0720 cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=EUspDBNiAAAA:8 a=5ZayD7Dtjcd0oo6PAqQA:9 a=QEXdDO2ut3YA:10 a=324X-CrmTo6CU4MGRt3R:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjI1MDA5MiBTYWx0ZWRfX2BbKfLfnFrYd 3kQLU6/gvYB2Oa3p5mdtiPLnfd2fnzbNtI7j3NEeo4hxwiZWdVvDFhCtILixSCOenLrgQczGpd+ 0upp3sdl0fdqPl17ywLm6CBJZnHUXAAfdXUvvNtJ7h2DP5rEWiO5+xUTBTQvHYctTmn6X/BtkDa 6SFIhOOgF5ol/JSIY447Aw5JMe04NSJB0eoAZ7H7EG+i308KdYYfuskSSZE5CGFLzff4+J4i7zK eTkRQX+QpKBvaaFLGbNR1GaeZRhFtgD0yaEGjYgPrJbWo3wFiSjrZsejElmMB4KcK2SvrshHKL/ HrZukurQv1BUXcrqNu7CAEeqnatb2va3+Mwq41rL0U2mx4vF8kxpksf4k7ypGbz2uutEfDoGjuW hVkpUMIXawlciH9y8vE1kzSdKrrN9xck5QNTa6LX5e3T4naIYrfstGhSRYhvwPtStB4iv9tiNyc 0eAWZqn/r4GTQ0U6BBQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-25_01,2026-06-24_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 bulkscore=0 clxscore=1015 priorityscore=1501 impostorscore=0 adultscore=0 spamscore=0 malwarescore=0 lowpriorityscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2606250092 The byte-cntr function provided by the CTCU device is used to transfer data from the ETR buffer to the userspace. An interrupt is triggered if the data size exceeds the threshold set in the BYTECNTRVAL register. The interrupt handler counts the number of triggered interruptions and the read function will read the data from the synced ETR buffer. Switching the sysfs_buf when current buffer is full or the timeout is triggered and resets rrp and rwp registers after switched the buffer. The synced buffer will become available for reading after the switch. Byte-cntr workflow: start -> ctcu_enable(ctcu_byte_cntr_start) -> tmc_enable_etr_sink -> tmc_read_prepare_etr(jump to tmc_read_prepare_byte_cntr) -> tmc_etr_get_sysfs_trace(jump to tmc_byte_cntr_get_data) -> tmc_disable_etr_sink -> ctcu_disable(ctcu_byte_cntr_stop) -> tmc_read_unprepare_etr(jump to tmc_read_unprepare_byte_cntr) -> finish Signed-off-by: Jie Gan --- .../ABI/testing/sysfs-bus-coresight-devices-ctcu | 9 + drivers/hwtracing/coresight/Makefile | 2 +- .../hwtracing/coresight/coresight-ctcu-byte-cntr.c | 327 +++++++++++++++++= ++++ drivers/hwtracing/coresight/coresight-ctcu-core.c | 127 +++++++- drivers/hwtracing/coresight/coresight-ctcu.h | 81 ++++- drivers/hwtracing/coresight/coresight-tmc-core.c | 3 +- drivers/hwtracing/coresight/coresight-tmc-etr.c | 115 +++++++- drivers/hwtracing/coresight/coresight-tmc.h | 9 + 8 files changed, 647 insertions(+), 26 deletions(-) diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-ctcu b/D= ocumentation/ABI/testing/sysfs-bus-coresight-devices-ctcu new file mode 100644 index 000000000000..beef0be21969 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-ctcu @@ -0,0 +1,9 @@ +What: /sys/bus/coresight/devices//irq_enabled[0:1] +Date: June 2026 +KernelVersion: 7.3 +Contact: Tingwei Zhang ; Jinlong Ma= o ; Jie Gan +Description: + (RW) Configure the flag to enable interrupt to count data during CTCU en= ablement. + An interrupt is generated when the data size exceeds the value set in th= e IRQ register. + 0 : disable + 1 : enable diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/cores= ight/Makefile index ab16d06783a5..821a1b06b20c 100644 --- a/drivers/hwtracing/coresight/Makefile +++ b/drivers/hwtracing/coresight/Makefile @@ -55,5 +55,5 @@ coresight-cti-y :=3D coresight-cti-core.o coresight-cti-p= latform.o \ obj-$(CONFIG_ULTRASOC_SMB) +=3D ultrasoc-smb.o obj-$(CONFIG_CORESIGHT_DUMMY) +=3D coresight-dummy.o obj-$(CONFIG_CORESIGHT_CTCU) +=3D coresight-ctcu.o -coresight-ctcu-y :=3D coresight-ctcu-core.o +coresight-ctcu-y :=3D coresight-ctcu-core.o coresight-ctcu-byte-cntr.o obj-$(CONFIG_CORESIGHT_KUNIT_TESTS) +=3D coresight-kunit-tests.o diff --git a/drivers/hwtracing/coresight/coresight-ctcu-byte-cntr.c b/drive= rs/hwtracing/coresight/coresight-ctcu-byte-cntr.c new file mode 100644 index 000000000000..5ab97a71f02f --- /dev/null +++ b/drivers/hwtracing/coresight/coresight-ctcu-byte-cntr.c @@ -0,0 +1,327 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include +#include + +#include "coresight-ctcu.h" +#include "coresight-priv.h" +#include "coresight-tmc.h" + +static irqreturn_t byte_cntr_handler(int irq, void *data) +{ + struct ctcu_byte_cntr *byte_cntr_data =3D data; + + atomic_inc(&byte_cntr_data->irq_cnt); + wake_up(&byte_cntr_data->wq); + + return IRQ_HANDLED; +} + +static void ctcu_cfg_byte_cntr_reg(struct ctcu_drvdata *drvdata, u32 val, + u32 offset) +{ + /* A one value for IRQCTRL register represents 8 bytes */ + ctcu_program_register(drvdata, val / 8, offset); +} + +static struct ctcu_byte_cntr *ctcu_get_byte_cntr(struct coresight_device *= ctcu, + struct coresight_device *etr) +{ + struct ctcu_drvdata *drvdata =3D dev_get_drvdata(ctcu->dev.parent); + int port; + + port =3D coresight_get_in_port(etr, ctcu); + if (port < 0 || port > 1) + return NULL; + + return &drvdata->byte_cntr_data[port]; +} + +static bool ctcu_byte_cntr_switch_buffer(struct tmc_drvdata *etr_drvdata, + struct ctcu_byte_cntr *byte_cntr_data) +{ + struct etr_buf_node *nd, *next, *curr_node =3D NULL, *picked_node =3D NUL= L; + struct etr_buf *curr_buf =3D etr_drvdata->sysfs_buf; + bool found_free_buf =3D false; + unsigned long flags; + + if (WARN_ON(!etr_drvdata || !byte_cntr_data)) + return false; + + /* Stop the ETR before initiating the switch */ + if (coresight_get_mode(etr_drvdata->csdev) !=3D CS_MODE_DISABLED) + tmc_etr_enable_disable_hw(etr_drvdata, false); + + /* + * Serialise the sysfs_buf/etr_buf swap against the ETR sink + * enable/disable paths which also touch these fields under the + * spinlock. tmc_etr_enable_disable_hw() takes the same lock, so it + * must be called outside this critical section. + */ + raw_spin_lock_irqsave(&etr_drvdata->spinlock, flags); + list_for_each_entry_safe(nd, next, &etr_drvdata->etr_buf_list, link) { + /* curr_buf is free for next round */ + if (nd->sysfs_buf =3D=3D curr_buf) { + nd->is_free =3D true; + curr_node =3D nd; + } else if (!found_free_buf && nd->is_free) { + picked_node =3D nd; + found_free_buf =3D true; + } + } + + if (found_free_buf) { + curr_node->pos =3D 0; + curr_node->reading =3D true; + byte_cntr_data->buf_node =3D curr_node; + etr_drvdata->sysfs_buf =3D picked_node->sysfs_buf; + etr_drvdata->etr_buf =3D picked_node->sysfs_buf; + picked_node->is_free =3D false; + /* Reset irq_cnt for next etr_buf */ + atomic_set(&byte_cntr_data->irq_cnt, 0); + } + raw_spin_unlock_irqrestore(&etr_drvdata->spinlock, flags); + + /* Restart the ETR once a free buffer is available */ + if (found_free_buf && + coresight_get_mode(etr_drvdata->csdev) !=3D CS_MODE_DISABLED) + tmc_etr_enable_disable_hw(etr_drvdata, true); + + return found_free_buf; +} + +/* + * ctcu_byte_cntr_get_data() - reads data from the deactivated and filled = buffer. + * The byte-cntr reading work reads data from the deactivated and filled b= uffer. + * The read operation waits for a buffer to become available, either fille= d or + * upon timeout, and then reads trace data from the synced buffer. + */ +static ssize_t tmc_byte_cntr_get_data(struct tmc_drvdata *etr_drvdata, lof= f_t pos, + size_t len, char **bufpp) +{ + struct coresight_device *ctcu =3D tmc_etr_get_ctcu_device(etr_drvdata); + struct device *dev =3D &etr_drvdata->csdev->dev; + struct ctcu_byte_cntr *byte_cntr_data; + struct etr_buf *sysfs_buf; + atomic_t *irq_cnt; + ssize_t actual; + int ret; + + byte_cntr_data =3D ctcu_get_byte_cntr(ctcu, etr_drvdata->csdev); + if (!byte_cntr_data || !byte_cntr_data->irq_enabled) + return -EINVAL; + + irq_cnt =3D &byte_cntr_data->irq_cnt; + +wait_buffer: + if (!byte_cntr_data->buf_node) { + ret =3D wait_event_interruptible_timeout(byte_cntr_data->wq, + (atomic_read(irq_cnt) >=3D MAX_IRQ_CNT - 1) || + !byte_cntr_data->enable, + BYTE_CNTR_TIMEOUT); + if (ret < 0) + return ret; + /* + * The current etr_buf is almost full or timeout is triggered, + * so switch the buffer and mark the switched buffer as reading. + */ + if (byte_cntr_data->enable) { + if (!ctcu_byte_cntr_switch_buffer(etr_drvdata, byte_cntr_data)) { + dev_err(dev, "Switch buffer failed for the byte-cntr\n"); + return -ENOMEM; + } + } else { + /* Exit byte-cntr reading */ + return 0; + } + } + + /* Check the status of current etr_buf */ + if (atomic_read(irq_cnt) >=3D MAX_IRQ_CNT) + dev_warn(dev, "Data overwrite happened\n"); + + pos =3D byte_cntr_data->buf_node->pos; + sysfs_buf =3D byte_cntr_data->buf_node->sysfs_buf; + actual =3D tmc_etr_read_sysfs_buf(sysfs_buf, pos, len, bufpp); + if (actual <=3D 0) { + /* Reset buf_node upon reading is finished or failed */ + byte_cntr_data->buf_node->reading =3D false; + byte_cntr_data->buf_node =3D NULL; + + /* + * Nothing in the buffer, waiting for the next buffer + * to be filled. + */ + if (actual =3D=3D 0) + goto wait_buffer; + } + + return actual; +} + +static int tmc_read_prepare_byte_cntr(struct tmc_drvdata *etr_drvdata) +{ + struct coresight_device *ctcu =3D tmc_etr_get_ctcu_device(etr_drvdata); + struct ctcu_byte_cntr *byte_cntr_data; + unsigned long flags; + int ret =3D 0; + + /* byte-cntr is operating with SYSFS mode being enabled only */ + if (coresight_get_mode(etr_drvdata->csdev) !=3D CS_MODE_SYSFS) + return -EINVAL; + + byte_cntr_data =3D ctcu_get_byte_cntr(ctcu, etr_drvdata->csdev); + if (!byte_cntr_data || !byte_cntr_data->irq_enabled) + return -EINVAL; + + raw_spin_lock_irqsave(&byte_cntr_data->spin_lock, flags); + if (byte_cntr_data->reading) { + raw_spin_unlock_irqrestore(&byte_cntr_data->spin_lock, flags); + return -EBUSY; + } + + /* byte_cntr_data->enable may race with ctcu_platform_remove() */ + if (!byte_cntr_data->enable) { + raw_spin_unlock_irqrestore(&byte_cntr_data->spin_lock, flags); + return -ENODEV; + } + + byte_cntr_data->reading =3D true; + raw_spin_unlock_irqrestore(&byte_cntr_data->spin_lock, flags); + /* Setup an available etr_buf_list for byte-cntr */ + ret =3D tmc_create_etr_buf_list(etr_drvdata, 2); + if (ret) { + byte_cntr_data->reading =3D false; + return ret; + } + + scoped_guard(raw_spinlock_irqsave, &byte_cntr_data->spin_lock) { + atomic_set(&byte_cntr_data->irq_cnt, 0); + /* + * Configure the byte-cntr register to enable IRQ. The + * configured size is 5% of the buffer_size. + */ + ctcu_cfg_byte_cntr_reg(byte_cntr_data->ctcu_drvdata, + etr_drvdata->size / MAX_IRQ_CNT, + byte_cntr_data->irq_ctrl_offset); + byte_cntr_data->buf_node =3D NULL; + } + /* enable_irq_wake() may sleep on slow-bus irqchips, call it unlocked */ + enable_irq_wake(byte_cntr_data->irq); + + return 0; +} + +static int tmc_read_unprepare_byte_cntr(struct tmc_drvdata *etr_drvdata) +{ + struct coresight_device *ctcu =3D tmc_etr_get_ctcu_device(etr_drvdata); + struct ctcu_byte_cntr *byte_cntr_data; + + /* + * Do the unprepare operation only when the byte_cntr_data->reading + * is truly set + */ + byte_cntr_data =3D ctcu_get_byte_cntr(ctcu, etr_drvdata->csdev); + if (!byte_cntr_data || !byte_cntr_data->irq_enabled || + !byte_cntr_data->reading) + return -EINVAL; + + tmc_clean_etr_buf_list(etr_drvdata); + scoped_guard(raw_spinlock_irqsave, &byte_cntr_data->spin_lock) { + /* Configure the byte-cntr register to disable IRQ */ + ctcu_cfg_byte_cntr_reg(byte_cntr_data->ctcu_drvdata, 0, + byte_cntr_data->irq_ctrl_offset); + byte_cntr_data->buf_node =3D NULL; + byte_cntr_data->reading =3D false; + } + /* + * The threshold IRQ is already disabled by the register write above, + * so no wake event can arrive here. disable_irq_wake() may sleep on + * slow-bus irqchips, so call it outside the spin_lock. + */ + disable_irq_wake(byte_cntr_data->irq); + wake_up(&byte_cntr_data->wq); + + return 0; +} + +const struct tmc_sysfs_ops byte_cntr_sysfs_ops =3D { + .read_prepare =3D tmc_read_prepare_byte_cntr, + .read_unprepare =3D tmc_read_unprepare_byte_cntr, + .get_trace_data =3D tmc_byte_cntr_get_data, +}; + +/* Start the byte-cntr function when the path is enabled. */ +void ctcu_byte_cntr_start(struct coresight_device *csdev, struct coresight= _path *path) +{ + struct coresight_device *sink =3D coresight_get_sink(path); + struct ctcu_byte_cntr *byte_cntr_data; + + byte_cntr_data =3D ctcu_get_byte_cntr(csdev, sink); + if (!byte_cntr_data) + return; + + /* Don't start byte-cntr function when irq_enabled is not set. */ + if (!byte_cntr_data->irq_enabled || byte_cntr_data->enable) + return; + + guard(raw_spinlock_irqsave)(&byte_cntr_data->spin_lock); + byte_cntr_data->enable =3D true; +} + +/* Stop the byte-cntr function when the path is disabled. */ +void ctcu_byte_cntr_stop(struct coresight_device *csdev, struct coresight_= path *path) +{ + struct coresight_device *sink =3D coresight_get_sink(path); + struct ctcu_byte_cntr *byte_cntr_data; + + if (coresight_get_mode(sink) =3D=3D CS_MODE_SYSFS) + return; + + byte_cntr_data =3D ctcu_get_byte_cntr(csdev, sink); + if (!byte_cntr_data) + return; + + guard(raw_spinlock_irqsave)(&byte_cntr_data->spin_lock); + byte_cntr_data->enable =3D false; +} + +void ctcu_byte_cntr_init(struct device *dev, struct ctcu_drvdata *drvdata,= int etr_num) +{ + struct ctcu_byte_cntr *byte_cntr_data; + struct device_node *nd =3D dev->of_node; + int irq_num, ret, i, irq_registered =3D 0; + + for (i =3D 0; i < etr_num; i++) { + byte_cntr_data =3D &drvdata->byte_cntr_data[i]; + irq_num =3D of_irq_get(nd, i); + if (irq_num < 0) { + dev_err(dev, "Failed to get IRQ from DT for port%d\n", i); + continue; + } + + ret =3D devm_request_irq(dev, irq_num, byte_cntr_handler, + IRQF_TRIGGER_RISING | IRQF_SHARED, + dev_name(dev), byte_cntr_data); + if (ret) { + dev_err(dev, "Failed to register IRQ for port%d\n", i); + continue; + } + + byte_cntr_data->irq =3D irq_num; + byte_cntr_data->ctcu_drvdata =3D drvdata; + init_waitqueue_head(&byte_cntr_data->wq); + raw_spin_lock_init(&byte_cntr_data->spin_lock); + irq_registered++; + } + + if (irq_registered) + tmc_etr_set_byte_cntr_sysfs_ops(&byte_cntr_sysfs_ops); +} diff --git a/drivers/hwtracing/coresight/coresight-ctcu-core.c b/drivers/hw= tracing/coresight/coresight-ctcu-core.c index e8720026c9e3..2da1a6f3d29f 100644 --- a/drivers/hwtracing/coresight/coresight-ctcu-core.c +++ b/drivers/hwtracing/coresight/coresight-ctcu-core.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights res= erved. + * Copyright (c) 2024-2026 Qualcomm Innovation Center, Inc. All rights res= erved. + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ =20 #include @@ -18,6 +19,7 @@ =20 #include "coresight-ctcu.h" #include "coresight-priv.h" +#include "coresight-tmc.h" =20 #define ctcu_writel(drvdata, val, offset) __raw_writel((val), drvdata->bas= e + offset) #define ctcu_readl(drvdata, offset) __raw_readl(drvdata->base + offset) @@ -43,17 +45,21 @@ =20 #define CTCU_ATID_REG_BIT(traceid) (traceid % 32) #define CTCU_ATID_REG_SIZE 0x10 +#define CTCU_ETR0_IRQCTRL 0x6c +#define CTCU_ETR1_IRQCTRL 0x70 #define CTCU_ETR0_ATID0 0xf8 #define CTCU_ETR1_ATID0 0x108 =20 static const struct ctcu_etr_config sa8775p_etr_cfgs[] =3D { { - .atid_offset =3D CTCU_ETR0_ATID0, - .port_num =3D 0, + .atid_offset =3D CTCU_ETR0_ATID0, + .irq_ctrl_offset =3D CTCU_ETR0_IRQCTRL, + .port_num =3D 0, }, { - .atid_offset =3D CTCU_ETR1_ATID0, - .port_num =3D 1, + .atid_offset =3D CTCU_ETR1_ATID0, + .irq_ctrl_offset =3D CTCU_ETR1_IRQCTRL, + .port_num =3D 1, }, }; =20 @@ -62,6 +68,85 @@ static const struct ctcu_config sa8775p_cfgs =3D { .num_etr_config =3D ARRAY_SIZE(sa8775p_etr_cfgs), }; =20 +void ctcu_program_register(struct ctcu_drvdata *drvdata, u32 val, u32 offs= et) +{ + CS_UNLOCK(drvdata->base); + ctcu_writel(drvdata, val, offset); + CS_LOCK(drvdata->base); +} + +static ssize_t irq_enabled_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct ctcu_byte_cntr_irq_attribute *irq_attr =3D + container_of(attr, struct ctcu_byte_cntr_irq_attribute, attr); + struct ctcu_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + u8 port =3D irq_attr->port; + + if (!drvdata->byte_cntr_data[port].irq_ctrl_offset) + return -EINVAL; + + return sysfs_emit(buf, "%u\n", + (unsigned int)drvdata->byte_cntr_data[port].irq_enabled); +} + +static ssize_t irq_enabled_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t size) +{ + struct ctcu_byte_cntr_irq_attribute *irq_attr =3D + container_of(attr, struct ctcu_byte_cntr_irq_attribute, attr); + struct ctcu_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + u8 port =3D irq_attr->port; + unsigned long val; + + if (kstrtoul(buf, 0, &val)) + return -EINVAL; + + guard(raw_spinlock_irqsave)(&drvdata->byte_cntr_data[port].spin_lock); + if (drvdata->byte_cntr_data[port].reading) + return -EBUSY; + else if (drvdata->byte_cntr_data[port].irq_ctrl_offset) + drvdata->byte_cntr_data[port].irq_enabled =3D !!val; + + return size; +} + +static umode_t irq_enabled_is_visible(struct kobject *kobj, + struct attribute *attr, int n) +{ + struct device_attribute *dev_attr =3D + container_of(attr, struct device_attribute, attr); + struct ctcu_byte_cntr_irq_attribute *irq_attr =3D + container_of(dev_attr, struct ctcu_byte_cntr_irq_attribute, attr); + struct device *dev =3D kobj_to_dev(kobj); + struct ctcu_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + u8 port =3D irq_attr->port; + + if (drvdata && drvdata->byte_cntr_data[port].irq_ctrl_offset) + return attr->mode; + + return 0; +} + +static struct attribute *ctcu_attrs[] =3D { + ctcu_byte_cntr_irq_rw(0), + ctcu_byte_cntr_irq_rw(1), + NULL, +}; + +static struct attribute_group ctcu_attr_grp =3D { + .attrs =3D ctcu_attrs, + .is_visible =3D irq_enabled_is_visible, +}; + +static const struct attribute_group *ctcu_attr_grps[] =3D { + &ctcu_attr_grp, + NULL, +}; + static void ctcu_program_atid_register(struct ctcu_drvdata *drvdata, u32 r= eg_offset, u8 bit, bool enable) { @@ -140,11 +225,15 @@ static int ctcu_set_etr_traceid(struct coresight_devi= ce *csdev, struct coresight static int ctcu_enable(struct coresight_device *csdev, enum cs_mode mode, struct coresight_path *path) { + ctcu_byte_cntr_start(csdev, path); + return ctcu_set_etr_traceid(csdev, path, true); } =20 static int ctcu_disable(struct coresight_device *csdev, struct coresight_p= ath *path) { + ctcu_byte_cntr_stop(csdev, path); + return ctcu_set_etr_traceid(csdev, path, false); } =20 @@ -195,7 +284,10 @@ static int ctcu_probe(struct platform_device *pdev) for (i =3D 0; i < cfgs->num_etr_config; i++) { etr_cfg =3D &cfgs->etr_cfgs[i]; drvdata->atid_offset[i] =3D etr_cfg->atid_offset; + drvdata->byte_cntr_data[i].irq_ctrl_offset =3D + etr_cfg->irq_ctrl_offset; } + ctcu_byte_cntr_init(dev, drvdata, cfgs->num_etr_config); } } =20 @@ -209,6 +301,7 @@ static int ctcu_probe(struct platform_device *pdev) desc.dev =3D dev; desc.ops =3D &ctcu_ops; desc.access =3D CSDEV_ACCESS_IOMEM(base); + desc.groups =3D ctcu_attr_grps; raw_spin_lock_init(&drvdata->spin_lock); =20 drvdata->csdev =3D coresight_register(&desc); @@ -244,10 +337,34 @@ static int ctcu_platform_probe(struct platform_device= *pdev) static void ctcu_platform_remove(struct platform_device *pdev) { struct ctcu_drvdata *drvdata =3D platform_get_drvdata(pdev); + struct ctcu_byte_cntr *byte_cntr_data; + unsigned long flags; + int i; =20 if (WARN_ON(!drvdata)) return; =20 + /* + * Signal all active byte-cntr readers to exit, then wait for them to + * finish before resetting the ops pointer and freeing driver data. + * Without this, a reader blocked in wait_event_interruptible_timeout() + * would access the freed ctcu_drvdata wait-queue head (use-after-free). + */ + for (i =3D 0; i < ETR_MAX_NUM; i++) { + byte_cntr_data =3D &drvdata->byte_cntr_data[i]; + raw_spin_lock_irqsave(&byte_cntr_data->spin_lock, flags); + /* Set enable=3Dfalse for all ports to signal teardown to racing readers= */ + byte_cntr_data->enable =3D false; + if (!byte_cntr_data->reading) { + raw_spin_unlock_irqrestore(&byte_cntr_data->spin_lock, flags); + continue; + } + raw_spin_unlock_irqrestore(&byte_cntr_data->spin_lock, flags); + wake_up_all(&byte_cntr_data->wq); + wait_event(byte_cntr_data->wq, !byte_cntr_data->reading); + } + + tmc_etr_reset_byte_cntr_sysfs_ops(); ctcu_remove(pdev); pm_runtime_disable(&pdev->dev); } diff --git a/drivers/hwtracing/coresight/coresight-ctcu.h b/drivers/hwtraci= ng/coresight/coresight-ctcu.h index e9594c38dd91..a2ae0a0d91d0 100644 --- a/drivers/hwtracing/coresight/coresight-ctcu.h +++ b/drivers/hwtracing/coresight/coresight-ctcu.h @@ -1,23 +1,31 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights res= erved. + * Copyright (c) 2024-2026 Qualcomm Innovation Center, Inc. All rights res= erved. + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ =20 #ifndef _CORESIGHT_CTCU_H #define _CORESIGHT_CTCU_H + +#include #include "coresight-trace-id.h" =20 /* Maximum number of supported ETR devices for a single CTCU. */ #define ETR_MAX_NUM 2 =20 +#define BYTE_CNTR_TIMEOUT (3 * HZ) +#define MAX_IRQ_CNT 20 + /** * struct ctcu_etr_config * @atid_offset: offset to the ATID0 Register. - * @port_num: in-port number of CTCU device that connected to ETR. + * @port_num: in-port number of the CTCU device that connected to ETR. + * @irq_ctrl_offset: offset to the BYTECNTRVAL register. */ struct ctcu_etr_config { const u32 atid_offset; const u32 port_num; + const u32 irq_ctrl_offset; }; =20 struct ctcu_config { @@ -25,15 +33,68 @@ struct ctcu_config { int num_etr_config; }; =20 -struct ctcu_drvdata { - void __iomem *base; - struct clk *apb_clk; - struct device *dev; - struct coresight_device *csdev; +/** + * struct ctcu_byte_cntr + * @enable: indicates that byte_cntr function is enabled or not. + * @irq_enabled: indicates that the interruption is enabled. + * @reading: indicates that byte_cntr is reading. + * @irq: allocated number of the IRQ. + * @irq_cnt: IRQ count number of the triggered interruptions. + * @wq: waitqueue for reading data from ETR buffer. + * @spin_lock: spinlock of the byte_cntr_data. + * @irq_ctrl_offset: offset to the BYTECNTVAL Register. + * @ctcu_drvdata: drvdata of the CTCU device. + * @buf_node: etr_buf_node for reading. + */ +struct ctcu_byte_cntr { + bool enable; + bool irq_enabled; + bool reading; + int irq; + atomic_t irq_cnt; + wait_queue_head_t wq; raw_spinlock_t spin_lock; - u32 atid_offset[ETR_MAX_NUM]; - /* refcnt for each traceid of each sink */ - u8 traceid_refcnt[ETR_MAX_NUM][CORESIGHT_TRACE_ID_RES_TOP]; + u32 irq_ctrl_offset; + struct ctcu_drvdata *ctcu_drvdata; + struct etr_buf_node *buf_node; }; =20 +struct ctcu_drvdata { + void __iomem *base; + struct clk *apb_clk; + struct device *dev; + struct coresight_device *csdev; + struct ctcu_byte_cntr byte_cntr_data[ETR_MAX_NUM]; + raw_spinlock_t spin_lock; + u32 atid_offset[ETR_MAX_NUM]; + /* refcnt for each traceid of each sink */ + u8 traceid_refcnt[ETR_MAX_NUM][CORESIGHT_TRACE_ID_RES_TOP]; +}; + +/** + * struct ctcu_byte_cntr_irq_attribute + * @attr: The device attribute. + * @port: port number. + */ +struct ctcu_byte_cntr_irq_attribute { + struct device_attribute attr; + u8 port; +}; + +#define ctcu_byte_cntr_irq_rw(port) \ + (&((struct ctcu_byte_cntr_irq_attribute[]) { \ + { \ + __ATTR(irq_enabled##port, 0644, irq_enabled_show, \ + irq_enabled_store), \ + port, \ + } \ + })[0].attr.attr) + +void ctcu_program_register(struct ctcu_drvdata *drvdata, u32 val, u32 offs= et); + +/* Byte-cntr functions */ +void ctcu_byte_cntr_start(struct coresight_device *csdev, struct coresight= _path *path); +void ctcu_byte_cntr_stop(struct coresight_device *csdev, struct coresight_= path *path); +void ctcu_byte_cntr_init(struct device *dev, struct ctcu_drvdata *drvdata,= int port_num); + #endif diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwt= racing/coresight/coresight-tmc-core.c index 4b40b692be4d..6ad09995ba87 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-core.c +++ b/drivers/hwtracing/coresight/coresight-tmc-core.c @@ -293,7 +293,8 @@ static ssize_t tmc_read(struct file *file, char __user = *data, size_t len, return -EFAULT; } =20 - *ppos +=3D actual; + if (!tmc_etr_update_buf_node_pos(drvdata, actual)) + *ppos +=3D actual; dev_dbg(&drvdata->csdev->dev, "%zu bytes copied\n", actual); =20 return actual; diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtr= acing/coresight/coresight-tmc-etr.c index 2b26ce6455a7..e78f8891f11e 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -1168,6 +1168,9 @@ static int tmc_etr_enable_hw(struct tmc_drvdata *drvd= ata, return rc; } =20 +/* Assumes a single CTCU instance per system, as on all current Qualcomm S= oCs. */ +static const struct tmc_sysfs_ops *byte_cntr_sysfs_ops; + /* * Return the available trace data in the buffer (starts at etr_buf->offse= t, * limited by etr_buf->len) from @pos, with a maximum limit of @len, @@ -1178,23 +1181,39 @@ static int tmc_etr_enable_hw(struct tmc_drvdata *dr= vdata, * We are protected here by drvdata->reading !=3D 0, which ensures the * sysfs_buf stays alive. */ -ssize_t tmc_etr_get_sysfs_trace(struct tmc_drvdata *drvdata, - loff_t pos, size_t len, char **bufpp) +ssize_t tmc_etr_read_sysfs_buf(struct etr_buf *sysfs_buf, loff_t pos, + size_t len, char **bufpp) { s64 offset; ssize_t actual =3D len; - struct etr_buf *etr_buf =3D drvdata->sysfs_buf; =20 - if (pos + actual > etr_buf->len) - actual =3D etr_buf->len - pos; + if (pos + actual > sysfs_buf->len) + actual =3D sysfs_buf->len - pos; if (actual <=3D 0) return actual; =20 /* Compute the offset from which we read the data */ - offset =3D etr_buf->offset + pos; - if (offset >=3D etr_buf->size) - offset -=3D etr_buf->size; - return tmc_etr_buf_get_data(etr_buf, offset, actual, bufpp); + offset =3D sysfs_buf->offset + pos; + if (offset >=3D sysfs_buf->size) + offset -=3D sysfs_buf->size; + return tmc_etr_buf_get_data(sysfs_buf, offset, actual, bufpp); +} +EXPORT_SYMBOL_GPL(tmc_etr_read_sysfs_buf); + +ssize_t tmc_etr_get_sysfs_trace(struct tmc_drvdata *drvdata, + loff_t pos, size_t len, char **bufpp) +{ + ssize_t ret; + const struct tmc_sysfs_ops *byte_cntr_ops =3D READ_ONCE(byte_cntr_sysfs_o= ps); + + if (byte_cntr_ops) { + ret =3D byte_cntr_ops->get_trace_data(drvdata, pos, len, bufpp); + /* Return the filled buffer */ + if (ret > 0 || ret =3D=3D -ENOMEM) + return ret; + } + + return tmc_etr_read_sysfs_buf(drvdata->sysfs_buf, pos, len, bufpp); } =20 static struct etr_buf * @@ -1248,6 +1267,39 @@ static void __tmc_etr_disable_hw(struct tmc_drvdata = *drvdata) =20 } =20 +static void tmc_etr_reset_sysfs_buf(struct tmc_drvdata *drvdata) +{ + u32 sts; + + CS_UNLOCK(drvdata->base); + tmc_write_rrp(drvdata, drvdata->sysfs_buf->hwaddr); + tmc_write_rwp(drvdata, drvdata->sysfs_buf->hwaddr); + sts =3D readl_relaxed(drvdata->base + TMC_STS) & ~TMC_STS_FULL; + writel_relaxed(sts, drvdata->base + TMC_STS); + CS_LOCK(drvdata->base); +} + +/** + * tmc_etr_enable_disable_hw - enable/disable the ETR hw. + * @drvdata: drvdata of the TMC device. + * @enable: indicates enable/disable. + */ +void tmc_etr_enable_disable_hw(struct tmc_drvdata *drvdata, bool enable) +{ + unsigned long flags; + + raw_spin_lock_irqsave(&drvdata->spinlock, flags); + if (enable) { + tmc_etr_reset_sysfs_buf(drvdata); + __tmc_etr_enable_hw(drvdata); + } else { + __tmc_etr_disable_hw(drvdata); + } + + raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); +} +EXPORT_SYMBOL_GPL(tmc_etr_enable_disable_hw); + void tmc_etr_disable_hw(struct tmc_drvdata *drvdata) { __tmc_etr_disable_hw(drvdata); @@ -2068,15 +2120,54 @@ int tmc_create_etr_buf_list(struct tmc_drvdata *drv= data, int num_nodes) } EXPORT_SYMBOL_GPL(tmc_create_etr_buf_list); =20 +void tmc_etr_set_byte_cntr_sysfs_ops(const struct tmc_sysfs_ops *sysfs_ops) +{ + WRITE_ONCE(byte_cntr_sysfs_ops, sysfs_ops); +} +EXPORT_SYMBOL_GPL(tmc_etr_set_byte_cntr_sysfs_ops); + +void tmc_etr_reset_byte_cntr_sysfs_ops(void) +{ + WRITE_ONCE(byte_cntr_sysfs_ops, NULL); +} +EXPORT_SYMBOL_GPL(tmc_etr_reset_byte_cntr_sysfs_ops); + +bool tmc_etr_update_buf_node_pos(struct tmc_drvdata *drvdata, ssize_t size) +{ + struct etr_buf_node *nd, *next; + + if (drvdata->config_type !=3D TMC_CONFIG_TYPE_ETR) + return false; + + list_for_each_entry_safe(nd, next, &drvdata->etr_buf_list, link) { + if (nd && nd->reading) { + nd->pos +=3D size; + return true; + } + } + + return false; +} + int tmc_read_prepare_etr(struct tmc_drvdata *drvdata) { int ret =3D 0; unsigned long flags; + const struct tmc_sysfs_ops *byte_cntr_ops; =20 /* config types are set a boot time and never change */ if (WARN_ON_ONCE(drvdata->config_type !=3D TMC_CONFIG_TYPE_ETR)) return -EINVAL; =20 + byte_cntr_ops =3D READ_ONCE(byte_cntr_sysfs_ops); + if (byte_cntr_ops) { + ret =3D byte_cntr_ops->read_prepare(drvdata); + if (!ret || ret =3D=3D -EBUSY) + return ret; + + ret =3D 0; + } + raw_spin_lock_irqsave(&drvdata->spinlock, flags); if (drvdata->reading) { ret =3D -EBUSY; @@ -2108,11 +2199,17 @@ int tmc_read_unprepare_etr(struct tmc_drvdata *drvd= ata) { unsigned long flags; struct etr_buf *sysfs_buf =3D NULL; + const struct tmc_sysfs_ops *byte_cntr_ops; =20 /* config types are set a boot time and never change */ if (WARN_ON_ONCE(drvdata->config_type !=3D TMC_CONFIG_TYPE_ETR)) return -EINVAL; =20 + byte_cntr_ops =3D READ_ONCE(byte_cntr_sysfs_ops); + if (byte_cntr_ops) + if (!byte_cntr_ops->read_unprepare(drvdata)) + return 0; + raw_spin_lock_irqsave(&drvdata->spinlock, flags); =20 /* RE-enable the TMC if need be */ diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracin= g/coresight/coresight-tmc.h index fbb015079872..a15e2f93f16a 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.h +++ b/drivers/hwtracing/coresight/coresight-tmc.h @@ -211,12 +211,15 @@ struct tmc_resrv_buf { /** * @sysfs_buf: Allocated sysfs_buf. * @is_free: Indicates whether the buffer is free to choose. + * @reading: Indicates byte_cntr is reading the buffer attached to + * the node. * @pos: Offset to the start of the buffer. * @link: list_head of the node. */ struct etr_buf_node { struct etr_buf *sysfs_buf; bool is_free; + bool reading; loff_t pos; struct list_head link; }; @@ -480,5 +483,11 @@ struct etr_buf *tmc_etr_get_buffer(struct coresight_de= vice *csdev, extern const struct attribute_group coresight_etr_group; void tmc_clean_etr_buf_list(struct tmc_drvdata *drvdata); int tmc_create_etr_buf_list(struct tmc_drvdata *drvdata, int num_nodes); +void tmc_etr_set_byte_cntr_sysfs_ops(const struct tmc_sysfs_ops *sysfs_ops= ); +void tmc_etr_reset_byte_cntr_sysfs_ops(void); +void tmc_etr_enable_disable_hw(struct tmc_drvdata *drvdata, bool enable); +bool tmc_etr_update_buf_node_pos(struct tmc_drvdata *drvdata, ssize_t size= ); +ssize_t tmc_etr_read_sysfs_buf(struct etr_buf *sysfs_buf, loff_t pos, + size_t len, char **bufpp); =20 #endif --=20 2.34.1 From nobody Sun Jun 28 10:37:02 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 389D5386552 for ; Thu, 25 Jun 2026 10:47:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782384424; cv=none; b=Bu+ipGdUDFx9BmSp0rESSxMA1jNT1M9s1jYE0dzAK4kfzFnjUjMd4Z1UgGpRHKopDgWONUCIN7sO64ZQpL07wGqpLdxtal8nrcbJc+cp+BkZ59bOKYLvd6GOztBQLZ7zmPJnNjVtBNNxxggJvFeTXkaFEZMP7YqloWm81FjzMFc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782384424; c=relaxed/simple; bh=CUIELfXlwJTfTZB2/mLXR2/oqYjuzytsMwJ/vjvrA64=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ANL+V/0EZNwDtZVtOa5igxBdaDQofc8JkjwMbwq6tixgAn9Sq5Qx9fa+YKD1B5gCxPadMZykaKP0ak3kDUS5RTGydwvPVfgkFGq0VnxzhtUQpmUK93W9rZJLbuFIlekzIJw3biSKsrLMkuaI9gANWSojylKeYNDd+P4CH50EL2Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=fk548a1p; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=LDtIGbwQ; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="fk548a1p"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="LDtIGbwQ" Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 65P9k1tK1724353 for ; Thu, 25 Jun 2026 10:47:02 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= amQLXC3mPMBsoTlzFWETG088elIkyj3mulEteTG2VJY=; b=fk548a1p1uV29Ju7 HiKgi7JjavYI3l9tEWsM+32xETGNOwmd//wdEPeROdcxi6tpSdOEAv8TP6glRzz+ xfmZHlrscoW5mL9oxQRYsike4DhOAPMem9lm5w5Eyz+oW1ctlSw16up6NcpaIbCb FEvS/jZpXjTcKbtCj+dvb7xJghvocdP4oGIn25Nq4F8rRLx6qGLrOVnGcXGva0nq T7cjiaTDvb1En44a5eK4bvu/UowrQFHX548z9h/irPuFBf7WpSoubFOnPa2ZoGon ekwc8Mm+PyCOSfysnCrFebyCxchHlGsNecJy0TEwkdZ4ftZXz0RG3a2IkEEqSDht fn7ZVw== Received: from mail-pl1-f199.google.com (mail-pl1-f199.google.com [209.85.214.199]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4f0j7duwms-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Thu, 25 Jun 2026 10:47:02 +0000 (GMT) Received: by mail-pl1-f199.google.com with SMTP id d9443c01a7336-2c79e5de32cso18327885ad.2 for ; Thu, 25 Jun 2026 03:47:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1782384421; x=1782989221; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=amQLXC3mPMBsoTlzFWETG088elIkyj3mulEteTG2VJY=; b=LDtIGbwQm3BeEOXMGiWyrlMMKZObhhAU8jeFjVL9bsZjUdUQu6Nf4srDSqP9oPMWZ5 VaBidNS9Q6n4FelGRLESTQdAiF0FdhFwAnmIkHFzsIgCXyZHsq58yBzrCpj6+ojZ6+uY lJ4MbzR8JTXCY3z2jL6fOLUJs5tsFu4ilCYwZ0eezaB5n+kjkCCIFhMVWu5LwXVHLf8b ZhlG6q/Gp1zA5YoArpbnZDuZWDTS3G391jo53DV2zlsp4cwr2qrZ4lBsZAIHz4vry4zR E6XaGVdq9alAFQqCEy+nYaJhFuosElU7N/QT3MIesAbZiIMrnCBcvScRQTTMruZZK/f6 jcWQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1782384421; x=1782989221; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=amQLXC3mPMBsoTlzFWETG088elIkyj3mulEteTG2VJY=; b=lVIFIBojf7xWvvdgSzyLLB/qUBZSdCfDsXSch2uRLbcNhs9fIs5kJpgntnwsgv8DXR Py19gmR5sqAE2Ni5f1zFQQmQat/QPttpzHnDGnmwz5qjQZcPK7mf6oODEOFvdQ8ejzKR +dft24s38qEltUHechM1N4oJRDINwipiNycWH/uMMs3CT9YoUx4d24z1bOv/BFIu7LR1 CldtffBULkic8BXWg3a3q6fBveWo1lIJQWCnvdVeBKrlHcuEyrE9yG/e1dtODqN1T1Xq QEtDgJU5W3AKP8oLaqk+9x0BQhShLd7+wumRrRp0RFhzCr+0lZVcZ8R/u6Q0JDUGCINm rtbA== X-Forwarded-Encrypted: i=1; AHgh+RpD6weeDr0onk+VmUvE0P/MqbGsBm2lwzw4dFWz8dqHnNrOWey123bliA6vbkblaeLr70al7e5qTXDE9gs=@vger.kernel.org X-Gm-Message-State: AOJu0YytlMRQeJrpoUSdVqsbNBWOFfa2NUVnU4PK4ZceNXMcs2nFuOMZ METD+qDsHBKLROUYrLQJNfR5k6igpVfeQZcYlfCpcbxou06xtaFLpK/cdw13Q3efQ5dKb5YrmcI 1Xb31B3s7KoIHjVip8zp6P9JmOacFdeKBzO1/9xT5c6/49zm5DAeBHdz7SvdM5Wkc1fhFzn9eP8 TOpQ== X-Gm-Gg: AfdE7cmhOdKYgc/cTB34jgRFqbBNgVOhpbjsC7nTxBWEDsj6CxKhpZRP5KuNijHoQGh uNLFl2cFKcIUQi66Xa06jcItYxhGVLaya/A5SKNmAbo+O6ILy9sRtxCtWoQqsvszBQFh4K9AodQ U6W7rpS0vuwcCCmC0tn+HLLE0mc9KETzLUxWh6x4vNnUvm5QTby3qjUbez/p2OmsA/INSLB8K0L 0LA0vlnyJGBcGq8pp9SUmFnRFdYjT4YseqggmJ7FnLE/v4mr/fTnlnxYF8ofIiTrb2aPwkOwOd4 0fwBCUp/uXpnp+O9ruuFXmZqmhkd9EiZ+4WUeiyk/uMxwWcxsTht9Tcc6dy5+1cCDdSlFTExlg5 yKNVQ+MN+cSniKK4OD3XhAqfsT5M6XE9e0M2xUYLtrgUb2fQd8jesgn8KFvLDbq0wrmvjsTlKbA == X-Received: by 2002:a17:903:1a08:b0:2c7:f7bc:633e with SMTP id d9443c01a7336-2c7fc743afbmr21143175ad.13.1782384421148; Thu, 25 Jun 2026 03:47:01 -0700 (PDT) X-Received: by 2002:a17:903:1a08:b0:2c7:f7bc:633e with SMTP id d9443c01a7336-2c7fc743afbmr21142825ad.13.1782384420687; Thu, 25 Jun 2026 03:47:00 -0700 (PDT) Received: from jiegan-gv.ap.qualcomm.com (tpe-colo-wan-fw-bordernet.qualcomm.com. [103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2c7f63d58e9sm17114035ad.60.2026.06.25.03.46.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Jun 2026 03:47:00 -0700 (PDT) From: Jie Gan Date: Thu, 25 Jun 2026 18:45:57 +0800 Subject: [PATCH v19 7/7] arm64: dts: qcom: lemans: add interrupts to CTCU device Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260625-enable-byte-cntr-for-ctcu-v19-7-8fbbf22e8381@oss.qualcomm.com> References: <20260625-enable-byte-cntr-for-ctcu-v19-0-8fbbf22e8381@oss.qualcomm.com> In-Reply-To: <20260625-enable-byte-cntr-for-ctcu-v19-0-8fbbf22e8381@oss.qualcomm.com> To: Suzuki K Poulose , Mike Leach , James Clark , Leo Yan , Alexander Shishkin , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Tingwei Zhang , Jie Gan , Bjorn Andersson , Konrad Dybcio , Yuanfang Zhang , Mao Jinlong Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1782384373; l=769; i=jie.gan@oss.qualcomm.com; s=20250909; h=from:subject:message-id; bh=CUIELfXlwJTfTZB2/mLXR2/oqYjuzytsMwJ/vjvrA64=; b=peF9+aYTtaL21BpUX6WUviTZt97HLGhKOLkRbA+DSbfmcO8COqsEDQ4DiHiwh/Fa3HzjlN0UH tXcMvfWfVCTCJC5ldseja94DiRiDIVDztU6S8YZ+EiWMXc1yjECxhxT X-Developer-Key: i=jie.gan@oss.qualcomm.com; a=ed25519; pk=3LxxUZRPCNkvPDlWOvXfJNqNO4SfGdy3eghMb8puHuk= X-Proofpoint-GUID: qRDeq40tjWQbvPIibYt6v3K6SvBZC45n X-Authority-Analysis: v=2.4 cv=NvHhtcdJ c=1 sm=1 tr=0 ts=6a3d0726 cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=EUspDBNiAAAA:8 a=gBkj9RZkAcI1HbXH1KoA:9 a=QEXdDO2ut3YA:10 a=324X-CrmTo6CU4MGRt3R:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwNjI1MDA5MiBTYWx0ZWRfX7ouujVRvDSHF aRQbwHkNdvvrYulosfvCS3bMgmP0zThHpKdSMWCSbZK3LPNM5HtsiiQOajHzDOTGUnbDgC7Pix3 G8nm7FvVLZY+o6vokHhhGP4itddsOOE= X-Proofpoint-ORIG-GUID: qRDeq40tjWQbvPIibYt6v3K6SvBZC45n X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjI1MDA5MiBTYWx0ZWRfX/q/O0+yfPfqp HJJH2lBRD231jqTF3/PXQtBG+fGI1TbQokeyxlIjwnng3vCsnAvYhVkGcnXl8pEZ9NdxYGRVPQV bvqmCt6hb7XfcenY1pIJUytOKiFYcyRT2CX5iDi/iVREwXsxbi2qksrg0jiDvsXCceyC7RqkaKB 7wX+G/S19ltfA5dH5d4jFu34NlInwOE3mj/2hXC00G6BRsTfJiMceaHl/pOrlnU8TM6s+4zbgM/ ANg1TddlYhQCwEIyU0kzlWXpbFWLLmnRFSPD2Jn8A+jDHy2H5NR/CokSnz8zYvZ9A5EZ3GT8yax bWG4odNukoXzALV5bOGB5t6ba5cdNcwADCIFEJ3WBfSQGGbkSqtq+wj+Qr7nuQyVOYKkUrZjOsD NoT62D9mF3zxJn9Xv0yadNPNvU5h0H6KdDvnJ3T9c10J+/YA8xOU5Q5ZFn6eA9nbIcogAV1GRm5 ty/dWL0MdKuPPNGPusw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-25_01,2026-06-24_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 priorityscore=1501 suspectscore=0 adultscore=0 impostorscore=0 phishscore=0 spamscore=0 bulkscore=0 lowpriorityscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2606250092 Add interrupts to enable byte-cntr function for TMC ETR devices. Reviewed-by: Konrad Dybcio Signed-off-by: Jie Gan --- arch/arm64/boot/dts/qcom/lemans.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qco= m/lemans.dtsi index 353a6e6fd3ac..2b4debc39db0 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -3150,6 +3150,9 @@ ctcu@4001000 { clocks =3D <&aoss_qmp>; clock-names =3D "apb"; =20 + interrupts =3D , + ; + in-ports { #address-cells =3D <1>; #size-cells =3D <0>; --=20 2.34.1