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charset="utf-8" On s390 systems, which use a machine level hypervisor, PCI devices are always accessed through a form of PCI pass-through which fundamentally operates on a per PCI function granularity. This is also reflected in the s390 PCI hotplug driver which creates hotplug slots for individual PCI functions. Its reset_slot() function, which is a wrapper for zpci_hot_reset_device(), thus also resets individual functions. Currently, the kernel's PCI_SLOT() macro assigns the same pci_slot object to multifunction devices. This approach worked fine on s390 systems that only exposed virtual functions as individual PCI domains to the operating system. Since commit 44510d6fa0c0 ("s390/pci: Handling multifunctions") s390 supports exposing the topology of multifunction PCI devices by grouping them in a shared PCI domain. This creates a problem when resetting a function through the hotplug driver's slot_reset() interface. When attempting to reset a function through the hotplug driver, the shared slot assignment causes the wrong function to be reset instead of the intended one. It also leaks memory as we do create a pci_slot object for the function, but don't correctly free it in pci_slot_release(). Add a flag for struct pci_slot to allow per function PCI slots for functions managed through a hypervisor, which exposes individual PCI functions while retaining the topology. Since we can use all 8 bits for slot 'number' (for ARI devices), change slot 'number' u16 to account for special values -1 and PCI_SLOT_ALL_DEVICES. Fixes: 44510d6fa0c0 ("s390/pci: Handling multifunctions") Cc: stable@vger.kernel.org Suggested-by: Niklas Schnelle Reviewed-by: Niklas Schnelle Signed-off-by: Farhan Ali --- drivers/pci/hotplug/rpaphp_slot.c | 2 +- drivers/pci/pci.c | 5 +++-- drivers/pci/slot.c | 33 +++++++++++++++++++++++-------- include/linux/pci.h | 8 ++++++-- 4 files changed, 35 insertions(+), 13 deletions(-) diff --git a/drivers/pci/hotplug/rpaphp_slot.c b/drivers/pci/hotplug/rpaphp= _slot.c index 67362e5b9971..92eabf5f61b9 100644 --- a/drivers/pci/hotplug/rpaphp_slot.c +++ b/drivers/pci/hotplug/rpaphp_slot.c @@ -84,7 +84,7 @@ int rpaphp_register_slot(struct slot *slot) struct hotplug_slot *php_slot =3D &slot->hotplug_slot; u32 my_index; int retval; - int slotno =3D -1; + int slotno =3D PCI_SLOT_PLACEHOLDER; =20 dbg("%s registering slot:path[%pOF] index[%x], name[%s] pdomain[%x] type[= %d]\n", __func__, slot->dn, slot->index, slot->name, diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index d34266651ad0..f5f8291482b0 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -4865,8 +4865,9 @@ static int pci_reset_hotplug_slot(struct hotplug_slot= *hotplug, bool probe) =20 static int pci_dev_reset_slot_function(struct pci_dev *dev, bool probe) { - if (dev->multifunction || dev->subordinate || !dev->slot || - dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET) + if (dev->subordinate || !dev->slot || + dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET || + (dev->multifunction && !dev->slot->per_func_slot)) return -ENOTTY; =20 return pci_reset_hotplug_slot(dev->slot->hotplug, probe); diff --git a/drivers/pci/slot.c b/drivers/pci/slot.c index 6d5cd37bfb1e..894d6213ed30 100644 --- a/drivers/pci/slot.c +++ b/drivers/pci/slot.c @@ -37,7 +37,7 @@ static const struct sysfs_ops pci_slot_sysfs_ops =3D { =20 static ssize_t address_read_file(struct pci_slot *slot, char *buf) { - if (slot->number =3D=3D 0xff) + if (slot->number =3D=3D (u16)PCI_SLOT_PLACEHOLDER) return sysfs_emit(buf, "%04x:%02x\n", pci_domain_nr(slot->bus), slot->bus->number); @@ -72,6 +72,23 @@ static ssize_t cur_speed_read_file(struct pci_slot *slot= , char *buf) return bus_speed_read(slot->bus->cur_bus_speed, buf); } =20 +static bool pci_dev_matches_slot(struct pci_dev *dev, struct pci_slot *slo= t) +{ + if (slot->per_func_slot) + return dev->devfn =3D=3D slot->number; + + return slot->number =3D=3D PCI_SLOT_ALL_DEVICES || + PCI_SLOT(dev->devfn) =3D=3D slot->number; +} + +static bool pci_slot_enabled_per_func(void) +{ + if (IS_ENABLED(CONFIG_S390)) + return true; + + return false; +} + static void pci_slot_release(struct kobject *kobj) { struct pci_dev *dev; @@ -82,8 +99,7 @@ static void pci_slot_release(struct kobject *kobj) =20 down_read(&pci_bus_sem); list_for_each_entry(dev, &slot->bus->devices, bus_list) - if (slot->number =3D=3D PCI_SLOT_ALL_DEVICES || - PCI_SLOT(dev->devfn) =3D=3D slot->number) + if (pci_dev_matches_slot(dev, slot)) dev->slot =3D NULL; up_read(&pci_bus_sem); =20 @@ -187,8 +203,7 @@ void pci_dev_assign_slot(struct pci_dev *dev) =20 mutex_lock(&pci_slot_mutex); list_for_each_entry(slot, &dev->bus->slots, list) - if (slot->number =3D=3D PCI_SLOT_ALL_DEVICES || - PCI_SLOT(dev->devfn) =3D=3D slot->number) + if (pci_dev_matches_slot(dev, slot)) dev->slot =3D slot; mutex_unlock(&pci_slot_mutex); } @@ -267,7 +282,7 @@ struct pci_slot *pci_create_slot(struct pci_bus *parent= , int slot_nr, =20 mutex_lock(&pci_slot_mutex); =20 - if (slot_nr =3D=3D -1) + if (slot_nr =3D=3D PCI_SLOT_PLACEHOLDER) goto placeholder; =20 /* @@ -298,6 +313,9 @@ struct pci_slot *pci_create_slot(struct pci_bus *parent= , int slot_nr, slot->bus =3D pci_bus_get(parent); slot->number =3D slot_nr; =20 + if (pci_slot_enabled_per_func()) + slot->per_func_slot =3D 1; + slot->kobj.kset =3D pci_slots_kset; =20 slot_name =3D make_slot_name(name); @@ -318,8 +336,7 @@ struct pci_slot *pci_create_slot(struct pci_bus *parent= , int slot_nr, =20 down_read(&pci_bus_sem); list_for_each_entry(dev, &parent->devices, bus_list) - if (slot_nr =3D=3D PCI_SLOT_ALL_DEVICES || - PCI_SLOT(dev->devfn) =3D=3D slot_nr) + if (pci_dev_matches_slot(dev, slot)) dev->slot =3D slot; up_read(&pci_bus_sem); =20 diff --git a/include/linux/pci.h b/include/linux/pci.h index 2c4454583c11..d58982aa8730 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -78,14 +78,18 @@ * and, if ARI Forwarding is enabled, functions may appear to be on multip= le * devices. */ -#define PCI_SLOT_ALL_DEVICES 0xfe +#define PCI_SLOT_ALL_DEVICES 0xfeff + +/* Used to identify a slot as a placeholder */ +#define PCI_SLOT_PLACEHOLDER -1 =20 /* pci_slot represents a physical slot */ struct pci_slot { struct pci_bus *bus; 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charset="utf-8" The current reset process saves the device's config space state before reset and restores it afterward. However errors may occur unexpectedly and it may then be impossible to save config space because the device may be inaccessible (e.g. DPC). This results in saving invalid values that get written back to the device during state restoration. With a reset we want to recover/restore the device into a functional state. So avoid saving the state of the config space when the device config space is inaccessible. Reviewed-by: Niklas Schnelle Reviewed-by: Bjorn Helgaas Signed-off-by: Farhan Ali --- drivers/pci/pci.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index f5f8291482b0..973d23e41c48 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -722,6 +722,27 @@ u16 pci_find_dvsec_capability(struct pci_dev *dev, u16= vendor, u16 dvsec) } EXPORT_SYMBOL_GPL(pci_find_dvsec_capability); =20 +static bool pci_dev_config_accessible(struct pci_dev *dev, char *msg) +{ + u32 val; + + /* + * If device's config space is inaccessible it can return ~0 for + * any reads. Since VFs can also return ~0 for Device and Vendor ID + * check Command and Status registers. Note that this is racy + * because the device may become inaccessible partway through + * next access. + */ + pci_read_config_dword(dev, PCI_COMMAND, &val); + if (PCI_POSSIBLE_ERROR(val)) { + pci_warn(dev, "Device config space inaccessible; unable to %s\n", + msg); + return false; + } + + return true; +} + /** * pci_find_parent_resource - return resource region of parent bus of given * region @@ -5027,6 +5048,9 @@ static void pci_dev_save_and_disable(struct pci_dev *= dev) */ pci_set_power_state(dev, PCI_D0); =20 + if (!pci_dev_config_accessible(dev, "save state")) + return; + pci_save_state(dev); /* * Disable the device by clearing the Command register, except for --=20 2.43.0 From nobody Tue Jun 23 07:06:26 2026 Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 439B534104E; Mon, 22 Jun 2026 17:18:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" If a device is in an error state, then it's config space may not be accssible. Add additional check to validate if a device's config space is accessible before doing an FLR reset. Reviewed-by: Benjamin Block Reviewed-by: Niklas Schnelle Signed-off-by: Farhan Ali --- drivers/pci/pci.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 973d23e41c48..521a4bb189d7 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -4352,6 +4352,9 @@ int pcie_flr(struct pci_dev *dev) { int ret; =20 + if (!pci_dev_config_accessible(dev, "FLR")) + return -ENOTTY; + if (!pci_wait_for_pending_transaction(dev)) pci_err(dev, "timed out waiting for pending transaction; performing func= tion level reset anyway\n"); =20 --=20 2.43.0 From nobody Tue Jun 23 07:06:26 2026 Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A61D4342CA7; Mon, 22 Jun 2026 17:18:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.156.1 ARC-Seal: i=1; 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Mon, 22 Jun 2026 17:18:44 +0000 (GMT) Received: from IBM-D32RQW3.ibm.com (unknown [9.61.248.203]) by smtpav05.dal12v.mail.ibm.com (Postfix) with ESMTP; Mon, 22 Jun 2026 17:18:43 +0000 (GMT) From: Farhan Ali To: linux-s390@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Cc: helgaas@kernel.org, alex@shazbot.org, alifm@linux.ibm.com, schnelle@linux.ibm.com, mjrosato@linux.ibm.com Subject: [PATCH v20 4/4] PCI/MSI: Enable memory decoding before restoring MSI-X messages Date: Mon, 22 Jun 2026 10:18:40 -0700 Message-ID: <20260622171840.1618-5-alifm@linux.ibm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260622171840.1618-1-alifm@linux.ibm.com> References: <20260622171840.1618-1-alifm@linux.ibm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Authority-Analysis: v=2.4 cv=I4VVgtgg c=1 sm=1 tr=0 ts=6a396e77 cx=c_pps a=aDMHemPKRhS1OARIsFnwRA==:117 a=aDMHemPKRhS1OARIsFnwRA==:17 a=FelO9ux0wxsA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=uAbxVGIbfxUO_5tXvNgY:22 a=VnNF1IyMAAAA:8 a=kR1LtElmgzqE7PBWmM4A:9 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjIyMDE2OSBTYWx0ZWRfXwhAvYlTBv5U+ CpyomKB031HF0ir/no8uO3PdTE3M6zrM5ChS9BPr4uHhqzrriPpWLnCVhICz8483W0p3xFFmnPy qX8229+kl6qxar/dc6M1z3YBp5Pk/qTSxnzZO9vQmLG6YVGY3hULK/48L7Y2r1ywjUaBg+Lcfse QbNWWtes0/1ArZTl+KQxeaQbPEQqJUb5eNo5JjRy5fXgS4yoVdG5ekAB6JXBcOFCAnwo9uAWypm W63c26z3jkbL0H6R8RnCaUOc7EgWMgsOlszG9WdVvGP94As+PP9kp5TuwwY3lSbdlhEn1jwx6fK wtmrvMSy9xOp4V3fNY1y8bcA7sGOjENVek2JKLvhpVnWWMyrYpugeLsXhKmQx6tB9yWC/q2XPq2 i/Se20X1EHmUAHjJRefq7wIXoKGSEi6t5vFsPRdImWsIatF9zKqQEQexKIYzKSHDnH3a45bCfK+ ZP6korv+Fa/d+Xuypyg== X-Proofpoint-GUID: FJLXJNB220G98A0eJi4v7aQrneYDoRq7 X-Proofpoint-ORIG-GUID: FJLXJNB220G98A0eJi4v7aQrneYDoRq7 X-Proofpoint-Spam-Info: AW1haW4tMjYwNjIyMDE2OSBTYWx0ZWRfXxGlwXWswPlvG woA7be5WlYNBROGctrvZF2HRIQr3/zbAYQYhsjGJoOHIHciWUecYiq+rhs8H7LWw9g7nIUqTiJO 3PXgc8+qyZZCDNL7NT3eQ9WgMbTuTVU= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-22_03,2026-06-22_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 malwarescore=0 clxscore=1015 impostorscore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 priorityscore=1501 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2606220169 Content-Type: text/plain; charset="utf-8" The current MSI-X restoration path assumes the Command register Memory bit is enabled when writing MSI-X messages. But its possible the last saved and restored state of device may not have the Memory bit enabled, even if a device driver later enables Memory bit and MSI-X. Attempting to access Memory space without Memory bit enabled can lead to Unsupported Request (UR) from the device. Fix this by enabling Memory bit and restore it afterwards. Signed-off-by: Farhan Ali Reviewed-by: Niklas Schnelle Reviewed-by: Thomas Gleixner --- drivers/pci/msi/msi.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/pci/msi/msi.c b/drivers/pci/msi/msi.c index 81d24a270a79..46a0d9f68a57 100644 --- a/drivers/pci/msi/msi.c +++ b/drivers/pci/msi/msi.c @@ -874,6 +874,7 @@ void __pci_restore_msix_state(struct pci_dev *dev) { struct msi_desc *entry; bool write_msg; + u16 cmd; =20 if (!dev->msix_enabled) return; @@ -882,6 +883,8 @@ void __pci_restore_msix_state(struct pci_dev *dev) pci_intx_for_msi(dev, 0); pci_msix_clear_and_set_ctrl(dev, 0, PCI_MSIX_FLAGS_ENABLE | PCI_MSIX_FLAGS_MASKALL); + pci_read_config_word(dev, PCI_COMMAND, &cmd); + pci_write_config_word(dev, PCI_COMMAND, cmd | PCI_COMMAND_MEMORY); =20 write_msg =3D arch_restore_msi_irqs(dev); =20 @@ -893,6 +896,7 @@ void __pci_restore_msix_state(struct pci_dev *dev) } } =20 + pci_write_config_word(dev, PCI_COMMAND, cmd); pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL, 0); } =20 --=20 2.43.0