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Mon, 22 Jun 2026 01:31:09 -0700 (PDT) From: Tomer Maimon To: andrew@codeconstruct.com.au, wim@linux-watchdog.org, linux@roeck-us.net, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: openbmc@lists.ozlabs.org, linux-watchdog@vger.kernel.org, linux-doc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, avifishman70@gmail.com, tmaimon77@gmail.com, tali.perry1@gmail.com, venture@google.com, yuenn@google.com, benjaminfair@google.com, corbet@lwn.net, skhan@linuxfoundation.org, joel@jms.id.au Subject: [PATCH v2 1/3] dt-bindings: watchdog: npcm: add GCR syscon property Date: Mon, 22 Jun 2026 11:30:44 +0300 Message-Id: <20260622083046.3189603-2-tmaimon77@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260622083046.3189603-1-tmaimon77@gmail.com> References: <20260622083046.3189603-1-tmaimon77@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Describe syscon property that handles general control registers (GCR) in Nuvoton BMC NPCM watchdog driver. Signed-off-by: Tomer Maimon --- .../devicetree/bindings/watchdog/nuvoton,npcm750-wdt.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/watchdog/nuvoton,npcm750-wdt= .yaml b/Documentation/devicetree/bindings/watchdog/nuvoton,npcm750-wdt.yaml index 7aa30f5b5c49..4f00f099b2d2 100644 --- a/Documentation/devicetree/bindings/watchdog/nuvoton,npcm750-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/nuvoton,npcm750-wdt.yaml @@ -40,6 +40,12 @@ properties: clock-frequency: description: Frequency in Hz of the clock that drives the NPCM timer. =20 + nuvoton,sysgcr: + $ref: /schemas/types.yaml#/definitions/phandle + description: + a phandle to access GCR registers on NPCM750 and NPCM845 watchdog + instances. + required: - compatible - reg --=20 2.34.1 From nobody Tue Jun 30 16:38:08 2026 Received: from mail-wm1-f46.google.com (mail-wm1-f46.google.com [209.85.128.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 71EC8391834 for ; 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Mon, 22 Jun 2026 01:31:12 -0700 (PDT) Received: from taln60.nuvoton.co.il ([212.199.177.18]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-492494497ffsm200809105e9.11.2026.06.22.01.31.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Jun 2026 01:31:12 -0700 (PDT) From: Tomer Maimon To: andrew@codeconstruct.com.au, wim@linux-watchdog.org, linux@roeck-us.net, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: openbmc@lists.ozlabs.org, linux-watchdog@vger.kernel.org, linux-doc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, avifishman70@gmail.com, tmaimon77@gmail.com, tali.perry1@gmail.com, venture@google.com, yuenn@google.com, benjaminfair@google.com, corbet@lwn.net, skhan@linuxfoundation.org, joel@jms.id.au Subject: [PATCH v2 2/3] docs: watchdog: npcm: Add reset status description Date: Mon, 22 Jun 2026 11:30:45 +0300 Message-Id: <20260622083046.3189603-3-tmaimon77@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260622083046.3189603-1-tmaimon77@gmail.com> References: <20260622083046.3189603-1-tmaimon77@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add documentation describing how the NPCM watchdog driver reports reset causes through bootstatus on NPCM750 and NPCM845 systems. Document the reset flag mapping, the watchdog instance mapping for WDIOF_CARDRESET, and the NPCM750/NPCM845 latch handling. Also mention sysfs bootstatus reporting when watchdog sysfs support is enabled. Signed-off-by: Tomer Maimon --- Documentation/watchdog/index.rst | 1 + Documentation/watchdog/npcm_wdt.rst | 70 +++++++++++++++++++++++++++++ 2 files changed, 71 insertions(+) create mode 100644 Documentation/watchdog/npcm_wdt.rst diff --git a/Documentation/watchdog/index.rst b/Documentation/watchdog/inde= x.rst index 1cea24681e6b..ef29e861e837 100644 --- a/Documentation/watchdog/index.rst +++ b/Documentation/watchdog/index.rst @@ -9,6 +9,7 @@ Watchdog Support =20 hpwdt mlx-wdt + npcm_wdt pcwd-watchdog watchdog-api watchdog-kernel-api diff --git a/Documentation/watchdog/npcm_wdt.rst b/Documentation/watchdog/n= pcm_wdt.rst new file mode 100644 index 000000000000..48f0c7920c11 --- /dev/null +++ b/Documentation/watchdog/npcm_wdt.rst @@ -0,0 +1,70 @@ +.. SPDX-License-Identifier: GPL-2.0 + +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +NPCM Watchdog +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +The NPCM watchdog driver can report reset-cause information on +``nuvoton,npcm750-wdt`` and ``nuvoton,npcm845-wdt`` systems. + +Userspace can read the latched reset cause through +``WDIOC_GETBOOTSTATUS``. When ``CONFIG_WATCHDOG_SYSFS`` is enabled, the +same value is also visible through ``/sys/class/watchdog/watchdogN/bootsta= tus``. + +The mapping is fixed in the driver. It exposes the SoC reset indications +through the generic watchdog bootstatus flags and is not configurable from +Device Tree. + +.. list-table:: Reset-cause mapping + :header-rows: 1 + + * - Platform + - Reset indication + - Bootstatus flag + - Reported meaning + * - NPCM750 and NPCM845 + - ``PORST`` + - ``WDIOF_OVERHEAT`` + - power-on reset + * - NPCM750 and NPCM845 + - ``CORST`` + - ``WDIOF_FANFAULT`` + - core reset + * - NPCM750 and NPCM845 + - ``SWR1RST`` + - ``WDIOF_EXTERN1`` + - software reset source 1 + * - NPCM750 and NPCM845 + - ``SWR2RST`` + - ``WDIOF_EXTERN2`` + - software reset source 2 + * - NPCM750 and NPCM845 + - ``SWR3RST`` + - ``WDIOF_POWERUNDER`` + - software reset source 3 + * - NPCM750 + - ``SWR4RST`` + - ``WDIOF_POWEROVER`` + - software reset source 4 + * - NPCM845 + - ``TIP reset`` (``INTCR2[25]``) + - ``WDIOF_POWEROVER`` + - TIP reset + +``WDIOF_CARDRESET`` is reported only for the watchdog instance whose own +reset-status bit is latched. On systems with three watchdog instances, this +maps ``WD0RST``, ``WD1RST``, and ``WD2RST`` to ``watchdog0``, ``watchdog1`= `, +and ``watchdog2`` respectively. + +The driver may report ``WDIOF_CARDRESET`` together with one or more of the +reset-cause flags listed above. + +On NPCM750, the driver samples ``RESSR`` and clears the latched reset bits +after reading them. + +On NPCM845, the driver samples ``INTCR2``. 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Mon, 22 Jun 2026 01:31:15 -0700 (PDT) Received: from taln60.nuvoton.co.il ([212.199.177.18]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-492494497ffsm200809105e9.11.2026.06.22.01.31.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Jun 2026 01:31:14 -0700 (PDT) From: Tomer Maimon To: andrew@codeconstruct.com.au, wim@linux-watchdog.org, linux@roeck-us.net, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: openbmc@lists.ozlabs.org, linux-watchdog@vger.kernel.org, linux-doc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, avifishman70@gmail.com, tmaimon77@gmail.com, tali.perry1@gmail.com, venture@google.com, yuenn@google.com, benjaminfair@google.com, corbet@lwn.net, skhan@linuxfoundation.org, joel@jms.id.au Subject: [PATCH v2 3/3] watchdog: npcm: add bootstatus support Date: Mon, 22 Jun 2026 11:30:46 +0300 Message-Id: <20260622083046.3189603-4-tmaimon77@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260622083046.3189603-1-tmaimon77@gmail.com> References: <20260622083046.3189603-1-tmaimon77@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The NPCM750 uses RESSR and the NPCM845 uses INTCR2 to latch reset indications. Read those bits during probe and map them into watchdog bootstatus flags. For NPCM845, cache the sampled INTCR2 state in SCRPAD10 after the reset status bits are cleared so later probes can report the same boot-time state. Also report WDIOF_CARDRESET for the watchdog instance whose reset bit is latched, while leaving WPCM450 behavior unchanged. Signed-off-by: Tomer Maimon --- drivers/watchdog/npcm_wdt.c | 197 +++++++++++++++++++++++++++++++++++- 1 file changed, 195 insertions(+), 2 deletions(-) diff --git a/drivers/watchdog/npcm_wdt.c b/drivers/watchdog/npcm_wdt.c index e62ea054bc61..98660419ec3f 100644 --- a/drivers/watchdog/npcm_wdt.c +++ b/drivers/watchdog/npcm_wdt.c @@ -7,14 +7,51 @@ #include #include #include +#include #include #include #include +#include #include #include =20 #define NPCM_WTCR 0x1C =20 +/* NPCM GCR module */ +#define NPCM_RESSR_OFFSET 0x6C +#define NPCM_INTCR2_OFFSET 0x60 +#define NPCM8XX_SCRPAD10_OFFSET 0xE28 + +#define NPCM_PORST BIT(31) +#define NPCM_CORST BIT(30) +#define NPCM_WD0RST BIT(29) +#define NPCM_SWR1RST BIT(28) +#define NPCM_SWR2RST BIT(27) +#define NPCM_SWR3RST BIT(26) +#define NPCM_SWR4RST BIT(25) +#define NPCM_WD1RST BIT(24) +#define NPCM_WD2RST BIT(23) +#define NPCM8XX_RST (GENMASK(31, 23) | GENMASK(15, 12)) +#define NPCM8XX_TIP_RESET BIT(25) /* Replaces SWRST4 on NPCM8xx */ + +/* Per-instance mapping of MMIO base address to its RESSR/INTCR2 reset bit= . */ +struct npcm_wdt_rst_map { + phys_addr_t base; + u32 rst_bit; +}; + +struct npcm_wdt_status_map { + u32 rst_bit; + u32 wdiof_flag; +}; + +struct npcm_wdt_data { + const struct npcm_wdt_rst_map *rst_map; + unsigned int rst_map_size; + const struct npcm_wdt_status_map *status_map; + unsigned int status_map_size; +}; + #define NPCM_WTCLK (BIT(10) | BIT(11)) /* Clock divider */ #define NPCM_WTE BIT(7) /* Enable */ #define NPCM_WTIE BIT(6) /* Enable irq */ @@ -47,6 +84,50 @@ struct npcm_wdt { struct clk *clk; }; =20 +static const struct npcm_wdt_rst_map npcm750_rst_map[] =3D { + { 0xf000801c, NPCM_WD0RST }, + { 0xf000901c, NPCM_WD1RST }, + { 0xf000a01c, NPCM_WD2RST }, +}; + +static const struct npcm_wdt_status_map npcm750_status_map[] =3D { + { NPCM_PORST, WDIOF_OVERHEAT }, + { NPCM_CORST, WDIOF_FANFAULT }, + { NPCM_SWR1RST, WDIOF_EXTERN1 }, + { NPCM_SWR2RST, WDIOF_EXTERN2 }, + { NPCM_SWR3RST, WDIOF_POWERUNDER }, + { NPCM_SWR4RST, WDIOF_POWEROVER }, +}; + +static const struct npcm_wdt_data npcm750_data =3D { + .rst_map =3D npcm750_rst_map, + .rst_map_size =3D ARRAY_SIZE(npcm750_rst_map), + .status_map =3D npcm750_status_map, + .status_map_size =3D ARRAY_SIZE(npcm750_status_map), +}; + +static const struct npcm_wdt_rst_map npcm845_rst_map[] =3D { + { 0xf000801c, NPCM_WD0RST }, + { 0xf000901c, NPCM_WD1RST }, + { 0xf000a01c, NPCM_WD2RST }, +}; + +static const struct npcm_wdt_status_map npcm845_status_map[] =3D { + { NPCM_PORST, WDIOF_OVERHEAT }, + { NPCM_CORST, WDIOF_FANFAULT }, + { NPCM_SWR1RST, WDIOF_EXTERN1 }, + { NPCM_SWR2RST, WDIOF_EXTERN2 }, + { NPCM_SWR3RST, WDIOF_POWERUNDER }, + { NPCM8XX_TIP_RESET, WDIOF_POWEROVER }, +}; + +static const struct npcm_wdt_data npcm845_data =3D { + .rst_map =3D npcm845_rst_map, + .rst_map_size =3D ARRAY_SIZE(npcm845_rst_map), + .status_map =3D npcm845_status_map, + .status_map_size =3D ARRAY_SIZE(npcm845_status_map), +}; + static inline struct npcm_wdt *to_npcm_wdt(struct watchdog_device *wdd) { return container_of(wdd, struct npcm_wdt, wdd); @@ -169,6 +250,92 @@ static bool npcm_is_running(struct watchdog_device *wd= d) return readl(wdt->reg) & NPCM_WTE; } =20 +static void npcm_get_reset_status(struct npcm_wdt *wdt, struct device *dev, + const struct npcm_wdt_data *data, + resource_size_t start) +{ + struct regmap *gcr_regmap; + u32 rstval =3D 0; + unsigned int i; + int ret; + + if (!data) + return; + + gcr_regmap =3D syscon_regmap_lookup_by_phandle(dev->of_node, + "nuvoton,sysgcr"); + if (IS_ERR(gcr_regmap)) { + dev_warn(dev, + "Failed to find nuvoton,sysgcr, WD reset status not supported\n"); + return; + } + + if (of_device_is_compatible(dev->of_node, "nuvoton,npcm845-wdt")) { + ret =3D regmap_read(gcr_regmap, NPCM_INTCR2_OFFSET, &rstval); + if (ret) { + dev_warn(dev, "Failed to read INTCR2 reset status: %d\n", + ret); + return; + } + + if (rstval & NPCM8XX_RST) { + ret =3D regmap_write(gcr_regmap, NPCM_INTCR2_OFFSET, + rstval & ~NPCM8XX_RST); + if (ret) { + dev_warn(dev, + "Failed to clear INTCR2 reset status: %d\n", + ret); + return; + } + + ret =3D regmap_write(gcr_regmap, NPCM8XX_SCRPAD10_OFFSET, + rstval); + if (ret) { + dev_warn(dev, + "Failed to cache reset status in SCRPAD10: %d\n", + ret); + return; + } + } else { + ret =3D regmap_read(gcr_regmap, NPCM8XX_SCRPAD10_OFFSET, + &rstval); + if (ret) { + dev_warn(dev, + "Failed to read cached reset status from SCRPAD10: %d\n", + ret); + return; + } + } + } else if (of_device_is_compatible(dev->of_node, "nuvoton,npcm750-wdt")) { + ret =3D regmap_read(gcr_regmap, NPCM_RESSR_OFFSET, &rstval); + if (ret) { + dev_warn(dev, "Failed to read RESSR reset status: %d\n", + ret); + return; + } + + ret =3D regmap_write(gcr_regmap, NPCM_RESSR_OFFSET, rstval); + if (ret) { + dev_warn(dev, "Failed to clear RESSR reset status: %d\n", + ret); + return; + } + } + + for (i =3D 0; i < data->status_map_size; i++) { + if (rstval & data->status_map[i].rst_bit) + wdt->wdd.bootstatus |=3D data->status_map[i].wdiof_flag; + } + + for (i =3D 0; i < data->rst_map_size; i++) { + if (data->rst_map[i].base =3D=3D start && + rstval & data->rst_map[i].rst_bit) { + wdt->wdd.bootstatus |=3D WDIOF_CARDRESET; + break; + } + } +} + static const struct watchdog_info npcm_wdt_info =3D { .identity =3D KBUILD_MODNAME, .options =3D WDIOF_SETTIMEOUT @@ -176,6 +343,20 @@ static const struct watchdog_info npcm_wdt_info =3D { | WDIOF_MAGICCLOSE, }; =20 +static const struct watchdog_info npcm_wdt_rst_info =3D { + .identity =3D KBUILD_MODNAME, + .options =3D WDIOF_SETTIMEOUT + | WDIOF_KEEPALIVEPING + | WDIOF_MAGICCLOSE + | WDIOF_CARDRESET + | WDIOF_OVERHEAT + | WDIOF_FANFAULT + | WDIOF_EXTERN1 + | WDIOF_EXTERN2 + | WDIOF_POWERUNDER + | WDIOF_POWEROVER, +}; + static const struct watchdog_ops npcm_wdt_ops =3D { .owner =3D THIS_MODULE, .start =3D npcm_wdt_start, @@ -188,7 +369,10 @@ static const struct watchdog_ops npcm_wdt_ops =3D { static int npcm_wdt_probe(struct platform_device *pdev) { struct device *dev =3D &pdev->dev; + const struct npcm_wdt_data *data =3D device_get_match_data(dev); + struct resource *res; struct npcm_wdt *wdt; + resource_size_t start; int irq; int ret; =20 @@ -196,10 +380,16 @@ static int npcm_wdt_probe(struct platform_device *pde= v) if (!wdt) return -ENOMEM; =20 + res =3D platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) + return -EINVAL; + wdt->reg =3D devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(wdt->reg)) return PTR_ERR(wdt->reg); =20 + start =3D res->start; + wdt->clk =3D devm_clk_get_optional(&pdev->dev, NULL); if (IS_ERR(wdt->clk)) return PTR_ERR(wdt->clk); @@ -208,7 +398,7 @@ static int npcm_wdt_probe(struct platform_device *pdev) if (irq < 0) return irq; =20 - wdt->wdd.info =3D &npcm_wdt_info; + wdt->wdd.info =3D data ? &npcm_wdt_rst_info : &npcm_wdt_info; wdt->wdd.ops =3D &npcm_wdt_ops; wdt->wdd.min_timeout =3D 1; wdt->wdd.max_timeout =3D 2750; @@ -220,6 +410,8 @@ static int npcm_wdt_probe(struct platform_device *pdev) /* Ensure timeout is able to be represented by the hardware */ npcm_wdt_set_timeout(&wdt->wdd, wdt->wdd.timeout); =20 + npcm_get_reset_status(wdt, dev, data, start); + if (npcm_is_running(&wdt->wdd)) { /* Restart with the default or device-tree specified timeout */ npcm_wdt_start(&wdt->wdd); @@ -243,7 +435,8 @@ static int npcm_wdt_probe(struct platform_device *pdev) #ifdef CONFIG_OF static const struct of_device_id npcm_wdt_match[] =3D { {.compatible =3D "nuvoton,wpcm450-wdt"}, - {.compatible =3D "nuvoton,npcm750-wdt"}, + {.compatible =3D "nuvoton,npcm750-wdt", .data =3D &npcm750_data}, + {.compatible =3D "nuvoton,npcm845-wdt", .data =3D &npcm845_data}, {}, }; MODULE_DEVICE_TABLE(of, npcm_wdt_match); --=20 2.34.1