From nobody Tue Jun 30 05:35:10 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7358338B7DC; Tue, 23 Jun 2026 17:32:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782235975; cv=none; b=fVROdJNbI9ZyUQ48wsbzsx9ab9QnipCPVLke0igXkeuV3zSsYLOc9j/ebSqLAIVmUyg5VAhEzMnPFs+VvS7S6fcPLIDlF1mv1ze2gX6jpWmgmRJdNuOgecHhqU4rofszjNs/dhacVHXvaZWOzt9VpbY3DrMBD8mR04O9kSXFOCY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782235975; c=relaxed/simple; bh=6DVBrnCq5bmt+ll0ZWJey6dNV/vHdCzXNW0bHcIz61o=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=E3Z3avbCMnUhr6VB0fe/gmFclv4MD8hSWwjFpw2cH8/1DYEzOOwaSFgDefP9QLQqkgwrCgMPVB7rGSXMTha6sdKERwZuUrx56WSUh+lphUHTwyTBqxFDGzfLKO9Z9QAElls1Lov2+FFA4qZC+V/q0t1volBXY06s4ooCQi/RuIQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=YB6SiHm5; arc=none smtp.client-ip=198.175.65.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="YB6SiHm5" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1782235973; x=1813771973; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=6DVBrnCq5bmt+ll0ZWJey6dNV/vHdCzXNW0bHcIz61o=; b=YB6SiHm5scIuXyIrOG7oDLgBz9jNWn/0hRPhYxkAQUSp3Qitu9Hye+4V ikLrp81OyC62DCVb7WeTwuNv905YwOfL6D0IhS4NyMViPfSjPV90V0xy0 h9Ms5kBzzC/JglMOVH7V8VTNaAD9gfEWs/aLy0SjmY0ZfH5FznLUaug6Y SAwwIb0GxR3mXosU2crumT5W3wpk6IcmaRntrgt79kv1xIgYa8RLIyrcz u0KhJpPkexfrlvZvofLswpMolvYvHdbl57yDdSSQ6/Hbsy+MGlyZwauJJ AGphHH75idzVTl46aY48NU5jaBaJiCnkXhzyQbqB9Q1HWt5eHgdTYCRrr w==; X-CSE-ConnectionGUID: cH6IhuWKT4+x/kM+gS0WEw== X-CSE-MsgGUID: +csoSylsSry3jXwYWJQUHw== X-IronPort-AV: E=McAfee;i="6800,10657,11826"; a="100414772" X-IronPort-AV: E=Sophos;i="6.24,221,1774335600"; d="scan'208";a="100414772" Received: from orviesa010.jf.intel.com ([10.64.159.150]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Jun 2026 10:32:52 -0700 X-CSE-ConnectionGUID: 9oXY0NbYT6iPJFD0nsnnAA== X-CSE-MsgGUID: U20VLWv6Szal0E2YC7K6rA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,221,1774335600"; d="scan'208";a="248700399" Received: from guptapa-desk.jf.intel.com (HELO desk) ([10.165.239.46]) by orviesa010-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Jun 2026 10:32:53 -0700 Date: Tue, 23 Jun 2026 10:32:52 -0700 From: Pawan Gupta To: x86@kernel.org, Jon Kohler , Nikolay Borisov , "H. Peter Anvin" , Josh Poimboeuf , David Kaplan , Sean Christopherson , Borislav Petkov , Dave Hansen , Peter Zijlstra , Alexei Starovoitov , Daniel Borkmann , Andrii Nakryiko , KP Singh , Jiri Olsa , "David S. Miller" , David Laight , Andy Lutomirski , Thomas Gleixner , Ingo Molnar , David Ahern , Martin KaFai Lau , Eduard Zingerman , Song Liu , Yonghong Song , John Fastabend , Stanislav Fomichev , Hao Luo , Paolo Bonzini , Jonathan Corbet , Jason Baron , Alice Ryhl , Steven Rostedt , Ard Biesheuvel , Shuah Khan Cc: linux-kernel@vger.kernel.org, kvm@vger.kernel.org, Asit Mallick , Tao Zhang , bpf@vger.kernel.org, netdev@vger.kernel.org, linux-doc@vger.kernel.org Subject: [PATCH v12 01/12] x86/bhi: x86/vmscape: Move LFENCE out of clear_bhb_loop() Message-ID: <20260622-vmscape-bhb-v12-1-76cbda0ae3e5@linux.intel.com> X-Mailer: b4 0.16-dev References: <20260622-vmscape-bhb-v12-0-76cbda0ae3e5@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20260622-vmscape-bhb-v12-0-76cbda0ae3e5@linux.intel.com> Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Currently, the BHB clearing sequence is followed by an LFENCE to prevent transient execution of subsequent indirect branches prematurely. However, the LFENCE barrier could be unnecessary in certain cases. For example, when the kernel is using the BHI_DIS_S mitigation, and BHB clearing is only needed for userspace. In such cases, the LFENCE is redundant because ring transitions would provide the necessary serialization. Below is a quick recap of BHI mitigation options: On Alder Lake and newer BHI_DIS_S: Hardware control to mitigate BHI in ring0. This has low performance overhead. Long loop: Alternatively, a longer version of the BHB clearing sequence can be used to mitigate BHI. It can also be used to mitigate the BHI variant of VMSCAPE. This is not yet implemented in Linux. On older CPUs Short loop: Clears BHB at kernel entry and VMexit. The "Long loop" is effective on older CPUs as well, but should be avoided because of unnecessary overhead. On Alder Lake and newer CPUs, eIBRS isolates the indirect targets between guest and host. But when affected by the BHI variant of VMSCAPE, a guest's branch history may still influence indirect branches in userspace. This also means the big hammer IBPB could be replaced with a cheaper option that clears the BHB at exit-to-userspace after a VMexit. In preparation for adding the support for the BHB sequence (without LFENCE) on newer CPUs, move the LFENCE to the caller side after clear_bhb_loop() is executed. Allow callers to decide whether they need the LFENCE or not. This adds a few extra bytes to the call sites, but it obviates the need for multiple variants of clear_bhb_loop(). Suggested-by: Dave Hansen Tested-by: Jon Kohler Reviewed-by: Nikolay Borisov Acked-by: Borislav Petkov (AMD) Signed-off-by: Pawan Gupta --- arch/x86/entry/entry_64.S | 5 ++++- arch/x86/include/asm/nospec-branch.h | 4 ++-- arch/x86/net/bpf_jit_comp.c | 2 ++ 3 files changed, 8 insertions(+), 3 deletions(-) diff --git a/arch/x86/entry/entry_64.S b/arch/x86/entry/entry_64.S index 42447b1e1dff..3a180a36ca0e 100644 --- a/arch/x86/entry/entry_64.S +++ b/arch/x86/entry/entry_64.S @@ -1528,6 +1528,9 @@ SYM_CODE_END(rewind_stack_and_make_dead) * refactored in the future if needed. The .skips are for safety, to ensure * that all RETs are in the second half of a cacheline to mitigate Indirect * Target Selection, rather than taking the slowpath via its_return_thunk. + * + * Note, callers should use a speculation barrier like LFENCE immediately = after + * a call to this function to ensure BHB is cleared before indirect branch= es. */ SYM_FUNC_START(clear_bhb_loop) ANNOTATE_NOENDBR @@ -1562,7 +1565,7 @@ SYM_FUNC_START(clear_bhb_loop) sub $1, %ecx jnz 1b .Lret2: RET -5: lfence +5: pop %rbp RET SYM_FUNC_END(clear_bhb_loop) diff --git a/arch/x86/include/asm/nospec-branch.h b/arch/x86/include/asm/no= spec-branch.h index 4f4b5e8a1574..70b377fcbc1c 100644 --- a/arch/x86/include/asm/nospec-branch.h +++ b/arch/x86/include/asm/nospec-branch.h @@ -331,11 +331,11 @@ =20 #ifdef CONFIG_X86_64 .macro CLEAR_BRANCH_HISTORY - ALTERNATIVE "", "call clear_bhb_loop", X86_FEATURE_CLEAR_BHB_LOOP + ALTERNATIVE "", "call clear_bhb_loop; lfence", X86_FEATURE_CLEAR_BHB_LOOP .endm =20 .macro CLEAR_BRANCH_HISTORY_VMEXIT - ALTERNATIVE "", "call clear_bhb_loop", X86_FEATURE_CLEAR_BHB_VMEXIT + ALTERNATIVE "", "call clear_bhb_loop; lfence", X86_FEATURE_CLEAR_BHB_VMEX= IT .endm #else #define CLEAR_BRANCH_HISTORY diff --git a/arch/x86/net/bpf_jit_comp.c b/arch/x86/net/bpf_jit_comp.c index ea9e707e8abf..f58ff2891d7d 100644 --- a/arch/x86/net/bpf_jit_comp.c +++ b/arch/x86/net/bpf_jit_comp.c @@ -1624,6 +1624,8 @@ static int emit_spectre_bhb_barrier(u8 **pprog, u8 *i= p, =20 if (emit_call(&prog, func, ip)) return -EINVAL; + /* Don't speculate past this until BHB is cleared */ + EMIT_LFENCE(); EMIT1(0x59); /* pop rcx */ EMIT1(0x58); /* pop rax */ } --=20 2.34.1 From nobody Tue Jun 30 05:35:10 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6DA6F38B7DC; Tue, 23 Jun 2026 17:33:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782235989; cv=none; b=Mh2uAJYAmfWegHHd8hd0Z/OFc2DX6oCs7zIuGc3G17FCnBiZ5IcvsPIpP2dbuBd9xqK9teIMu/6lTjTSH3fTjVuB+n7g/vkhOV1Ps28gXxfATfiX5laZKxfZlj5gkbb5WjhX5PXN0Xk+rwDQ8qanV99lUiEvTKfum0zHsbvHL8U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782235989; c=relaxed/simple; bh=FqPeAu2aXn50pK5Y76zeGXtcTS8WHY1hC22NrxzcURI=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=pryIcZ6imkscJ9TMNEo/MpuYjf/Cs/K7MuYOiisMmCjXEY1aca0BIiLOJIKvTkDJZntUbkAB8ah1rlmZCGQ22yzGULb3YBUL+STxObB7wkq/OPI4+eAu7DHMw5M8BiXdto3yQeW05w5NF/eh8G/921tqL7Ke5SPTpxC8+KbVjmE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=CFa+Bkjh; arc=none smtp.client-ip=198.175.65.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="CFa+Bkjh" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1782235988; x=1813771988; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=FqPeAu2aXn50pK5Y76zeGXtcTS8WHY1hC22NrxzcURI=; b=CFa+Bkjhss9yKkfEkjAXoLkwNcnRZxaEAcbUK7wjMOYUyi46aOoSusY7 bnFpX4u76eNt8sejlQ/yOpmiMTjCXmalwjwfFytFojrpuWGraaFJb/CEN G0tAooX8BuXgKdk1qO8Mu4vb+UNaKGBZOW6Hg9MIcYRKdKaD8nCh3TdSO iJcp5OApu4Ifol8Rvvjjzp9YczpVMc6ayqBItau/D05P8+zPQXnKtZeiA TVs9ttQF+0amDMLQH/lk5Y8x14gxFyoMVaKgsbsidMgIm2X2XlWj6a4IG GBaxH6HM/aWJ/pOxEL1qJsYlNFJpxHEtnp4cAJoD1yey01lqj/eqO1YSk Q==; X-CSE-ConnectionGUID: edfUalfZSF6oCjhF7QaRDw== X-CSE-MsgGUID: q4qcMT07RMCVOdDMLzAq3w== X-IronPort-AV: E=McAfee;i="6800,10657,11826"; a="100414824" X-IronPort-AV: E=Sophos;i="6.24,221,1774335600"; d="scan'208";a="100414824" Received: from orviesa010.jf.intel.com ([10.64.159.150]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Jun 2026 10:33:08 -0700 X-CSE-ConnectionGUID: Nj7kMV99Q/iFc2psnBJV0A== X-CSE-MsgGUID: 3zwjpVILRhyHzkyNiWFHkg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,221,1774335600"; d="scan'208";a="248700437" Received: from guptapa-desk.jf.intel.com (HELO desk) ([10.165.239.46]) by orviesa010-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Jun 2026 10:33:08 -0700 Date: Tue, 23 Jun 2026 10:33:07 -0700 From: Pawan Gupta To: x86@kernel.org, Jon Kohler , Nikolay Borisov , "H. Peter Anvin" , Josh Poimboeuf , David Kaplan , Sean Christopherson , Borislav Petkov , Dave Hansen , Peter Zijlstra , Alexei Starovoitov , Daniel Borkmann , Andrii Nakryiko , KP Singh , Jiri Olsa , "David S. Miller" , David Laight , Andy Lutomirski , Thomas Gleixner , Ingo Molnar , David Ahern , Martin KaFai Lau , Eduard Zingerman , Song Liu , Yonghong Song , John Fastabend , Stanislav Fomichev , Hao Luo , Paolo Bonzini , Jonathan Corbet , Jason Baron , Alice Ryhl , Steven Rostedt , Ard Biesheuvel , Shuah Khan Cc: linux-kernel@vger.kernel.org, kvm@vger.kernel.org, Asit Mallick , Tao Zhang , bpf@vger.kernel.org, netdev@vger.kernel.org, linux-doc@vger.kernel.org Subject: [PATCH v12 02/12] x86/bhi: Make clear_bhb_loop() effective on newer CPUs Message-ID: <20260622-vmscape-bhb-v12-2-76cbda0ae3e5@linux.intel.com> X-Mailer: b4 0.16-dev References: <20260622-vmscape-bhb-v12-0-76cbda0ae3e5@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20260622-vmscape-bhb-v12-0-76cbda0ae3e5@linux.intel.com> Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" As a mitigation for BHI, clear_bhb_loop() executes branches that overwrite the Branch History Buffer (BHB). On Alder Lake and newer parts this sequence is not sufficient because it doesn't clear enough entries. This was not an issue because these CPUs use the BHI_DIS_S hardware mitigation in the kernel. Now with VMSCAPE (BHI variant) it is also required to isolate branch history between guests and userspace. Since BHI_DIS_S only protects the kernel, the newer CPUs also use IBPB. A cheaper alternative to the current IBPB mitigation is clear_bhb_loop(). But it currently does not clear enough BHB entries to be effective on newer CPUs with larger BHB. At boot, dynamically set the loop count of clear_bhb_loop() such that it is effective on newer CPUs too. Introduce global loop counts, initializing them with appropriate value based on the hardware feature X86_FEATURE_BHI_CTRL. Suggested-by: Dave Hansen Acked-by: Borislav Petkov (AMD) Signed-off-by: Pawan Gupta Reviewed-by: Nikolay Borisov --- arch/x86/entry/entry_64.S | 8 +++++--- arch/x86/include/asm/nospec-branch.h | 2 ++ arch/x86/kernel/cpu/bugs.c | 13 +++++++++++++ 3 files changed, 20 insertions(+), 3 deletions(-) diff --git a/arch/x86/entry/entry_64.S b/arch/x86/entry/entry_64.S index 3a180a36ca0e..bbd4b1c7ec04 100644 --- a/arch/x86/entry/entry_64.S +++ b/arch/x86/entry/entry_64.S @@ -1536,7 +1536,9 @@ SYM_FUNC_START(clear_bhb_loop) ANNOTATE_NOENDBR push %rbp mov %rsp, %rbp - movl $5, %ecx + + movzbl bhb_seq_outer_loop(%rip), %ecx + ANNOTATE_INTRA_FUNCTION_CALL call 1f jmp 5f @@ -1556,8 +1558,8 @@ SYM_FUNC_START(clear_bhb_loop) * This should be ideally be: .skip 32 - (.Lret2 - 2f), 0xcc * but some Clang versions (e.g. 18) don't like this. */ - .skip 32 - 18, 0xcc -2: movl $5, %eax + .skip 32 - 20, 0xcc +2: movzbl bhb_seq_inner_loop(%rip), %eax 3: jmp 4f nop 4: sub $1, %eax diff --git a/arch/x86/include/asm/nospec-branch.h b/arch/x86/include/asm/no= spec-branch.h index 70b377fcbc1c..87b83ae7c97f 100644 --- a/arch/x86/include/asm/nospec-branch.h +++ b/arch/x86/include/asm/nospec-branch.h @@ -548,6 +548,8 @@ DECLARE_PER_CPU(u64, x86_spec_ctrl_current); extern void update_spec_ctrl_cond(u64 val); extern u64 spec_ctrl_current(void); =20 +extern u8 bhb_seq_inner_loop, bhb_seq_outer_loop; + /* * With retpoline, we must use IBRS to restrict branch prediction * before calling into firmware. diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index 83f51cab0b1e..2cb4a96247d8 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -2047,6 +2047,10 @@ enum bhi_mitigations { static enum bhi_mitigations bhi_mitigation __ro_after_init =3D IS_ENABLED(CONFIG_MITIGATION_SPECTRE_BHI) ? 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Peter Anvin" , Josh Poimboeuf , David Kaplan , Sean Christopherson , Borislav Petkov , Dave Hansen , Peter Zijlstra , Alexei Starovoitov , Daniel Borkmann , Andrii Nakryiko , KP Singh , Jiri Olsa , "David S. Miller" , David Laight , Andy Lutomirski , Thomas Gleixner , Ingo Molnar , David Ahern , Martin KaFai Lau , Eduard Zingerman , Song Liu , Yonghong Song , John Fastabend , Stanislav Fomichev , Hao Luo , Paolo Bonzini , Jonathan Corbet , Jason Baron , Alice Ryhl , Steven Rostedt , Ard Biesheuvel , Shuah Khan Cc: linux-kernel@vger.kernel.org, kvm@vger.kernel.org, Asit Mallick , Tao Zhang , bpf@vger.kernel.org, netdev@vger.kernel.org, linux-doc@vger.kernel.org Subject: [PATCH v12 03/12] x86/bhi: Rename clear_bhb_loop() to clear_bhb_loop_nofence() Message-ID: <20260622-vmscape-bhb-v12-3-76cbda0ae3e5@linux.intel.com> X-Mailer: b4 0.16-dev References: <20260622-vmscape-bhb-v12-0-76cbda0ae3e5@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20260622-vmscape-bhb-v12-0-76cbda0ae3e5@linux.intel.com> Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" To reflect the recent change that moved LFENCE to the caller side. Suggested-by: Borislav Petkov Reviewed-by: Nikolay Borisov Tested-by: Jon Kohler Signed-off-by: Pawan Gupta --- arch/x86/entry/entry_64.S | 8 ++++---- arch/x86/include/asm/nospec-branch.h | 6 +++--- arch/x86/net/bpf_jit_comp.c | 2 +- 3 files changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/x86/entry/entry_64.S b/arch/x86/entry/entry_64.S index bbd4b1c7ec04..1f56d086d312 100644 --- a/arch/x86/entry/entry_64.S +++ b/arch/x86/entry/entry_64.S @@ -1532,7 +1532,7 @@ SYM_CODE_END(rewind_stack_and_make_dead) * Note, callers should use a speculation barrier like LFENCE immediately = after * a call to this function to ensure BHB is cleared before indirect branch= es. */ -SYM_FUNC_START(clear_bhb_loop) +SYM_FUNC_START(clear_bhb_loop_nofence) ANNOTATE_NOENDBR push %rbp mov %rsp, %rbp @@ -1570,6 +1570,6 @@ SYM_FUNC_START(clear_bhb_loop) 5: pop %rbp RET -SYM_FUNC_END(clear_bhb_loop) -EXPORT_SYMBOL_FOR_KVM(clear_bhb_loop) -STACK_FRAME_NON_STANDARD(clear_bhb_loop) +SYM_FUNC_END(clear_bhb_loop_nofence) +EXPORT_SYMBOL_FOR_KVM(clear_bhb_loop_nofence) +STACK_FRAME_NON_STANDARD(clear_bhb_loop_nofence) diff --git a/arch/x86/include/asm/nospec-branch.h b/arch/x86/include/asm/no= spec-branch.h index 87b83ae7c97f..157eb69c7f0f 100644 --- a/arch/x86/include/asm/nospec-branch.h +++ b/arch/x86/include/asm/nospec-branch.h @@ -331,11 +331,11 @@ =20 #ifdef CONFIG_X86_64 .macro CLEAR_BRANCH_HISTORY - ALTERNATIVE "", "call clear_bhb_loop; lfence", X86_FEATURE_CLEAR_BHB_LOOP + ALTERNATIVE "", "call clear_bhb_loop_nofence; lfence", X86_FEATURE_CLEAR_= BHB_LOOP .endm =20 .macro CLEAR_BRANCH_HISTORY_VMEXIT - ALTERNATIVE "", "call clear_bhb_loop; lfence", X86_FEATURE_CLEAR_BHB_VMEX= IT + ALTERNATIVE "", "call clear_bhb_loop_nofence; lfence", X86_FEATURE_CLEAR_= BHB_VMEXIT .endm #else #define CLEAR_BRANCH_HISTORY @@ -389,7 +389,7 @@ extern void entry_untrain_ret(void); extern void write_ibpb(void); =20 #ifdef CONFIG_X86_64 -extern void clear_bhb_loop(void); +extern void clear_bhb_loop_nofence(void); #endif =20 extern void (*x86_return_thunk)(void); diff --git a/arch/x86/net/bpf_jit_comp.c b/arch/x86/net/bpf_jit_comp.c index f58ff2891d7d..e6d17eb4d949 100644 --- a/arch/x86/net/bpf_jit_comp.c +++ b/arch/x86/net/bpf_jit_comp.c @@ -1619,7 +1619,7 @@ static int emit_spectre_bhb_barrier(u8 **pprog, u8 *i= p, EMIT1(0x51); /* push rcx */ ip +=3D 2; =20 - func =3D (u8 *)clear_bhb_loop; + func =3D (u8 *)clear_bhb_loop_nofence; ip +=3D x86_call_depth_emit_accounting(&prog, func, ip); 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Peter Anvin" , Josh Poimboeuf , David Kaplan , Sean Christopherson , Borislav Petkov , Dave Hansen , Peter Zijlstra , Alexei Starovoitov , Daniel Borkmann , Andrii Nakryiko , KP Singh , Jiri Olsa , "David S. Miller" , David Laight , Andy Lutomirski , Thomas Gleixner , Ingo Molnar , David Ahern , Martin KaFai Lau , Eduard Zingerman , Song Liu , Yonghong Song , John Fastabend , Stanislav Fomichev , Hao Luo , Paolo Bonzini , Jonathan Corbet , Jason Baron , Alice Ryhl , Steven Rostedt , Ard Biesheuvel , Shuah Khan Cc: linux-kernel@vger.kernel.org, kvm@vger.kernel.org, Asit Mallick , Tao Zhang , bpf@vger.kernel.org, netdev@vger.kernel.org, linux-doc@vger.kernel.org Subject: [PATCH v12 04/12] x86/vmscape: Rename x86_ibpb_exit_to_user to x86_predictor_flush_exit_to_user Message-ID: <20260622-vmscape-bhb-v12-4-76cbda0ae3e5@linux.intel.com> X-Mailer: b4 0.16-dev References: <20260622-vmscape-bhb-v12-0-76cbda0ae3e5@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20260622-vmscape-bhb-v12-0-76cbda0ae3e5@linux.intel.com> Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" With the upcoming changes x86_ibpb_exit_to_user will also be used when BHB clearing sequence is used. Rename it cover both the cases. No functional change. Suggested-by: Sean Christopherson Tested-by: Jon Kohler Acked-by: Sean Christopherson Signed-off-by: Pawan Gupta --- arch/x86/include/asm/entry-common.h | 6 +++--- arch/x86/include/asm/nospec-branch.h | 2 +- arch/x86/kernel/cpu/bugs.c | 4 ++-- arch/x86/kvm/x86.c | 2 +- 4 files changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/x86/include/asm/entry-common.h b/arch/x86/include/asm/ent= ry-common.h index eca24b5e07f4..e2b985929083 100644 --- a/arch/x86/include/asm/entry-common.h +++ b/arch/x86/include/asm/entry-common.h @@ -82,11 +82,11 @@ static inline void arch_exit_to_user_mode_prepare(struc= t pt_regs *regs, current_thread_info()->status &=3D ~(TS_COMPAT | TS_I386_REGS_POKED); #endif =20 - /* Avoid unnecessary reads of 'x86_ibpb_exit_to_user' */ + /* Avoid unnecessary reads of 'x86_predictor_flush_exit_to_user' */ if (cpu_feature_enabled(X86_FEATURE_IBPB_EXIT_TO_USER) && - this_cpu_read(x86_ibpb_exit_to_user)) { + this_cpu_read(x86_predictor_flush_exit_to_user)) { indirect_branch_prediction_barrier(); - this_cpu_write(x86_ibpb_exit_to_user, false); + this_cpu_write(x86_predictor_flush_exit_to_user, false); } } #define arch_exit_to_user_mode_prepare arch_exit_to_user_mode_prepare diff --git a/arch/x86/include/asm/nospec-branch.h b/arch/x86/include/asm/no= spec-branch.h index 157eb69c7f0f..0381db59c39d 100644 --- a/arch/x86/include/asm/nospec-branch.h +++ b/arch/x86/include/asm/nospec-branch.h @@ -533,7 +533,7 @@ void alternative_msr_write(unsigned int msr, u64 val, u= nsigned int feature) : "memory"); } =20 -DECLARE_PER_CPU(bool, x86_ibpb_exit_to_user); +DECLARE_PER_CPU(bool, x86_predictor_flush_exit_to_user); =20 static inline void indirect_branch_prediction_barrier(void) { diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index 2cb4a96247d8..002bf4adccc3 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -65,8 +65,8 @@ EXPORT_PER_CPU_SYMBOL_GPL(x86_spec_ctrl_current); * be needed to before running userspace. That IBPB will flush the branch * predictor content. */ -DEFINE_PER_CPU(bool, x86_ibpb_exit_to_user); -EXPORT_PER_CPU_SYMBOL_GPL(x86_ibpb_exit_to_user); +DEFINE_PER_CPU(bool, x86_predictor_flush_exit_to_user); +EXPORT_PER_CPU_SYMBOL_GPL(x86_predictor_flush_exit_to_user); =20 u64 x86_pred_cmd __ro_after_init =3D PRED_CMD_IBPB; =20 diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 0550359ed798..721ff7667dc0 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -11557,7 +11557,7 @@ static int vcpu_enter_guest(struct kvm_vcpu *vcpu) * may migrate to. */ if (cpu_feature_enabled(X86_FEATURE_IBPB_EXIT_TO_USER)) - this_cpu_write(x86_ibpb_exit_to_user, true); + this_cpu_write(x86_predictor_flush_exit_to_user, true); =20 /* * Consume any pending interrupts, including the possible source of --=20 2.34.1 From nobody Tue Jun 30 05:35:10 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.8]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F04FD3B2A0; Tue, 23 Jun 2026 17:33:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.8 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782236037; cv=none; b=Su1wxXe+mRfjY5OHC6Yf5yZYuHeRtUccvBTsdPbxS0x6m1Bah8JbRq5Ml1SDIKn4gu1hEiDsPz9mHkf+mHX74tSmGwIvbi8zqeHH30i9jncGAVmDogNKJ2hUShex1DJOHYRczOZ36ZmEkVvFRIBEz0e+dcNxj9qv3tmZPdyTHa8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782236037; c=relaxed/simple; bh=Z+UBFYvZmhxdkKBWIZKrd5/Lkbp8grvu2K8zVnKyDK0=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=fZBsQQGfWgvuludhJjL3p7+HcEFR999hqh7qUKcqJ5wcFdEWOMVJoQr5L1pGvp7VK5i+AbeEJgQ9zkX2xtlkar/WN4V7j120RXf9CItIaYMieQjjiG1tsFxFbkyTH93lpYCkPx061rzrWSV+q6v9b6ei1RPasxHTcvfCGlVhACQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=DIQ7RB9S; arc=none smtp.client-ip=192.198.163.8 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="DIQ7RB9S" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1782236036; x=1813772036; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=Z+UBFYvZmhxdkKBWIZKrd5/Lkbp8grvu2K8zVnKyDK0=; b=DIQ7RB9SLZbyddyt1JddQ6VzTcJzaKC+Z6mMVg0NdUfQq/5ATMCPXsQG BBHgfnmW7puvr4rCbf3Z3EP6b8d46var+3nIfBIPQ3KlqdmHM/t6A9AuH UpjVDSBQ23b+6nhEazmyUk/uS8EDHQuH+eSVMmg7B5QkU3QIegD3Z48i7 gFq0nkUdZ0gP6bwyfGUWxwkS0C1C2vU3vwnRO8VUE0YIZdhq0WckjQy+V zT8oMV26QL4PIdsHLxmQPOKPnROLWA9n78lPw8cKBQSAFkp43KaYHhL5H jQ0wY4Tg9aeGtwR9gCelDIxTlpfzuCKnGtJjUEP7MQvKQU1sgbejKkATc Q==; X-CSE-ConnectionGUID: OmlCYye7RqidHu75ClNMxQ== X-CSE-MsgGUID: 2/BWkCD/TQi7FlqA/QnXXA== X-IronPort-AV: E=McAfee;i="6800,10657,11826"; a="100538911" X-IronPort-AV: E=Sophos;i="6.24,221,1774335600"; d="scan'208";a="100538911" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Jun 2026 10:33:55 -0700 X-CSE-ConnectionGUID: Kkoub9noTrauJdBPrt2/fw== X-CSE-MsgGUID: hZ8sT9knTOeO6g6JrLuYng== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,221,1774335600"; d="scan'208";a="273646784" Received: from guptapa-desk.jf.intel.com (HELO desk) ([10.165.239.46]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Jun 2026 10:33:54 -0700 Date: Tue, 23 Jun 2026 10:33:54 -0700 From: Pawan Gupta To: x86@kernel.org, Jon Kohler , Nikolay Borisov , "H. Peter Anvin" , Josh Poimboeuf , David Kaplan , Sean Christopherson , Borislav Petkov , Dave Hansen , Peter Zijlstra , Alexei Starovoitov , Daniel Borkmann , Andrii Nakryiko , KP Singh , Jiri Olsa , "David S. Miller" , David Laight , Andy Lutomirski , Thomas Gleixner , Ingo Molnar , David Ahern , Martin KaFai Lau , Eduard Zingerman , Song Liu , Yonghong Song , John Fastabend , Stanislav Fomichev , Hao Luo , Paolo Bonzini , Jonathan Corbet , Jason Baron , Alice Ryhl , Steven Rostedt , Ard Biesheuvel , Shuah Khan Cc: linux-kernel@vger.kernel.org, kvm@vger.kernel.org, Asit Mallick , Tao Zhang , bpf@vger.kernel.org, netdev@vger.kernel.org, linux-doc@vger.kernel.org Subject: [PATCH v12 05/12] x86/vmscape: Move mitigation selection to a switch() Message-ID: <20260622-vmscape-bhb-v12-5-76cbda0ae3e5@linux.intel.com> X-Mailer: b4 0.16-dev References: <20260622-vmscape-bhb-v12-0-76cbda0ae3e5@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20260622-vmscape-bhb-v12-0-76cbda0ae3e5@linux.intel.com> Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This ensures that all mitigation modes are explicitly handled, while keeping the mitigation selection for each mode together. This also prepares for adding BHB-clearing mitigation mode for VMSCAPE. Tested-by: Jon Kohler Reviewed-by: Nikolay Borisov Signed-off-by: Pawan Gupta --- arch/x86/kernel/cpu/bugs.c | 24 ++++++++++++++++++++---- 1 file changed, 20 insertions(+), 4 deletions(-) diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index 002bf4adccc3..636280c612f0 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -3088,17 +3088,33 @@ early_param("vmscape", vmscape_parse_cmdline); =20 static void __init vmscape_select_mitigation(void) { - if (!boot_cpu_has_bug(X86_BUG_VMSCAPE) || - !boot_cpu_has(X86_FEATURE_IBPB)) { + if (!boot_cpu_has_bug(X86_BUG_VMSCAPE)) { vmscape_mitigation =3D VMSCAPE_MITIGATION_NONE; return; } =20 - if (vmscape_mitigation =3D=3D VMSCAPE_MITIGATION_AUTO) { - if (should_mitigate_vuln(X86_BUG_VMSCAPE)) + if ((vmscape_mitigation =3D=3D VMSCAPE_MITIGATION_AUTO) && + !should_mitigate_vuln(X86_BUG_VMSCAPE)) + vmscape_mitigation =3D VMSCAPE_MITIGATION_NONE; + + switch (vmscape_mitigation) { + case VMSCAPE_MITIGATION_NONE: + break; + + case VMSCAPE_MITIGATION_IBPB_EXIT_TO_USER: + if (!boot_cpu_has(X86_FEATURE_IBPB)) + vmscape_mitigation =3D VMSCAPE_MITIGATION_NONE; + break; + + case VMSCAPE_MITIGATION_AUTO: + if (boot_cpu_has(X86_FEATURE_IBPB)) vmscape_mitigation =3D VMSCAPE_MITIGATION_IBPB_EXIT_TO_USER; else vmscape_mitigation =3D VMSCAPE_MITIGATION_NONE; + break; + + default: + break; } } =20 --=20 2.34.1 From nobody Tue Jun 30 05:35:10 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.8]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BC7FD38C402; Tue, 23 Jun 2026 17:34:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.8 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782236053; cv=none; b=NrieUfyrCj8k7nrWXxumjXV7lKotOqKih2gTpDjFEW057hFcnNYRLC0DxyK3n+wgIGPUnVLXyhBuY61yH+W5vPC9KU0tOi/ctl/YyDMc/YA5n9bfaqFvCQv0fJfOC3QoNFCQYZb0Fu5AcggpjWr38COp4rdd/7o8dFJKHyvum14= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782236053; c=relaxed/simple; bh=lGXmoDCnvuNn6+Ag0TSIQD5cl4oZWRNteh+zvj/PmHs=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=FQbNJIy+U6Db4DlQb3YumkQgPY0g6WTB2S9cONDd/PO8nu1XCWqxNCBOeS1J739AgX4ypa7tiDuMoy0vwtz+fSBtsyrUJENq+sOXYBOjdxBKWx3iHkQYhlLjfXUKkVswa2jeoJ0yv1uTdS3e/ZKQOtB6kOd8lkxrWqYM9l1mJKY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=a1DgdeHK; arc=none smtp.client-ip=192.198.163.8 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="a1DgdeHK" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1782236052; x=1813772052; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=lGXmoDCnvuNn6+Ag0TSIQD5cl4oZWRNteh+zvj/PmHs=; b=a1DgdeHKxyikAgGhhZgt3bzZi31hEuAd3tJejmrgNQ6coO7KIpMHGSzn gz+vnQTL1to4qqf276bsg3AXPi99orBmCHMKRlUNTAkvyHD/pITiUcWWB rYHIVaIGZSrCcn2shF/aczPJv9I+LaTDhMLUqAotp7dhvhXT+psuf4RcX p3zXSiMz0hIc3n4WAqA5hZuT7XGv3Ft7C/p33NyieaknyB9kzycMZSQWx /akg4IMf3hM1HjRe18uVZLAqPO4bfR5J9koU3cTmep5Vs6X4sT4ku7EM0 98RFLkUSclKK0JELUoAS41DE30vXllXPsOcHyTLmrpklVNge0i3SB8mqi g==; X-CSE-ConnectionGUID: 8FVKHv4dRyCMVQKPvAXe5A== X-CSE-MsgGUID: mJ6TMQqARo+CSpaqAsdb+Q== X-IronPort-AV: E=McAfee;i="6800,10657,11826"; a="100538950" X-IronPort-AV: E=Sophos;i="6.24,221,1774335600"; d="scan'208";a="100538950" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Jun 2026 10:34:11 -0700 X-CSE-ConnectionGUID: yAmqSnJPToywv7nXFZ/ckA== X-CSE-MsgGUID: ZHPUrfAERpOeywn5dwK/Cg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,221,1774335600"; d="scan'208";a="273646841" Received: from guptapa-desk.jf.intel.com (HELO desk) ([10.165.239.46]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Jun 2026 10:34:10 -0700 Date: Tue, 23 Jun 2026 10:34:10 -0700 From: Pawan Gupta To: x86@kernel.org, Jon Kohler , Nikolay Borisov , "H. Peter Anvin" , Josh Poimboeuf , David Kaplan , Sean Christopherson , Borislav Petkov , Dave Hansen , Peter Zijlstra , Alexei Starovoitov , Daniel Borkmann , Andrii Nakryiko , KP Singh , Jiri Olsa , "David S. Miller" , David Laight , Andy Lutomirski , Thomas Gleixner , Ingo Molnar , David Ahern , Martin KaFai Lau , Eduard Zingerman , Song Liu , Yonghong Song , John Fastabend , Stanislav Fomichev , Hao Luo , Paolo Bonzini , Jonathan Corbet , Jason Baron , Alice Ryhl , Steven Rostedt , Ard Biesheuvel , Shuah Khan Cc: linux-kernel@vger.kernel.org, kvm@vger.kernel.org, Asit Mallick , Tao Zhang , bpf@vger.kernel.org, netdev@vger.kernel.org, linux-doc@vger.kernel.org Subject: [PATCH v12 06/12] x86/vmscape: Use write_ibpb() instead of indirect_branch_prediction_barrier() Message-ID: <20260622-vmscape-bhb-v12-6-76cbda0ae3e5@linux.intel.com> X-Mailer: b4 0.16-dev References: <20260622-vmscape-bhb-v12-0-76cbda0ae3e5@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20260622-vmscape-bhb-v12-0-76cbda0ae3e5@linux.intel.com> Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" indirect_branch_prediction_barrier() is a wrapper to write_ibpb(), which also checks if the CPU supports IBPB. For VMSCAPE, call to indirect_branch_prediction_barrier() is only possible when CPU supports IBPB. Simply call write_ibpb() directly to avoid unnecessary alternative patching. Suggested-by: Dave Hansen Tested-by: Jon Kohler Reviewed-by: Nikolay Borisov Signed-off-by: Pawan Gupta --- arch/x86/include/asm/entry-common.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/include/asm/entry-common.h b/arch/x86/include/asm/ent= ry-common.h index e2b985929083..3be6d4c356ed 100644 --- a/arch/x86/include/asm/entry-common.h +++ b/arch/x86/include/asm/entry-common.h @@ -85,7 +85,7 @@ static inline void arch_exit_to_user_mode_prepare(struct = pt_regs *regs, /* Avoid unnecessary reads of 'x86_predictor_flush_exit_to_user' */ if (cpu_feature_enabled(X86_FEATURE_IBPB_EXIT_TO_USER) && this_cpu_read(x86_predictor_flush_exit_to_user)) { - indirect_branch_prediction_barrier(); + write_ibpb(); this_cpu_write(x86_predictor_flush_exit_to_user, false); } } --=20 2.34.1 From nobody Tue Jun 30 05:35:10 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0B65730BF69; Tue, 23 Jun 2026 17:34:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782236068; cv=none; b=WvAdCfT/Y+DqL73zvPyJF2uW3uEFYAJeOIlSTvSLFVAag8ZfmEYNiEA9unZApGc95bAxmWSaZmixbrVP9gw7PimxDAvfvZdUKDf8EF0/elNwJ1GgW6XSN7ati+7Foe7AplHnGysyx6AhWO9d5WdTXZePNBUSqICVYfNoemu3zJY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782236068; c=relaxed/simple; bh=ru4xmAG5090zMTorvzBMO3CkMmXYAyYQWFiIdf/Og8c=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=DEl58yX2sd6i7SztHdNlA79WI3bjUzwvWwtrVzrqHDIMoLHKLbjNsUGeGuaGHYvjxSEvzFLWkxIM0b66GKGJoS2JbZLDUBgEJqMDFLxaMmm5D4++S199v7UNpafNNtK+63ONqtEmGaIxnXvJriu4/m2Oost2mdSIcamfDJ6ERd8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=jH/sg/32; arc=none smtp.client-ip=198.175.65.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="jH/sg/32" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1782236067; x=1813772067; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=ru4xmAG5090zMTorvzBMO3CkMmXYAyYQWFiIdf/Og8c=; b=jH/sg/32qssJVc2slRAADa9uJoTxurohvvh6xGvk3rxpoEFe5z4aCfM2 WDqZlOSluqUfrUUYyqsYRIZVmIseMdwGrpVaKY8+m316h3G9P5gUKvzkG 2084DjHDEkbLEl98lW7BGWXZNQtpjC70UkPkJtBoqXTDVK4Agvxla02rM ZZXwNJYBcw5gpQpnutLtFIQhNiHLMxJ90Sewim7nl4nPwYJGIl4LbrnRY 6Zuki8LXtMYx4E9wfLpjT20QEWp+FX2IdFmAHTKJpCtv7Q3R/9rYhzFSA ANFSgQM1bQfbQ5O2MpFMf+9DGKW3YsdQn82NSOxIp/1c/pj95Lp7f+RYJ g==; X-CSE-ConnectionGUID: ohOXgrVxQJ6QeFVgsbFmjQ== X-CSE-MsgGUID: o6V9ijYFQXeiWtL1+szp+A== X-IronPort-AV: E=McAfee;i="6800,10657,11826"; a="100414944" X-IronPort-AV: E=Sophos;i="6.24,221,1774335600"; d="scan'208";a="100414944" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Jun 2026 10:34:26 -0700 X-CSE-ConnectionGUID: 6wSkGP6/Sau1gn3LkRf6RQ== X-CSE-MsgGUID: bDL9NoYfQhOpSnvbLMl24w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,221,1774335600"; d="scan'208";a="249687588" Received: from guptapa-desk.jf.intel.com (HELO desk) ([10.165.239.46]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Jun 2026 10:34:27 -0700 Date: Tue, 23 Jun 2026 10:34:25 -0700 From: Pawan Gupta To: x86@kernel.org, Jon Kohler , Nikolay Borisov , "H. Peter Anvin" , Josh Poimboeuf , David Kaplan , Sean Christopherson , Borislav Petkov , Dave Hansen , Peter Zijlstra , Alexei Starovoitov , Daniel Borkmann , Andrii Nakryiko , KP Singh , Jiri Olsa , "David S. Miller" , David Laight , Andy Lutomirski , Thomas Gleixner , Ingo Molnar , David Ahern , Martin KaFai Lau , Eduard Zingerman , Song Liu , Yonghong Song , John Fastabend , Stanislav Fomichev , Hao Luo , Paolo Bonzini , Jonathan Corbet , Jason Baron , Alice Ryhl , Steven Rostedt , Ard Biesheuvel , Shuah Khan Cc: linux-kernel@vger.kernel.org, kvm@vger.kernel.org, Asit Mallick , Tao Zhang , bpf@vger.kernel.org, netdev@vger.kernel.org, linux-doc@vger.kernel.org Subject: [PATCH v12 07/12] static_call: Define EXPORT_STATIC_CALL_FOR_MODULES() Message-ID: <20260622-vmscape-bhb-v12-7-76cbda0ae3e5@linux.intel.com> X-Mailer: b4 0.16-dev References: <20260622-vmscape-bhb-v12-0-76cbda0ae3e5@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20260622-vmscape-bhb-v12-0-76cbda0ae3e5@linux.intel.com> Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" There is EXPORT_STATIC_CALL_TRAMP() that hides the static key from all modules. But there is no equivalent of EXPORT_SYMBOL_FOR_MODULES() to restrict symbol visibility to only certain modules. Add EXPORT_STATIC_CALL_FOR_MODULES(name, mods) that wraps both the key and the trampoline with EXPORT_SYMBOL_FOR_MODULES(), allowing only a limited set of modules to see and update the static key. The immediate user is KVM, in the following commit. checkpatch reported below warnings with this change that I believe don't apply in this case: include/linux/static_call.h:219: WARNING: Non-declarative macros with mul= tiple statements should be enclosed in a do - while loop include/linux/static_call.h:220: WARNING: EXPORT_SYMBOL(foo); should imme= diately follow its function/variable Suggested-by: Peter Zijlstra Signed-off-by: Pawan Gupta --- include/linux/static_call.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/include/linux/static_call.h b/include/linux/static_call.h index 78a77a4ae0ea..b610afd1ed55 100644 --- a/include/linux/static_call.h +++ b/include/linux/static_call.h @@ -216,6 +216,9 @@ extern long __static_call_return0(void); #define EXPORT_STATIC_CALL_GPL(name) \ EXPORT_SYMBOL_GPL(STATIC_CALL_KEY(name)); \ EXPORT_SYMBOL_GPL(STATIC_CALL_TRAMP(name)) +#define EXPORT_STATIC_CALL_FOR_MODULES(name, mods) \ + EXPORT_SYMBOL_FOR_MODULES(STATIC_CALL_KEY(name), mods); \ + EXPORT_SYMBOL_FOR_MODULES(STATIC_CALL_TRAMP(name), mods) =20 /* Leave the key unexported, so modules can't change static call targets: = */ #define EXPORT_STATIC_CALL_TRAMP(name) \ @@ -276,6 +279,9 @@ extern long __static_call_return0(void); #define EXPORT_STATIC_CALL_GPL(name) \ EXPORT_SYMBOL_GPL(STATIC_CALL_KEY(name)); \ EXPORT_SYMBOL_GPL(STATIC_CALL_TRAMP(name)) +#define EXPORT_STATIC_CALL_FOR_MODULES(name, mods) \ + EXPORT_SYMBOL_FOR_MODULES(STATIC_CALL_KEY(name), mods); \ + EXPORT_SYMBOL_FOR_MODULES(STATIC_CALL_TRAMP(name), mods) =20 /* Leave the key unexported, so modules can't change static call targets: = */ #define EXPORT_STATIC_CALL_TRAMP(name) \ @@ -346,6 +352,8 @@ static inline int static_call_text_reserved(void *start= , void *end) =20 #define EXPORT_STATIC_CALL(name) EXPORT_SYMBOL(STATIC_CALL_KEY(name)) #define EXPORT_STATIC_CALL_GPL(name) EXPORT_SYMBOL_GPL(STATIC_CALL_KEY(nam= e)) +#define EXPORT_STATIC_CALL_FOR_MODULES(name, mods) \ + EXPORT_SYMBOL_FOR_MODULES(STATIC_CALL_KEY(name), mods) =20 #endif /* CONFIG_HAVE_STATIC_CALL */ =20 --=20 2.34.1 From nobody Tue Jun 30 05:35:10 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 584E738C2B8; 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a="100414986" X-IronPort-AV: E=Sophos;i="6.24,221,1774335600"; d="scan'208";a="100414986" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Jun 2026 10:34:41 -0700 X-CSE-ConnectionGUID: 65kKS9OBRXKCxe0IHEOtwA== X-CSE-MsgGUID: dZylsM7yQC25fVOamVuTGw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,221,1774335600"; d="scan'208";a="249687621" Received: from guptapa-desk.jf.intel.com (HELO desk) ([10.165.239.46]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Jun 2026 10:34:42 -0700 Date: Tue, 23 Jun 2026 10:34:41 -0700 From: Pawan Gupta To: x86@kernel.org, Jon Kohler , Nikolay Borisov , "H. Peter Anvin" , Josh Poimboeuf , David Kaplan , Sean Christopherson , Borislav Petkov , Dave Hansen , Peter Zijlstra , Alexei Starovoitov , Daniel Borkmann , Andrii Nakryiko , KP Singh , Jiri Olsa , "David S. Miller" , David Laight , Andy Lutomirski , Thomas Gleixner , Ingo Molnar , David Ahern , Martin KaFai Lau , Eduard Zingerman , Song Liu , Yonghong Song , John Fastabend , Stanislav Fomichev , Hao Luo , Paolo Bonzini , Jonathan Corbet , Jason Baron , Alice Ryhl , Steven Rostedt , Ard Biesheuvel , Shuah Khan Cc: linux-kernel@vger.kernel.org, kvm@vger.kernel.org, Asit Mallick , Tao Zhang , bpf@vger.kernel.org, netdev@vger.kernel.org, linux-doc@vger.kernel.org Subject: [PATCH v12 08/12] KVM: Define EXPORT_STATIC_CALL_FOR_KVM() Message-ID: <20260622-vmscape-bhb-v12-8-76cbda0ae3e5@linux.intel.com> X-Mailer: b4 0.16-dev References: <20260622-vmscape-bhb-v12-0-76cbda0ae3e5@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20260622-vmscape-bhb-v12-0-76cbda0ae3e5@linux.intel.com> Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" EXPORT_SYMBOL_FOR_KVM() exists to export symbols to KVM modules. Static calls need the same treatment when the core kernel defines a static_call that KVM needs access to (e.g. from a VM-exit path). Define EXPORT_STATIC_CALL_FOR_KVM() as the static_call analogue of EXPORT_SYMBOL_FOR_KVM(). The same three-way logic applies: - KVM_SUB_MODULES defined: export to "kvm," plus all sub-modules - KVM=3Dm, no sub-modules: export to "kvm" only - KVM built-in: no export needed (noop) As with EXPORT_SYMBOL_FOR_KVM(), allow architectures to override both macros (e.g. to suppress the export when kvm.ko itself will not be built despite CONFIG_KVM=3Dm). Add the x86 no-op overrides in arch/x86/include/asm/kvm_types.h for that case. To keep the pair in sync, EXPORT_STATIC_CALL_FOR_KVM() is defined inside the EXPORT_SYMBOL_FOR_KVM #ifndef block; an arch that defines EXPORT_SYMBOL_FOR_KVM must also define EXPORT_STATIC_CALL_FOR_KVM or the build will fail with a compile-time error. As with EXPORT_SYMBOL_FOR_KVM(), allow architectures to override EXPORT_STATIC_CALL_FOR_KVM definition (e.g. to suppress the export when kvm.ko itself will not be built despite CONFIG_KVM=3Dm). Add the x86 no-op override in arch/x86/include/asm/kvm_types.h for that case. Architectures must also define EXPORT_STATIC_CALL_FOR_KVM when they define EXPORT_SYMBOL_FOR_KVM. Suggested-by: Sean Christopherson Acked-by: Sean Christopherson Signed-off-by: Pawan Gupta --- arch/x86/include/asm/kvm_types.h | 1 + include/linux/kvm_types.h | 10 +++++++++- 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/kvm_types.h b/arch/x86/include/asm/kvm_ty= pes.h index d7c704ed1be9..bceeaed2940e 100644 --- a/arch/x86/include/asm/kvm_types.h +++ b/arch/x86/include/asm/kvm_types.h @@ -15,6 +15,7 @@ * at least one vendor module is enabled. */ #define EXPORT_SYMBOL_FOR_KVM(symbol) +#define EXPORT_STATIC_CALL_FOR_KVM(symbol) #endif =20 #define KVM_ARCH_NR_OBJS_PER_MEMORY_CACHE 40 diff --git a/include/linux/kvm_types.h b/include/linux/kvm_types.h index a568d8e6f4e8..be602d3f287e 100644 --- a/include/linux/kvm_types.h +++ b/include/linux/kvm_types.h @@ -13,6 +13,8 @@ EXPORT_SYMBOL_FOR_MODULES(symbol, __stringify(KVM_SUB_MODULES)) #define EXPORT_SYMBOL_FOR_KVM(symbol) \ EXPORT_SYMBOL_FOR_MODULES(symbol, "kvm," __stringify(KVM_SUB_MODULES)) +#define EXPORT_STATIC_CALL_FOR_KVM(symbol) \ + EXPORT_STATIC_CALL_FOR_MODULES(symbol, "kvm," __stringify(KVM_SUB_MODULES= )) #else #define EXPORT_SYMBOL_FOR_KVM_INTERNAL(symbol) /* @@ -23,11 +25,17 @@ #ifndef EXPORT_SYMBOL_FOR_KVM #if IS_MODULE(CONFIG_KVM) #define EXPORT_SYMBOL_FOR_KVM(symbol) EXPORT_SYMBOL_FOR_MODULES(symbol, "k= vm") +#define EXPORT_STATIC_CALL_FOR_KVM(symbol) EXPORT_STATIC_CALL_FOR_MODULES(= symbol, "kvm") #else #define EXPORT_SYMBOL_FOR_KVM(symbol) +#define EXPORT_STATIC_CALL_FOR_KVM(symbol) #endif /* IS_MODULE(CONFIG_KVM) */ -#endif /* EXPORT_SYMBOL_FOR_KVM */ +#else +#ifndef EXPORT_STATIC_CALL_FOR_KVM +#error Must #define EXPORT_STATIC_CALL_FOR_KVM if #defining EXPORT_SYMBOL_= FOR_KVM #endif +#endif /* EXPORT_SYMBOL_FOR_KVM */ +#endif /* KVM_SUB_MODULES */ =20 #ifndef __ASSEMBLER__ =20 --=20 2.34.1 From nobody Tue Jun 30 05:35:10 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 671702F7F1B; Tue, 23 Jun 2026 17:34:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782236098; cv=none; b=H6ssEiHyyxdyg/nISG/FvedfngzzYZVTwnb7AJii8yasyYDTDeucs3C+4IYt4VQolpTaqk+X/wGFzORj9lQnpkublDjXqfcPUe/RGGydLLA446KgkBWeLCkoFeoLp4HlVuDNV64xcR7i0OjpXxZMLfusVv1FlCQnSmet40sx5dE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782236098; c=relaxed/simple; bh=Eu0LwUOp+wbc1TQfcb9wTQgFYagdSpHojNfkmeyOQzw=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=RDzazvuq4a/MZr10rYhHMwO8RXgJZLjzg5vzVg22cf7hO3CV9PGuQWPmdLSx/xzgBkB2516fldoj7aWux/kmwDOHe3OcgqhP/amp37JTJZpuBurWxWOe35cDqIijmj9ulxartmQxPKLmIMP2iUUBCdP0zocm+v8B/sX9kmBLaU8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=HcG8Cysx; arc=none smtp.client-ip=198.175.65.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="HcG8Cysx" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1782236097; x=1813772097; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=Eu0LwUOp+wbc1TQfcb9wTQgFYagdSpHojNfkmeyOQzw=; b=HcG8CysxnnB+cHrJcFgcuKevb88+DQKglNfFNjRjwhvd1taFQVb0b/Fx A5ngBCSdbGBv0BCVuM+wvV7JFCYy05Gp2lAedV/bZ1dgx2pnZCyZNhvim cGhu3Lqqwpr0SmvVNKmv6MPysMsJJw8mqjy3IDp6h92rwEw1Vjewjx+OM /MXjF/SX3b1KI/ZQyMYJY2AUGlCYeCksiy7yJ7aEzcasb18zw1YxptWxq 6qsFfflweecFjThHAu0UQEKgRQ0T0IInXiT7/S/b90MayWrWXHEyT2/dI VKSSibWecVXZm9OFEQYh/kKAi4ev5cEgrrRHY2yabOSSkBmKCkId3erxR A==; X-CSE-ConnectionGUID: 5+1PAqHGTtyJqD32hrg/Dg== X-CSE-MsgGUID: VR0E7LAtQzaIXv/ZWRavYA== X-IronPort-AV: E=McAfee;i="6800,10657,11826"; a="100415025" X-IronPort-AV: E=Sophos;i="6.24,221,1774335600"; d="scan'208";a="100415025" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Jun 2026 10:34:57 -0700 X-CSE-ConnectionGUID: XSlbAON5SAezsmDkjooYFA== X-CSE-MsgGUID: +6sbI7rqTCm8oWQ3pLa/+Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,221,1774335600"; d="scan'208";a="249687670" Received: from guptapa-desk.jf.intel.com (HELO desk) ([10.165.239.46]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Jun 2026 10:34:57 -0700 Date: Tue, 23 Jun 2026 10:34:56 -0700 From: Pawan Gupta To: x86@kernel.org, Jon Kohler , Nikolay Borisov , "H. Peter Anvin" , Josh Poimboeuf , David Kaplan , Sean Christopherson , Borislav Petkov , Dave Hansen , Peter Zijlstra , Alexei Starovoitov , Daniel Borkmann , Andrii Nakryiko , KP Singh , Jiri Olsa , "David S. Miller" , David Laight , Andy Lutomirski , Thomas Gleixner , Ingo Molnar , David Ahern , Martin KaFai Lau , Eduard Zingerman , Song Liu , Yonghong Song , John Fastabend , Stanislav Fomichev , Hao Luo , Paolo Bonzini , Jonathan Corbet , Jason Baron , Alice Ryhl , Steven Rostedt , Ard Biesheuvel , Shuah Khan Cc: linux-kernel@vger.kernel.org, kvm@vger.kernel.org, Asit Mallick , Tao Zhang , bpf@vger.kernel.org, netdev@vger.kernel.org, linux-doc@vger.kernel.org Subject: [PATCH v12 09/12] x86/vmscape: Use static_call() for predictor flush Message-ID: <20260622-vmscape-bhb-v12-9-76cbda0ae3e5@linux.intel.com> X-Mailer: b4 0.16-dev References: <20260622-vmscape-bhb-v12-0-76cbda0ae3e5@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20260622-vmscape-bhb-v12-0-76cbda0ae3e5@linux.intel.com> Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Adding more mitigation options at exit-to-userspace for VMSCAPE would usually require a series of checks to decide which mitigation to use. In this case, the mitigation is done by calling a function, which is decided at boot. So, adding more feature flags and multiple checks can be avoided by using static_call() to the mitigating function. Replace the flag-based mitigation selector with a static_call(). This also frees the existing X86_FEATURE_IBPB_EXIT_TO_USER. Suggested-by: Dave Hansen Tested-by: Jon Kohler Acked-by: Sean Christopherson Signed-off-by: Pawan Gupta --- arch/x86/Kconfig | 1 + arch/x86/include/asm/cpufeatures.h | 2 +- arch/x86/include/asm/entry-common.h | 7 +++---- arch/x86/include/asm/nospec-branch.h | 3 +++ arch/x86/kernel/cpu/bugs.c | 9 ++++++++- arch/x86/kvm/x86.c | 2 +- 6 files changed, 17 insertions(+), 7 deletions(-) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index f3f7cb01d69d..c5965bcf14c1 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -2717,6 +2717,7 @@ config MITIGATION_TSA config MITIGATION_VMSCAPE bool "Mitigate VMSCAPE" depends on KVM + depends on HAVE_STATIC_CALL default y help Enable mitigation for VMSCAPE attacks. VMSCAPE is a hardware security diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpuf= eatures.h index 1d506e5d6f46..09f956b72637 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -504,7 +504,7 @@ #define X86_FEATURE_TSA_SQ_NO (21*32+11) /* AMD CPU not vulnerable to TSA= -SQ */ #define X86_FEATURE_TSA_L1_NO (21*32+12) /* AMD CPU not vulnerable to TSA= -L1 */ #define X86_FEATURE_CLEAR_CPU_BUF_VM (21*32+13) /* Clear CPU buffers using= VERW before VMRUN */ -#define X86_FEATURE_IBPB_EXIT_TO_USER (21*32+14) /* Use IBPB on exit-to-us= erspace, see VMSCAPE bug */ +/* Free */ #define X86_FEATURE_ABMC (21*32+15) /* Assignable Bandwidth Monitoring Co= unters */ #define X86_FEATURE_MSR_IMM (21*32+16) /* MSR immediate form instructions= */ #define X86_FEATURE_SGX_EUPDATESVN (21*32+17) /* Support for ENCLS[EUPDATE= SVN] instruction */ diff --git a/arch/x86/include/asm/entry-common.h b/arch/x86/include/asm/ent= ry-common.h index 3be6d4c356ed..d5b390c76f00 100644 --- a/arch/x86/include/asm/entry-common.h +++ b/arch/x86/include/asm/entry-common.h @@ -4,6 +4,7 @@ =20 #include #include +#include =20 #include #include @@ -82,10 +83,8 @@ static inline void arch_exit_to_user_mode_prepare(struct= pt_regs *regs, current_thread_info()->status &=3D ~(TS_COMPAT | TS_I386_REGS_POKED); #endif =20 - /* Avoid unnecessary reads of 'x86_predictor_flush_exit_to_user' */ - if (cpu_feature_enabled(X86_FEATURE_IBPB_EXIT_TO_USER) && - this_cpu_read(x86_predictor_flush_exit_to_user)) { - write_ibpb(); + if (unlikely(this_cpu_read(x86_predictor_flush_exit_to_user))) { + static_call_cond(vmscape_predictor_flush)(); this_cpu_write(x86_predictor_flush_exit_to_user, false); } } diff --git a/arch/x86/include/asm/nospec-branch.h b/arch/x86/include/asm/no= spec-branch.h index 0381db59c39d..066fd8095200 100644 --- a/arch/x86/include/asm/nospec-branch.h +++ b/arch/x86/include/asm/nospec-branch.h @@ -542,6 +542,9 @@ static inline void indirect_branch_prediction_barrier(v= oid) :: "rax", "rcx", "rdx", "memory"); } =20 +#include +DECLARE_STATIC_CALL(vmscape_predictor_flush, write_ibpb); + /* The Intel SPEC CTRL MSR base value cache */ extern u64 x86_spec_ctrl_base; DECLARE_PER_CPU(u64, x86_spec_ctrl_current); diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index 636280c612f0..bfc0e41697f6 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -144,6 +144,13 @@ EXPORT_SYMBOL_GPL(cpu_buf_idle_clear); */ DEFINE_STATIC_KEY_FALSE(switch_mm_cond_l1d_flush); =20 +/* + * Controls how vmscape is mitigated e.g. via IBPB or BHB-clear + * sequence. This defaults to no mitigation. + */ +DEFINE_STATIC_CALL_NULL(vmscape_predictor_flush, write_ibpb); +EXPORT_STATIC_CALL_FOR_KVM(vmscape_predictor_flush); + #undef pr_fmt #define pr_fmt(fmt) "mitigations: " fmt =20 @@ -3133,7 +3140,7 @@ static void __init vmscape_update_mitigation(void) static void __init vmscape_apply_mitigation(void) { if (vmscape_mitigation =3D=3D VMSCAPE_MITIGATION_IBPB_EXIT_TO_USER) - setup_force_cpu_cap(X86_FEATURE_IBPB_EXIT_TO_USER); + static_call_update(vmscape_predictor_flush, write_ibpb); } =20 #undef pr_fmt diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 721ff7667dc0..fcd61c47653f 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -11556,7 +11556,7 @@ static int vcpu_enter_guest(struct kvm_vcpu *vcpu) * set for the CPU that actually ran the guest, and not the CPU that it * may migrate to. */ - if (cpu_feature_enabled(X86_FEATURE_IBPB_EXIT_TO_USER)) + if (static_call_query(vmscape_predictor_flush)) this_cpu_write(x86_predictor_flush_exit_to_user, true); =20 /* --=20 2.34.1 From nobody Tue Jun 30 05:35:10 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7AB3838CFE1; Tue, 23 Jun 2026 17:35:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782236113; cv=none; b=SwUdApqWZyNoJCFiMQ4HJtw7rogzP8sCsqRKuIce929W7ZXjE2Lc8M5APLKA56Boqx06B8nZH3eWRitIW+ZW3DRmxPWdMxyvvWlGiZ+4vFfijM0WBzdXOXNSPknH2y/cnND2p8vMU/3RYjX1kBCJAtrtWrwEPdCu+gyizWIX4mY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782236113; c=relaxed/simple; bh=A79rL4qxRxF7ycuhclRP6P1oxxPfK5g73gkq6CMSKog=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=g7J385hEdF9DmZWeNva2c45aJjzt2EAAwfNcbBpLqsyco+xAnHg5/b2tfXyzUQbMhPAZYczRQwvh//atL0E1BuBOydv24N9hRky3GGygh04ikbPFQlrhTjYj40jbKBHrcyYeMsdTw3VQ+4Nvpvov9kLLg5P5/2sWfZanrKPEaxk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=YmaiVbtA; arc=none smtp.client-ip=198.175.65.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="YmaiVbtA" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1782236112; x=1813772112; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=A79rL4qxRxF7ycuhclRP6P1oxxPfK5g73gkq6CMSKog=; b=YmaiVbtABrCqdTpeMoqdWvM6js3AB9t/hhZt/ctkNBzgdrwiHZMc5uRN ibyqmTPUsohb7SD5dSMFFHa2Y5yRbP/EuphbolgMeCUjgBnSPpK+HS/wi b+ZV1vXy0jD1mBZp234qHb3to2Cj2SEaJei8f5IsVoFY9ptYoyQrEFkpc qHGuaClESso/NDYnkaJTorX6r+nzD7Gk8CNURqwlYdp6o3kLhy7t07tQo fXsURuadRLhxfbPGCBVmi0/jbaESSoM/m7qndlkfx5nqgGqAAJc2PTfDa kmOcraS0MXLRUEjbs08a/H28KLa3Mi2rVTPAEiT9Swi7hygJOjJaMgnOq A==; X-CSE-ConnectionGUID: VKkXrAMnTHqU9LvgSWimzg== X-CSE-MsgGUID: D52tXPsPRq6umHiS1DYjgA== X-IronPort-AV: E=McAfee;i="6800,10657,11826"; a="100415064" X-IronPort-AV: E=Sophos;i="6.24,221,1774335600"; d="scan'208";a="100415064" Received: from orviesa010.jf.intel.com ([10.64.159.150]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Jun 2026 10:35:12 -0700 X-CSE-ConnectionGUID: uOtvg+fDQuWMFB0eZJzG9A== X-CSE-MsgGUID: Qqn4raj5R3WnoML1LU0oWw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,221,1774335600"; d="scan'208";a="248700586" Received: from guptapa-desk.jf.intel.com (HELO desk) ([10.165.239.46]) by orviesa010-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Jun 2026 10:35:12 -0700 Date: Tue, 23 Jun 2026 10:35:11 -0700 From: Pawan Gupta To: x86@kernel.org, Jon Kohler , Nikolay Borisov , "H. Peter Anvin" , Josh Poimboeuf , David Kaplan , Sean Christopherson , Borislav Petkov , Dave Hansen , Peter Zijlstra , Alexei Starovoitov , Daniel Borkmann , Andrii Nakryiko , KP Singh , Jiri Olsa , "David S. Miller" , David Laight , Andy Lutomirski , Thomas Gleixner , Ingo Molnar , David Ahern , Martin KaFai Lau , Eduard Zingerman , Song Liu , Yonghong Song , John Fastabend , Stanislav Fomichev , Hao Luo , Paolo Bonzini , Jonathan Corbet , Jason Baron , Alice Ryhl , Steven Rostedt , Ard Biesheuvel , Shuah Khan Cc: linux-kernel@vger.kernel.org, kvm@vger.kernel.org, Asit Mallick , Tao Zhang , bpf@vger.kernel.org, netdev@vger.kernel.org, linux-doc@vger.kernel.org Subject: [PATCH v12 10/12] x86/vmscape: Deploy BHB clearing mitigation Message-ID: <20260622-vmscape-bhb-v12-10-76cbda0ae3e5@linux.intel.com> X-Mailer: b4 0.16-dev References: <20260622-vmscape-bhb-v12-0-76cbda0ae3e5@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20260622-vmscape-bhb-v12-0-76cbda0ae3e5@linux.intel.com> Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" IBPB mitigation for VMSCAPE is an overkill on CPUs that are only affected by the BHI variant of VMSCAPE. On such CPUs, eIBRS already provides indirect branch isolation between guest and host userspace. However, branch history from guest may also influence the indirect branches in host userspace. To mitigate the BHI aspect, use the BHB clearing sequence. Since now, IBPB is not the only mitigation for VMSCAPE, update the documentation to reflect that =3Dauto could select either IBPB or BHB clear mitigation based on the CPU. Reviewed-by: Nikolay Borisov Tested-by: Jon Kohler Signed-off-by: Pawan Gupta --- Documentation/admin-guide/hw-vuln/vmscape.rst | 11 ++++++++- Documentation/admin-guide/kernel-parameters.txt | 4 +++- arch/x86/include/asm/entry-common.h | 4 ++++ arch/x86/include/asm/nospec-branch.h | 2 ++ arch/x86/kernel/cpu/bugs.c | 30 +++++++++++++++++++--= ---- 5 files changed, 42 insertions(+), 9 deletions(-) diff --git a/Documentation/admin-guide/hw-vuln/vmscape.rst b/Documentation/= admin-guide/hw-vuln/vmscape.rst index d9b9a2b6c114..7c40cf70ad7a 100644 --- a/Documentation/admin-guide/hw-vuln/vmscape.rst +++ b/Documentation/admin-guide/hw-vuln/vmscape.rst @@ -86,6 +86,10 @@ The possible values in this file are: run a potentially malicious guest and issues an IBPB before the first exit to userspace after VM-exit. =20 + * 'Mitigation: Clear BHB before exit to userspace': + + As above, conditional BHB clearing mitigation is enabled. + * 'Mitigation: IBPB on VMEXIT': =20 IBPB is issued on every VM-exit. This occurs when other mitigations like @@ -102,9 +106,14 @@ The mitigation can be controlled via the ``vmscape=3D`= ` command line parameter: =20 * ``vmscape=3Dibpb``: =20 - Enable conditional IBPB mitigation (default when CONFIG_MITIGATION_VMSC= APE=3Dy). + Enable conditional IBPB mitigation. =20 * ``vmscape=3Dforce``: =20 Force vulnerability detection and mitigation even on processors that are not known to be affected. + + * ``vmscape=3Dauto``: + + Choose the mitigation based on the VMSCAPE variant the CPU is affected = by. + (default when CONFIG_MITIGATION_VMSCAPE=3Dy) diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentatio= n/admin-guide/kernel-parameters.txt index 97007f4f69d4..38594df8859f 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -8337,9 +8337,11 @@ Kernel parameters =20 off - disable the mitigation ibpb - use Indirect Branch Prediction Barrier - (IBPB) mitigation (default) + (IBPB) mitigation force - force vulnerability detection even on unaffected processors + auto - (default) use IBPB or BHB clear + mitigation based on CPU =20 vsyscall=3D [X86-64,EARLY] Controls the behavior of vsyscalls (i.e. calls to diff --git a/arch/x86/include/asm/entry-common.h b/arch/x86/include/asm/ent= ry-common.h index d5b390c76f00..befa14a19817 100644 --- a/arch/x86/include/asm/entry-common.h +++ b/arch/x86/include/asm/entry-common.h @@ -84,6 +84,10 @@ static inline void arch_exit_to_user_mode_prepare(struct= pt_regs *regs, #endif =20 if (unlikely(this_cpu_read(x86_predictor_flush_exit_to_user))) { + /* + * Since the mitigation is for userspace, an explicit + * speculation barrier is not required after flush. + */ static_call_cond(vmscape_predictor_flush)(); this_cpu_write(x86_predictor_flush_exit_to_user, false); } diff --git a/arch/x86/include/asm/nospec-branch.h b/arch/x86/include/asm/no= spec-branch.h index 066fd8095200..38478383139b 100644 --- a/arch/x86/include/asm/nospec-branch.h +++ b/arch/x86/include/asm/nospec-branch.h @@ -390,6 +390,8 @@ extern void write_ibpb(void); =20 #ifdef CONFIG_X86_64 extern void clear_bhb_loop_nofence(void); +#else +static inline void clear_bhb_loop_nofence(void) {} #endif =20 extern void (*x86_return_thunk)(void); diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index bfc0e41697f6..1082ed1fb2e6 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -61,9 +61,8 @@ DEFINE_PER_CPU(u64, x86_spec_ctrl_current); EXPORT_PER_CPU_SYMBOL_GPL(x86_spec_ctrl_current); =20 /* - * Set when the CPU has run a potentially malicious guest. An IBPB will - * be needed to before running userspace. That IBPB will flush the branch - * predictor content. + * Set when the CPU has run a potentially malicious guest. Indicates that a + * branch predictor flush is needed before running userspace. */ DEFINE_PER_CPU(bool, x86_predictor_flush_exit_to_user); EXPORT_PER_CPU_SYMBOL_GPL(x86_predictor_flush_exit_to_user); @@ -3061,13 +3060,15 @@ enum vmscape_mitigations { VMSCAPE_MITIGATION_AUTO, VMSCAPE_MITIGATION_IBPB_EXIT_TO_USER, VMSCAPE_MITIGATION_IBPB_ON_VMEXIT, + VMSCAPE_MITIGATION_BHB_CLEAR_EXIT_TO_USER, }; =20 static const char * const vmscape_strings[] =3D { - [VMSCAPE_MITIGATION_NONE] =3D "Vulnerable", + [VMSCAPE_MITIGATION_NONE] =3D "Vulnerable", /* [VMSCAPE_MITIGATION_AUTO] */ - [VMSCAPE_MITIGATION_IBPB_EXIT_TO_USER] =3D "Mitigation: IBPB before exit = to userspace", - [VMSCAPE_MITIGATION_IBPB_ON_VMEXIT] =3D "Mitigation: IBPB on VMEXIT", + [VMSCAPE_MITIGATION_IBPB_EXIT_TO_USER] =3D "Mitigation: IBPB before exit= to userspace", + [VMSCAPE_MITIGATION_IBPB_ON_VMEXIT] =3D "Mitigation: IBPB on VMEXIT", + [VMSCAPE_MITIGATION_BHB_CLEAR_EXIT_TO_USER] =3D "Mitigation: Clear BHB be= fore exit to userspace", }; =20 static enum vmscape_mitigations vmscape_mitigation __ro_after_init =3D @@ -3085,6 +3086,8 @@ static int __init vmscape_parse_cmdline(char *str) } else if (!strcmp(str, "force")) { setup_force_cpu_bug(X86_BUG_VMSCAPE); vmscape_mitigation =3D VMSCAPE_MITIGATION_AUTO; + } else if (!strcmp(str, "auto")) { + vmscape_mitigation =3D VMSCAPE_MITIGATION_AUTO; } else { pr_err("Ignoring unknown vmscape=3D%s option.\n", str); } @@ -3114,7 +3117,17 @@ static void __init vmscape_select_mitigation(void) break; =20 case VMSCAPE_MITIGATION_AUTO: - if (boot_cpu_has(X86_FEATURE_IBPB)) + /* + * CPUs with BHI_CTRL(ADL and newer) can avoid the IBPB and use + * BHB clear sequence. These CPUs are only vulnerable to the BHI + * variant of the VMSCAPE attack, and thus they do not require a + * full predictor flush. + * + * Note, in 32-bit mode BHB clear sequence is not supported. + */ + if (boot_cpu_has(X86_FEATURE_BHI_CTRL) && IS_ENABLED(CONFIG_X86_64)) + vmscape_mitigation =3D VMSCAPE_MITIGATION_BHB_CLEAR_EXIT_TO_USER; + else if (boot_cpu_has(X86_FEATURE_IBPB)) vmscape_mitigation =3D VMSCAPE_MITIGATION_IBPB_EXIT_TO_USER; else vmscape_mitigation =3D VMSCAPE_MITIGATION_NONE; @@ -3141,6 +3154,8 @@ static void __init vmscape_apply_mitigation(void) { if (vmscape_mitigation =3D=3D VMSCAPE_MITIGATION_IBPB_EXIT_TO_USER) static_call_update(vmscape_predictor_flush, write_ibpb); + else if (vmscape_mitigation =3D=3D VMSCAPE_MITIGATION_BHB_CLEAR_EXIT_TO_U= SER) + static_call_update(vmscape_predictor_flush, clear_bhb_loop_nofence); } =20 #undef pr_fmt @@ -3232,6 +3247,7 @@ void cpu_bugs_smt_update(void) break; case VMSCAPE_MITIGATION_IBPB_ON_VMEXIT: case VMSCAPE_MITIGATION_IBPB_EXIT_TO_USER: + case VMSCAPE_MITIGATION_BHB_CLEAR_EXIT_TO_USER: /* * Hypervisors can be attacked across-threads, warn for SMT when * STIBP is not already enabled system-wide. --=20 2.34.1 From nobody Tue Jun 30 05:35:10 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4D4AA38CFE1; Tue, 23 Jun 2026 17:35:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782236138; cv=none; b=LMZk4OpSNq57es+jpcQ9zLy3INR8W6pacPkmJAb7LO/26COYZ/gKvNiL6of/x23fthXH6VHs6iMVuQNY0EkIR5zUTkuHwDpC41mYDEOh9A8d+UAhn6vTUnl29zMACEwDil4XOrIaAwj1AcGxQVm2blqpZcSwhuVFBgAf98BPlAI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782236138; c=relaxed/simple; bh=6gK4EmiJjoxMBErZvB2QlG52OKl4TSLVAd68WmRFl3s=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=MviVngm70s9Eck3TW6IVrcoZTtrpzk36WYTbgVmyHwHFILN/a/K7QUbV8IPhw1YQn03gLf6fKTiJ6KqE4DpF0MJHpk/8ZgYhxLd8IDQnm1GQS+EWk4RKcRxO8+27grc+IMPsGWYYF7WHgUKh0qMHaGy9BvaQ0QplN4D+PgJPYec= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=gNHRSJxU; arc=none smtp.client-ip=198.175.65.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="gNHRSJxU" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1782236137; x=1813772137; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=6gK4EmiJjoxMBErZvB2QlG52OKl4TSLVAd68WmRFl3s=; b=gNHRSJxU6pyB9n7ydn/QK0YAeAfhG88RIP7ttz6x4pA4uOC36XY1f16E bke7DyC+Q32csClN2cD60rk+BbFFy6luq5mLSShuMGP9t+/imloenEQ5N l5NP548pulUhf2HYCMWAiiFNpYHqgo8094yOaWsKBdPNK5xpMPNrXXH1/ sFzs41ng9YE2klXBkvZ4PRIaJ2VbM93+LfSF38htlKwv2BbcGhhgLNnCT h7C01JV9twuLJIxUXlK6UeF2sl9wHyLvqtqgpj7x9cx/mm1OMgA8pj5u4 qYDBcwbn+70KEaMEgTkyMdSZVV9FWpXGEsDUXroBnB0v8v8oPu3vpKPoQ w==; X-CSE-ConnectionGUID: JK06WcvBSoG4HxxOWp7nKw== X-CSE-MsgGUID: vT4xlU9IQCCx0+NYkUriZg== X-IronPort-AV: E=McAfee;i="6800,10657,11826"; a="100415107" X-IronPort-AV: E=Sophos;i="6.24,221,1774335600"; d="scan'208";a="100415107" Received: from orviesa010.jf.intel.com ([10.64.159.150]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Jun 2026 10:35:28 -0700 X-CSE-ConnectionGUID: Dhetkyr+QjCOyeyKNFgC3w== X-CSE-MsgGUID: Y1eBjy8nTYOOBHTanUVvyg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,221,1774335600"; d="scan'208";a="248700606" Received: from guptapa-desk.jf.intel.com (HELO desk) ([10.165.239.46]) by orviesa010-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Jun 2026 10:35:27 -0700 Date: Tue, 23 Jun 2026 10:35:26 -0700 From: Pawan Gupta To: x86@kernel.org, Jon Kohler , Nikolay Borisov , "H. Peter Anvin" , Josh Poimboeuf , David Kaplan , Sean Christopherson , Borislav Petkov , Dave Hansen , Peter Zijlstra , Alexei Starovoitov , Daniel Borkmann , Andrii Nakryiko , KP Singh , Jiri Olsa , "David S. Miller" , David Laight , Andy Lutomirski , Thomas Gleixner , Ingo Molnar , David Ahern , Martin KaFai Lau , Eduard Zingerman , Song Liu , Yonghong Song , John Fastabend , Stanislav Fomichev , Hao Luo , Paolo Bonzini , Jonathan Corbet , Jason Baron , Alice Ryhl , Steven Rostedt , Ard Biesheuvel , Shuah Khan Cc: linux-kernel@vger.kernel.org, kvm@vger.kernel.org, Asit Mallick , Tao Zhang , bpf@vger.kernel.org, netdev@vger.kernel.org, linux-doc@vger.kernel.org Subject: [PATCH v12 11/12] x86/vmscape: Resolve conflict between attack-vectors and vmscape=force Message-ID: <20260622-vmscape-bhb-v12-11-76cbda0ae3e5@linux.intel.com> X-Mailer: b4 0.16-dev References: <20260622-vmscape-bhb-v12-0-76cbda0ae3e5@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20260622-vmscape-bhb-v12-0-76cbda0ae3e5@linux.intel.com> Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" vmscape=3Dforce option currently defaults to AUTO mitigation. This lets attack-vector controls to override the vmscape mitigation. Preventing the user from being able to force VMSCAPE mitigation. When vmscape mitigation is forced, allow it be deployed irrespective of attack vectors. Introduce VMSCAPE_MITIGATION_ON that wins over attack-vector controls. Tested-by: Jon Kohler Reviewed-by: Nikolay Borisov Signed-off-by: Pawan Gupta --- arch/x86/kernel/cpu/bugs.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index 1082ed1fb2e6..fbdb137720c4 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -3058,6 +3058,7 @@ static void __init srso_apply_mitigation(void) enum vmscape_mitigations { VMSCAPE_MITIGATION_NONE, VMSCAPE_MITIGATION_AUTO, + VMSCAPE_MITIGATION_ON, VMSCAPE_MITIGATION_IBPB_EXIT_TO_USER, VMSCAPE_MITIGATION_IBPB_ON_VMEXIT, VMSCAPE_MITIGATION_BHB_CLEAR_EXIT_TO_USER, @@ -3066,6 +3067,7 @@ enum vmscape_mitigations { static const char * const vmscape_strings[] =3D { [VMSCAPE_MITIGATION_NONE] =3D "Vulnerable", /* [VMSCAPE_MITIGATION_AUTO] */ + /* [VMSCAPE_MITIGATION_ON] */ [VMSCAPE_MITIGATION_IBPB_EXIT_TO_USER] =3D "Mitigation: IBPB before exit= to userspace", [VMSCAPE_MITIGATION_IBPB_ON_VMEXIT] =3D "Mitigation: IBPB on VMEXIT", [VMSCAPE_MITIGATION_BHB_CLEAR_EXIT_TO_USER] =3D "Mitigation: Clear BHB be= fore exit to userspace", @@ -3085,7 +3087,7 @@ static int __init vmscape_parse_cmdline(char *str) vmscape_mitigation =3D VMSCAPE_MITIGATION_IBPB_EXIT_TO_USER; } else if (!strcmp(str, "force")) { setup_force_cpu_bug(X86_BUG_VMSCAPE); - vmscape_mitigation =3D VMSCAPE_MITIGATION_AUTO; + vmscape_mitigation =3D VMSCAPE_MITIGATION_ON; } else if (!strcmp(str, "auto")) { vmscape_mitigation =3D VMSCAPE_MITIGATION_AUTO; } else { @@ -3117,6 +3119,7 @@ static void __init vmscape_select_mitigation(void) break; =20 case VMSCAPE_MITIGATION_AUTO: + case VMSCAPE_MITIGATION_ON: /* * CPUs with BHI_CTRL(ADL and newer) can avoid the IBPB and use * BHB clear sequence. These CPUs are only vulnerable to the BHI @@ -3244,6 +3247,7 @@ void cpu_bugs_smt_update(void) switch (vmscape_mitigation) { case VMSCAPE_MITIGATION_NONE: case VMSCAPE_MITIGATION_AUTO: + case VMSCAPE_MITIGATION_ON: break; case VMSCAPE_MITIGATION_IBPB_ON_VMEXIT: case VMSCAPE_MITIGATION_IBPB_EXIT_TO_USER: --=20 2.34.1 From nobody Tue Jun 30 05:35:10 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 131F538C421; Tue, 23 Jun 2026 17:35:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.17 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782236145; cv=none; b=P6iglxOqESqb6ItA5Lx5mif7s9bQh7LsgcGQSVcfUnxmBkvaTrrQeriB/FYxPgLNmWBZYutXGi7nojucYum4g4pK52aOji1tQL0JfOn0kLoITr6A47jYmFI/KzAV4+nSKaJtcFG17Jzh7ZLx4s44zWpnqpc1z9CZMtIXxZE0kKE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782236145; c=relaxed/simple; bh=94D0wGLu9lcd5K0S96Sl3+6gcUnzDIU3puBcw/u2nY0=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=ezUNUy1RX5dP1R+TWJ6SjAqf8up2TQJfy8UD7VlbnOaORoB/yMF3dL6fHUKPnhw0s7JUDR1MQAEiwDlaQU3quFcaPM/XJuAPqOnndyN/vPSZf9MIabVKFTWU/MVuVBE+lclwrf80TTDxaEcTF8uRzn3iG02n8TQ9RMyvPAmeXyA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=AclBI/fJ; arc=none smtp.client-ip=198.175.65.17 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="AclBI/fJ" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1782236144; x=1813772144; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=94D0wGLu9lcd5K0S96Sl3+6gcUnzDIU3puBcw/u2nY0=; b=AclBI/fJZ0248jHGU0RkGiNHLyqYK2CtiPbnySqHjdJmBeEl0lQVmN/8 II56n20o87NbpE0kZR2itbLWpGkmt5285geSXH0EP1Og7pFcc1ojQyPII wqT5fHbrVFcIxNIUl/N1YjbqbYodxEm1IIoqxKW7YIbxmKINQ/4Thy8mw HpVeBIme1jiZk+Ta5CAwOQKeEmnbZ8OQeiRTNBZXMZ7CT/0etJHPeTu9T PxHftVMhqK5MQLO9cRaLBChwSzVWlqA6cLnNdj+2yTmWPSGLSzDzNoY9e Z5YmmWzQOWGbVCsBzHT17CIaBn/kBj+XUeWcKyDY1KF3b/xxSGkFGuZEC A==; X-CSE-ConnectionGUID: DoIjqlqpSgm5Fu2WdnYaCQ== X-CSE-MsgGUID: YF4pKXCEQ9uhnYrEVrWnOQ== X-IronPort-AV: E=McAfee;i="6800,10657,11826"; a="82989466" X-IronPort-AV: E=Sophos;i="6.24,221,1774335600"; d="scan'208";a="82989466" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by orvoesa109.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Jun 2026 10:35:43 -0700 X-CSE-ConnectionGUID: 5cmpgFLhTPuCgwM+dDNdxQ== X-CSE-MsgGUID: r2lf2r41Qsq4OAltcWDl6Q== X-ExtLoop1: 1 Received: from guptapa-desk.jf.intel.com (HELO desk) ([10.165.239.46]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Jun 2026 10:35:42 -0700 Date: Tue, 23 Jun 2026 10:35:42 -0700 From: Pawan Gupta To: x86@kernel.org, Jon Kohler , Nikolay Borisov , "H. Peter Anvin" , Josh Poimboeuf , David Kaplan , Sean Christopherson , Borislav Petkov , Dave Hansen , Peter Zijlstra , Alexei Starovoitov , Daniel Borkmann , Andrii Nakryiko , KP Singh , Jiri Olsa , "David S. Miller" , David Laight , Andy Lutomirski , Thomas Gleixner , Ingo Molnar , David Ahern , Martin KaFai Lau , Eduard Zingerman , Song Liu , Yonghong Song , John Fastabend , Stanislav Fomichev , Hao Luo , Paolo Bonzini , Jonathan Corbet , Jason Baron , Alice Ryhl , Steven Rostedt , Ard Biesheuvel , Shuah Khan Cc: linux-kernel@vger.kernel.org, kvm@vger.kernel.org, Asit Mallick , Tao Zhang , bpf@vger.kernel.org, netdev@vger.kernel.org, linux-doc@vger.kernel.org Subject: [PATCH v12 12/12] x86/vmscape: Add cmdline vmscape=on to override attack vector controls Message-ID: <20260622-vmscape-bhb-v12-12-76cbda0ae3e5@linux.intel.com> X-Mailer: b4 0.16-dev References: <20260622-vmscape-bhb-v12-0-76cbda0ae3e5@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20260622-vmscape-bhb-v12-0-76cbda0ae3e5@linux.intel.com> Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In general, individual mitigation knobs override the attack vector controls. For VMSCAPE, =3Dibpb exists but nothing to select BHB clearing mitigation. The =3Dforce option would select BHB clearing when supported, b= ut with a side-effect of also forcing the bug, hence deploying the mitigation on unaffected parts too. Add a new cmdline option vmscape=3Don to enable the mitigation based on the VMSCAPE variant the CPU is affected by. Reviewed-by: Nikolay Borisov Tested-by: Jon Kohler Signed-off-by: Pawan Gupta --- Documentation/admin-guide/hw-vuln/vmscape.rst | 4 ++++ Documentation/admin-guide/kernel-parameters.txt | 2 ++ arch/x86/kernel/cpu/bugs.c | 2 ++ 3 files changed, 8 insertions(+) diff --git a/Documentation/admin-guide/hw-vuln/vmscape.rst b/Documentation/= admin-guide/hw-vuln/vmscape.rst index 7c40cf70ad7a..2558a5c3d956 100644 --- a/Documentation/admin-guide/hw-vuln/vmscape.rst +++ b/Documentation/admin-guide/hw-vuln/vmscape.rst @@ -117,3 +117,7 @@ The mitigation can be controlled via the ``vmscape=3D``= command line parameter: =20 Choose the mitigation based on the VMSCAPE variant the CPU is affected = by. (default when CONFIG_MITIGATION_VMSCAPE=3Dy) + + * ``vmscape=3Don``: + + Same as ``auto``, except that it overrides attack vector controls. diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentatio= n/admin-guide/kernel-parameters.txt index 38594df8859f..1320baf9264c 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -8342,6 +8342,8 @@ Kernel parameters unaffected processors auto - (default) use IBPB or BHB clear mitigation based on CPU + on - same as "auto", but override attack + vector control =20 vsyscall=3D [X86-64,EARLY] Controls the behavior of vsyscalls (i.e. calls to diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index fbdb137720c4..4e0b77fb21dd 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -3088,6 +3088,8 @@ static int __init vmscape_parse_cmdline(char *str) } else if (!strcmp(str, "force")) { setup_force_cpu_bug(X86_BUG_VMSCAPE); vmscape_mitigation =3D VMSCAPE_MITIGATION_ON; + } else if (!strcmp(str, "on")) { + vmscape_mitigation =3D VMSCAPE_MITIGATION_ON; } else if (!strcmp(str, "auto")) { vmscape_mitigation =3D VMSCAPE_MITIGATION_AUTO; } else { --=20 2.34.1