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Thu, 18 Jun 2026 11:19:53 -0700 (PDT) Received: from iku.Home ([2a06:5906:61b:2d00:3bf7:d534:a488:f67d]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-465090c42e1sm869435f8f.11.2026.06.18.11.19.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Jun 2026 11:19:52 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Brian Masney , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm Cc: linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v4 1/5] clk: renesas: rzv2h-cpg: Use per-SoC PLL reference frequency for calculations Date: Thu, 18 Jun 2026 19:19:45 +0100 Message-ID: <20260618181949.3036280-2-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260618181949.3036280-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20260618181949.3036280-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Introduce a per-SoC PLL reference input frequency parameter to avoid relying on a hardcoded 24MHz constant during PLL configuration math. Add an input_fref member to struct rzv2h_pll_limits. In the core calculation helper rzv2h_get_pll_pars(), derive the base input clock rate from limits->input_fref, utilizing the conditional ternary operator to fall back to 24MHz if the struct field is left uninitialized (0), and drop the obsolete macro RZ_V2H_OSC_CLK_IN_MEGA. This abstraction permits the reuse of the common PLL divider logic on newer SoC platforms like the RZ/T2H, which feature a 48 MHz PLL reference clock input instead of the 24 MHz signal used by RZ/V2H(P), without disrupting existing platforms. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven --- v3->v4: - Fixed MHz to Hz for input_fref in the doc comment for struct rzv2h_pll_limits. - Added RB tag from Geert. v2->v3: - No change v1->v2: - Dropped RZ_V2H_OSC_CLK_IN_MEGA macro in favor of direct use of the input_fref field with a fallback. - Updated the doc to specify the default value of input_freq when it is 0. - Updated commit message --- drivers/clk/renesas/rzv2h-cpg.c | 8 ++++---- include/linux/clk/renesas.h | 5 +++++ 2 files changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/clk/renesas/rzv2h-cpg.c b/drivers/clk/renesas/rzv2h-cp= g.c index e271c04cee34..fff89f2bdc0b 100644 --- a/drivers/clk/renesas/rzv2h-cpg.c +++ b/drivers/clk/renesas/rzv2h-cpg.c @@ -218,7 +218,6 @@ struct rzv2h_plldsi_div_clk { #define to_plldsi_div_clk(_hw) \ container_of(_hw, struct rzv2h_plldsi_div_clk, hw) =20 -#define RZ_V2H_OSC_CLK_IN_MEGA (24 * MEGA) #define RZV2H_MAX_DIV_TABLES (16) =20 /** @@ -242,6 +241,7 @@ struct rzv2h_plldsi_div_clk { bool rzv2h_get_pll_pars(const struct rzv2h_pll_limits *limits, struct rzv2h_pll_pars *pars, u64 freq_millihz) { + unsigned long input_fref =3D limits->input_fref ?: (24 * MEGA); u64 fout_min_millihz =3D mul_u32_u32(limits->fout.min, MILLI); u64 fout_max_millihz =3D mul_u32_u32(limits->fout.max, MILLI); struct rzv2h_pll_pars p, best; @@ -254,7 +254,7 @@ bool rzv2h_get_pll_pars(const struct rzv2h_pll_limits *= limits, best.error_millihz =3D S64_MAX; =20 for (p.p =3D limits->p.min; p.p <=3D limits->p.max; p.p++) { - u32 fref =3D RZ_V2H_OSC_CLK_IN_MEGA / p.p; + u32 fref =3D input_fref / p.p; u16 divider; =20 for (divider =3D 1 << limits->s.min, p.s =3D limits->s.min; @@ -335,9 +335,9 @@ bool rzv2h_get_pll_pars(const struct rzv2h_pll_limits *= limits, continue; =20 /* PLL_M component of (output * 65536 * PLL_P) */ - output =3D mul_u32_u32(p.m * 65536, RZ_V2H_OSC_CLK_IN_MEGA); + output =3D mul_u32_u32(p.m * 65536, input_fref); /* PLL_K component of (output * 65536 * PLL_P) */ - output +=3D p.k * RZ_V2H_OSC_CLK_IN_MEGA; + output +=3D p.k * input_fref; /* Make it in mHz */ output *=3D MILLI; output =3D DIV_U64_ROUND_CLOSEST(output, 65536 * p.p * divider); diff --git a/include/linux/clk/renesas.h b/include/linux/clk/renesas.h index 0949400f44de..798bb0b54bab 100644 --- a/include/linux/clk/renesas.h +++ b/include/linux/clk/renesas.h @@ -53,6 +53,9 @@ static inline void rzg2l_cpg_dsi_div_set_divider(u8 divid= er, int target) { } * various parameters used to configure a PLL. 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Thu, 18 Jun 2026 11:19:53 -0700 (PDT) Received: from iku.Home ([2a06:5906:61b:2d00:3bf7:d534:a488:f67d]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-465090c42e1sm869435f8f.11.2026.06.18.11.19.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Jun 2026 11:19:53 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Brian Masney , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm Cc: linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v4 2/5] clk: renesas: cpg-mssr: Implement dedicated MSTP delay logic for RZ/T2H LCDC and RTC Date: Thu, 18 Jun 2026 19:19:46 +0100 Message-ID: <20260618181949.3036280-3-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260618181949.3036280-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20260618181949.3036280-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Introduce a dedicated clock delay mechanism, cpg_rzt2h_mstp_delay(), to satisfy the module-stop (MSTP) state release requirements specified in the RZ/T2H hardware manual. Per the hardware manual, while a standard 10 us delay (satisfying 7 dummy reads) is sufficient for most IP blocks, the LCDC requires 100 dummy reads (142 us) and the RTC requires 300 dummy reads (428 us) to stabilize after being released from a module-stop state. Implement a conditional bitmask filter helper that switches wait intervals based on the packaged module clock index. In cpg_mstp_clock_endisable(), the clock index and individual target bits are known, allowing an exact match. In the resume path cpg_mssr_resume_noirq(), where individual bits are not tracked, pass a fallback register index base (`reg * 32`) with bit verification masked out to match on the peripheral's register group block instead. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven --- v3->v4: - Added RB tag from Geert. v2->v3: - No change v1->v2: - Dropped using table based approach in favor of direct conditional checks = on the clock index. - Updated commit message to reflect the new approach. --- drivers/clk/renesas/renesas-cpg-mssr.c | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/r= enesas-cpg-mssr.c index 5b84cbee030b..4ed056b18d31 100644 --- a/drivers/clk/renesas/renesas-cpg-mssr.c +++ b/drivers/clk/renesas/renesas-cpg-mssr.c @@ -253,6 +253,22 @@ static void cpg_rzt2h_mstp_write(struct cpg_mssr_priv = *priv, u16 offset, u32 val writel(value, base + RZT2H_MSTPCR_OFFSET(offset)); } =20 +static void cpg_rzt2h_mstp_delay(u32 idx, bool bit_valid) +{ + unsigned int mask =3D bit_valid ? GENMASK(31, 0) : GENMASK(31, 5); + + if (idx =3D=3D (MOD_CLK_PACK(1204) & mask)) { + /* LCDC needs 100 dummy reads, or 142us */ + udelay(142); + } else if (idx =3D=3D (MOD_CLK_PACK(605) & mask)) { + /* RTC needs 300 dummy reads, or 428us */ + udelay(428); + } else { + /* default 7 dummy reads, or 10us */ + udelay(10); + } +} + static int cpg_mstp_clock_endisable(struct clk_hw *hw, bool enable) { struct mstp_clock *clock =3D to_mstp_clock(hw); @@ -312,7 +328,7 @@ static int cpg_mstp_clock_endisable(struct clk_hw *hw, = bool enable) * register, we simply add a delay after the read operation. */ cpg_rzt2h_mstp_read(priv, priv->control_regs[reg]); - udelay(10); + cpg_rzt2h_mstp_delay(clock->index, true); return 0; } =20 @@ -1142,7 +1158,7 @@ static int cpg_mssr_resume_noirq(struct device *dev) cpg_rzt2h_mstp_write(priv, priv->control_regs[reg], newval); /* See cpg_mstp_clock_endisable() on why this is necessary. */ cpg_rzt2h_mstp_read(priv, priv->control_regs[reg]); - udelay(10); + cpg_rzt2h_mstp_delay(reg * 32, false); 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charset="utf-8" From: Lad Prabhakar Add the LCDC clockd (LCDC_CLKD) definition for the Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs. LCDC_CLKD is used as the operating clock for LCDC. Signed-off-by: Lad Prabhakar Acked-by: Conor Dooley Reviewed-by: Geert Uytterhoeven --- v3->v4: - No change v2->v3: - No change v1->v2: - Added Acked-by and Reviewed-by tags. --- include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h | 1 + include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h | 1 + 2 files changed, 2 insertions(+) diff --git a/include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h b/inclu= de/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h index c4863e444458..f6cb8d649a46 100644 --- a/include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h +++ b/include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h @@ -34,5 +34,6 @@ #define R9A09G077_XSPI_CLK0 22 #define R9A09G077_XSPI_CLK1 23 #define R9A09G077_PCLKCAN 24 +#define R9A09G077_LCDC_CLKD 25 =20 #endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G077_CPG_H__ */ diff --git a/include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h b/inclu= de/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h index 0d53f1e65077..312e563b322e 100644 --- a/include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h +++ b/include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h @@ -34,5 +34,6 @@ #define R9A09G087_XSPI_CLK0 22 #define R9A09G087_XSPI_CLK1 23 #define R9A09G087_PCLKCAN 24 +#define R9A09G087_LCDC_CLKD 25 =20 #endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G087_CPG_H__ */ --=20 2.54.0 From nobody Fri Jun 19 13:54:32 2026 Received: from mail-wm1-f54.google.com (mail-wm1-f54.google.com [209.85.128.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 128E23603E0 for ; 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charset="utf-8" From: Lad Prabhakar Move the RZ/V2H PLL and divider parameter calculation helpers from rzv2h-cpg.c into a new reusable library. Introduce the CLK_RZV2H_CPG_LIB Kconfig symbol and add rzv2h-cpg-lib.c to host the PLL parameter search algorithms currently implemented by rzv2h_get_pll_pars() and rzv2h_get_pll_divs_pars(). Export the helpers as rzv2h_cpg_get_pll_pars() and rzv2h_cpg_get_pll_divs_pars() for use by other drivers. Update the public clock header to expose the new interfaces and provide compatibility aliases for the existing helper names, avoiding build breakage for current users while allowing future conversions to the new API. This prepares for reuse of the PLL and divider calculation logic by other Renesas clock drivers, including upcoming RZ/T2H and RZ/N2H CPG support, without duplicating the implementation. Signed-off-by: Lad Prabhakar --- v3->v4: - Added macros for rzv2h_get_pll_pars and rzv2h_get_pll_divs_pars v2->v3: - Added export.h include in rzv2h-cpg-lib.c. v1->v2: - New patch --- drivers/clk/renesas/Kconfig | 4 + drivers/clk/renesas/Makefile | 1 + drivers/clk/renesas/rzv2h-cpg-lib.c | 217 ++++++++++++++++++++++++++++ drivers/clk/renesas/rzv2h-cpg.c | 203 -------------------------- include/linux/clk/renesas.h | 29 ++-- 5 files changed, 238 insertions(+), 216 deletions(-) create mode 100644 drivers/clk/renesas/rzv2h-cpg-lib.c diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig index 0203ecbb3882..7659550b8566 100644 --- a/drivers/clk/renesas/Kconfig +++ b/drivers/clk/renesas/Kconfig @@ -260,8 +260,12 @@ config CLK_RZG2L =20 config CLK_RZV2H bool "RZ/{G3E,V2H(P)} family clock support" if COMPILE_TEST + select CLK_RZV2H_CPG_LIB select RESET_CONTROLLER =20 +config CLK_RZV2H_CPG_LIB + bool "RZV2H CPG library functions" if COMPILE_TEST + config CLK_RENESAS_VBATTB tristate "Renesas VBATTB clock controller" depends on ARCH_RZG2L || COMPILE_TEST diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile index bd2bed91ab29..ac790e56034b 100644 --- a/drivers/clk/renesas/Makefile +++ b/drivers/clk/renesas/Makefile @@ -52,6 +52,7 @@ obj-$(CONFIG_CLK_RCAR_GEN3_CPG) +=3D rcar-gen3-cpg.o obj-$(CONFIG_CLK_RCAR_GEN4_CPG) +=3D rcar-gen4-cpg.o obj-$(CONFIG_CLK_RCAR_USB2_CLOCK_SEL) +=3D rcar-usb2-clock-sel.o obj-$(CONFIG_CLK_RZG2L) +=3D rzg2l-cpg.o +obj-$(CONFIG_CLK_RZV2H_CPG_LIB) +=3D rzv2h-cpg-lib.o obj-$(CONFIG_CLK_RZV2H) +=3D rzv2h-cpg.o =20 # Generic diff --git a/drivers/clk/renesas/rzv2h-cpg-lib.c b/drivers/clk/renesas/rzv2= h-cpg-lib.c new file mode 100644 index 000000000000..124239c7327e --- /dev/null +++ b/drivers/clk/renesas/rzv2h-cpg-lib.c @@ -0,0 +1,217 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * RZV2H CPG Library. This library provides common functions to calculate + * PLL parameters for the RZV2H SoC. + * + * Copyright (C) 2026 Renesas Electronics Corp. + * + */ + +#include +#include +#include +#include +#include + +/** + * rzv2h_cpg_get_pll_pars - Finds the best combination of PLL parameters + * for a given frequency. + * + * @limits: Pointer to the structure containing the limits for the PLL par= ameters + * @pars: Pointer to the structure where the best calculated PLL parameter= s values + * will be stored + * @freq_millihz: Target output frequency in millihertz + * + * This function calculates the best set of PLL parameters (M, K, P, S) to= achieve + * the desired frequency. + * There is no direct formula to calculate the PLL parameters, as it's an = open + * system of equations, therefore this function uses an iterative approach= to + * determine the best solution. The best solution is one that minimizes th= e error + * (desired frequency - actual frequency). + * + * Return: true if a valid set of parameters values is found, false otherw= ise. + */ +bool rzv2h_cpg_get_pll_pars(const struct rzv2h_pll_limits *limits, + struct rzv2h_pll_pars *pars, u64 freq_millihz) +{ + unsigned long input_fref =3D limits->input_fref ?: (24 * MEGA); + u64 fout_min_millihz =3D mul_u32_u32(limits->fout.min, MILLI); + u64 fout_max_millihz =3D mul_u32_u32(limits->fout.max, MILLI); + struct rzv2h_pll_pars p, best; + + if (freq_millihz > fout_max_millihz || + freq_millihz < fout_min_millihz) + return false; + + /* Initialize best error to maximum possible value */ + best.error_millihz =3D S64_MAX; + + for (p.p =3D limits->p.min; p.p <=3D limits->p.max; p.p++) { + u32 fref =3D input_fref / p.p; + u16 divider; + + for (divider =3D 1 << limits->s.min, p.s =3D limits->s.min; + p.s <=3D limits->s.max; p.s++, divider <<=3D 1) { + for (p.m =3D limits->m.min; p.m <=3D limits->m.max; p.m++) { + u64 output_m, output_k_range; + s64 pll_k, output_k; + u64 fvco, output; + + /* + * The frequency generated by the PLL + divider + * is calculated as follows: + * + * With: + * Freq =3D Ffout =3D Ffvco / 2^(pll_s) + * Ffvco =3D (pll_m + (pll_k / 65536)) * Ffref + * Ffref =3D 24MHz / pll_p + * + * Freq can also be rewritten as: + * Freq =3D Ffvco / 2^(pll_s) + * =3D ((pll_m + (pll_k / 65536)) * Ffref) / 2^(pll_s) + * =3D (pll_m * Ffref) / 2^(pll_s) + ((pll_k / 65536) * Ffref) / = 2^(pll_s) + * =3D output_m + output_k + * + * Every parameter has been determined at this + * point, but pll_k. + * + * Considering that: + * limits->k.min <=3D pll_k <=3D limits->k.max + * Then: + * -0.5 <=3D (pll_k / 65536) < 0.5 + * Therefore: + * -Ffref / (2 * 2^(pll_s)) <=3D output_k < Ffref / (2 * 2^(pll_s)) + */ + + /* Compute output M component (in mHz) */ + output_m =3D DIV_ROUND_CLOSEST_ULL(mul_u32_u32(p.m, fref) * MILLI, + divider); + /* Compute range for output K (in mHz) */ + output_k_range =3D DIV_ROUND_CLOSEST_ULL(mul_u32_u32(fref, MILLI), + 2 * divider); + /* + * No point in continuing if we can't achieve + * the desired frequency + */ + if (freq_millihz < (output_m - output_k_range) || + freq_millihz >=3D (output_m + output_k_range)) { + continue; + } + + /* + * Compute the K component + * + * Since: + * Freq =3D output_m + output_k + * Then: + * output_k =3D Freq - output_m + * =3D ((pll_k / 65536) * Ffref) / 2^(pll_s) + * Therefore: + * pll_k =3D (output_k * 65536 * 2^(pll_s)) / Ffref + */ + output_k =3D freq_millihz - output_m; + pll_k =3D div_s64(output_k * 65536ULL * divider, + fref); + pll_k =3D DIV_S64_ROUND_CLOSEST(pll_k, MILLI); + + /* Validate K value within allowed limits */ + if (pll_k < limits->k.min || + pll_k > limits->k.max) + continue; + + p.k =3D pll_k; + + /* Compute (Ffvco * 65536) */ + fvco =3D mul_u32_u32(p.m * 65536 + p.k, fref); + if (fvco < mul_u32_u32(limits->fvco.min, 65536) || + fvco > mul_u32_u32(limits->fvco.max, 65536)) + continue; + + /* PLL_M component of (output * 65536 * PLL_P) */ + output =3D mul_u32_u32(p.m * 65536, input_fref); + /* PLL_K component of (output * 65536 * PLL_P) */ + output +=3D p.k * input_fref; + /* Make it in mHz */ + output *=3D MILLI; + output =3D DIV_U64_ROUND_CLOSEST(output, 65536 * p.p * divider); + + /* Check output frequency against limits */ + if (output < fout_min_millihz || + output > fout_max_millihz) + continue; + + p.error_millihz =3D freq_millihz - output; + p.freq_millihz =3D output; + + /* If an exact match is found, return immediately */ + if (p.error_millihz =3D=3D 0) { + *pars =3D p; + return true; + } + + /* Update best match if error is smaller */ + if (abs(best.error_millihz) > abs(p.error_millihz)) + best =3D p; + } + } + } + + /* If no valid parameters were found, return false */ + if (best.error_millihz =3D=3D S64_MAX) + return false; + + *pars =3D best; + return true; +} +EXPORT_SYMBOL_NS_GPL(rzv2h_cpg_get_pll_pars, "RZV2H_CPG"); + +/* + * rzv2h_cpg_get_pll_divs_pars - Finds the best combination of PLL paramet= ers + * and divider value for a given frequency. + * + * @limits: Pointer to the structure containing the limits for the PLL par= ameters + * @pars: Pointer to the structure where the best calculated PLL parameter= s and + * divider values will be stored + * @table: Pointer to the array of valid divider values + * @table_size: Size of the divider values array + * @freq_millihz: Target output frequency in millihertz + * + * This function calculates the best set of PLL parameters (M, K, P, S) an= d divider + * value to achieve the desired frequency. See rzv2h_cpg_get_pll_pars() fo= r more + * details on how the PLL parameters are calculated. + * + * freq_millihz is the desired frequency generated by the PLL followed by a + * a gear. + */ +bool rzv2h_cpg_get_pll_divs_pars(const struct rzv2h_pll_limits *limits, + struct rzv2h_pll_div_pars *pars, + const u8 *table, u8 table_size, u64 freq_millihz) +{ + struct rzv2h_pll_div_pars p, best; + + best.div.error_millihz =3D S64_MAX; + p.div.error_millihz =3D S64_MAX; + for (unsigned int i =3D 0; i < table_size; i++) { + if (!rzv2h_cpg_get_pll_pars(limits, &p.pll, freq_millihz * table[i])) + continue; + + p.div.divider_value =3D table[i]; + p.div.freq_millihz =3D DIV_U64_ROUND_CLOSEST(p.pll.freq_millihz, table[i= ]); + p.div.error_millihz =3D freq_millihz - p.div.freq_millihz; + + if (p.div.error_millihz =3D=3D 0) { + *pars =3D p; + return true; + } + + if (abs(best.div.error_millihz) > abs(p.div.error_millihz)) + best =3D p; + } + + if (best.div.error_millihz =3D=3D S64_MAX) + return false; + + *pars =3D best; + return true; +} +EXPORT_SYMBOL_NS_GPL(rzv2h_cpg_get_pll_divs_pars, "RZV2H_CPG"); diff --git a/drivers/clk/renesas/rzv2h-cpg.c b/drivers/clk/renesas/rzv2h-cp= g.c index fff89f2bdc0b..738dfafc6d9c 100644 --- a/drivers/clk/renesas/rzv2h-cpg.c +++ b/drivers/clk/renesas/rzv2h-cpg.c @@ -220,209 +220,6 @@ struct rzv2h_plldsi_div_clk { =20 #define RZV2H_MAX_DIV_TABLES (16) =20 -/** - * rzv2h_get_pll_pars - Finds the best combination of PLL parameters - * for a given frequency. - * - * @limits: Pointer to the structure containing the limits for the PLL par= ameters - * @pars: Pointer to the structure where the best calculated PLL parameter= s values - * will be stored - * @freq_millihz: Target output frequency in millihertz - * - * This function calculates the best set of PLL parameters (M, K, P, S) to= achieve - * the desired frequency. - * There is no direct formula to calculate the PLL parameters, as it's an = open - * system of equations, therefore this function uses an iterative approach= to - * determine the best solution. The best solution is one that minimizes th= e error - * (desired frequency - actual frequency). - * - * Return: true if a valid set of parameters values is found, false otherw= ise. - */ -bool rzv2h_get_pll_pars(const struct rzv2h_pll_limits *limits, - struct rzv2h_pll_pars *pars, u64 freq_millihz) -{ - unsigned long input_fref =3D limits->input_fref ?: (24 * MEGA); - u64 fout_min_millihz =3D mul_u32_u32(limits->fout.min, MILLI); - u64 fout_max_millihz =3D mul_u32_u32(limits->fout.max, MILLI); - struct rzv2h_pll_pars p, best; - - if (freq_millihz > fout_max_millihz || - freq_millihz < fout_min_millihz) - return false; - - /* Initialize best error to maximum possible value */ - best.error_millihz =3D S64_MAX; - - for (p.p =3D limits->p.min; p.p <=3D limits->p.max; p.p++) { - u32 fref =3D input_fref / p.p; - u16 divider; - - for (divider =3D 1 << limits->s.min, p.s =3D limits->s.min; - p.s <=3D limits->s.max; p.s++, divider <<=3D 1) { - for (p.m =3D limits->m.min; p.m <=3D limits->m.max; p.m++) { - u64 output_m, output_k_range; - s64 pll_k, output_k; - u64 fvco, output; - - /* - * The frequency generated by the PLL + divider - * is calculated as follows: - * - * With: - * Freq =3D Ffout =3D Ffvco / 2^(pll_s) - * Ffvco =3D (pll_m + (pll_k / 65536)) * Ffref - * Ffref =3D 24MHz / pll_p - * - * Freq can also be rewritten as: - * Freq =3D Ffvco / 2^(pll_s) - * =3D ((pll_m + (pll_k / 65536)) * Ffref) / 2^(pll_s) - * =3D (pll_m * Ffref) / 2^(pll_s) + ((pll_k / 65536) * Ffref) / = 2^(pll_s) - * =3D output_m + output_k - * - * Every parameter has been determined at this - * point, but pll_k. - * - * Considering that: - * limits->k.min <=3D pll_k <=3D limits->k.max - * Then: - * -0.5 <=3D (pll_k / 65536) < 0.5 - * Therefore: - * -Ffref / (2 * 2^(pll_s)) <=3D output_k < Ffref / (2 * 2^(pll_s)) - */ - - /* Compute output M component (in mHz) */ - output_m =3D DIV_ROUND_CLOSEST_ULL(mul_u32_u32(p.m, fref) * MILLI, - divider); - /* Compute range for output K (in mHz) */ - output_k_range =3D DIV_ROUND_CLOSEST_ULL(mul_u32_u32(fref, MILLI), - 2 * divider); - /* - * No point in continuing if we can't achieve - * the desired frequency - */ - if (freq_millihz < (output_m - output_k_range) || - freq_millihz >=3D (output_m + output_k_range)) { - continue; - } - - /* - * Compute the K component - * - * Since: - * Freq =3D output_m + output_k - * Then: - * output_k =3D Freq - output_m - * =3D ((pll_k / 65536) * Ffref) / 2^(pll_s) - * Therefore: - * pll_k =3D (output_k * 65536 * 2^(pll_s)) / Ffref - */ - output_k =3D freq_millihz - output_m; - pll_k =3D div_s64(output_k * 65536ULL * divider, - fref); - pll_k =3D DIV_S64_ROUND_CLOSEST(pll_k, MILLI); - - /* Validate K value within allowed limits */ - if (pll_k < limits->k.min || - pll_k > limits->k.max) - continue; - - p.k =3D pll_k; - - /* Compute (Ffvco * 65536) */ - fvco =3D mul_u32_u32(p.m * 65536 + p.k, fref); - if (fvco < mul_u32_u32(limits->fvco.min, 65536) || - fvco > mul_u32_u32(limits->fvco.max, 65536)) - continue; - - /* PLL_M component of (output * 65536 * PLL_P) */ - output =3D mul_u32_u32(p.m * 65536, input_fref); - /* PLL_K component of (output * 65536 * PLL_P) */ - output +=3D p.k * input_fref; - /* Make it in mHz */ - output *=3D MILLI; - output =3D DIV_U64_ROUND_CLOSEST(output, 65536 * p.p * divider); - - /* Check output frequency against limits */ - if (output < fout_min_millihz || - output > fout_max_millihz) - continue; - - p.error_millihz =3D freq_millihz - output; - p.freq_millihz =3D output; - - /* If an exact match is found, return immediately */ - if (p.error_millihz =3D=3D 0) { - *pars =3D p; - return true; - } - - /* Update best match if error is smaller */ - if (abs(best.error_millihz) > abs(p.error_millihz)) - best =3D p; - } - } - } - - /* If no valid parameters were found, return false */ - if (best.error_millihz =3D=3D S64_MAX) - return false; - - *pars =3D best; - return true; -} -EXPORT_SYMBOL_NS_GPL(rzv2h_get_pll_pars, "RZV2H_CPG"); - -/* - * rzv2h_get_pll_divs_pars - Finds the best combination of PLL parameters - * and divider value for a given frequency. - * - * @limits: Pointer to the structure containing the limits for the PLL par= ameters - * @pars: Pointer to the structure where the best calculated PLL parameter= s and - * divider values will be stored - * @table: Pointer to the array of valid divider values - * @table_size: Size of the divider values array - * @freq_millihz: Target output frequency in millihertz - * - * This function calculates the best set of PLL parameters (M, K, P, S) an= d divider - * value to achieve the desired frequency. See rzv2h_get_pll_pars() for mo= re details - * on how the PLL parameters are calculated. - * - * freq_millihz is the desired frequency generated by the PLL followed by a - * a gear. - */ -bool rzv2h_get_pll_divs_pars(const struct rzv2h_pll_limits *limits, - struct rzv2h_pll_div_pars *pars, - const u8 *table, u8 table_size, u64 freq_millihz) -{ - struct rzv2h_pll_div_pars p, best; - - best.div.error_millihz =3D S64_MAX; - p.div.error_millihz =3D S64_MAX; - for (unsigned int i =3D 0; i < table_size; i++) { - if (!rzv2h_get_pll_pars(limits, &p.pll, freq_millihz * table[i])) - continue; - - p.div.divider_value =3D table[i]; - p.div.freq_millihz =3D DIV_U64_ROUND_CLOSEST(p.pll.freq_millihz, table[i= ]); - p.div.error_millihz =3D freq_millihz - p.div.freq_millihz; - - if (p.div.error_millihz =3D=3D 0) { - *pars =3D p; - return true; - } - - if (abs(best.div.error_millihz) > abs(p.div.error_millihz)) - best =3D p; - } - - if (best.div.error_millihz =3D=3D S64_MAX) - return false; - - *pars =3D best; - return true; -} -EXPORT_SYMBOL_NS_GPL(rzv2h_get_pll_divs_pars, "RZV2H_CPG"); - /** * struct rzv2h_plldsi_mux_clk - PLL DSI MUX clock * diff --git a/include/linux/clk/renesas.h b/include/linux/clk/renesas.h index 798bb0b54bab..c9495558cd5c 100644 --- a/include/linux/clk/renesas.h +++ b/include/linux/clk/renesas.h @@ -189,28 +189,31 @@ struct rzv2h_pll_div_pars { .k =3D { .min =3D -32768, .max =3D 32767 }, \ } \ =20 -#ifdef CONFIG_CLK_RZV2H -bool rzv2h_get_pll_pars(const struct rzv2h_pll_limits *limits, - struct rzv2h_pll_pars *pars, u64 freq_millihz); +#ifdef CONFIG_CLK_RZV2H_CPG_LIB +bool rzv2h_cpg_get_pll_pars(const struct rzv2h_pll_limits *limits, + struct rzv2h_pll_pars *pars, u64 freq_millihz); =20 -bool rzv2h_get_pll_divs_pars(const struct rzv2h_pll_limits *limits, - struct rzv2h_pll_div_pars *pars, - const u8 *table, u8 table_size, u64 freq_millihz); +bool rzv2h_cpg_get_pll_divs_pars(const struct rzv2h_pll_limits *limits, + struct rzv2h_pll_div_pars *pars, + const u8 *table, u8 table_size, u64 freq_millihz); #else -static inline bool rzv2h_get_pll_pars(const struct rzv2h_pll_limits *limit= s, - struct rzv2h_pll_pars *pars, - u64 freq_millihz) +static inline bool rzv2h_cpg_get_pll_pars(const struct rzv2h_pll_limits *l= imits, + struct rzv2h_pll_pars *pars, + u64 freq_millihz) { return false; } =20 -static inline bool rzv2h_get_pll_divs_pars(const struct rzv2h_pll_limits *= limits, - struct rzv2h_pll_div_pars *pars, - const u8 *table, u8 table_size, - u64 freq_millihz) +static inline bool rzv2h_cpg_get_pll_divs_pars(const struct rzv2h_pll_limi= ts *limits, + struct rzv2h_pll_div_pars *pars, + const u8 *table, u8 table_size, + u64 freq_millihz) { return false; } #endif =20 +#define rzv2h_get_pll_pars rzv2h_cpg_get_pll_pars +#define rzv2h_get_pll_divs_pars rzv2h_cpg_get_pll_divs_pars + #endif --=20 2.54.0 From nobody Fri Jun 19 13:54:32 2026 Received: from mail-wr1-f45.google.com (mail-wr1-f45.google.com [209.85.221.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 282043655ED for ; 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Thu, 18 Jun 2026 11:19:56 -0700 (PDT) Received: from iku.Home ([2a06:5906:61b:2d00:3bf7:d534:a488:f67d]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-465090c42e1sm869435f8f.11.2026.06.18.11.19.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Jun 2026 11:19:55 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Brian Masney , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm Cc: linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v4 5/5] clk: renesas: r9a09g077: Add LCDC and PLL3 clock support for RZ/T2H display pipeline Date: Thu, 18 Jun 2026 19:19:49 +0100 Message-ID: <20260618181949.3036280-6-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260618181949.3036280-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20260618181949.3036280-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Add the clock definitions and PLL logic required to supply the LCDC (VSPD/FCPVD/DU) blocks on the RZ/T2H (R9A09G077) SoC. The RZ/T2H display subsystem depends on a dedicated PLL (PLL3) and a set of new derived clocks. Introduce a new PLL clock type and implement rate recalculation, programming and locking sequences for PLL3 using the RZ/T2H specific divider and VCO limits. Add the corresponding muxes and divider entries, expose the LCDC core clock, and register the LCDC module clock using the correct PCLK parent. This enables the RZ/T2H clock driver to generate the display pipeline clocking tree needed by the DU and VSP-based composition engines, allowing upcoming display support to be integrated without duplicating CPG logic. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven --- v3->v4: - Added RB tag from Geert. v2->v3: - In r9a09g077_cpg_lcdc_div_determine_rate() made use of=20 clk_hw_get_parent_by_index() to ensure we retrieve pll3 as the parent. v1->v2: - Switched to use the new library - Kconfig now selects CLK_RZV2H_CPG_LIB - Renamed CPG_PLLEN to CPG_PLL_EN_EN - Renamed LCDCDIV to LCDC_CLKD - Changed ctr0/1 in r9a09g077_cpg_pll3_clk_recalc_rate() to use u32 --- drivers/clk/renesas/Kconfig | 2 + drivers/clk/renesas/r9a09g077-cpg.c | 373 +++++++++++++++++++++++++++- 2 files changed, 374 insertions(+), 1 deletion(-) diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig index 7659550b8566..5c0238e878b7 100644 --- a/drivers/clk/renesas/Kconfig +++ b/drivers/clk/renesas/Kconfig @@ -218,10 +218,12 @@ config CLK_R9A09G057 config CLK_R9A09G077 bool "RZ/T2H clock support" if COMPILE_TEST select CLK_RENESAS_CPG_MSSR + select CLK_RZV2H_CPG_LIB =20 config CLK_R9A09G087 bool "RZ/N2H clock support" if COMPILE_TEST select CLK_RENESAS_CPG_MSSR + select CLK_RZV2H_CPG_LIB =20 config CLK_SH73A0 bool "SH-Mobile AG5 clock support" if COMPILE_TEST diff --git a/drivers/clk/renesas/r9a09g077-cpg.c b/drivers/clk/renesas/r9a0= 9g077-cpg.c index f777601a23b9..873c41ae5606 100644 --- a/drivers/clk/renesas/r9a09g077-cpg.c +++ b/drivers/clk/renesas/r9a09g077-cpg.c @@ -8,16 +8,23 @@ =20 #include #include +#include #include #include +#include +#include #include #include +#include #include +#include =20 #include #include #include "renesas-cpg-mssr.h" =20 +MODULE_IMPORT_NS("RZV2H_CPG"); + #define RZT2H_REG_BLOCK_SHIFT 11 #define RZT2H_REG_OFFSET_MASK GENMASK(10, 0) #define RZT2H_REG_CONF(block, offset) (((block) << RZT2H_REG_BLOCK_SHIFT) = | \ @@ -66,11 +73,26 @@ #define DIVSCI2ASYNC CONF_PACK(SCKCR3, 10, 2) #define DIVSCI3ASYNC CONF_PACK(SCKCR3, 12, 2) #define DIVSCI4ASYNC CONF_PACK(SCKCR3, 14, 2) +#define LCDCDIVSEL CONF_PACK(SCKCR3, 20, 4) + +#define PLL3EN FIELD_PREP_CONST(OFFSET_MASK, (0xc0)) + +#define CPG_PLL_EN_EN BIT(0) +#define CPG_PLL3_VCO_CTR0(x) ((x) + 0x4) +#define CPG_PLL3_VCO_CTR0_PDIV GENMASK(21, 16) +#define CPG_PLL3_VCO_CTR0_MDIV GENMASK(9, 0) +#define CPG_PLL3_VCO_CTR1(x) ((x) + 0x8) +#define CPG_PLL3_VCO_CTR1_KDIV GENMASK(31, 16) +#define CPG_PLL3_VCO_CTR1_SDIV GENMASK(2, 0) +#define CPG_PLL_MON(x) ((x) - 0x10) +#define CPG_PLL_MON_LOCK BIT(0) =20 enum rzt2h_clk_types { CLK_TYPE_RZT2H_DIV =3D CLK_TYPE_CUSTOM, /* Clock with divider */ CLK_TYPE_RZT2H_MUX, /* Clock with clock source selector */ CLK_TYPE_RZT2H_FSELXSPI, /* Clock with FSELXSPIn source selector */ + CLK_TYPE_RZT2H_PLL3, /* PLL3 Clock */ + CLK_TYPE_RZT2H_LCDCDIV, /* LCDC divider clock */ }; =20 #define DEF_DIV(_name, _id, _parent, _conf, _dtable) \ @@ -83,10 +105,51 @@ enum rzt2h_clk_types { #define DEF_DIV_FSELXSPI(_name, _id, _parent, _conf, _dtable) \ DEF_TYPE(_name, _id, CLK_TYPE_RZT2H_FSELXSPI, .conf =3D _conf, \ .parent =3D _parent, .dtable =3D _dtable, .flag =3D 0) +#define DEF_PLL3(_name, _id, _parent, _conf) \ + DEF_TYPE(_name, _id, CLK_TYPE_RZT2H_PLL3, .conf =3D _conf, \ + .parent =3D _parent) +#define DEF_DIV_LCDC(_name, _id, _parent, _conf, _dtable) \ + DEF_TYPE(_name, _id, CLK_TYPE_RZT2H_LCDCDIV, .conf =3D _conf, \ + .parent =3D _parent, .dtable =3D _dtable, .flag =3D CLK_SET_RATE_PARENT) + +struct pll_clk { + void __iomem *reg; + const struct rzv2h_pll_limits *limits; + struct device *dev; + struct rzv2h_pll_pars pll_parameters; + struct clk_hw hw; + unsigned long cur_rate; +}; + +#define to_pll(_hw) container_of(_hw, struct pll_clk, hw) + +struct r9a09g077_lcdc_div_clk { + const struct clk_div_table *dtable; + void __iomem *reg; + struct device *dev; + struct clk_hw hw; + u32 conf; + u8 divider; +}; + +#define to_lcdc_div_clk(_hw) \ + container_of(_hw, struct r9a09g077_lcdc_div_clk, hw) + +#define RZT2H_MAX_LCDC_DIV_TABLES 16 + +static const struct rzv2h_pll_limits r9a09g077_cpg_pll3_limits =3D { + .input_fref =3D 48 * MEGA, + .fout =3D { .min =3D 25 * MEGA, .max =3D 430 * MEGA }, + .fvco =3D { .min =3D 1600 * MEGA, .max =3D 3200 * MEGA }, + .m =3D { .min =3D 0x40, .max =3D 0x3ff }, + .p =3D { .min =3D 0x2, .max =3D 0x8 }, + .s =3D { .min =3D 0x0, .max =3D 0x6 }, + .k =3D { .min =3D -32768, .max =3D 32767 }, +}; =20 enum clk_ids { /* Core Clock Outputs exported to DT */ - LAST_DT_CORE_CLK =3D R9A09G077_PCLKCAN, + LAST_DT_CORE_CLK =3D R9A09G077_LCDC_CLKD, =20 /* External Input Clocks */ CLK_EXTAL, @@ -96,10 +159,12 @@ enum clk_ids { CLK_PLL0, CLK_PLL1, CLK_PLL2, + CLK_PLL3, CLK_PLL4, CLK_SEL_CLK_PLL0, CLK_SEL_CLK_PLL1, CLK_SEL_CLK_PLL2, + CLK_SEL_CLK_PLL3, CLK_SEL_CLK_PLL4, CLK_PLL4D1, CLK_PLL4D1_DIV3, @@ -107,6 +172,7 @@ enum clk_ids { CLK_PLL4D3, CLK_PLL4D3_DIV10, CLK_PLL4D3_DIV20, + CLK_PLL4D50, CLK_SCI0ASYNC, CLK_SCI1ASYNC, CLK_SCI2ASYNC, @@ -119,6 +185,7 @@ enum clk_ids { CLK_SPI3ASYNC, CLK_DIVSELXSPI0_SCKCR, CLK_DIVSELXSPI1_SCKCR, + CLK_LCDDIVSEL, =20 /* Module Clocks */ MOD_CLK_BASE, @@ -130,6 +197,26 @@ static const struct clk_div_table dtable_1_2[] =3D { {0, 0}, }; =20 +static const struct clk_div_table dtable_2_32[] =3D { + {0, 2}, + {1, 4}, + {2, 6}, + {3, 8}, + {4, 10}, + {5, 12}, + {6, 14}, + {7, 16}, + {8, 18}, + {9, 20}, + {10, 22}, + {11, 24}, + {12, 26}, + {13, 28}, + {14, 30}, + {15, 32}, + {0, 0}, +}; + static const struct clk_div_table dtable_6_8_16_32_64[] =3D { {6, 64}, {5, 32}, @@ -152,6 +239,7 @@ static const struct clk_div_table dtable_24_25_30_32[] = =3D { static const char * const sel_clk_pll0[] =3D { ".loco", ".pll0" }; static const char * const sel_clk_pll1[] =3D { ".loco", ".pll1" }; static const char * const sel_clk_pll2[] =3D { ".loco", ".pll2" }; +static const char * const sel_clk_pll3[] =3D { ".loco", ".pll3" }; static const char * const sel_clk_pll4[] =3D { ".loco", ".pll4" }; static const char * const sel_clk_pll4d1_div3_div4[] =3D { ".pll4d1_div3",= ".pll4d1_div4" }; static const char * const sel_clk_pll4d3_div10_div20[] =3D { ".pll4d3_div1= 0", ".pll4d3_div20" }; @@ -173,10 +261,14 @@ static const struct cpg_core_clk r9a09g077_core_clks[= ] __initconst =3D { sel_clk_pll1, ARRAY_SIZE(sel_clk_pll1), CLK_MUX_READ_ONLY), DEF_MUX(".sel_clk_pll2", CLK_SEL_CLK_PLL2, SEL_PLL, sel_clk_pll2, ARRAY_SIZE(sel_clk_pll2), CLK_MUX_READ_ONLY), + DEF_MUX(".sel_clk_pll3", CLK_SEL_CLK_PLL3, SEL_PLL, + sel_clk_pll3, ARRAY_SIZE(sel_clk_pll3), CLK_MUX_READ_ONLY), DEF_MUX(".sel_clk_pll4", CLK_SEL_CLK_PLL4, SEL_PLL, sel_clk_pll4, ARRAY_SIZE(sel_clk_pll4), CLK_MUX_READ_ONLY), =20 DEF_FIXED(".pll4d1", CLK_PLL4D1, CLK_SEL_CLK_PLL4, 1, 1), + DEF_FIXED(".pll4d50", CLK_PLL4D50, CLK_SEL_CLK_PLL4, 50, 1), + DEF_PLL3(".pll3", CLK_PLL3, CLK_PLL4D50, PLL3EN), DEF_FIXED(".pll4d1_div3", CLK_PLL4D1_DIV3, CLK_PLL4D1, 3, 1), DEF_FIXED(".pll4d1_div4", CLK_PLL4D1_DIV4, CLK_PLL4D1, 4, 1), DEF_FIXED(".pll4d3", CLK_PLL4D3, CLK_SEL_CLK_PLL4, 3, 1), @@ -229,6 +321,7 @@ static const struct cpg_core_clk r9a09g077_core_clks[] = __initconst =3D { DEF_FIXED("PCLKL", R9A09G077_CLK_PCLKL, CLK_SEL_CLK_PLL1, 16, 1), DEF_FIXED("PCLKAH", R9A09G077_CLK_PCLKAH, CLK_PLL4D1, 6, 1), DEF_FIXED("PCLKAM", R9A09G077_CLK_PCLKAM, CLK_PLL4D1, 12, 1), + DEF_FIXED("PCLKAL", R9A09G077_CLK_PCLKAL, CLK_PLL4D1, 24, 1), DEF_FIXED("SDHI_CLKHS", R9A09G077_SDHI_CLKHS, CLK_SEL_CLK_PLL2, 1, 1), DEF_FIXED("USB_CLK", R9A09G077_USB_CLK, CLK_PLL4D1, 48, 1), DEF_FIXED("ETCLKA", R9A09G077_ETCLKA, CLK_SEL_CLK_PLL1, 5, 1), @@ -242,6 +335,8 @@ static const struct cpg_core_clk r9a09g077_core_clks[] = __initconst =3D { FSELXSPI1, dtable_6_8_16_32_64), DEF_MUX("PCLKCAN", R9A09G077_PCLKCAN, FSELCANFD, sel_clk_pll4d3_div10_div20, ARRAY_SIZE(sel_clk_pll4d3_div10_div20), 0), + DEF_DIV_LCDC("LCDC_CLKD", R9A09G077_LCDC_CLKD, CLK_SEL_CLK_PLL3, LCDCDIVS= EL, + dtable_2_32), }; =20 static const struct mssr_mod_clk r9a09g077_mod_clks[] __initconst =3D { @@ -272,6 +367,7 @@ static const struct mssr_mod_clk r9a09g077_mod_clks[] _= _initconst =3D { DEF_MOD("sci5fck", 600, CLK_SCI5ASYNC), DEF_MOD("iic2", 601, R9A09G077_CLK_PCLKL), DEF_MOD("spi3", 602, CLK_SPI3ASYNC), + DEF_MOD("lcdc", 1204, R9A09G077_CLK_PCLKAL), DEF_MOD("sdhi0", 1212, R9A09G077_CLK_PCLKAM), DEF_MOD("sdhi1", 1213, R9A09G077_CLK_PCLKAM), }; @@ -481,6 +577,276 @@ r9a09g077_cpg_fselxspi_div_clk_register(struct device= *dev, return hw->clk; } =20 +static unsigned long r9a09g077_cpg_pll3_clk_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct pll_clk *pll_clk =3D to_pll(hw); + u32 ctr0, ctr1; + u8 pdiv, sdiv; + u64 rate; + u16 mdiv; + s16 kdiv; + + ctr0 =3D readl(CPG_PLL3_VCO_CTR0(pll_clk->reg)); + ctr1 =3D readl(CPG_PLL3_VCO_CTR1(pll_clk->reg)); + + pdiv =3D FIELD_GET(CPG_PLL3_VCO_CTR0_PDIV, ctr0); + mdiv =3D FIELD_GET(CPG_PLL3_VCO_CTR0_MDIV, ctr0); + kdiv =3D (s16)FIELD_GET(CPG_PLL3_VCO_CTR1_KDIV, ctr1); + sdiv =3D FIELD_GET(CPG_PLL3_VCO_CTR1_SDIV, ctr1); + + rate =3D mul_u64_u32_shr(parent_rate, (mdiv << 16) + kdiv, 16 + sdiv); + + return DIV_ROUND_CLOSEST_ULL(rate, pdiv); +} + +static int r9a09g077_cpg_pll3_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + struct pll_clk *pll_clk =3D to_pll(hw); + u64 rate_millihz; + + if (req->rate =3D=3D pll_clk->cur_rate) + return 0; + + rate_millihz =3D mul_u32_u32(req->rate, MILLI); + if (!rzv2h_cpg_get_pll_pars(pll_clk->limits, &pll_clk->pll_parameters, + rate_millihz)) { + dev_dbg(pll_clk->dev, + "failed to determine rate for req->rate: %lu\n", + req->rate); + return -EINVAL; + } + req->rate =3D DIV_ROUND_CLOSEST_ULL(pll_clk->pll_parameters.freq_millihz,= MILLI); + pll_clk->cur_rate =3D req->rate; + + return 0; +} + +static int r9a09g077_cpg_pll3_set_rate(struct clk_hw *hw, unsigned long ra= te, + unsigned long parent_rate) +{ + struct pll_clk *pll_clk =3D to_pll(hw); + struct rzv2h_pll_pars *params =3D &pll_clk->pll_parameters; + void __iomem *offset =3D pll_clk->reg; + u32 val; + int ret; + + /* Put PLL into standby mode */ + writel(0, offset); + ret =3D readl_poll_timeout_atomic(CPG_PLL_MON(offset), + val, !(val & CPG_PLL_MON_LOCK), + 100, 2000); + if (ret) { + dev_err(pll_clk->dev, "Failed to put PLL into standby mode"); + return ret; + } + + /* Output clock setting 1 */ + val =3D readl(CPG_PLL3_VCO_CTR0(offset)); + FIELD_MODIFY(CPG_PLL3_VCO_CTR0_MDIV, &val, params->m); + FIELD_MODIFY(CPG_PLL3_VCO_CTR0_PDIV, &val, params->p); + writel(val, CPG_PLL3_VCO_CTR0(offset)); + + /* Output clock setting 2 */ + val =3D readl(CPG_PLL3_VCO_CTR1(offset)); + FIELD_MODIFY(CPG_PLL3_VCO_CTR1_KDIV, &val, params->k); + FIELD_MODIFY(CPG_PLL3_VCO_CTR1_SDIV, &val, params->s); + writel(val, CPG_PLL3_VCO_CTR1(offset)); + + writel(CPG_PLL_EN_EN, offset); + + /* PLL normal mode transition, output clock stability check */ + ret =3D readl_poll_timeout_atomic(CPG_PLL_MON(offset), + val, (val & CPG_PLL_MON_LOCK), + 100, 2000); + if (ret) { + writel(0, offset); + dev_err(pll_clk->dev, "Failed to put PLL into normal mode"); + return ret; + } + + return 0; +} + +static const struct clk_ops r9a09g077_cpg_pll3_ops =3D { + .recalc_rate =3D r9a09g077_cpg_pll3_clk_recalc_rate, + .determine_rate =3D r9a09g077_cpg_pll3_determine_rate, + .set_rate =3D r9a09g077_cpg_pll3_set_rate, +}; + +static struct clk * __init +r9a09g077_cpg_pll3_clk_register(struct device *dev, + const struct cpg_core_clk *core, + void __iomem *addr, + struct cpg_mssr_pub *pub, + const struct rzv2h_pll_limits *limits) +{ + struct clk_init_data init =3D {}; + const struct clk *parent; + const char *parent_name; + struct pll_clk *pll_clk; + int ret; + + parent =3D pub->clks[core->parent]; + if (IS_ERR(parent)) + return ERR_CAST(parent); + + pll_clk =3D devm_kzalloc(dev, sizeof(*pll_clk), GFP_KERNEL); + if (!pll_clk) + return ERR_PTR(-ENOMEM); + + parent_name =3D __clk_get_name(parent); + init.name =3D core->name; + init.ops =3D &r9a09g077_cpg_pll3_ops; + init.parent_names =3D &parent_name; + init.num_parents =3D 1; + + pll_clk->dev =3D dev; + pll_clk->hw.init =3D &init; + pll_clk->reg =3D addr; + pll_clk->limits =3D limits; + + ret =3D devm_clk_hw_register(dev, &pll_clk->hw); + if (ret) + return ERR_PTR(ret); + + return pll_clk->hw.clk; +} + +static int r9a09g077_cpg_lcdc_div_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + struct r9a09g077_lcdc_div_clk *dsi_div =3D to_lcdc_div_clk(hw); + struct clk_hw *mux_hw =3D clk_hw_get_parent(hw); + u8 table[RZT2H_MAX_LCDC_DIV_TABLES] =3D { 0 }; + struct rzv2h_pll_div_pars dsi_params; + const struct clk_div_table *div; + struct pll_clk *pll_clk; + unsigned int i =3D 0; + u64 freq_millihz; + + /* index 1 is always .pll3 in sel_clk_pll3[] */ + pll_clk =3D to_pll(clk_hw_get_parent_by_index(mux_hw, 1)); + + for (div =3D dsi_div->dtable; div->div; div++) { + if (i >=3D RZT2H_MAX_LCDC_DIV_TABLES) + return -EINVAL; + table[i++] =3D div->div; + } + + freq_millihz =3D mul_u32_u32(req->rate, MILLI); + + if (!rzv2h_cpg_get_pll_divs_pars(pll_clk->limits, &dsi_params, table, + i, freq_millihz)) { + dev_err(dsi_div->dev, + "LCDC divider failed to determine rate for req->rate: %lu\n", + req->rate); + return -EINVAL; + } + + req->rate =3D DIV_ROUND_CLOSEST_ULL(dsi_params.div.freq_millihz, MILLI); + req->best_parent_rate =3D req->rate * dsi_params.div.divider_value; + dsi_div->divider =3D dsi_params.div.divider_value; + pll_clk->cur_rate =3D req->best_parent_rate; + pll_clk->pll_parameters =3D dsi_params.pll; + + return 0; +} + +static int r9a09g077_cpg_lcdc_div_set_rate(struct clk_hw *hw, + unsigned long rate, + unsigned long parent_rate) +{ + struct r9a09g077_lcdc_div_clk *dsi_div =3D to_lcdc_div_clk(hw); + const struct clk_div_table *clkt; + bool divider_found =3D false; + u32 val, shift; + + for (clkt =3D dsi_div->dtable; clkt->div; clkt++) { + if (clkt->div =3D=3D dsi_div->divider) { + divider_found =3D true; + break; + } + } + + if (!divider_found) + return -EINVAL; + + shift =3D GET_SHIFT(dsi_div->conf); + val =3D readl(dsi_div->reg); + val &=3D ~(clk_div_mask(GET_WIDTH(dsi_div->conf)) << shift); + val |=3D clkt->val << shift; + writel(val, dsi_div->reg); + + return 0; +} + +static unsigned long +r9a09g077_cpg_lcdc_div_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct r9a09g077_lcdc_div_clk *dsi_div =3D to_lcdc_div_clk(hw); + u32 div; + + div =3D readl(dsi_div->reg); + div >>=3D GET_SHIFT(dsi_div->conf); + div &=3D clk_div_mask(GET_WIDTH(dsi_div->conf)); + div =3D dsi_div->dtable[div].div; + + return DIV_ROUND_CLOSEST_ULL(parent_rate, div); +} + +static const struct clk_ops r9a09g077_cpg_lcdc_div_ops =3D { + .recalc_rate =3D r9a09g077_cpg_lcdc_div_recalc_rate, + .determine_rate =3D r9a09g077_cpg_lcdc_div_determine_rate, + .set_rate =3D r9a09g077_cpg_lcdc_div_set_rate, +}; + +static struct clk * __init +r9a09g077_cpg_lcdc_div_clk_register(struct device *dev, + const struct cpg_core_clk *core, + void __iomem *addr, + struct cpg_mssr_pub *pub) +{ + struct r9a09g077_lcdc_div_clk *clk_hw_data; + struct clk_init_data init =3D {}; + struct clk **clks =3D pub->clks; + const struct clk *parent; + const char *parent_name; + struct clk_hw *hw; + int ret; + + parent =3D clks[core->parent]; + if (IS_ERR(parent)) + return ERR_CAST(parent); + + clk_hw_data =3D devm_kzalloc(dev, sizeof(*clk_hw_data), GFP_KERNEL); + if (!clk_hw_data) + return ERR_PTR(-ENOMEM); + + clk_hw_data->dtable =3D core->dtable; + clk_hw_data->reg =3D addr; + clk_hw_data->conf =3D core->conf; + clk_hw_data->dev =3D dev; + clk_hw_data->divider =3D 32; /* Initialize divider for LCDC */ + + parent_name =3D __clk_get_name(parent); + init.name =3D core->name; + init.ops =3D &r9a09g077_cpg_lcdc_div_ops; + init.flags =3D core->flag; + init.parent_names =3D &parent_name; + init.num_parents =3D 1; + + hw =3D &clk_hw_data->hw; + hw->init =3D &init; + ret =3D devm_clk_hw_register(dev, hw); + if (ret) + return ERR_PTR(ret); + + return hw->clk; +} + static struct clk * __init r9a09g077_cpg_clk_register(struct device *dev, const struct cpg_core_clk *= core, const struct cpg_mssr_info *info, @@ -497,6 +863,11 @@ r9a09g077_cpg_clk_register(struct device *dev, const s= truct cpg_core_clk *core, return r9a09g077_cpg_mux_clk_register(dev, core, addr, pub); case CLK_TYPE_RZT2H_FSELXSPI: return r9a09g077_cpg_fselxspi_div_clk_register(dev, core, addr, pub); + case CLK_TYPE_RZT2H_PLL3: + return r9a09g077_cpg_pll3_clk_register(dev, core, pub->base1 + offset, + pub, &r9a09g077_cpg_pll3_limits); + case CLK_TYPE_RZT2H_LCDCDIV: + return r9a09g077_cpg_lcdc_div_clk_register(dev, core, addr, pub); default: return ERR_PTR(-EINVAL); } --=20 2.54.0