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charset="utf-8" From: Richard Zhu The i.MX95 PCIe controller introduces three additional dedicated hardware interrupt lines for specific events: - intr: general controller events - aer: Advanced Error Reporting events - pme: Power Management Events These interrupts are optional on i.MX95. PCIe basic functionality (enumeration, configuration, and data transfer) works correctly without them, as the controller can operate using only the existing msi interrupt. Earlier i.MX PCIe variants (imx6q, imx6sx, imx6qp, imx7d, imx8mm, imx8mp, imx8mq, imx8q) do not have these three dedicated interrupt lines. Update the binding to allow up to 5 interrupts for i.MX95, while restricting earlier variants to a maximum of 2 interrupts using conditional constraints (if/then schema). This ensures the schema accurately reflects the hardware capabilities of each SoC variant. Signed-off-by: Richard Zhu Reviewed-by: Frank Li --- .../bindings/pci/fsl,imx6q-pcie.yaml | 25 +++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/Do= cumentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml index e8b8131f5f23b..4f56e8e4f1008 100644 --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml @@ -58,12 +58,18 @@ properties: items: - description: builtin MSI controller. - description: builtin DMA controller. + - description: PCIe event interrupt. + - description: builtin AER SPI standalone interrupt line. + - description: builtin PME SPI standalone interrupt line. =20 interrupt-names: minItems: 1 items: - const: msi - const: dma + - const: intr + - const: aer + - const: pme =20 reset-gpio: deprecated: true @@ -249,6 +255,25 @@ allOf: - const: ref - const: extref # Optional =20 + - if: + properties: + compatible: + enum: + - fsl,imx6q-pcie + - fsl,imx6sx-pcie + - fsl,imx6qp-pcie + - fsl,imx7d-pcie + - fsl,imx8mm-pcie + - fsl,imx8mp-pcie + - fsl,imx8mq-pcie + - fsl,imx8q-pcie + then: + properties: + interrupts: + maxItems: 2 + interrupt-names: + maxItems: 2 + unevaluatedProperties: false =20 examples: --=20 2.34.1 From nobody Fri Jun 19 08:49:05 2026 Received: from MRWPR03CU001.outbound.protection.outlook.com (mail-francesouthazon11011046.outbound.protection.outlook.com [40.107.130.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 264E426E70E; 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charset="utf-8" From: Richard Zhu The current PCIe device tree configuration only defines the MSI interrupt, which is sufficient for basic PCIe operation but limits advanced functionality. Add the following interrupt lines to pcie0 and pcie1 nodes: - dma: DMA interrupt for PCIe DMA operations - intr: General controller events and link state changes - aer: Advanced Error Reporting interrupt - pme: Power Management Event interrupt This enables enhanced PCIe features and capabilities that were previously unavailable due to missing interrupt definitions. Signed-off-by: Richard Zhu --- arch/arm64/boot/dts/freescale/imx95.dtsi | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts= /freescale/imx95.dtsi index 3e35c956a4d7a..1a9803f967901 100644 --- a/arch/arm64/boot/dts/freescale/imx95.dtsi +++ b/arch/arm64/boot/dts/freescale/imx95.dtsi @@ -1945,8 +1945,12 @@ pcie0: pcie@4c300000 { bus-range =3D <0x00 0xff>; num-lanes =3D <1>; num-viewport =3D <8>; - interrupts =3D ; - interrupt-names =3D "msi"; + interrupts =3D , + , + , + , + ; + interrupt-names =3D "msi", "dma", "intr", "aer", "pme"; #interrupt-cells =3D <1>; interrupt-map-mask =3D <0 0 0 0x7>; interrupt-map =3D <0 0 0 1 &gic 0 0 GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, @@ -2020,8 +2024,12 @@ pcie1: pcie@4c380000 { bus-range =3D <0x00 0xff>; num-lanes =3D <1>; num-viewport =3D <8>; - interrupts =3D ; - interrupt-names =3D "msi"; + interrupts =3D , + , + , + , + ; + interrupt-names =3D "msi", "dma", "intr", "aer", "pme"; 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charset="utf-8" From: Richard Zhu The PCIe link can go down due to various unexpected circumstances. Add root port reset support to enable link recovery for the i.MX PCIe controller when the optional "intr" interrupt is present. When a link down event occurs, reset the root port by: uninitializing the PCIe controller, re-initializing it, and restarting the link. On i.MX95 platforms, link events and PME share the same interrupt line. The link event interrupt cannot use a threaded-only IRQ handler because the PME driver uses request_irq() with only the IRQF_SHARED flag set, which requires a primary handler. To handle this shared interrupt scenario, register a primary interrupt handler with IRQF_SHARED for link events and manipulate the link event enable bits to ensure the shared interrupt source triggers only one handler at a time. Signed-off-by: Richard Zhu --- drivers/pci/controller/dwc/pci-imx6.c | 132 ++++++++++++++++++++++++++ 1 file changed, 132 insertions(+) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller= /dwc/pci-imx6.c index 773ab65b2afac..3de70f41b0b85 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -79,6 +79,11 @@ #define IMX95_SID_MASK GENMASK(5, 0) #define IMX95_MAX_LUT 32 =20 +#define IMX95_LINK_INT_CTRL_STS 0x1040 +#define IMX95_PE0_INT_STS 0x10e8 +#define IMX95_LINK_DOWN_INT_STS BIT(11) +#define IMX95_LINK_DOWN_INT_EN BIT(10) + #define IMX95_PCIE_RST_CTRL 0x3010 #define IMX95_PCIE_COLD_RST BIT(0) =20 @@ -126,6 +131,8 @@ enum imx_pcie_variants { #define IMX_PCIE_MAX_INSTANCES 2 =20 struct imx_pcie; +static int imx_pcie_reset_root_port(struct pci_host_bridge *bridge, + struct pci_dev *pdev); =20 struct imx_pcie_drvdata { enum imx_pcie_variants variant; @@ -158,6 +165,7 @@ struct imx_pcie { bool supports_clkreq; bool enable_ext_refclk; struct regmap *iomuxc_gpr; + int lnk_intr; u16 msi_ctrl; u32 controller_id; struct reset_control *pciephy_reset; @@ -1394,6 +1402,13 @@ static int imx_pcie_host_init(struct dw_pcie_rp *pp) =20 imx_setup_phy_mpll(imx_pcie); =20 + /* + * Callback invoked by PCI core when link down is detected and + * recovery is needed. + */ + if (pp->bridge) + pp->bridge->reset_root_port =3D imx_pcie_reset_root_port; + return 0; =20 err_phy_off: @@ -1661,6 +1676,9 @@ static int imx_pcie_suspend_noirq(struct device *dev) if (!(imx_pcie->drvdata->flags & IMX_PCIE_FLAG_SUPPORTS_SUSPEND)) return 0; =20 + if (imx_pcie->lnk_intr > 0) + regmap_clear_bits(imx_pcie->iomuxc_gpr, IMX95_LINK_INT_CTRL_STS, + IMX95_LINK_DOWN_INT_EN); imx_pcie_msi_save_restore(imx_pcie, true); if (imx_check_flag(imx_pcie, IMX_PCIE_FLAG_HAS_LUT)) imx_pcie_lut_save(imx_pcie); @@ -1711,6 +1729,9 @@ static int imx_pcie_resume_noirq(struct device *dev) if (imx_check_flag(imx_pcie, IMX_PCIE_FLAG_HAS_LUT)) imx_pcie_lut_restore(imx_pcie); imx_pcie_msi_save_restore(imx_pcie, false); + if (imx_pcie->lnk_intr > 0) + regmap_set_bits(imx_pcie->iomuxc_gpr, IMX95_LINK_INT_CTRL_STS, + IMX95_LINK_DOWN_INT_EN); =20 return 0; } @@ -1720,6 +1741,86 @@ static const struct dev_pm_ops imx_pcie_pm_ops =3D { imx_pcie_resume_noirq) }; =20 +static irqreturn_t imx_pcie_lnk_irq_isr(int irq, void *priv) +{ + struct imx_pcie *imx_pcie =3D priv; + struct dw_pcie *pci =3D imx_pcie->pci; + struct device *dev =3D pci->dev; + u32 val; + + regmap_read(imx_pcie->iomuxc_gpr, IMX95_LINK_INT_CTRL_STS, &val); + if (val & IMX95_LINK_DOWN_INT_STS) { + dev_dbg(dev, "PCIe link down detected, initiating recovery\n"); + /* Clear link down interrupt status by writing 1b'1 to it */ + regmap_set_bits(imx_pcie->iomuxc_gpr, IMX95_LINK_INT_CTRL_STS, + IMX95_LINK_DOWN_INT_STS); + if (!(val & IMX95_LINK_DOWN_INT_EN)) + return IRQ_NONE; + regmap_clear_bits(imx_pcie->iomuxc_gpr, IMX95_LINK_INT_CTRL_STS, + IMX95_LINK_DOWN_INT_EN); + + return IRQ_WAKE_THREAD; + } + + regmap_read(imx_pcie->iomuxc_gpr, IMX95_PE0_INT_STS, &val); + if (unlikely(val)) + regmap_write(imx_pcie->iomuxc_gpr, IMX95_PE0_INT_STS, val); + + return IRQ_NONE; +} + +static irqreturn_t imx_pcie_lnk_irq_thread(int irq, void *priv) +{ + struct imx_pcie *imx_pcie =3D priv; + struct dw_pcie *pci =3D imx_pcie->pci; + struct dw_pcie_rp *pp =3D &pci->pp; + struct pci_dev *port; + + for_each_pci_bridge(port, pp->bridge->bus) + if (pci_pcie_type(port) =3D=3D PCI_EXP_TYPE_ROOT_PORT) + pci_host_handle_link_down(port); + + regmap_set_bits(imx_pcie->iomuxc_gpr, IMX95_LINK_INT_CTRL_STS, + IMX95_LINK_DOWN_INT_EN); + + return IRQ_HANDLED; +} + +static int imx_pcie_reset_root_port(struct pci_host_bridge *bridge, + struct pci_dev *pdev) +{ + struct pci_bus *bus =3D bridge->bus; + struct dw_pcie_rp *pp =3D bus->sysdata; + struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); + struct imx_pcie *imx_pcie =3D to_imx_pcie(pci); + int ret; + + imx_pcie_msi_save_restore(imx_pcie, true); + if (imx_check_flag(imx_pcie, IMX_PCIE_FLAG_HAS_LUT)) + imx_pcie_lut_save(imx_pcie); + imx_pcie_stop_link(pci); + imx_pcie_host_exit(pp); + + ret =3D imx_pcie_host_init(pp); + if (ret) { + dev_err(pci->dev, "Failed to re-init PCIe\n"); + return ret; + } + ret =3D dw_pcie_setup_rc(pp); + if (ret) + return ret; + + imx_pcie_start_link(pci); + dw_pcie_wait_for_link(pci); + + if (imx_check_flag(imx_pcie, IMX_PCIE_FLAG_HAS_LUT)) + imx_pcie_lut_restore(imx_pcie); + imx_pcie_msi_save_restore(imx_pcie, false); + + dev_dbg(pci->dev, "Root port reset completed\n"); + return 0; +} + static int imx_pcie_probe(struct platform_device *pdev) { struct device *dev =3D &pdev->dev; @@ -1919,15 +2020,46 @@ static int imx_pcie_probe(struct platform_device *p= dev) val |=3D PCI_MSI_FLAGS_ENABLE; dw_pcie_writew_dbi(pci, offset + PCI_MSI_FLAGS, val); } + + /* Get link event irq if it is present */ + imx_pcie->lnk_intr =3D platform_get_irq_byname_optional(pdev, "intr"); + if (imx_pcie->lnk_intr =3D=3D -EPROBE_DEFER) { + ret =3D -EPROBE_DEFER; + goto err_host_deinit; + } + if (imx_pcie->lnk_intr > 0) { + ret =3D devm_request_threaded_irq(dev, imx_pcie->lnk_intr, + imx_pcie_lnk_irq_isr, + imx_pcie_lnk_irq_thread, + IRQF_SHARED, + "lnk", imx_pcie); + if (ret) { + dev_err_probe(dev, ret, + "unable to request LNK IRQ\n"); + goto err_host_deinit; + } + + regmap_set_bits(imx_pcie->iomuxc_gpr, + IMX95_LINK_INT_CTRL_STS, + IMX95_LINK_DOWN_INT_EN); + } } =20 return 0; + +err_host_deinit: + dw_pcie_host_deinit(&pci->pp); + + return ret; } =20 static void imx_pcie_shutdown(struct platform_device *pdev) { struct imx_pcie *imx_pcie =3D platform_get_drvdata(pdev); =20 + if (imx_pcie->lnk_intr > 0) + regmap_clear_bits(imx_pcie->iomuxc_gpr, IMX95_LINK_INT_CTRL_STS, + IMX95_LINK_DOWN_INT_EN); /* bring down link, so bootloader gets clean state in case of reboot */ imx_pcie_assert_core_reset(imx_pcie); imx_pcie_assert_perst(imx_pcie, true); --=20 2.34.1