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Reviewed-by: Krzysztof Kozlowski Signed-off-by: Matthew Leung --- .../devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 6 ++= ++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-p= hy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.= yaml index 3a35120a77ec..9e9e34a63bef 100644 --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml @@ -18,6 +18,8 @@ properties: enum: - qcom,glymur-qmp-gen4x2-pcie-phy - qcom,glymur-qmp-gen5x4-pcie-phy + - qcom,hawi-qmp-gen3x2-pcie-phy + - qcom,hawi-qmp-gen4x1-pcie-phy - qcom,kaanapali-qmp-gen3x2-pcie-phy - qcom,qcs615-qmp-gen3x1-pcie-phy - qcom,qcs8300-qmp-gen4x2-pcie-phy @@ -183,6 +185,8 @@ allOf: enum: - qcom,glymur-qmp-gen4x2-pcie-phy - qcom,glymur-qmp-gen5x4-pcie-phy + - qcom,hawi-qmp-gen3x2-pcie-phy + - qcom,hawi-qmp-gen4x1-pcie-phy - qcom,qcs8300-qmp-gen4x2-pcie-phy - qcom,sa8775p-qmp-gen4x2-pcie-phy - qcom,sa8775p-qmp-gen4x4-pcie-phy @@ -208,6 +212,8 @@ allOf: enum: - qcom,glymur-qmp-gen4x2-pcie-phy - qcom,glymur-qmp-gen5x4-pcie-phy + - qcom,hawi-qmp-gen3x2-pcie-phy + - qcom,hawi-qmp-gen4x1-pcie-phy - qcom,kaanapali-qmp-gen3x2-pcie-phy - qcom,sm8550-qmp-gen4x2-pcie-phy - qcom,sm8650-qmp-gen4x2-pcie-phy --=20 2.34.1 From nobody Fri Jun 19 19:55:23 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 23D753431E7 for ; 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Add the new register offset headers for all four sub-blocks: - QSERDES-COM offsets - QSERDES TX/RX offsets - PCS offsets - PCS PCIe-specific offsets Signed-off-by: Matthew Leung --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 1 + drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v10.h | 18 ++++++++ drivers/phy/qualcomm/phy-qcom-qmp-pcs-v10.h | 22 ++++++++++ .../phy/qualcomm/phy-qcom-qmp-qserdes-com-v10.h | 49 ++++++++++++++++++= ++++ .../phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v10.h | 47 ++++++++++++++++++= +++ drivers/phy/qualcomm/phy-qcom-qmp.h | 5 +++ 6 files changed, 142 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcom= m/phy-qcom-qmp-pcie.c index fed2fc9bb311..ba17e53d000f 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -40,6 +40,7 @@ #include "phy-qcom-qmp-qserdes-com-v8.h" #include "phy-qcom-qmp-pcs-pcie-v8.h" #include "phy-qcom-qmp-qserdes-txrx-pcie-v8.h" +#include "phy-qcom-qmp-pcs-pcie-v10.h" =20 #define PHY_INIT_COMPLETE_TIMEOUT 10000 =20 diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v10.h b/drivers/phy= /qualcomm/phy-qcom-qmp-pcs-pcie-v10.h new file mode 100644 index 000000000000..2cdcc211bd93 --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v10.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef QCOM_PHY_QMP_PCS_PCIE_V10_H_ +#define QCOM_PHY_QMP_PCS_PCIE_V10_H_ + +/* Only for QMP V10 PHY - PCIE PCS registers */ +#define QPHY_PCIE_V10_PCS_POWER_STATE_CONFIG2 0x00c +#define QPHY_PCIE_V10_PCS_POWER_STATE_CONFIG4 0x014 +#define QPHY_PCIE_V10_PCS_ENDPOINT_REFCLK_DRIVE 0x020 +#define QPHY_PCIE_V10_PCS_OSC_DTCT_ACTIONS 0x094 +#define QPHY_PCIE_V10_PCS_EQ_CONFIG1 0x0a4 +#define QPHY_PCIE_V10_PCS_RXEQEVAL_TIME 0x0f4 +#define QPHY_PCIE_V10_PCS_POWER_STATE_CONFIG6 0x0f8 + +#endif diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v10.h b/drivers/phy/qual= comm/phy-qcom-qmp-pcs-v10.h new file mode 100644 index 000000000000..165ce8a28f61 --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v10.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef QCOM_PHY_QMP_PCS_V10_H_ +#define QCOM_PHY_QMP_PCS_V10_H_ + +/* Only for QMP V10 PHY - PCIe PCS registers */ +#define QPHY_V10_PCS_SW_RESET 0x000 +#define QPHY_V10_PCS_PCS_STATUS1 0x014 +#define QPHY_V10_PCS_POWER_DOWN_CONTROL 0x040 +#define QPHY_V10_PCS_START_CONTROL 0x044 +#define QPHY_V10_PCS_REFGEN_REQ_CONFIG1 0x0dc +#define QPHY_V10_PCS_G12S1_TXDEEMPH_M6DB 0x168 +#define QPHY_V10_PCS_G3S2_PRE_GAIN 0x170 +#define QPHY_V10_PCS_RX_SIGDET_LVL 0x188 +#define QPHY_V10_PCS_RATE_SLEW_CNTRL1 0x198 +#define QPHY_V10_PCS_PCS_TX_RX_CONFIG 0x1d0 +#define QPHY_V10_PCS_EQ_CONFIG2 0x1e4 + +#endif diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v10.h b/drivers/= phy/qualcomm/phy-qcom-qmp-qserdes-com-v10.h new file mode 100644 index 000000000000..09199e7b4aac --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v10.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef QCOM_PHY_QMP_QSERDES_COM_V10_H_ +#define QCOM_PHY_QMP_QSERDES_COM_V10_H_ + +/* Only for QMP V10 PHY - QSERDES COM registers */ +#define QSERDES_V10_COM_SSC_STEP_SIZE1_MODE1 0x00 +#define QSERDES_V10_COM_SSC_STEP_SIZE2_MODE1 0x04 +#define QSERDES_V10_COM_CP_CTRL_MODE1 0x10 +#define QSERDES_V10_COM_PLL_RCTRL_MODE1 0x14 +#define QSERDES_V10_COM_PLL_CCTRL_MODE1 0x18 +#define QSERDES_V10_COM_CORECLK_DIV_MODE1 0x1c +#define QSERDES_V10_COM_LOCK_CMP1_MODE1 0x20 +#define QSERDES_V10_COM_LOCK_CMP2_MODE1 0x24 +#define QSERDES_V10_COM_DEC_START_MODE1 0x28 +#define QSERDES_V10_COM_DIV_FRAC_START1_MODE1 0x30 +#define QSERDES_V10_COM_DIV_FRAC_START2_MODE1 0x34 +#define QSERDES_V10_COM_DIV_FRAC_START3_MODE1 0x38 +#define QSERDES_V10_COM_HSCLK_SEL_1 0x3c +#define QSERDES_V10_COM_SSC_STEP_SIZE1_MODE0 0x60 +#define QSERDES_V10_COM_SSC_STEP_SIZE2_MODE0 0x64 +#define QSERDES_V10_COM_CP_CTRL_MODE0 0x70 +#define QSERDES_V10_COM_PLL_RCTRL_MODE0 0x74 +#define QSERDES_V10_COM_PLL_CCTRL_MODE0 0x78 +#define QSERDES_V10_COM_LOCK_CMP1_MODE0 0x80 +#define QSERDES_V10_COM_LOCK_CMP2_MODE0 0x84 +#define QSERDES_V10_COM_DEC_START_MODE0 0x88 +#define QSERDES_V10_COM_DIV_FRAC_START1_MODE0 0x90 +#define QSERDES_V10_COM_DIV_FRAC_START2_MODE0 0x94 +#define QSERDES_V10_COM_DIV_FRAC_START3_MODE0 0x98 +#define QSERDES_V10_COM_BG_TIMER 0xbc +#define QSERDES_V10_COM_SSC_EN_CENTER 0xc0 +#define QSERDES_V10_COM_SSC_PER1 0xcc +#define QSERDES_V10_COM_SSC_PER2 0xd0 +#define QSERDES_V10_COM_CLK_ENABLE1 0xe0 +#define QSERDES_V10_COM_SYS_CLK_CTRL 0xe4 +#define QSERDES_V10_COM_PLL_IVCO 0xf4 +#define QSERDES_V10_COM_SYSCLK_EN_SEL 0x110 +#define QSERDES_V10_COM_LOCK_CMP_EN 0x120 +#define QSERDES_V10_COM_VCO_TUNE_MAP 0x140 +#define QSERDES_V10_COM_CLK_SELECT 0x164 +#define QSERDES_V10_COM_CORE_CLK_EN 0x170 +#define QSERDES_V10_COM_CMN_CONFIG_1 0x174 +#define QSERDES_V10_COM_ADDITIONAL_MISC_3 0x1bc + +#endif diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v10.h b/drivers= /phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v10.h new file mode 100644 index 000000000000..d81ebdde0063 --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v10.h @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef QCOM_PHY_QMP_QSERDES_TXRX_V10_H_ +#define QCOM_PHY_QMP_QSERDES_TXRX_V10_H_ + +#define QSERDES_V10_TX_RES_CODE_LANE_OFFSET_TX 0x03c +#define QSERDES_V10_TX_RES_CODE_LANE_OFFSET_RX 0x040 +#define QSERDES_V10_TX_LANE_MODE_1 0x084 +#define QSERDES_V10_TX_LANE_MODE_3 0x08c +#define QSERDES_V10_TX_LANE_MODE_4 0x090 +#define QSERDES_V10_TX_LANE_MODE_5 0x094 +#define QSERDES_V10_TX_PI_QEC_CTRL 0x0e4 + +#define QSERDES_V10_RX_UCDR_FO_GAIN 0x008 +#define QSERDES_V10_RX_UCDR_SO_GAIN 0x014 +#define QSERDES_V10_RX_UCDR_SB2_THRESH1 0x04c +#define QSERDES_V10_RX_UCDR_SB2_THRESH2 0x050 +#define QSERDES_V10_RX_TX_ADAPT_PRE_THRESH1 0x0c4 +#define QSERDES_V10_RX_TX_ADAPT_PRE_THRESH2 0x0c8 +#define QSERDES_V10_RX_TX_ADAPT_POST_THRESH 0x0cc +#define QSERDES_V10_RX_VGA_CAL_CNTRL2 0x0d8 +#define QSERDES_V10_RX_GM_CAL 0x0dc +#define QSERDES_V10_RX_RX_IDAC_TSETTLE_LOW 0x0f8 +#define QSERDES_V10_RX_SIGDET_ENABLES 0x118 +#define QSERDES_V10_RX_SIGDET_CNTRL 0x11c +#define QSERDES_V10_RX_RX_MODE_00_LOW 0x15c +#define QSERDES_V10_RX_RX_MODE_00_HIGH 0x160 +#define QSERDES_V10_RX_RX_MODE_00_HIGH2 0x164 +#define QSERDES_V10_RX_RX_MODE_00_HIGH3 0x168 +#define QSERDES_V10_RX_RX_MODE_00_HIGH4 0x16c +#define QSERDES_V10_RX_RX_MODE_01_LOW 0x170 +#define QSERDES_V10_RX_RX_MODE_01_HIGH 0x174 +#define QSERDES_V10_RX_RX_MODE_01_HIGH2 0x178 +#define QSERDES_V10_RX_RX_MODE_01_HIGH3 0x17c +#define QSERDES_V10_RX_RX_MODE_01_HIGH4 0x180 +#define QSERDES_V10_RX_RX_MODE_10_LOW 0x184 +#define QSERDES_V10_RX_RX_MODE_10_HIGH 0x188 +#define QSERDES_V10_RX_RX_MODE_10_HIGH2 0x18c +#define QSERDES_V10_RX_RX_MODE_10_HIGH3 0x190 +#define QSERDES_V10_RX_RX_MODE_10_HIGH4 0x194 +#define QSERDES_V10_RX_DFE_CTLE_POST_CAL_OFFSET 0x1a4 +#define QSERDES_V10_RX_SIGDET_CAL_TRIM 0x1f8 + +#endif diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy= -qcom-qmp.h index a873bdd7bffe..7af77572970e 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp.h @@ -39,6 +39,9 @@ #include "phy-qcom-qmp-qserdes-txrx-v8.h" #include "phy-qcom-qmp-qserdes-lalb-v8.h" =20 +#include "phy-qcom-qmp-qserdes-com-v10.h" +#include "phy-qcom-qmp-qserdes-txrx-v10.h" + #include "phy-qcom-qmp-qserdes-pll.h" =20 #include "phy-qcom-qmp-pcs-v2.h" @@ -65,6 +68,8 @@ =20 #include "phy-qcom-qmp-pcs-v8_50.h" =20 +#include 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Add the new register offset headers for all four sub-blocks: - QSERDES-COM offsets - QSERDES TX/RX offsets - PCS offsets - PCS PCIe-specific offsets Signed-off-by: Matthew Leung --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 1 + .../phy/qualcomm/phy-qcom-qmp-pcs-pcie-v10_60.h | 26 +++++ drivers/phy/qualcomm/phy-qcom-qmp-pcs-v10_60.h | 23 +++++ .../phy/qualcomm/phy-qcom-qmp-qserdes-com-v10_60.h | 55 +++++++++++ .../qualcomm/phy-qcom-qmp-qserdes-txrx-v10_60.h | 109 +++++++++++++++++= ++++ drivers/phy/qualcomm/phy-qcom-qmp.h | 5 + 6 files changed, 219 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcom= m/phy-qcom-qmp-pcie.c index ba17e53d000f..fb66e2a97ce0 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -41,6 +41,7 @@ #include "phy-qcom-qmp-pcs-pcie-v8.h" #include "phy-qcom-qmp-qserdes-txrx-pcie-v8.h" #include "phy-qcom-qmp-pcs-pcie-v10.h" +#include "phy-qcom-qmp-pcs-pcie-v10_60.h" =20 #define PHY_INIT_COMPLETE_TIMEOUT 10000 =20 diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v10_60.h b/drivers/= phy/qualcomm/phy-qcom-qmp-pcs-pcie-v10_60.h new file mode 100644 index 000000000000..2df5a45010a4 --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v10_60.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef QCOM_PHY_QMP_PCS_PCIE_V10_60_H_ +#define QCOM_PHY_QMP_PCS_PCIE_V10_60_H_ + +/* Only for QMP V10_60 PHY - PCIE PCS registers */ +#define QPHY_PCIE_V10_60_PCS_POWER_STATE_CONFIG2 0x00c +#define QPHY_PCIE_V10_60_PCS_TX_RX_CONFIG 0x018 +#define QPHY_PCIE_V10_60_PCS_ENDPOINT_REFCLK_DRIVE 0x01c +#define QPHY_PCIE_V10_60_PCS_OSC_DTCT_ACTIONS 0x090 +#define QPHY_PCIE_V10_60_PCS_EQ_CONFIG1 0x0a0 +#define QPHY_PCIE_V10_60_PCS_G3_RXEQEVAL_TIME 0x0f0 +#define QPHY_PCIE_V10_60_PCS_G4_RXEQEVAL_TIME 0x0f4 +#define QPHY_PCIE_V10_60_PCS_G4_EQ_CONFIG5 0x108 +#define QPHY_PCIE_V10_60_PCS_G4_PRE_GAIN 0x15c +#define QPHY_PCIE_V10_60_PCS_RX_MARGINING_CONFIG1 0x17c +#define QPHY_PCIE_V10_60_PCS_RX_MARGINING_CONFIG3 0x184 +#define QPHY_PCIE_V10_60_PCS_RX_MARGINING_CONFIG5 0x18c +#define QPHY_PCIE_V10_60_PCS_G3_FOM_EQ_CONFIG5 0x1ac +#define QPHY_PCIE_V10_60_PCS_G4_FOM_EQ_CONFIG5 0x1c0 +#define QPHY_PCIE_V10_60_PCS_POWER_STATE_CONFIG6 0x1d0 + +#endif diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v10_60.h b/drivers/phy/q= ualcomm/phy-qcom-qmp-pcs-v10_60.h new file mode 100644 index 000000000000..e4558b69489d --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v10_60.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef QCOM_PHY_QMP_PCS_V10_60_H_ +#define QCOM_PHY_QMP_PCS_V10_60_H_ + +/* Only for QMP V10_60 PHY - PCIe PCS registers */ +#define QPHY_V10_60_PCS_SW_RESET 0x000 +#define QPHY_V10_60_PCS_PCS_STATUS1 0x014 +#define QPHY_V10_60_PCS_POWER_DOWN_CONTROL 0x040 +#define QPHY_V10_60_PCS_START_CONTROL 0x044 +#define QPHY_V10_60_PCS_G12S1_TXDEEMPH_M6DB 0x170 +#define QPHY_V10_60_PCS_G3S2_PRE_GAIN 0x178 +#define QPHY_V10_60_PCS_RX_SIGDET_LVL 0x190 +#define QPHY_V10_60_PCS_ELECIDLE_DLY_SEL 0x1b8 +#define QPHY_V10_60_PCS_PCS_TX_RX_CONFIG1 0x1dc +#define QPHY_V10_60_PCS_PCS_TX_RX_CONFIG2 0x1e0 +#define QPHY_V10_60_PCS_EQ_CONFIG4 0x1f8 +#define QPHY_V10_60_PCS_EQ_CONFIG5 0x1fc + +#endif diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v10_60.h b/drive= rs/phy/qualcomm/phy-qcom-qmp-qserdes-com-v10_60.h new file mode 100644 index 000000000000..39351bef8b63 --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v10_60.h @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef QCOM_PHY_QMP_QSERDES_COM_V10_60_H_ +#define QCOM_PHY_QMP_QSERDES_COM_V10_60_H_ + +/* Only for QMP V10_60 PHY - QSERDES COM registers */ +#define QSERDES_V10_60_COM_SSC_STEP_SIZE1_MODE1 0x00 +#define QSERDES_V10_60_COM_SSC_STEP_SIZE2_MODE1 0x04 +#define QSERDES_V10_60_COM_CP_CTRL_MODE1 0x10 +#define QSERDES_V10_60_COM_PLL_RCTRL_MODE1 0x14 +#define QSERDES_V10_60_COM_PLL_CCTRL_MODE1 0x18 +#define QSERDES_V10_60_COM_CORECLK_DIV_MODE1 0x1c +#define QSERDES_V10_60_COM_LOCK_CMP1_MODE1 0x20 +#define QSERDES_V10_60_COM_LOCK_CMP2_MODE1 0x24 +#define QSERDES_V10_60_COM_DEC_START_MODE1 0x28 +#define QSERDES_V10_60_COM_DIV_FRAC_START1_MODE1 0x30 +#define QSERDES_V10_60_COM_DIV_FRAC_START2_MODE1 0x34 +#define QSERDES_V10_60_COM_DIV_FRAC_START3_MODE1 0x38 +#define QSERDES_V10_60_COM_HSCLK_SEL_1 0x3c +#define QSERDES_V10_60_COM_SSC_STEP_SIZE1_MODE0 0x60 +#define QSERDES_V10_60_COM_SSC_STEP_SIZE2_MODE0 0x64 +#define QSERDES_V10_60_COM_CP_CTRL_MODE0 0x70 +#define QSERDES_V10_60_COM_PLL_RCTRL_MODE0 0x74 +#define QSERDES_V10_60_COM_PLL_CCTRL_MODE0 0x78 +#define QSERDES_V10_60_COM_CORECLK_DIV_MODE0 0x7c +#define QSERDES_V10_60_COM_LOCK_CMP1_MODE0 0x80 +#define QSERDES_V10_60_COM_LOCK_CMP2_MODE0 0x84 +#define QSERDES_V10_60_COM_DEC_START_MODE0 0x88 +#define QSERDES_V10_60_COM_DIV_FRAC_START1_MODE0 0x90 +#define QSERDES_V10_60_COM_DIV_FRAC_START2_MODE0 0x94 +#define QSERDES_V10_60_COM_DIV_FRAC_START3_MODE0 0x98 +#define QSERDES_V10_60_COM_HSCLK_HS_SWITCH_SEL_1 0x9c +#define QSERDES_V10_60_COM_BG_TIMER 0xbc +#define QSERDES_V10_60_COM_SSC_PER1 0xcc +#define QSERDES_V10_60_COM_SSC_PER2 0xd0 +#define QSERDES_V10_60_COM_BIAS_EN_CLKBUFLR_EN 0xdc +#define QSERDES_V10_60_COM_CLK_ENABLE1 0xe0 +#define QSERDES_V10_60_COM_SYS_CLK_CTRL 0xe4 +#define QSERDES_V10_60_COM_PLL_IVCO 0xf4 +#define QSERDES_V10_60_COM_SYSCLK_EN_SEL 0x110 +#define QSERDES_V10_60_COM_LOCK_CMP_EN 0x120 +#define QSERDES_V10_60_COM_LOCK_CMP_CFG 0x124 +#define QSERDES_V10_60_COM_VCO_TUNE_MAP 0x140 +#define QSERDES_V10_60_COM_CLK_SELECT 0x164 +#define QSERDES_V10_60_COM_CORE_CLK_EN 0x170 +#define QSERDES_V10_60_COM_CMN_CONFIG_1 0x174 +#define QSERDES_V10_60_COM_CMN_MISC1 0x184 +#define QSERDES_V10_60_COM_CMN_MODE 0x188 +#define QSERDES_V10_60_COM_VCO_DC_LEVEL_CTRL 0x198 +#define QSERDES_V10_60_COM_PLL_SPARE_FOR_ECO 0x2b4 + +#endif diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v10_60.h b/driv= ers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v10_60.h new file mode 100644 index 000000000000..3150a494685e --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v10_60.h @@ -0,0 +1,109 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef QCOM_PHY_QMP_QSERDES_TXRX_V10_60_H_ +#define QCOM_PHY_QMP_QSERDES_TXRX_V10_60_H_ + +#define QSERDES_V10_60_TXRX_RES_CODE_LANE_OFFSET_TX 0x034 +#define QSERDES_V10_60_TXRX_RES_CODE_LANE_OFFSET_RX 0x038 +#define QSERDES_V10_60_TXRX_LANE_MODE_1 0x080 +#define QSERDES_V10_60_TXRX_LANE_MODE_2 0x084 +#define QSERDES_V10_60_TXRX_LANE_MODE_3 0x088 +#define QSERDES_V10_60_TXRX_UCDR_FASTLOCK_FO_GAIN_RATE1 0x0c8 +#define QSERDES_V10_60_TXRX_UCDR_FASTLOCK_FO_GAIN_RATE2 0x0cc +#define QSERDES_V10_60_TXRX_UCDR_FASTLOCK_FO_GAIN_RATE3 0x0d0 +#define QSERDES_V10_60_TXRX_UCDR_FASTLOCK_FO_GAIN_RATE4 0x0d4 +#define QSERDES_V10_60_TXRX_UCDR_FASTLOCK_SO_GAIN_RATE1 0x0e0 +#define QSERDES_V10_60_TXRX_UCDR_FASTLOCK_SO_GAIN_RATE2 0x0e4 +#define QSERDES_V10_60_TXRX_UCDR_FASTLOCK_SO_GAIN_RATE3 0x0e8 +#define QSERDES_V10_60_TXRX_UCDR_FASTLOCK_SO_GAIN_RATE4 0x0ec +#define QSERDES_V10_60_TXRX_UCDR_PI_CTRL1 0x12c +#define QSERDES_V10_60_TXRX_UCDR_PI_CTRL2 0x130 +#define QSERDES_V10_60_TXRX_UCDR_PI_CTRL3 0x134 +#define QSERDES_V10_60_TXRX_UCDR_PI_CTRL4 0x138 +#define QSERDES_V10_60_TXRX_SVS_MODE_CTRL 0x19c +#define QSERDES_V10_60_TXRX_RXCLK_DIV2_CTRL 0x1a0 +#define QSERDES_V10_60_TXRX_RX_BAND_CTRL0 0x1a4 +#define QSERDES_V10_60_TXRX_RX_TERM_BW_CTRL0 0x1ac +#define QSERDES_V10_60_TXRX_RX_TERM_BW_CTRL1 0x1b0 +#define QSERDES_V10_60_TXRX_UCDR_FO_GAIN_RATE1 0x1b8 +#define QSERDES_V10_60_TXRX_UCDR_FO_GAIN_RATE2 0x1bc +#define QSERDES_V10_60_TXRX_UCDR_FO_GAIN_RATE3 0x1c0 +#define QSERDES_V10_60_TXRX_UCDR_FO_GAIN_RATE4 0x1c4 +#define QSERDES_V10_60_TXRX_UCDR_SO_GAIN_RATE1 0x1d0 +#define QSERDES_V10_60_TXRX_UCDR_SO_GAIN_RATE2 0x1d4 +#define QSERDES_V10_60_TXRX_UCDR_SO_GAIN_RATE3 0x1d8 +#define QSERDES_V10_60_TXRX_UCDR_SO_GAIN_RATE4 0x1dc +#define QSERDES_V10_60_TXRX_UCDR_PI_CONTROLS 0x1e4 +#define QSERDES_V10_60_TXRX_AUXDATA_BIN_RATE3 0x200 +#define QSERDES_V10_60_TXRX_AUXDATA_BIN_RATE4 0x204 +#define QSERDES_V10_60_TXRX_EOM_MAX_ERR_LIMIT_LSB 0x218 +#define QSERDES_V10_60_TXRX_EOM_MAX_ERR_LIMIT_MSB 0x21c +#define QSERDES_V10_60_TXRX_VGA_CAL_CNTRL1 0x280 +#define QSERDES_V10_60_TXRX_VGA_CAL_MAN_VAL 0x288 +#define QSERDES_V10_60_TXRX_GM_CAL 0x29c +#define QSERDES_V10_60_TXRX_RX_EQU_ADAPTOR_CNTRL6 0x2b8 +#define QSERDES_V10_60_TXRX_SIGDET_ENABLES 0x2d4 +#define QSERDES_V10_60_TXRX_SIGDET_CNTRL 0x2d8 +#define QSERDES_V10_60_TXRX_SIGDET_LVL 0x2dc +#define QSERDES_V10_60_TXRX_SIGDET_DEGLITCH_CNTRL 0x2e0 +#define QSERDES_V10_60_TXRX_RX_MODE_RATE_0_1_B0 0x314 +#define QSERDES_V10_60_TXRX_RX_MODE_RATE_0_1_B1 0x318 +#define QSERDES_V10_60_TXRX_RX_MODE_RATE_0_1_B2 0x31c +#define QSERDES_V10_60_TXRX_RX_MODE_RATE_0_1_B3 0x320 +#define QSERDES_V10_60_TXRX_RX_MODE_RATE_0_1_B4 0x324 +#define QSERDES_V10_60_TXRX_RX_MODE_RATE_0_1_B5 0x328 +#define QSERDES_V10_60_TXRX_RX_MODE_RATE_0_1_B6 0x32c +#define QSERDES_V10_60_TXRX_RX_MODE_RATE_0_1_B7 0x330 +#define QSERDES_V10_60_TXRX_RX_MODE_RATE_0_1_B8 0x334 +#define QSERDES_V10_60_TXRX_RX_MODE_RATE_0_1_B9 0x338 +#define QSERDES_V10_60_TXRX_RX_MODE_RATE_0_1_B10 0x33c +#define QSERDES_V10_60_TXRX_RX_MODE_RATE2_B0 0x340 +#define QSERDES_V10_60_TXRX_RX_MODE_RATE2_B1 0x344 +#define QSERDES_V10_60_TXRX_RX_MODE_RATE2_B2 0x348 +#define QSERDES_V10_60_TXRX_RX_MODE_RATE2_B3 0x34c +#define QSERDES_V10_60_TXRX_RX_MODE_RATE2_B4 0x350 +#define QSERDES_V10_60_TXRX_RX_MODE_RATE2_B5 0x354 +#define QSERDES_V10_60_TXRX_RX_MODE_RATE2_B6 0x358 +#define QSERDES_V10_60_TXRX_RX_MODE_RATE2_B7 0x35c +#define QSERDES_V10_60_TXRX_RX_MODE_RATE2_B8 0x360 +#define QSERDES_V10_60_TXRX_RX_MODE_RATE2_B9 0x364 +#define QSERDES_V10_60_TXRX_RX_MODE_RATE2_B10 0x368 +#define QSERDES_V10_60_TXRX_RX_MODE_RATE3_B0 0x36c +#define QSERDES_V10_60_TXRX_RX_MODE_RATE3_B1 0x370 +#define QSERDES_V10_60_TXRX_RX_MODE_RATE3_B2 0x374 +#define QSERDES_V10_60_TXRX_RX_MODE_RATE3_B3 0x378 +#define QSERDES_V10_60_TXRX_RX_MODE_RATE3_B4 0x37c +#define QSERDES_V10_60_TXRX_RX_MODE_RATE3_B5 0x380 +#define QSERDES_V10_60_TXRX_RX_MODE_RATE3_B6 0x384 +#define QSERDES_V10_60_TXRX_RX_MODE_RATE3_B7 0x388 +#define QSERDES_V10_60_TXRX_RX_MODE_RATE3_B8 0x38c +#define QSERDES_V10_60_TXRX_RX_MODE_RATE3_B9 0x390 +#define QSERDES_V10_60_TXRX_RX_MODE_RATE3_B10 0x394 +#define QSERDES_V10_60_TXRX_RX_MODE_RATE4_SA_B0 0x398 +#define QSERDES_V10_60_TXRX_RX_MODE_RATE4_SA_B1 0x39c +#define QSERDES_V10_60_TXRX_RX_MODE_RATE4_SA_B2 0x3a0 +#define QSERDES_V10_60_TXRX_RX_MODE_RATE4_SA_B3 0x3a4 +#define QSERDES_V10_60_TXRX_RX_MODE_RATE4_SA_B4 0x3a8 +#define QSERDES_V10_60_TXRX_RX_MODE_RATE4_SA_B5 0x3ac +#define QSERDES_V10_60_TXRX_RX_MODE_RATE4_SA_B6 0x3b0 +#define QSERDES_V10_60_TXRX_RX_MODE_RATE4_SA_B7 0x3b4 +#define QSERDES_V10_60_TXRX_RX_MODE_RATE4_SA_B8 0x3b8 +#define QSERDES_V10_60_TXRX_RX_MODE_RATE4_SA_B9 0x3bc +#define QSERDES_V10_60_TXRX_RX_MODE_RATE4_SA_B10 0x3c0 +#define QSERDES_V10_60_TXRX_Q_PI_INTRINSIC_BIAS_RATE32 0x478 +#define QSERDES_V10_60_TXRX_Q_PI_INTRINSIC_BIAS_RATE45 0x47c +#define QSERDES_V10_60_TXRX_SIGDET_CAL_CTRL1 0x4c8 +#define QSERDES_V10_60_TXRX_SIGDET_CAL_CTRL2 0x4cc +#define QSERDES_V10_60_TXRX_SIGDET_CAL_TRIM 0x4d0 +#define QSERDES_V10_60_TXRX_TX_BAND0 0x4e8 +#define QSERDES_V10_60_TXRX_TX_BAND1 0x4ec +#define QSERDES_V10_60_TXRX_SEL_10B_8B 0x4f4 +#define QSERDES_V10_60_TXRX_SEL_20B_10B 0x4f8 +#define QSERDES_V10_60_TXRX_EQ_RCF_CTRL_RATE3 0x53c +#define QSERDES_V10_60_TXRX_EQ_RCF_CTRL_RATE4 0x540 +#define QSERDES_V10_60_TXRX_PHPRE_CTRL 0x5e8 + +#endif diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy= -qcom-qmp.h index 7af77572970e..3a4a0a9a9e4d 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp.h @@ -42,6 +42,9 @@ #include "phy-qcom-qmp-qserdes-com-v10.h" #include "phy-qcom-qmp-qserdes-txrx-v10.h" =20 +#include "phy-qcom-qmp-qserdes-com-v10_60.h" +#include "phy-qcom-qmp-qserdes-txrx-v10_60.h" + #include "phy-qcom-qmp-qserdes-pll.h" =20 #include "phy-qcom-qmp-pcs-v2.h" @@ -70,6 +73,8 @@ =20 #include "phy-qcom-qmp-pcs-v10.h" =20 +#include "phy-qcom-qmp-pcs-v10_60.h" + /* QPHY_SW_RESET bit */ #define SW_RESET BIT(0) /* QPHY_POWER_DOWN_CONTROL */ --=20 2.34.1 From nobody Fri Jun 19 19:55:23 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-30c0670a1b4sm619430eec.8.2026.06.18.14.54.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 Jun 2026 14:54:59 -0700 (PDT) From: Matthew Leung Date: Thu, 18 Jun 2026 21:54:39 +0000 Subject: [PATCH v3 4/4] phy: qcom: qmp-pcie: Add QMP PCIe PHY support for Hawi Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260618-hawi-phy-pcie-v3-4-3fa42ca45ea4@oss.qualcomm.com> References: <20260618-hawi-phy-pcie-v3-0-3fa42ca45ea4@oss.qualcomm.com> In-Reply-To: <20260618-hawi-phy-pcie-v3-0-3fa42ca45ea4@oss.qualcomm.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Matthew Leung X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1781819694; l=21800; i=matthew.leung@oss.qualcomm.com; s=20260428; h=from:subject:message-id; bh=aBXWJ0r4or2tqJncgmtJelcxw20MKlf/BGJn+EVJx5I=; b=lFOo+RBu9IlZqUXiAdPYbIimZFg8p05py9+j7JQOkhVP8q/BjhfRD5a50YYrkPT1xm5f9N3nb EAlDo8I4/H+CGCx5Y81GWTLOnCRTXx2nAPX3LegvgxkYx7cNCaeHZ9z X-Developer-Key: i=matthew.leung@oss.qualcomm.com; a=ed25519; pk=aT25ggJo5PMHLN9N+TsZ3s/BVU++kEYuiFebPWe21+o= X-Proofpoint-GUID: v9YS20hsCX-I0o2FY5V_8wGMOGtorxOZ X-Proofpoint-ORIG-GUID: v9YS20hsCX-I0o2FY5V_8wGMOGtorxOZ X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjE4MDIwMCBTYWx0ZWRfXxfT3pr884YkO kXm+FcF8kdZpQPylfhN/f/X9v2VGUUWvd+7dbyspNr1eO3f4oFh2tmFTRKbLis2mOUEDEG9fJIi rAb4e52W5RR8PYJGEEoNRgLF9UzLIcgTRps4pSTAGV74DTzVHcGaszB3dYL3OtchCBKbg19+Fmd I7EEAxB2dmOgUo7RKbhFKu59UVQlK032i8yuCWbHKn8rSjvH9DN64xCDBVilEnWqn3o8pUBk0CC Tzdyl9sYhjeuaPXRhzC35mVqBOH6sgDExNyHSP8RQIUdAPRsVoxjDaMQhzk9a8ooLz7nvJI91Mk pXhUIEy2jGKT1I0rY02a96pCYpMqkGB5MnUI6e7b5+0FGGMGHrnyOlknq4KjIG041I6fLF0Z6tz xP1ELLaPltn4/8WCpysDzFAnM0mwkfouKMTeSI0CrW8zWa8rcYBwAaBMEXRr5L7fiyYYNjqlesI b3kRpd3K+S7xsruroNg== X-Authority-Analysis: v=2.4 cv=H6LrBeYi c=1 sm=1 tr=0 ts=6a346935 cx=c_pps a=cFYjgdjTJScbgFmBucgdfQ==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=EUspDBNiAAAA:8 a=0NEZ95bNQYYi-I2mXMoA:9 a=QEXdDO2ut3YA:10 a=scEy_gLbYbu1JhEsrz4S:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwNjE4MDIwMCBTYWx0ZWRfXzoF8FjCMphDR XVnj2dc5X/yFp0kv67Q3KYQn/rx+pdtwOqQMHN2/89bxqVUlq8DT87Ju5c4Vje0dXztmD8YBSr8 vgZGB+4KQXjaBTRfAtuHAzjQtFyeUE0= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-18_04,2026-06-18_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 priorityscore=1501 phishscore=0 lowpriorityscore=0 impostorscore=0 spamscore=0 suspectscore=0 malwarescore=0 clxscore=1015 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2606180200 Add the QMP PCIe PHY support for the Gen3 x2 and Gen4 x1 PHY found on the Hawi platform. Signed-off-by: Matthew Leung --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 373 +++++++++++++++++++++++++++= ++++ 1 file changed, 373 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcom= m/phy-qcom-qmp-pcie.c index fb66e2a97ce0..ca3a5d974422 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -118,6 +118,20 @@ static const unsigned int pciephy_v8_50_regs_layout[QP= HY_LAYOUT_SIZE] =3D { [QPHY_PCS_POWER_DOWN_CONTROL] =3D QPHY_V8_50_PCS_POWER_DOWN_CONTROL, }; =20 +static const unsigned int pciephy_v10_regs_layout[QPHY_LAYOUT_SIZE] =3D { + [QPHY_SW_RESET] =3D QPHY_V10_PCS_SW_RESET, + [QPHY_START_CTRL] =3D QPHY_V10_PCS_START_CONTROL, + [QPHY_PCS_STATUS] =3D QPHY_V10_PCS_PCS_STATUS1, + [QPHY_PCS_POWER_DOWN_CONTROL] =3D QPHY_V10_PCS_POWER_DOWN_CONTROL, +}; + +static const unsigned int pciephy_v10_60_regs_layout[QPHY_LAYOUT_SIZE] =3D= { + [QPHY_SW_RESET] =3D QPHY_V10_60_PCS_SW_RESET, + [QPHY_START_CTRL] =3D QPHY_V10_60_PCS_START_CONTROL, + [QPHY_PCS_STATUS] =3D QPHY_V10_60_PCS_PCS_STATUS1, + [QPHY_PCS_POWER_DOWN_CONTROL] =3D QPHY_V10_60_PCS_POWER_DOWN_CONTROL, +}; + static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] =3D { QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14), QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), @@ -3222,6 +3236,287 @@ static const struct qmp_phy_init_tbl kaanapali_qmp_= gen3x2_pcie_pcs_misc_tbl[] =3D QMP_PHY_INIT_CFG(QPHY_PCIE_V8_PCS_POWER_STATE_CONFIG6, 0x1f), }; =20 +static const struct qmp_phy_init_tbl hawi_qmp_gen3x2_pcie_serdes_tbl[] =3D= { + QMP_PHY_INIT_CFG(QSERDES_V10_COM_SSC_EN_CENTER, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V10_COM_SSC_PER1, 0x62), + QMP_PHY_INIT_CFG(QSERDES_V10_COM_SSC_PER2, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V10_COM_SSC_STEP_SIZE1_MODE0, 0xf8), + QMP_PHY_INIT_CFG(QSERDES_V10_COM_SSC_STEP_SIZE2_MODE0, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V10_COM_SSC_STEP_SIZE1_MODE1, 0x93), + QMP_PHY_INIT_CFG(QSERDES_V10_COM_SSC_STEP_SIZE2_MODE1, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V10_COM_CLK_ENABLE1, 0x90), + QMP_PHY_INIT_CFG(QSERDES_V10_COM_SYS_CLK_CTRL, 0x82), + QMP_PHY_INIT_CFG(QSERDES_V10_COM_PLL_IVCO, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V10_COM_CP_CTRL_MODE0, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V10_COM_CP_CTRL_MODE1, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V10_COM_PLL_RCTRL_MODE0, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V10_COM_PLL_RCTRL_MODE1, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V10_COM_PLL_CCTRL_MODE0, 0x36), + QMP_PHY_INIT_CFG(QSERDES_V10_COM_PLL_CCTRL_MODE1, 0x36), + QMP_PHY_INIT_CFG(QSERDES_V10_COM_SYSCLK_EN_SEL, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V10_COM_BG_TIMER, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V10_COM_LOCK_CMP_EN, 0x42), + QMP_PHY_INIT_CFG(QSERDES_V10_COM_LOCK_CMP1_MODE0, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V10_COM_LOCK_CMP2_MODE0, 0x0d), + QMP_PHY_INIT_CFG(QSERDES_V10_COM_LOCK_CMP1_MODE1, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V10_COM_LOCK_CMP2_MODE1, 0x1a), + QMP_PHY_INIT_CFG(QSERDES_V10_COM_DEC_START_MODE0, 0x41), + QMP_PHY_INIT_CFG(QSERDES_V10_COM_DEC_START_MODE1, 0x34), + QMP_PHY_INIT_CFG(QSERDES_V10_COM_DIV_FRAC_START1_MODE0, 0xab), + QMP_PHY_INIT_CFG(QSERDES_V10_COM_DIV_FRAC_START2_MODE0, 0xaa), + QMP_PHY_INIT_CFG(QSERDES_V10_COM_DIV_FRAC_START3_MODE0, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V10_COM_DIV_FRAC_START1_MODE1, 0x55), + QMP_PHY_INIT_CFG(QSERDES_V10_COM_DIV_FRAC_START2_MODE1, 0x55), + QMP_PHY_INIT_CFG(QSERDES_V10_COM_DIV_FRAC_START3_MODE1, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V10_COM_VCO_TUNE_MAP, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V10_COM_CLK_SELECT, 0x34), + QMP_PHY_INIT_CFG(QSERDES_V10_COM_HSCLK_SEL_1, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V10_COM_CORECLK_DIV_MODE1, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V10_COM_CMN_CONFIG_1, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V10_COM_ADDITIONAL_MISC_3, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V10_COM_CORE_CLK_EN, 0xa0), +}; + +static const struct qmp_phy_init_tbl hawi_qmp_gen3x2_pcie_rx_tbl[] =3D { + QMP_PHY_INIT_CFG(QSERDES_V10_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), + QMP_PHY_INIT_CFG(QSERDES_V10_RX_GM_CAL, 0x11), + QMP_PHY_INIT_CFG(QSERDES_V10_RX_RX_MODE_00_HIGH, 0xbf), + QMP_PHY_INIT_CFG(QSERDES_V10_RX_RX_MODE_00_HIGH2, 0xbf), + QMP_PHY_INIT_CFG(QSERDES_V10_RX_RX_MODE_00_HIGH3, 0xb7), + QMP_PHY_INIT_CFG(QSERDES_V10_RX_RX_MODE_00_HIGH4, 0xec), + QMP_PHY_INIT_CFG(QSERDES_V10_RX_RX_MODE_00_LOW, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V10_RX_RX_MODE_01_HIGH, 0x09), + QMP_PHY_INIT_CFG(QSERDES_V10_RX_RX_MODE_01_HIGH2, 0x49), + QMP_PHY_INIT_CFG(QSERDES_V10_RX_RX_MODE_01_HIGH3, 0x1b), + QMP_PHY_INIT_CFG(QSERDES_V10_RX_RX_MODE_01_HIGH4, 0x9c), + QMP_PHY_INIT_CFG(QSERDES_V10_RX_RX_MODE_01_LOW, 0xd1), + QMP_PHY_INIT_CFG(QSERDES_V10_RX_RX_MODE_10_HIGH, 0x09), + QMP_PHY_INIT_CFG(QSERDES_V10_RX_RX_MODE_10_HIGH2, 0x49), + QMP_PHY_INIT_CFG(QSERDES_V10_RX_RX_MODE_10_HIGH3, 0x1b), + QMP_PHY_INIT_CFG(QSERDES_V10_RX_RX_MODE_10_HIGH4, 0x9c), + QMP_PHY_INIT_CFG(QSERDES_V10_RX_RX_MODE_10_LOW, 0xd1), + QMP_PHY_INIT_CFG(QSERDES_V10_RX_TX_ADAPT_PRE_THRESH1, 0x3e), + QMP_PHY_INIT_CFG(QSERDES_V10_RX_TX_ADAPT_PRE_THRESH2, 0x1e), + QMP_PHY_INIT_CFG(QSERDES_V10_RX_TX_ADAPT_POST_THRESH, 0xd2), + QMP_PHY_INIT_CFG(QSERDES_V10_RX_UCDR_FO_GAIN, 0x09), + QMP_PHY_INIT_CFG(QSERDES_V10_RX_UCDR_SO_GAIN, 0x05), + QMP_PHY_INIT_CFG(QSERDES_V10_RX_UCDR_SB2_THRESH1, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V10_RX_UCDR_SB2_THRESH2, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V10_RX_VGA_CAL_CNTRL2, 0x09), + QMP_PHY_INIT_CFG(QSERDES_V10_RX_SIGDET_ENABLES, 0x1c), + QMP_PHY_INIT_CFG(QSERDES_V10_RX_SIGDET_CNTRL, 0x60), + QMP_PHY_INIT_CFG(QSERDES_V10_RX_RX_IDAC_TSETTLE_LOW, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V10_RX_SIGDET_CAL_TRIM, 0x08), +}; + +static const struct qmp_phy_init_tbl hawi_qmp_gen3x2_pcie_tx_tbl[] =3D { + QMP_PHY_INIT_CFG(QSERDES_V10_TX_LANE_MODE_1, 0x25), + QMP_PHY_INIT_CFG(QSERDES_V10_TX_LANE_MODE_3, 0x10), + QMP_PHY_INIT_CFG(QSERDES_V10_TX_LANE_MODE_4, 0x31), + QMP_PHY_INIT_CFG(QSERDES_V10_TX_LANE_MODE_5, 0x7d), + QMP_PHY_INIT_CFG(QSERDES_V10_TX_PI_QEC_CTRL, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V10_TX_RES_CODE_LANE_OFFSET_RX, 0x09), + QMP_PHY_INIT_CFG(QSERDES_V10_TX_RES_CODE_LANE_OFFSET_TX, 0x14), +}; + +static const struct qmp_phy_init_tbl hawi_qmp_gen3x2_pcie_pcs_tbl[] =3D { + QMP_PHY_INIT_CFG(QPHY_V10_PCS_REFGEN_REQ_CONFIG1, 0x05), + QMP_PHY_INIT_CFG(QPHY_V10_PCS_RX_SIGDET_LVL, 0x77), + QMP_PHY_INIT_CFG(QPHY_V10_PCS_RATE_SLEW_CNTRL1, 0x0b), + QMP_PHY_INIT_CFG(QPHY_V10_PCS_EQ_CONFIG2, 0x0f), + QMP_PHY_INIT_CFG(QPHY_V10_PCS_PCS_TX_RX_CONFIG, 0x8c), + QMP_PHY_INIT_CFG(QPHY_V10_PCS_G12S1_TXDEEMPH_M6DB, 0x17), + QMP_PHY_INIT_CFG(QPHY_V10_PCS_G3S2_PRE_GAIN, 0x2e), +}; + +static const struct qmp_phy_init_tbl hawi_qmp_gen3x2_pcie_pcs_misc_tbl[] = =3D { + QMP_PHY_INIT_CFG(QPHY_PCIE_V10_PCS_EQ_CONFIG1, 0x1e), + QMP_PHY_INIT_CFG(QPHY_PCIE_V10_PCS_RXEQEVAL_TIME, 0x27), + QMP_PHY_INIT_CFG(QPHY_PCIE_V10_PCS_POWER_STATE_CONFIG2, 0x1d), + QMP_PHY_INIT_CFG(QPHY_PCIE_V10_PCS_POWER_STATE_CONFIG4, 0x07), + QMP_PHY_INIT_CFG(QPHY_PCIE_V10_PCS_POWER_STATE_CONFIG6, 0x1f), + QMP_PHY_INIT_CFG(QPHY_PCIE_V10_PCS_ENDPOINT_REFCLK_DRIVE, 0xc1), + QMP_PHY_INIT_CFG(QPHY_PCIE_V10_PCS_OSC_DTCT_ACTIONS, 0x00), +}; + +static const struct qmp_phy_init_tbl hawi_qmp_gen4x1_pcie_serdes_tbl[] =3D= { + QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_SSC_STEP_SIZE1_MODE1, 0x93), + QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_SSC_STEP_SIZE2_MODE1, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_CP_CTRL_MODE1, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_PLL_RCTRL_MODE1, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_PLL_CCTRL_MODE1, 0x36), + QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_CORECLK_DIV_MODE1, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_LOCK_CMP1_MODE1, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_LOCK_CMP2_MODE1, 0x1a), + QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_DEC_START_MODE1, 0x34), + QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_DIV_FRAC_START1_MODE1, 0x55), + QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_DIV_FRAC_START2_MODE1, 0x55), + QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_DIV_FRAC_START3_MODE1, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_HSCLK_SEL_1, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_SSC_STEP_SIZE1_MODE0, 0xf8), + QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_SSC_STEP_SIZE2_MODE0, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_CP_CTRL_MODE0, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_PLL_RCTRL_MODE0, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_PLL_CCTRL_MODE0, 0x36), + QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_CORECLK_DIV_MODE0, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_LOCK_CMP1_MODE0, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_LOCK_CMP2_MODE0, 0x0d), + QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_DEC_START_MODE0, 0x41), + QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_DIV_FRAC_START1_MODE0, 0xab), + QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_DIV_FRAC_START2_MODE0, 0xaa), + QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_DIV_FRAC_START3_MODE0, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_HSCLK_HS_SWITCH_SEL_1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_BG_TIMER, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_SSC_PER1, 0x62), + QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_SSC_PER2, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_BIAS_EN_CLKBUFLR_EN, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_CLK_ENABLE1, 0x90), + QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_SYS_CLK_CTRL, 0x82), + QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_PLL_IVCO, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_SYSCLK_EN_SEL, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_LOCK_CMP_EN, 0x46), + QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_LOCK_CMP_CFG, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_VCO_TUNE_MAP, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_CLK_SELECT, 0x34), + QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_CORE_CLK_EN, 0xa0), + QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_CMN_CONFIG_1, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_CMN_MISC1, 0x88), + QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_CMN_MODE, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_VCO_DC_LEVEL_CTRL, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V10_60_COM_PLL_SPARE_FOR_ECO, 0x02), +}; + +static const struct qmp_phy_init_tbl hawi_qmp_gen4x1_pcie_tx_tbl[] =3D { + QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RES_CODE_LANE_OFFSET_TX, 0x1a), + QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RES_CODE_LANE_OFFSET_RX, 0x12), + QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_SIGDET_CAL_CTRL1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_SIGDET_CAL_CTRL2, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_SIGDET_CAL_TRIM, 0x66), + QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_TX_BAND0, 0x05), + QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_TX_BAND1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_SEL_10B_8B, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_SEL_20B_10B, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_EQ_RCF_CTRL_RATE3, 0x22), + QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_EQ_RCF_CTRL_RATE4, 0x22), + QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_PHPRE_CTRL, 0x20), + QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_UCDR_FASTLOCK_FO_GAIN_RATE1, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_UCDR_FASTLOCK_FO_GAIN_RATE2, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_UCDR_FASTLOCK_FO_GAIN_RATE3, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_UCDR_FASTLOCK_FO_GAIN_RATE4, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_UCDR_FASTLOCK_SO_GAIN_RATE1, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_UCDR_FASTLOCK_SO_GAIN_RATE2, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_UCDR_FASTLOCK_SO_GAIN_RATE3, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_UCDR_FASTLOCK_SO_GAIN_RATE4, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_UCDR_PI_CTRL1, 0x40), + QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_UCDR_PI_CTRL2, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_UCDR_PI_CTRL3, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_UCDR_PI_CTRL4, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_SVS_MODE_CTRL, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RXCLK_DIV2_CTRL, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_BAND_CTRL0, 0x05), + QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_TERM_BW_CTRL0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_TERM_BW_CTRL1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_UCDR_FO_GAIN_RATE1, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_UCDR_FO_GAIN_RATE2, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_UCDR_FO_GAIN_RATE3, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_UCDR_FO_GAIN_RATE4, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_UCDR_SO_GAIN_RATE1, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_UCDR_SO_GAIN_RATE2, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_UCDR_SO_GAIN_RATE3, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_UCDR_SO_GAIN_RATE4, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_UCDR_PI_CONTROLS, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_AUXDATA_BIN_RATE3, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_AUXDATA_BIN_RATE4, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_EOM_MAX_ERR_LIMIT_LSB, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_EOM_MAX_ERR_LIMIT_MSB, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_VGA_CAL_CNTRL1, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_VGA_CAL_MAN_VAL, 0x8e), + QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_GM_CAL, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_EQU_ADAPTOR_CNTRL6, 0xca), + QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_SIGDET_ENABLES, 0x1c), + QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_SIGDET_CNTRL, 0x6f), + QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_SIGDET_LVL, 0x84), + QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_SIGDET_DEGLITCH_CNTRL, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_Q_PI_INTRINSIC_BIAS_RATE32, 0x11), + QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_Q_PI_INTRINSIC_BIAS_RATE45, 0x10), + QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE_0_1_B0, 0xc2), + QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE_0_1_B1, 0xc2), + QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE_0_1_B2, 0xd8), + QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE_0_1_B3, 0x05), + QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE_0_1_B4, 0x98), + QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE_0_1_B5, 0x36), + QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE_0_1_B6, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE_0_1_B7, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE_0_1_B8, 0xc0), + QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE_0_1_B9, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE_0_1_B10, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE2_B0, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE2_B1, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE2_B2, 0xd8), + QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE2_B3, 0x1a), + QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE2_B4, 0x98), + QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE2_B5, 0x36), + QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE2_B6, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE2_B7, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE2_B8, 0xc0), + QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE2_B9, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE2_B10, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE3_B0, 0x13), + QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE3_B1, 0xd3), + QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE3_B2, 0xc0), + QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE3_B3, 0x13), + QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE3_B4, 0x13), + QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE3_B5, 0x36), + QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE3_B6, 0x4c), + QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE3_B7, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE3_B8, 0xc0), + QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE3_B9, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE3_B10, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE4_SA_B0, 0x24), + QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE4_SA_B1, 0x24), + QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE4_SA_B2, 0xc0), + QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE4_SA_B3, 0x0b), + QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE4_SA_B4, 0x1a), + QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE4_SA_B5, 0x24), + QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE4_SA_B6, 0x2c), + QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE4_SA_B7, 0x86), + QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE4_SA_B8, 0x83), + QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE4_SA_B9, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_RX_MODE_RATE4_SA_B10, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_LANE_MODE_1, 0x0c), + QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_LANE_MODE_2, 0xc0), + QMP_PHY_INIT_CFG(QSERDES_V10_60_TXRX_LANE_MODE_3, 0x00), +}; + +static const struct qmp_phy_init_tbl hawi_qmp_gen4x1_pcie_pcs_tbl[] =3D { + QMP_PHY_INIT_CFG(QPHY_V10_60_PCS_G12S1_TXDEEMPH_M6DB, 0x17), + QMP_PHY_INIT_CFG(QPHY_V10_60_PCS_G3S2_PRE_GAIN, 0x2e), + QMP_PHY_INIT_CFG(QPHY_V10_60_PCS_RX_SIGDET_LVL, 0xcc), + QMP_PHY_INIT_CFG(QPHY_V10_60_PCS_ELECIDLE_DLY_SEL, 0x40), + QMP_PHY_INIT_CFG(QPHY_V10_60_PCS_PCS_TX_RX_CONFIG1, 0x04), + QMP_PHY_INIT_CFG(QPHY_V10_60_PCS_PCS_TX_RX_CONFIG2, 0x02), + QMP_PHY_INIT_CFG(QPHY_V10_60_PCS_EQ_CONFIG4, 0x00), + QMP_PHY_INIT_CFG(QPHY_V10_60_PCS_EQ_CONFIG5, 0x22), +}; + +static const struct qmp_phy_init_tbl hawi_qmp_gen4x1_pcie_pcs_misc_tbl[] = =3D { + QMP_PHY_INIT_CFG(QPHY_PCIE_V10_60_PCS_POWER_STATE_CONFIG2, 0x1d), + QMP_PHY_INIT_CFG(QPHY_PCIE_V10_60_PCS_TX_RX_CONFIG, 0xc0), + QMP_PHY_INIT_CFG(QPHY_PCIE_V10_60_PCS_ENDPOINT_REFCLK_DRIVE, 0xc1), + QMP_PHY_INIT_CFG(QPHY_PCIE_V10_60_PCS_OSC_DTCT_ACTIONS, 0x00), + QMP_PHY_INIT_CFG(QPHY_PCIE_V10_60_PCS_EQ_CONFIG1, 0x16), + QMP_PHY_INIT_CFG(QPHY_PCIE_V10_60_PCS_G3_RXEQEVAL_TIME, 0x27), + QMP_PHY_INIT_CFG(QPHY_PCIE_V10_60_PCS_G4_RXEQEVAL_TIME, 0x27), + QMP_PHY_INIT_CFG(QPHY_PCIE_V10_60_PCS_G4_EQ_CONFIG5, 0x02), + QMP_PHY_INIT_CFG(QPHY_PCIE_V10_60_PCS_G4_PRE_GAIN, 0x2e), + QMP_PHY_INIT_CFG(QPHY_PCIE_V10_60_PCS_RX_MARGINING_CONFIG1, 0x03), + QMP_PHY_INIT_CFG(QPHY_PCIE_V10_60_PCS_RX_MARGINING_CONFIG3, 0x28), + QMP_PHY_INIT_CFG(QPHY_PCIE_V10_60_PCS_RX_MARGINING_CONFIG5, 0x0f), + QMP_PHY_INIT_CFG(QPHY_PCIE_V10_60_PCS_G3_FOM_EQ_CONFIG5, 0xf2), + QMP_PHY_INIT_CFG(QPHY_PCIE_V10_60_PCS_G4_FOM_EQ_CONFIG5, 0xf2), + QMP_PHY_INIT_CFG(QPHY_PCIE_V10_60_PCS_POWER_STATE_CONFIG6, 0x1f), +}; + struct qmp_pcie_offsets { u16 serdes; u16 pcs; @@ -3534,6 +3829,24 @@ static const struct qmp_pcie_offsets qmp_pcie_offset= s_v8_50 =3D { .txrxz =3D 0xd000, }; =20 +static const struct qmp_pcie_offsets qmp_pcie_offsets_v10_0 =3D { + .serdes =3D 0x0000, + .pcs =3D 0x0400, + .pcs_misc =3D 0x0800, + .tx =3D 0x1000, + .rx =3D 0x1200, + .tx2 =3D 0x1800, + .rx2 =3D 0x1a00, +}; + +static const struct qmp_pcie_offsets qmp_pcie_offsets_v10_60 =3D { + .tx =3D 0x0000, + /* no .rx; tx and rx share the same register block */ + .serdes =3D 0x1000, + .pcs =3D 0x1400, + .pcs_misc =3D 0x1800, +}; + static const struct qmp_phy_cfg ipq8074_pciephy_cfg =3D { .lanes =3D 1, =20 @@ -4650,6 +4963,60 @@ static const struct qmp_phy_cfg glymur_qmp_gen4x2_pc= iephy_cfg =3D { .phy_status =3D PHYSTATUS_4_20, }; =20 +static const struct qmp_phy_cfg hawi_qmp_gen3x2_pciephy_cfg =3D { + .lanes =3D 2, + + .offsets =3D &qmp_pcie_offsets_v10_0, + + .tbls =3D { + .serdes =3D hawi_qmp_gen3x2_pcie_serdes_tbl, + .serdes_num =3D ARRAY_SIZE(hawi_qmp_gen3x2_pcie_serdes_tbl), + .tx =3D hawi_qmp_gen3x2_pcie_tx_tbl, + .tx_num =3D ARRAY_SIZE(hawi_qmp_gen3x2_pcie_tx_tbl), + .rx =3D hawi_qmp_gen3x2_pcie_rx_tbl, + .rx_num =3D ARRAY_SIZE(hawi_qmp_gen3x2_pcie_rx_tbl), + .pcs =3D hawi_qmp_gen3x2_pcie_pcs_tbl, + .pcs_num =3D ARRAY_SIZE(hawi_qmp_gen3x2_pcie_pcs_tbl), + .pcs_misc =3D hawi_qmp_gen3x2_pcie_pcs_misc_tbl, + .pcs_misc_num =3D ARRAY_SIZE(hawi_qmp_gen3x2_pcie_pcs_misc_tbl), + }, + + .reset_list =3D sdm845_pciephy_reset_l, + .num_resets =3D ARRAY_SIZE(sdm845_pciephy_reset_l), + .vreg_list =3D qmp_phy_vreg_l, + .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), + .regs =3D pciephy_v10_regs_layout, + + .pwrdn_ctrl =3D SW_PWRDN | REFCLK_DRV_DSBL, + .phy_status =3D PHYSTATUS, +}; + +static const struct qmp_phy_cfg hawi_qmp_gen4x1_pciephy_cfg =3D { + .lanes =3D 1, + + .offsets =3D &qmp_pcie_offsets_v10_60, + + .tbls =3D { + .serdes =3D hawi_qmp_gen4x1_pcie_serdes_tbl, + .serdes_num =3D ARRAY_SIZE(hawi_qmp_gen4x1_pcie_serdes_tbl), + .tx =3D hawi_qmp_gen4x1_pcie_tx_tbl, + .tx_num =3D ARRAY_SIZE(hawi_qmp_gen4x1_pcie_tx_tbl), + .pcs =3D hawi_qmp_gen4x1_pcie_pcs_tbl, + .pcs_num =3D ARRAY_SIZE(hawi_qmp_gen4x1_pcie_pcs_tbl), + .pcs_misc =3D hawi_qmp_gen4x1_pcie_pcs_misc_tbl, + .pcs_misc_num =3D ARRAY_SIZE(hawi_qmp_gen4x1_pcie_pcs_misc_tbl), + }, + + .reset_list =3D sdm845_pciephy_reset_l, + .num_resets =3D ARRAY_SIZE(sdm845_pciephy_reset_l), + .vreg_list =3D qmp_phy_vreg_l, + .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), + .regs =3D pciephy_v10_60_regs_layout, + + .pwrdn_ctrl =3D SW_PWRDN | REFCLK_DRV_DSBL, + .phy_status =3D PHYSTATUS_4_20, +}; + static void qmp_pcie_init_port_b(struct qmp_pcie *qmp, const struct qmp_ph= y_cfg_tbls *tbls) { const struct qmp_phy_cfg *cfg =3D qmp->cfg; @@ -5406,6 +5773,12 @@ static const struct of_device_id qmp_pcie_of_match_t= able[] =3D { }, { .compatible =3D "qcom,glymur-qmp-gen5x4-pcie-phy", .data =3D &glymur_qmp_gen5x4_pciephy_cfg, + }, { + .compatible =3D "qcom,hawi-qmp-gen3x2-pcie-phy", + .data =3D &hawi_qmp_gen3x2_pciephy_cfg, + }, { + .compatible =3D "qcom,hawi-qmp-gen4x1-pcie-phy", + .data =3D &hawi_qmp_gen4x1_pciephy_cfg, }, { .compatible =3D "qcom,ipq6018-qmp-pcie-phy", .data =3D &ipq6018_pciephy_cfg, --=20 2.34.1