From nobody Sun Jun 21 16:14:17 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 135CA4968F1; Wed, 17 Jun 2026 16:02:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781712160; cv=none; b=XysREmuC9z9ts1lipt/khdN1AHJdkzAgDU2rzIBe+2Ol/ugDnpDurFtd4SgNOHrPnpd9MToxbV6N2IpRK2LJq7dXk1u0ErVVQyi/0ZA1tKSQDADYWVBvudsZW0+G4Iq3VV8p7lDD7KOURi8Jd+8OZqCrSfGvtirEaH1DKd5b6F4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781712160; c=relaxed/simple; bh=BvE4HnJ0+NKh/FkcqzqWFwDrmCPCpBbtwofV7JtDels=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=dmjrTEfRh1oW3p0TxhpYjeOiBK1Zdjh1wd+4XPUDXQqPPBZoQsrbkDK3cerAHc4zPi35dXotgrGJpQl8stuhTLYClbkQ5mbNQ+fKVrhrRr1cs+H/VyahMjVrHsZ9BQBDkVsFM9cNFZWiICsk9qjTetDdTRfJuk7NuUr5e7AVr48= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=D7DeVLkU; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="D7DeVLkU" Received: by smtp.kernel.org (Postfix) with ESMTPSA id C20B11F000E9; Wed, 17 Jun 2026 16:02:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1781712146; bh=9ketLamsIu4nXHSCXS/VDY41zTZ0D6snL3P9DZeCAnY=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=D7DeVLkU5iCPVSmKs2l3x5HapnsFd9xtakPmyKlmxmRTw/i7xsMSJPYGCa05Rcklr KY8BPFbQKwg3w3hYKkUVJe1VA+vf6kdGAzzxNBXtPdtRWopro861zlqqK6SJpuZ9yZ T7Jdf/JoXWjjA2YADA5ypeIxxgAdJAHIBjNOqafuwNSwfWGlqcaB03wad95eILAQMb wna/FUssZIAHv5GSd7aGvNNQcd2JifO+yekjckx0OXur83N159d4nTd+CbuMuhj/pI 2/5C+2NnIlD7wsThBgyNiWieym3TVloDBJYlga8N0lcXjdyM/TIuj77boALWaZSmjW fhuMWrF3lbPkg== From: Thierry Reding Date: Wed, 17 Jun 2026 18:01:28 +0200 Subject: [PATCH v7 1/4] dt-bindings: pci: Strictly distinguish C0 from C1-C5 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260617-tegra264-pcie-v7-1-eae7ae964629@nvidia.com> References: <20260617-tegra264-pcie-v7-0-eae7ae964629@nvidia.com> In-Reply-To: <20260617-tegra264-pcie-v7-0-eae7ae964629@nvidia.com> To: Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding , Jonathan Hunter , Karthikeyan Mitran , Hou Zhiqiang , Thomas Petazzoni , =?utf-8?q?Pali_Roh=C3=A1r?= , Michal Simek , Kevin Xie , Thierry Reding , Aksh Garg Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Thierry Reding X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=5660; i=treding@nvidia.com; h=from:subject:message-id; bh=8YIMxjZKnFe8FJykhuykUjSoG8bMcRcjLCEHd6HXLQ0=; b=owEBbQKS/ZANAwAKAd0jrNd/PrOhAcsmYgBqMsUMSnrDDg5uW29OhpSeaEjhk0UdxKuGs4rNn KzfL8dL+YWJAjMEAAEKAB0WIQSI6sMIAUnM98CNyJ/dI6zXfz6zoQUCajLFDAAKCRDdI6zXfz6z oY4CD/0X50E8l7z88LSXq0VumD0SWT0Uh0tXYc7A/HVzANbJXYky0e8iA1gk1/1Aj1iGn/HD9Di NEvKXHJD/tyonOGT1mdpENuvQG17zSdbpNGmSLoKV+wcYBOPCFaCIiYg3gH9PGZ81nGehwaExRe NiINriey1ZozXbMCj+7s82ngM3RvsKgud09DJHEubpW/P/xlpRxjYJWmdWQvd43gB/qxUyi4B0y jz23tmQDq+lXhQAnJ/MAS32zuKJlR99AWB+AH/Iat/MpfgJ/5/QfqR71yAnrnsugWa4ezHF1F+a o/YJtaSSFMwSoj5BBeeYYZQdwnEhLHrXK2nXd7IIABqqHynS82qDroANYOheEn4qX5YgJG5cJse 7STTl1MIrDIHmfVmPotVJzz6nLh1PiXfv8jUvXOmhgn/qTxZGwQDOtMTpHBUNqCdbOG2miN3w4r WoGeRgeZtJzulWPwlx4T9aaRz2n+s6fVl/l2ZC1JWjJV6nK3oZTGAjb5dmu8XmAz/DnGql53QcP plkJVpLE9BVzdAh9VFAE5XOz0v3ThorOfncr92WujDCgmH9HDRswE1vdRkmFpNhRthBvZaH6p/J KXkpeO4+BszDigVEGCzB+3V3e7nzq14G7JaOqOXA8KvuZmFzngqgyKqRw/BAQn+xfCnloGT9saC Ug5Q1TofGPSj41Q== X-Developer-Key: i=treding@nvidia.com; a=openpgp; fpr=88EAC3080149CCF7C08DC89FDD23ACD77F3EB3A1 From: Thierry Reding Instead of using the ECAM registers as the first entry, strictly make a distinction between C0 and C1-C5. This is needed because otherwise the unit address doesn't match the first "reg" entry. We also cannot change the ordering of these nodes to follow the ECAM addresses because that would put them outside of their "control bus" hierarchy since the ECAM address space is a global one outside of any of the control busses. Signed-off-by: Thierry Reding --- Changes in v7: - undo changes suggested by Sashiko, should've trust the dedicated tool rather than the AI Changes in v6: - add maxItems as suggested by Sashiko Changes in v5: - rebase on top of v7.1-rc1, make it into a fix Changes in v4: - ECAM is outside of the controller's region, so it cannot be the first reg entry, otherwise we get warnings because it doesn't match the unit-address, so revert back to oneOf construct Changes in v2: - move ECAM region first and unify C0 vs. C1-C5 - move unevaluatedProperties to right before the examples - add description to clarify the two types of controllers - add examples for C0 and C1-C5 --- .../bindings/pci/nvidia,tegra264-pcie.yaml | 75 ++++++++++++++----= ---- 1 file changed, 50 insertions(+), 25 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yam= l b/Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yaml index dc4f8725c9f5..acb677d477fb 100644 --- a/Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yaml @@ -10,32 +10,23 @@ maintainers: - Thierry Reding - Jon Hunter =20 +description: | + Of the six PCIe controllers found on Tegra264, one (C0) is used for the + internal GPU and the other five (C1-C5) are routed to connectors such as + PCI or M.2 slots. Therefore the UPHY registers (XPL) exist only for C1 + through C5, but not for C0. + properties: compatible: const: nvidia,tegra264-pcie =20 reg: - description: | - Of the six PCIe controllers found on Tegra264, one (C0) is used for = the - internal GPU and the other five (C1-C5) are routed to connectors suc= h as - PCI or M.2 slots. Therefore the UPHY registers (XPL) exist only for = C1 - through C5, but not for C0. minItems: 4 - items: - - description: ECAM-compatible configuration space - - description: application layer registers - - description: transaction layer registers - - description: privileged transaction layer registers - - description: data link/physical layer registers (not available on = C0) + maxItems: 5 =20 reg-names: minItems: 4 - items: - - const: ecam - - const: xal - - const: xtl - - const: xtl-pri - - const: xpl + maxItems: 5 =20 interrupts: minItems: 1 @@ -70,6 +61,40 @@ required: =20 allOf: - $ref: /schemas/pci/pci-host-bridge.yaml# + - oneOf: + - description: C0 controller (no UPHY) + properties: + reg: + items: + - description: application layer registers + - description: transaction layer registers + - description: privileged transaction layer registers + - description: ECAM compatible configuration space + + reg-names: + items: + - const: xal + - const: xtl + - const: xtl-pri + - const: ecam + + - description: C1-C5 controllers (with UPHY) + properties: + reg: + items: + - description: application layer registers + - description: transaction layer registers + - description: privileged transaction layer registers + - description: data link/physical layer registers + - description: ECAM compatible configuration space + + reg-names: + items: + - const: xal + - const: xtl + - const: xtl-pri + - const: xpl + - const: ecam =20 unevaluatedProperties: false =20 @@ -81,11 +106,11 @@ examples: =20 pci@c000000 { compatible =3D "nvidia,tegra264-pcie"; - reg =3D <0xd0 0xb0000000 0x0 0x10000000>, - <0x00 0x0c000000 0x0 0x00004000>, + reg =3D <0x00 0x0c000000 0x0 0x00004000>, <0x00 0x0c004000 0x0 0x00001000>, - <0x00 0x0c005000 0x0 0x00001000>; - reg-names =3D "ecam", "xal", "xtl", "xtl-pri"; + <0x00 0x0c005000 0x0 0x00001000>, + <0xd0 0xb0000000 0x0 0x10000000>; + reg-names =3D "xal", "xtl", "xtl-pri", "ecam"; #address-cells =3D <3>; #size-cells =3D <2>; device_type =3D "pci"; @@ -118,12 +143,12 @@ examples: =20 pci@8400000 { compatible =3D "nvidia,tegra264-pcie"; - reg =3D <0xa8 0xb0000000 0x0 0x10000000>, - <0x00 0x08400000 0x0 0x00004000>, + reg =3D <0x00 0x08400000 0x0 0x00004000>, <0x00 0x08404000 0x0 0x00001000>, <0x00 0x08405000 0x0 0x00001000>, - <0x00 0x08410000 0x0 0x00010000>; - reg-names =3D "ecam", "xal", "xtl", "xtl-pri", "xpl"; + <0x00 0x08410000 0x0 0x00010000>, + <0xa8 0xb0000000 0x0 0x10000000>; + reg-names =3D "xal", "xtl", "xtl-pri", "xpl", "ecam"; #address-cells =3D <3>; #size-cells =3D <2>; device_type =3D "pci"; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260617-tegra264-pcie-v7-2-eae7ae964629@nvidia.com> References: <20260617-tegra264-pcie-v7-0-eae7ae964629@nvidia.com> In-Reply-To: <20260617-tegra264-pcie-v7-0-eae7ae964629@nvidia.com> To: Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding , Jonathan Hunter , Karthikeyan Mitran , Hou Zhiqiang , Thomas Petazzoni , =?utf-8?q?Pali_Roh=C3=A1r?= , Michal Simek , Kevin Xie , Thierry Reding , Aksh Garg Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Thierry Reding X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=7492; i=treding@nvidia.com; h=from:subject:message-id; bh=ogWzBW+DHXsXJyPZQjohxRSjVQ0Qs3oEo8BcfVyfLQk=; b=owEBbQKS/ZANAwAKAd0jrNd/PrOhAcsmYgBqMsUMPq9+rH88Qrp55QFFsojmF5R7/6zWsslBj FbEPPB39SyJAjMEAAEKAB0WIQSI6sMIAUnM98CNyJ/dI6zXfz6zoQUCajLFDAAKCRDdI6zXfz6z oeVVD/4szWYI/LqcrBjLQ7evSUaotOuFFUfQ1aDutME8d6Wrs+50r+zTztgeJ+engkidhY7kGuU w782vDVpPQ0mtfTOGBVlCQH1WhIMJmU9ylCmJgGZ3U2NHNikbep2gaJZZpRpRcfmhtbJWyBkCSD 098GqMY2Kr9uLVTAO8Xw3p6GcOTVjsGP9LrHVhYbNpDfZ228ykOuXTMxZhQ1YmsjQYJv2rmvGN3 2kw7gKPB6JJKBbSUakgvbYiTAVasXOWvhXVzKHt4x5N00S9KKApNWAR5VOOxZUlyLTUwv8RtGhQ NP0YewpIgx52RKHmNpl8yrkJ2v6FxNrUd+qlrLBPdRIrMF0YyiqZ79Q/lD9Tti3f9lkOHKF6j+P HyBSKdMPqNtCVZZVHQuwaD3gdHPMRt6HNObY/rfBV/Gzuuru9pRVAfbSNG5y/iYzYSG4uMXLe6g ptXeTKvSeEqB0X8ANgy4N0m+q34kdGSeIbDGN1MOwCMrPV8cB5uMExAahcYICf3HZO3pxBJlpGU DcLHlDP3xKjAzEPr0Sc2bWTkWQmnnDYtLSa4VAUoZqbXmWVMsahJq/1gFakuPuuDzGX4SXT1juP mLw58kMizF6JSno+WDjefiCxHItBXiTlNFKklWSTDcGVhyKO6l6JVK0klFYL9Mt1geECDm0PR9X eEFrYvU0bvjoUBA== X-Developer-Key: i=treding@nvidia.com; a=openpgp; fpr=88EAC3080149CCF7C08DC89FDD23ACD77F3EB3A1 From: Thierry Reding Instead of defining the wait values for each driver, use common values defined in the core pci.h header file. Note that while most drivers use the usleep_range(), it looks like these were mostly cargo culted and msleep() is a better choice given the fixed delay that the specification calls for. Convert all drivers to msleep() and use the existing definition. Signed-off-by: Thierry Reding Reviewed-by: Aksh Garg --- Changes in v7: - rebase on top of next-20260615 (resolve pci-aardvark.c conflict) Changes in v6: - convert all drivers to use msleep() (Lukas Wunner) Changes in v2: - fix build for Cadence --- drivers/pci/controller/cadence/pcie-cadence-host-common.c | 6 ++++-- drivers/pci/controller/cadence/pcie-cadence-lga-regs.h | 5 ----- drivers/pci/controller/mobiveil/pcie-mobiveil.c | 4 ++-- drivers/pci/controller/mobiveil/pcie-mobiveil.h | 5 ----- drivers/pci/controller/pci-aardvark.c | 7 ++----- drivers/pci/controller/pcie-xilinx-nwl.c | 9 ++------- drivers/pci/controller/plda/pcie-starfive.c | 9 ++------- 7 files changed, 12 insertions(+), 33 deletions(-) diff --git a/drivers/pci/controller/cadence/pcie-cadence-host-common.c b/dr= ivers/pci/controller/cadence/pcie-cadence-host-common.c index 18e4b6c760b5..0ef4396151b4 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-host-common.c +++ b/drivers/pci/controller/cadence/pcie-cadence-host-common.c @@ -16,6 +16,8 @@ #include "pcie-cadence-host-common.h" #include "../pci-host-common.h" =20 +#include "../../pci.h" + #define LINK_RETRAIN_TIMEOUT HZ =20 u64 bar_max_size[] =3D { @@ -54,12 +56,12 @@ int cdns_pcie_host_wait_for_link(struct cdns_pcie *pcie, int retries; =20 /* Check if the link is up or not */ - for (retries =3D 0; retries < LINK_WAIT_MAX_RETRIES; retries++) { + for (retries =3D 0; retries < PCIE_LINK_WAIT_MAX_RETRIES; retries++) { if (pcie_link_up(pcie)) { dev_info(dev, "Link up\n"); return 0; } - usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX); + msleep(PCIE_LINK_WAIT_SLEEP_MS); } =20 return -ETIMEDOUT; diff --git a/drivers/pci/controller/cadence/pcie-cadence-lga-regs.h b/drive= rs/pci/controller/cadence/pcie-cadence-lga-regs.h index 857b2140c5d2..15dc4fcaf45d 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-lga-regs.h +++ b/drivers/pci/controller/cadence/pcie-cadence-lga-regs.h @@ -10,11 +10,6 @@ =20 #include =20 -/* Parameters for the waiting for link up routine */ -#define LINK_WAIT_MAX_RETRIES 10 -#define LINK_WAIT_USLEEP_MIN 90000 -#define LINK_WAIT_USLEEP_MAX 100000 - /* Local Management Registers */ #define CDNS_PCIE_LM_BASE 0x00100000 =20 diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil.c b/drivers/pci/= controller/mobiveil/pcie-mobiveil.c index 62ecbaeb0a60..e8346851c49b 100644 --- a/drivers/pci/controller/mobiveil/pcie-mobiveil.c +++ b/drivers/pci/controller/mobiveil/pcie-mobiveil.c @@ -218,11 +218,11 @@ int mobiveil_bringup_link(struct mobiveil_pcie *pcie) int retries; =20 /* check if the link is up or not */ - for (retries =3D 0; retries < LINK_WAIT_MAX_RETRIES; retries++) { + for (retries =3D 0; retries < PCIE_LINK_WAIT_MAX_RETRIES; retries++) { if (mobiveil_pcie_link_up(pcie)) return 0; =20 - usleep_range(LINK_WAIT_MIN, LINK_WAIT_MAX); + msleep(PCIE_LINK_WAIT_SLEEP_MS); } =20 dev_err(&pcie->pdev->dev, "link never came up\n"); diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil.h b/drivers/pci/= controller/mobiveil/pcie-mobiveil.h index 7246de6a7176..11010a99e27c 100644 --- a/drivers/pci/controller/mobiveil/pcie-mobiveil.h +++ b/drivers/pci/controller/mobiveil/pcie-mobiveil.h @@ -122,11 +122,6 @@ #define IB_WIN_SIZE ((u64)256 * 1024 * 1024 * 1024) #define MAX_PIO_WINDOWS 8 =20 -/* Parameters for the waiting for link up routine */ -#define LINK_WAIT_MAX_RETRIES 10 -#define LINK_WAIT_MIN 90000 -#define LINK_WAIT_MAX 100000 - #define PAGED_ADDR_BNDRY 0xc00 #define OFFSET_TO_PAGE_ADDR(off) \ ((off & PAGE_LO_MASK) | PAGED_ADDR_BNDRY) diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller= /pci-aardvark.c index fd9c7d53e8a7..272c5c8fc1e5 100644 --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c @@ -256,9 +256,6 @@ enum { #define PIO_RETRY_CNT 750000 /* 1.5 s */ #define PIO_RETRY_DELAY 2 /* 2 us*/ =20 -#define LINK_WAIT_MAX_RETRIES 10 -#define LINK_WAIT_USLEEP_MIN 90000 -#define LINK_WAIT_USLEEP_MAX 100000 #define RETRAIN_WAIT_MAX_RETRIES 10 #define RETRAIN_WAIT_USLEEP_US 2000 =20 @@ -350,13 +347,13 @@ static int advk_pcie_wait_for_link(struct advk_pcie *= pcie) int retries; =20 /* check if the link is up or not */ - for (retries =3D 0; retries < LINK_WAIT_MAX_RETRIES; retries++) { + for (retries =3D 0; retries < PCIE_LINK_WAIT_MAX_RETRIES; retries++) { if (advk_pcie_link_up(pcie)) { pci_host_common_link_train_delay(pcie->link_gen); return 0; } =20 - usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX); + msleep(PCIE_LINK_WAIT_SLEEP_MS); } =20 return -ETIMEDOUT; diff --git a/drivers/pci/controller/pcie-xilinx-nwl.c b/drivers/pci/control= ler/pcie-xilinx-nwl.c index 7db2c96c6cec..0dee19fa24ca 100644 --- a/drivers/pci/controller/pcie-xilinx-nwl.c +++ b/drivers/pci/controller/pcie-xilinx-nwl.c @@ -140,11 +140,6 @@ #define PCIE_PHY_LINKUP_BIT BIT(0) #define PHY_RDY_LINKUP_BIT BIT(1) =20 -/* Parameters for the waiting for link up routine */ -#define LINK_WAIT_MAX_RETRIES 10 -#define LINK_WAIT_USLEEP_MIN 90000 -#define LINK_WAIT_USLEEP_MAX 100000 - struct nwl_msi { /* MSI information */ DECLARE_BITMAP(bitmap, INT_PCI_MSI_NR); struct irq_domain *dev_domain; @@ -203,10 +198,10 @@ static int nwl_wait_for_link(struct nwl_pcie *pcie) int retries; =20 /* check if the link is up or not */ - for (retries =3D 0; retries < LINK_WAIT_MAX_RETRIES; retries++) { + for (retries =3D 0; retries < PCIE_LINK_WAIT_MAX_RETRIES; retries++) { if (nwl_phy_link_up(pcie)) return 0; - usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX); + msleep(PCIE_LINK_WAIT_SLEEP_MS); } =20 dev_err(dev, "PHY link never came up\n"); diff --git a/drivers/pci/controller/plda/pcie-starfive.c b/drivers/pci/cont= roller/plda/pcie-starfive.c index 298036c3e7f9..2835c7af965e 100644 --- a/drivers/pci/controller/plda/pcie-starfive.c +++ b/drivers/pci/controller/plda/pcie-starfive.c @@ -45,11 +45,6 @@ #define STG_SYSCON_LNKSTA_OFFSET 0x170 #define DATA_LINK_ACTIVE BIT(5) =20 -/* Parameters for the waiting for link up routine */ -#define LINK_WAIT_MAX_RETRIES 10 -#define LINK_WAIT_USLEEP_MIN 90000 -#define LINK_WAIT_USLEEP_MAX 100000 - struct starfive_jh7110_pcie { struct plda_pcie_rp plda; struct reset_control *resets; @@ -217,12 +212,12 @@ static int starfive_pcie_host_wait_for_link(struct st= arfive_jh7110_pcie *pcie) int retries; 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b=FmX/pY1MfblqHs9BdBRdCrlABDU2toK5BgLT553peynVg76zFXtRw1UUqdFxwDSDz YMAW5VUYsrqOWbA9saQFrilmt/zT6JyY0sdvAdOLm1XRT9KSvcjXm1m9Qnu3YxwMuF H30bY8IqKPYImcPVonb1kcTaG2Gc+BLOJEsjPG8V6Mq62xCjTRNND7MOsFIVAd+TPp B5nTmxvFqRe2liMwcbBpKBfFHcYgnmf33YQqDMIJSNcBxgxk8rHby2tUk94agjwnDX biRTO8M/93SgvZz+EptYYS+hw+98BgfQi3j8dAldcOSY+ZUXmQjKLfpr9P/1BTsF1p c48dh73XNjYYQ== From: Thierry Reding Date: Wed, 17 Jun 2026 18:01:30 +0200 Subject: [PATCH v7 3/4] PCI: tegra: Add Tegra264 support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260617-tegra264-pcie-v7-3-eae7ae964629@nvidia.com> References: <20260617-tegra264-pcie-v7-0-eae7ae964629@nvidia.com> In-Reply-To: <20260617-tegra264-pcie-v7-0-eae7ae964629@nvidia.com> To: Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding , Jonathan Hunter , Karthikeyan Mitran , Hou Zhiqiang , Thomas Petazzoni , =?utf-8?q?Pali_Roh=C3=A1r?= , Michal Simek , Kevin Xie , Thierry Reding , Aksh Garg Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Thierry Reding , Manikanta Maddireddy X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=88EAC3080149CCF7C08DC89FDD23ACD77F3EB3A1 From: Thierry Reding Add a driver for the PCIe controller found on NVIDIA Tegra264 SoCs. The driver is very small, with its main purpose being to set up the address translation registers and then creating a standard PCI host using ECAM. Signed-off-by: Manikanta Maddireddy Signed-off-by: Thierry Reding --- Changes in v7: - select PCI_ECAM to satisfy the build dependency (Jonathan Hunter) - remove pre-silicon support patch to avoid extra build dependency Changes in v6: - remove unneeded pm_runtime_disable() call (Sashiko) - do not use noirq suspend/resume callbacks (Sashiko) - wrap PM ops in pm_ptr() macro (Sashiko) - use standard wait times with msleep() (Lukas Wunner) - properly check errors for wake IRQs - fix build failures /o\ Changes in v5: - make PCIE_TEGRA264 symbol tristate - drop dependency on PCI_MSI - reorganize tegra264_pcie struct - use standard wake-gpios property - rename tegra264_pcie_bpmp_set_rp_state() to tegra264_pcie_power_off() - use dev_err() instead of dev_info() for some error messages - add clarifying comment as to why bandwidth requests aren't fatal - address some compiler warnings on 32-bit physical address platforms - drop needless comments - explicitly deinitialize controller on suspend - use devm_pm_runtime_active_enabled() - rename "free" label to "free_ecam" - use dev_err_probe() in more places - reselect default pin state during resume, not probe - return early on absence of wake GPIO - simplify BW value calculation Changes in v2: - specify generations applicable for PCI_TEGRA driver to avoid confusion - drop SPDX-FileCopyrightText tag - rename link_state to link_up to clarify meaning - replace memset() by an empty initializer - sanity-check only enable BAR regions - bring PCI link out of reset in case firmware didn't - use common wait times instead of defining our own - use core helpers to parse and print PCI link speed - fix multi-line comment - use dev_err_probe() more ubiquitously - fix probe sequence and error cleanup - use DEFINE_NOIRQ_DEV_PM_OPS() to avoid warnings for !PM_SUSPEND - reuse more standard registers and remove unused register definitions - use %pe and ERR_PTR() to print symbolic errors - add signed-off-by from Manikanta as the original author - add myself as author after significantly modifying the driver pcie: remove pre-silicon conditionals --- drivers/pci/controller/Kconfig | 10 +- drivers/pci/controller/Makefile | 1 + drivers/pci/controller/pcie-tegra264.c | 538 +++++++++++++++++++++++++++++= ++++ 3 files changed, 548 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig index 2247709ef6d6..3045c8aecc7e 100644 --- a/drivers/pci/controller/Kconfig +++ b/drivers/pci/controller/Kconfig @@ -255,7 +255,15 @@ config PCI_TEGRA select IRQ_MSI_LIB help Say Y here if you want support for the PCIe host controller found - on NVIDIA Tegra SoCs. + on NVIDIA Tegra SoCs (Tegra20 through Tegra186). + +config PCIE_TEGRA264 + tristate "NVIDIA Tegra264 PCIe controller" + depends on ARCH_TEGRA || COMPILE_TEST + select PCI_ECAM + help + Say Y here if you want support for the PCIe host controller found + on NVIDIA Tegra264 SoCs. =20 config PCIE_RCAR_HOST bool "Renesas R-Car PCIe controller (host mode)" diff --git a/drivers/pci/controller/Makefile b/drivers/pci/controller/Makef= ile index ac8db283f0fe..d478743b5142 100644 --- a/drivers/pci/controller/Makefile +++ b/drivers/pci/controller/Makefile @@ -7,6 +7,7 @@ obj-$(CONFIG_PCI_HYPERV_INTERFACE) +=3D pci-hyperv-intf.o obj-$(CONFIG_PCI_MVEBU) +=3D pci-mvebu.o obj-$(CONFIG_PCI_AARDVARK) +=3D pci-aardvark.o obj-$(CONFIG_PCI_TEGRA) +=3D pci-tegra.o +obj-$(CONFIG_PCIE_TEGRA264) +=3D pcie-tegra264.o obj-$(CONFIG_PCI_RCAR_GEN2) +=3D pci-rcar-gen2.o obj-$(CONFIG_PCIE_RCAR_HOST) +=3D pcie-rcar.o pcie-rcar-host.o obj-$(CONFIG_PCIE_RCAR_EP) +=3D pcie-rcar.o pcie-rcar-ep.o diff --git a/drivers/pci/controller/pcie-tegra264.c b/drivers/pci/controlle= r/pcie-tegra264.c new file mode 100644 index 000000000000..e2d295ea4403 --- /dev/null +++ b/drivers/pci/controller/pcie-tegra264.c @@ -0,0 +1,538 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * PCIe host controller driver for Tegra264 SoC + * + * Copyright (c) 2022-2026, NVIDIA CORPORATION. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "../pci.h" + +/* XAL registers */ +#define XAL_RC_ECAM_BASE_HI 0x00 +#define XAL_RC_ECAM_BASE_LO 0x04 +#define XAL_RC_ECAM_BUSMASK 0x08 +#define XAL_RC_IO_BASE_HI 0x0c +#define XAL_RC_IO_BASE_LO 0x10 +#define XAL_RC_IO_LIMIT_HI 0x14 +#define XAL_RC_IO_LIMIT_LO 0x18 +#define XAL_RC_MEM_32BIT_BASE_HI 0x1c +#define XAL_RC_MEM_32BIT_BASE_LO 0x20 +#define XAL_RC_MEM_32BIT_LIMIT_HI 0x24 +#define XAL_RC_MEM_32BIT_LIMIT_LO 0x28 +#define XAL_RC_MEM_64BIT_BASE_HI 0x2c +#define XAL_RC_MEM_64BIT_BASE_LO 0x30 +#define XAL_RC_MEM_64BIT_LIMIT_HI 0x34 +#define XAL_RC_MEM_64BIT_LIMIT_LO 0x38 +#define XAL_RC_BAR_CNTL_STANDARD 0x40 +#define XAL_RC_BAR_CNTL_STANDARD_IOBAR_EN BIT(0) +#define XAL_RC_BAR_CNTL_STANDARD_32B_BAR_EN BIT(1) +#define XAL_RC_BAR_CNTL_STANDARD_64B_BAR_EN BIT(2) + +/* XTL registers */ +#define XTL_RC_PCIE_CFG_LINK_STATUS 0x5a + +#define XTL_RC_MGMT_PERST_CONTROL 0x218 +#define XTL_RC_MGMT_PERST_CONTROL_PERST_O_N BIT(0) + +#define XTL_RC_MGMT_CLOCK_CONTROL 0x47c +#define XTL_RC_MGMT_CLOCK_CONTROL_PEX_CLKREQ_I_N_PIN_USE_CONV_TO_PRSNT BIT= (9) + +struct tegra264_pcie { + struct device *dev; + + /* I/O memory */ + void __iomem *xal; + void __iomem *xtl; + void __iomem *ecam; + + /* bridge configuration */ + struct pci_config_window *cfg; + struct pci_host_bridge *bridge; + + /* wake IRQ */ + struct gpio_desc *wake_gpio; + unsigned int wake_irq; + + /* BPMP and bandwidth management */ + struct icc_path *icc_path; + struct tegra_bpmp *bpmp; + u32 ctl_id; + + bool link_up; +}; + +static int tegra264_pcie_parse_dt(struct tegra264_pcie *pcie) +{ + struct device *dev =3D pcie->dev; + int err; + + pcie->wake_gpio =3D devm_gpiod_get_optional(dev, "wake", GPIOD_IN); + if (IS_ERR(pcie->wake_gpio)) + return PTR_ERR(pcie->wake_gpio); + + if (!pcie->wake_gpio) + return 0; + + err =3D gpiod_to_irq(pcie->wake_gpio); + if (err < 0) + return dev_err_probe(dev, err, "failed to get wake IRQ\n"); + + pcie->wake_irq =3D (unsigned int)err; + + err =3D devm_device_init_wakeup(dev); + if (err < 0) + return dev_err_probe(dev, err, "failed to initialize wakeup\n"); + + err =3D devm_pm_set_wake_irq(dev, pcie->wake_irq); + if (err < 0) + return dev_err_probe(dev, err, "failed to set wakeup IRQ\n"); + + return 0; +} + +static void tegra264_pcie_power_off(struct tegra264_pcie *pcie) +{ + struct tegra_bpmp_message msg =3D {}; + struct mrq_pcie_request req =3D {}; + int err; + + req.cmd =3D CMD_PCIE_RP_CONTROLLER_OFF; + req.rp_ctrlr_off.rp_controller =3D pcie->ctl_id; + + msg.mrq =3D MRQ_PCIE; + msg.tx.data =3D &req; + msg.tx.size =3D sizeof(req); + + err =3D tegra_bpmp_transfer(pcie->bpmp, &msg); + if (err) + dev_err(pcie->dev, "failed to turn off PCIe #%u: %pe\n", + pcie->ctl_id, ERR_PTR(err)); + + if (msg.rx.ret) + dev_err(pcie->dev, "failed to turn off PCIe #%u: %d\n", + pcie->ctl_id, msg.rx.ret); +} + +static void tegra264_pcie_icc_set(struct tegra264_pcie *pcie) +{ + u32 value, speed, width; + int err; + + value =3D readw(pcie->ecam + XTL_RC_PCIE_CFG_LINK_STATUS); + speed =3D FIELD_GET(PCI_EXP_LNKSTA_CLS, value); + width =3D FIELD_GET(PCI_EXP_LNKSTA_NLW, value); + + value =3D Mbps_to_icc(width * PCIE_SPEED2MBS_ENC(pcie_link_speed[speed])); + + /* + * We don't want to error out here because a boot-critical device + * could be connected to this root port. Failure to set the bandwidth + * request may have an adverse impact on performance, but it is not + * generally fatal, so we opt to continue regardless so that users + * get a chance to fix things. + */ + err =3D icc_set_bw(pcie->icc_path, value, value); + if (err < 0) + dev_err(pcie->dev, + "failed to request bandwidth (%u MBps): %pe\n", + value, ERR_PTR(err)); +} + +/* + * The various memory regions used by the controller (I/O, memory, ECAM) a= re + * set up during early boot and have hardware-level protections in place. = If + * the DT ranges don't match what's been setup, the controller won't be ab= le + * to write the address endpoints properly, so make sure to validate that = DT + * and firmware programming agree on these ranges. + */ +static bool tegra264_pcie_check_ranges(struct platform_device *pdev) +{ + struct tegra264_pcie *pcie =3D platform_get_drvdata(pdev); + struct device_node *np =3D pcie->dev->of_node; + struct of_pci_range_parser parser; + phys_addr_t phys, limit, hi, lo; + struct of_pci_range range; + struct resource *res; + bool status =3D true; + u32 value; + int err; + + err =3D of_pci_range_parser_init(&parser, np); + if (err < 0) + return false; + + for_each_of_pci_range(&parser, &range) { + unsigned int addr_hi, addr_lo, limit_hi, limit_lo, enable; + unsigned long type =3D range.flags & IORESOURCE_TYPE_BITS; + phys_addr_t start, end, mask; + const char *region =3D NULL; + + end =3D range.cpu_addr + range.size - 1; + start =3D range.cpu_addr; + + switch (type) { + case IORESOURCE_IO: + addr_hi =3D XAL_RC_IO_BASE_HI; + addr_lo =3D XAL_RC_IO_BASE_LO; + limit_hi =3D XAL_RC_IO_LIMIT_HI; + limit_lo =3D XAL_RC_IO_LIMIT_LO; + enable =3D XAL_RC_BAR_CNTL_STANDARD_IOBAR_EN; + mask =3D SZ_64K - 1; + region =3D "I/O"; + break; + + case IORESOURCE_MEM: + if (range.flags & IORESOURCE_PREFETCH) { + addr_hi =3D XAL_RC_MEM_64BIT_BASE_HI; + addr_lo =3D XAL_RC_MEM_64BIT_BASE_LO; + limit_hi =3D XAL_RC_MEM_64BIT_LIMIT_HI; + limit_lo =3D XAL_RC_MEM_64BIT_LIMIT_LO; + enable =3D XAL_RC_BAR_CNTL_STANDARD_64B_BAR_EN; + region =3D "prefetchable memory"; + } else { + addr_hi =3D XAL_RC_MEM_32BIT_BASE_HI; + addr_lo =3D XAL_RC_MEM_32BIT_BASE_LO; + limit_hi =3D XAL_RC_MEM_32BIT_LIMIT_HI; + limit_lo =3D XAL_RC_MEM_32BIT_LIMIT_LO; + enable =3D XAL_RC_BAR_CNTL_STANDARD_32B_BAR_EN; + region =3D "memory"; + } + + mask =3D SZ_1M - 1; + break; + } + + /* not interested in anything that's not I/O or memory */ + if (!region) + continue; + + /* don't check regions that haven't been enabled */ + value =3D readl(pcie->xal + XAL_RC_BAR_CNTL_STANDARD); + if ((value & enable) =3D=3D 0) + continue; + + hi =3D readl(pcie->xal + addr_hi); + lo =3D readl(pcie->xal + addr_lo); + phys =3D ((hi << 16) << 16) | lo; + + hi =3D readl(pcie->xal + limit_hi); + lo =3D readl(pcie->xal + limit_lo); + limit =3D ((hi << 16) << 16) | lo | mask; + + if (phys !=3D start || limit !=3D end) { + dev_err(pcie->dev, + "%s region mismatch: %pap-%pap -> %pap-%pap\n", + region, &phys, &limit, &start, &end); + status =3D false; + } + } + + res =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, "ecam"); + if (!res) + return false; + + hi =3D readl(pcie->xal + XAL_RC_ECAM_BASE_HI); + lo =3D readl(pcie->xal + XAL_RC_ECAM_BASE_LO); + phys =3D ((hi << 16) << 16) | lo; + + value =3D readl(pcie->xal + XAL_RC_ECAM_BUSMASK); + limit =3D phys + ((value + 1) << 20) - 1; + + if (phys !=3D res->start || limit !=3D res->end) { + dev_err(pcie->dev, + "ECAM region mismatch: %pap-%pap -> %pap-%pap\n", + &phys, &limit, &res->start, &res->end); + status =3D false; + } + + return status; +} + +static bool tegra264_pcie_link_up(struct tegra264_pcie *pcie, + enum pci_bus_speed *speed) +{ + u16 value =3D readw(pcie->ecam + XTL_RC_PCIE_CFG_LINK_STATUS); + + if (value & PCI_EXP_LNKSTA_DLLLA) { + if (speed) + *speed =3D pcie_link_speed[FIELD_GET(PCI_EXP_LNKSTA_CLS, + value)]; + + return true; + } + + return false; +} + +static void tegra264_pcie_init(struct tegra264_pcie *pcie) +{ + enum pci_bus_speed speed; + unsigned int i; + u32 value; + + /* bring the endpoint out of reset */ + value =3D readl(pcie->xtl + XTL_RC_MGMT_PERST_CONTROL); + value |=3D XTL_RC_MGMT_PERST_CONTROL_PERST_O_N; + writel(value, pcie->xtl + XTL_RC_MGMT_PERST_CONTROL); + + for (i =3D 0; i < PCIE_LINK_WAIT_MAX_RETRIES; i++) { + if (tegra264_pcie_link_up(pcie, NULL)) + break; + + msleep(PCIE_LINK_WAIT_SLEEP_MS); + } + + if (tegra264_pcie_link_up(pcie, &speed)) { + msleep(PCIE_RESET_CONFIG_WAIT_MS); + dev_info(pcie->dev, "PCIe #%u link is up (speed: %s)\n", + pcie->ctl_id, pci_speed_string(speed)); + tegra264_pcie_icc_set(pcie); + pcie->link_up =3D true; + } else { + dev_info(pcie->dev, "PCIe #%u link is down\n", pcie->ctl_id); + + value =3D readl(pcie->xtl + XTL_RC_MGMT_CLOCK_CONTROL); + + /* + * Set link state only when link fails and no hot-plug feature + * is present. + */ + if ((value & XTL_RC_MGMT_CLOCK_CONTROL_PEX_CLKREQ_I_N_PIN_USE_CONV_TO_PR= SNT) =3D=3D 0) { + dev_info(pcie->dev, + "PCIe #%u link is down and not hotplug-capable, turning off\n", + pcie->ctl_id); + tegra264_pcie_power_off(pcie); + pcie->link_up =3D false; + } else { + pcie->link_up =3D true; + } + } +} + +static void tegra264_pcie_deinit(struct tegra264_pcie *pcie) +{ + u32 value; + + /* take the endpoint into reset */ + value =3D readl(pcie->xtl + XTL_RC_MGMT_PERST_CONTROL); + value &=3D ~XTL_RC_MGMT_PERST_CONTROL_PERST_O_N; + writel(value, pcie->xtl + XTL_RC_MGMT_PERST_CONTROL); +} + +static int tegra264_pcie_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct pci_host_bridge *bridge; + struct tegra264_pcie *pcie; + struct resource_entry *bus; + struct resource *res; + int err; + + bridge =3D devm_pci_alloc_host_bridge(dev, sizeof(struct tegra264_pcie)); + if (!bridge) + return dev_err_probe(dev, -ENOMEM, + "failed to allocate host bridge\n"); + + pcie =3D pci_host_bridge_priv(bridge); + platform_set_drvdata(pdev, pcie); + pcie->bridge =3D bridge; + pcie->dev =3D dev; + + err =3D tegra264_pcie_parse_dt(pcie); + if (err < 0) + return dev_err_probe(dev, err, "failed to parse device tree\n"); + + pcie->xal =3D devm_platform_ioremap_resource_byname(pdev, "xal"); + if (IS_ERR(pcie->xal)) + return dev_err_probe(dev, PTR_ERR(pcie->xal), + "failed to map XAL memory\n"); + + pcie->xtl =3D devm_platform_ioremap_resource_byname(pdev, "xtl-pri"); + if (IS_ERR(pcie->xtl)) + return dev_err_probe(dev, PTR_ERR(pcie->xtl), + "failed to map XTL-PRI memory\n"); + + bus =3D resource_list_first_type(&bridge->windows, IORESOURCE_BUS); + if (!bus) + return dev_err_probe(dev, -ENODEV, + "failed to get bus resources\n"); + + res =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, "ecam"); + if (!res) + return dev_err_probe(dev, -ENXIO, + "failed to get ECAM resource\n"); + + pcie->icc_path =3D devm_of_icc_get(dev, "write"); + if (IS_ERR(pcie->icc_path)) + return dev_err_probe(dev, PTR_ERR(pcie->icc_path), + "failed to get ICC\n"); + + pcie->bpmp =3D tegra_bpmp_get_with_id(dev, &pcie->ctl_id); + if (IS_ERR(pcie->bpmp)) + return dev_err_probe(dev, PTR_ERR(pcie->bpmp), + "failed to get BPMP\n"); + + err =3D devm_pm_runtime_set_active_enabled(dev); + if (err < 0) { + dev_err_probe(dev, err, "failed to enable runtime PM\n"); + goto put_bpmp; + } + + err =3D pm_runtime_get_sync(dev); + if (err < 0) { + dev_err_probe(dev, err, "failed to power on device\n"); + goto put_bpmp; + } + + /* sanity check that programmed ranges match what's in DT */ + if (!tegra264_pcie_check_ranges(pdev)) { + err =3D -EINVAL; + goto put_pm; + } + + pcie->cfg =3D pci_ecam_create(dev, res, bus->res, &pci_generic_ecam_ops); + if (IS_ERR(pcie->cfg)) { + err =3D dev_err_probe(dev, PTR_ERR(pcie->cfg), + "failed to create ECAM\n"); + goto put_pm; + } + + bridge->ops =3D (struct pci_ops *)&pci_generic_ecam_ops.pci_ops; + bridge->sysdata =3D pcie->cfg; + pcie->ecam =3D pcie->cfg->win; + + tegra264_pcie_init(pcie); + + if (!pcie->link_up) + return 0; + + err =3D pci_host_probe(bridge); + if (err < 0) { + dev_err_probe(dev, err, "failed to register host\n"); + goto free_ecam; + } + + return 0; + +free_ecam: + pci_ecam_free(pcie->cfg); +put_pm: + pm_runtime_put_sync(dev); +put_bpmp: + tegra_bpmp_put(pcie->bpmp); + + return err; +} + +static void tegra264_pcie_remove(struct platform_device *pdev) +{ + struct tegra264_pcie *pcie =3D platform_get_drvdata(pdev); + + /* + * If we undo tegra264_pcie_init() then link goes down and need + * controller reset to bring up the link again. Remove intention is + * to clean up the root bridge and re-enumerate during bind. + */ + pci_lock_rescan_remove(); + pci_stop_root_bus(pcie->bridge->bus); + pci_remove_root_bus(pcie->bridge->bus); + pci_unlock_rescan_remove(); + + pm_runtime_put_sync(&pdev->dev); + tegra_bpmp_put(pcie->bpmp); + pci_ecam_free(pcie->cfg); +} + +static int tegra264_pcie_suspend(struct device *dev) +{ + struct tegra264_pcie *pcie =3D dev_get_drvdata(dev); + int err; + + tegra264_pcie_deinit(pcie); + + if (pcie->wake_gpio && device_may_wakeup(dev)) { + err =3D enable_irq_wake(pcie->wake_irq); + if (err < 0) + dev_err(dev, "failed to enable wake IRQ: %pe\n", + ERR_PTR(err)); + } + + return 0; +} + +static int tegra264_pcie_resume(struct device *dev) +{ + struct tegra264_pcie *pcie =3D dev_get_drvdata(dev); + int err; + + err =3D pinctrl_pm_select_default_state(dev); + if (err < 0) + dev_err(dev, "failed to configure sideband pins: %pe\n", + ERR_PTR(err)); + + if (pcie->wake_gpio && device_may_wakeup(dev)) { + err =3D disable_irq_wake(pcie->wake_irq); + if (err < 0) + dev_err(dev, "failed to disable wake IRQ: %pe\n", + ERR_PTR(err)); + } + + if (pcie->link_up =3D=3D false) + return 0; + + tegra264_pcie_init(pcie); + + return 0; +} + +static DEFINE_SIMPLE_DEV_PM_OPS(tegra264_pcie_pm_ops, + tegra264_pcie_suspend, + tegra264_pcie_resume); + +static const struct of_device_id tegra264_pcie_of_match[] =3D { + { + .compatible =3D "nvidia,tegra264-pcie", + }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, tegra264_pcie_of_match); + +static struct platform_driver tegra264_pcie_driver =3D { + .probe =3D tegra264_pcie_probe, + .remove =3D tegra264_pcie_remove, + .driver =3D { + .name =3D "tegra264-pcie", + .pm =3D pm_ptr(&tegra264_pcie_pm_ops), + .of_match_table =3D tegra264_pcie_of_match, + }, +}; +module_platform_driver(tegra264_pcie_driver); + +MODULE_AUTHOR("Manikanta Maddireddy "); +MODULE_AUTHOR("Thierry Reding "); +MODULE_DESCRIPTION("NVIDIA Tegra264 PCIe host controller driver"); +MODULE_LICENSE("GPL"); --=20 2.54.0 From nobody Sun Jun 21 16:14:17 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 147A84A2E05; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="E477XrUk" Received: by smtp.kernel.org (Postfix) with ESMTPSA id D73F21F01558; Wed, 17 Jun 2026 16:02:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1781712154; bh=cp5BkG390f/fn9ldPF3mpiSrgkIetFpKVYvXrJB7/WU=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=E477XrUk2dw6FrkEB01E35B5mc3yzvjUx19J/vYBDs7vI+DGIEtx8pOq6jzVZrz+Q Im9DgfD/qC+EzOxYLu0CN+sEV7T6yISgGOloz1tA9QEa5RDvy+5AYZQLCDyGplwa6v d++w+eZ4MSk4UMDQxOtE4iBFFV8opeaFeauSk/qcFQoOfpjR62lSFzApctcJVnEkPF qRH6QhablCNTPUrJkslC1DGv0A25OEdyNvk/ngRVNjk7xj5b0U2CVVGmCs7oHaPjjT JPBl4uGMApfEroA8g6cHRBwKsq930XKTqv90H+Dx67h6m8ijOGyhPPj7PrsP/e1i/K I6RcyPUccuP9Q== From: Thierry Reding Date: Wed, 17 Jun 2026 18:01:31 +0200 Subject: [PATCH v7 4/4] arm64: tegra: Reorder reg and reg-names to match bindings Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260617-tegra264-pcie-v7-4-eae7ae964629@nvidia.com> References: <20260617-tegra264-pcie-v7-0-eae7ae964629@nvidia.com> In-Reply-To: <20260617-tegra264-pcie-v7-0-eae7ae964629@nvidia.com> To: Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding , Jonathan Hunter , Karthikeyan Mitran , Hou Zhiqiang , Thomas Petazzoni , =?utf-8?q?Pali_Roh=C3=A1r?= , Michal Simek , Kevin Xie , Thierry Reding , Aksh Garg Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Thierry Reding X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=4765; i=treding@nvidia.com; h=from:subject:message-id; bh=g4lQg9cZ99o24xfKWoKjSIFGaumk63ktv5zBQENtPlA=; b=owEBbQKS/ZANAwAKAd0jrNd/PrOhAcsmYgBqMsUNciDqZaew/sWNx3N02UnAfVlH6AQ0aW8b3 C53LXX1XBuJAjMEAAEKAB0WIQSI6sMIAUnM98CNyJ/dI6zXfz6zoQUCajLFDQAKCRDdI6zXfz6z oQ+AD/0YqfMEpfe+KyTdT2s+1mO2EZ5By76Fr+WrXUS3GypSQEx9jn9v/J1mFAQCQG5n1TX97oS qnmb28n466W96XUChkVXVIgHfqGra1B8wyOY8Si+gJW0vJFEwg6hVmOhpqJXMBY7Wnp1x0ufGOO JKCB3LYh6Rdwn3X1VVQxbG/LZ5gu7abPvotDxEWcDd5twtksEKwFcIddM6+cKKeVLD6umvgdXfV 8IGqwSNJoWIwBqrxat1wMKotBfpTVnlswnkHUlxGOdG2hrCm1dKhlugLOfb51UFw4c4hxZLFOM9 uHCX00MS4R2kySyQFX0sSFd4Fw2LU+miJWJ/7nCcYdMA1UtFBxxgl8FbjIj1wvxSfWmLukYcKhL o783Si/+0pyRn4aPdyNmaw3aVz7jnpqo31LGmAu9hgZuIu2iKR93/7+jfg4kz5QUfWaxWD3RuIS Nfku6OfshvZHe+T1BsSbhK+sJh+eL6ZMDq25W/7LbhVgbE4T0YtXo4V9/pXyQs0ZsK4+Xhfwbqp NuZIJ0xIrAgVIxKpbj31EwreBx6d9Uo685/7jDgb0mIXpT+sVLgf6QQC0DEiiN7rgyLsw5yEUX0 86DmpdiXqy7O1LmJERJcSCN61aHuy6Tz9nMxqAsVrT60e7IqLEnMlryQsF7KFYudNrbHROtZFLD kAfVJwndTWsCOtA== X-Developer-Key: i=treding@nvidia.com; a=openpgp; fpr=88EAC3080149CCF7C08DC89FDD23ACD77F3EB3A1 From: Thierry Reding The ECAM region cannot be the first entry in the "reg" property, because in that case the unit-address wouldn't match the first entry. The order of the nodes can also not be changed to match the ECAM entry because the ECAM region is global and outside of any of the control busses. Signed-off-by: Thierry Reding Acked-by: Manivannan Sadhasivam --- Changes in v5: - rebase onto v7.1-rc1 Changes in v4: - revert ECAM "reg" entry order Changes in v2: - order ECAM "reg" entry before others --- arch/arm64/boot/dts/nvidia/tegra264.dtsi | 48 ++++++++++++++++------------= ---- 1 file changed, 24 insertions(+), 24 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra264.dtsi b/arch/arm64/boot/dts= /nvidia/tegra264.dtsi index 8f4350c7793b..4c701abd25a8 100644 --- a/arch/arm64/boot/dts/nvidia/tegra264.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra264.dtsi @@ -3513,11 +3513,11 @@ cmdqv4: cmdqv@b200000 { =20 pci@c000000 { compatible =3D "nvidia,tegra264-pcie"; - reg =3D <0xd0 0xb0000000 0x0 0x10000000>, - <0x00 0x0c000000 0x0 0x00004000>, + reg =3D <0x00 0x0c000000 0x0 0x00004000>, <0x00 0x0c004000 0x0 0x00001000>, - <0x00 0x0c005000 0x0 0x00001000>; - reg-names =3D "ecam", "xal", "xtl", "xtl-pri"; + <0x00 0x0c005000 0x0 0x00001000>, + <0xd0 0xb0000000 0x0 0x10000000>; + reg-names =3D "xal", "xtl", "xtl-pri", "ecam"; #address-cells =3D <3>; #size-cells =3D <2>; device_type =3D "pci"; @@ -3893,12 +3893,12 @@ gpio_uphy: gpio@8300000 { =20 pci@8400000 { compatible =3D "nvidia,tegra264-pcie"; - reg =3D <0xa8 0xb0000000 0x0 0x10000000>, - <0x00 0x08400000 0x0 0x00004000>, + reg =3D <0x00 0x08400000 0x0 0x00004000>, <0x00 0x08404000 0x0 0x00001000>, <0x00 0x08405000 0x0 0x00001000>, - <0x00 0x08410000 0x0 0x00010000>; - reg-names =3D "ecam", "xal", "xtl", "xtl-pri", "xpl"; + <0x00 0x08410000 0x0 0x00010000>, + <0xa8 0xb0000000 0x0 0x10000000>; + reg-names =3D "xal", "xtl", "xtl-pri", "xpl", "ecam"; #address-cells =3D <3>; #size-cells =3D <2>; device_type =3D "pci"; @@ -3925,12 +3925,12 @@ pci@8400000 { =20 pci@8420000 { compatible =3D "nvidia,tegra264-pcie"; - reg =3D <0xb0 0xb0000000 0x0 0x10000000>, - <0x00 0x08420000 0x0 0x00004000>, + reg =3D <0x00 0x08420000 0x0 0x00004000>, <0x00 0x08424000 0x0 0x00001000>, <0x00 0x08425000 0x0 0x00001000>, - <0x00 0x08430000 0x0 0x00010000>; - reg-names =3D "ecam", "xal", "xtl", "xtl-pri", "xpl"; + <0x00 0x08430000 0x0 0x00010000>, + <0xb0 0xb0000000 0x0 0x10000000>; + reg-names =3D "xal", "xtl", "xtl-pri", "xpl", "ecam"; #address-cells =3D <3>; #size-cells =3D <2>; device_type =3D "pci"; @@ -3957,12 +3957,12 @@ pci@8420000 { =20 pci@8440000 { compatible =3D "nvidia,tegra264-pcie"; - reg =3D <0xb8 0xb0000000 0x0 0x10000000>, - <0x00 0x08440000 0x0 0x00004000>, + reg =3D <0x00 0x08440000 0x0 0x00004000>, <0x00 0x08444000 0x0 0x00001000>, <0x00 0x08445000 0x0 0x00001000>, - <0x00 0x08450000 0x0 0x00010000>; - reg-names =3D "ecam", "xal", "xtl", "xtl-pri", "xpl"; + <0x00 0x08450000 0x0 0x00010000>, + <0xb8 0xb0000000 0x0 0x10000000>; + reg-names =3D "xal", "xtl", "xtl-pri", "xpl", "ecam"; #address-cells =3D <3>; #size-cells =3D <2>; device_type =3D "pci"; @@ -3989,12 +3989,12 @@ pci@8440000 { =20 pci@8460000 { compatible =3D "nvidia,tegra264-pcie"; - reg =3D <0xc0 0xb0000000 0x0 0x10000000>, - <0x00 0x08460000 0x0 0x00004000>, + reg =3D <0x00 0x08460000 0x0 0x00004000>, <0x00 0x08464000 0x0 0x00001000>, <0x00 0x08465000 0x0 0x00001000>, - <0x00 0x08470000 0x0 0x00010000>; - reg-names =3D "ecam", "xal", "xtl", "xtl-pri", "xpl"; + <0x00 0x08470000 0x0 0x00010000>, + <0xc0 0xb0000000 0x0 0x10000000>; + reg-names =3D "xal", "xtl", "xtl-pri", "xpl", "ecam"; #address-cells =3D <3>; #size-cells =3D <2>; device_type =3D "pci"; @@ -4021,12 +4021,12 @@ pci@8460000 { =20 pci@8480000 { compatible =3D "nvidia,tegra264-pcie"; - reg =3D <0xc8 0xb0000000 0x0 0x10000000>, - <0x00 0x08480000 0x0 0x00004000>, + reg =3D <0x00 0x08480000 0x0 0x00004000>, <0x00 0x08484000 0x0 0x00001000>, <0x00 0x08485000 0x0 0x00001000>, - <0x00 0x08490000 0x0 0x00010000>; - reg-names =3D "ecam", "xal", "xtl", "xtl-pri", "xpl"; + <0x00 0x08490000 0x0 0x00010000>, + <0xc8 0xb0000000 0x0 0x10000000>; + reg-names =3D "xal", "xtl", "xtl-pri", "xpl", "ecam"; #address-cells =3D <3>; #size-cells =3D <2>; device_type =3D "pci"; --=20 2.54.0