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Tue, 16 Jun 2026 02:55:10 -0700 From: Akhil R To: Alexandre Belloni CC: Frank Li , Miquel Raynal , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Guenter Roeck , Philipp Zabel , Jon Hunter , Thierry Reding , , , , , , Akhil R Subject: [PATCH v4 01/12] dt-bindings: i3c: Add mipi-i3c-static-method to support SETAASA Date: Tue, 16 Jun 2026 09:54:15 +0000 Message-ID: <20260616095429.3947205-2-akhilrajeev@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260616095429.3947205-1-akhilrajeev@nvidia.com> References: <20260616095429.3947205-1-akhilrajeev@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF0002636A:EE_|DS0PR12MB7560:EE_ X-MS-Office365-Filtering-Correlation-Id: 2e29c2a0-ec4f-4752-9821-08decb8d6158 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700016|23010399003|7416014|376014|82310400026|18002099003|56012099006|11063799006|3023799007|22082099003|6133799003; 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charset="utf-8" Add the 'mipi-i3c-static-method' property mentioned in the MIPI I3C Discovery and Configuration Specification [1] to specify which discovery method an I3C device supports during bus initialization. The property is a bitmap, where a bit value of 1 indicates support for that method, and 0 indicates lack of support. Bit 0: SETDASA CCC (Direct) Bit 1: SETAASA CCC (Broadcast) Bit 2: Other CCC (vendor / standards extension) All other bits are reserved. It is specifically needed when an I3C device requires SETAASA for the address assignment. SETDASA will be supported by default if this property is absent, which means for now the property just serves as a flag to enable SETAASA, but keep the property as a bitmap to align with the specifications. [1] https://www.mipi.org/mipi-disco-for-i3c-download Signed-off-by: Akhil R --- .../devicetree/bindings/i3c/i3c.yaml | 36 ++++++++++++++++--- include/dt-bindings/i3c/i3c.h | 4 +++ 2 files changed, 35 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/i3c/i3c.yaml b/Documentation= /devicetree/bindings/i3c/i3c.yaml index e25fa72fd785..5603f2e7807d 100644 --- a/Documentation/devicetree/bindings/i3c/i3c.yaml +++ b/Documentation/devicetree/bindings/i3c/i3c.yaml @@ -31,10 +31,12 @@ properties: described in the device tree, which in turn means we have to describe I3C devices. =20 - Another use case for describing an I3C device in the device tree is = when - this I3C device has a static I2C address and we want to assign it a - specific I3C dynamic address before the DAA takes place (so that oth= er - devices on the bus can't take this dynamic address). + Other use-cases for describing an I3C device in the device tree are: + - When the I3C device has a static I2C address and we want to assign + it a specific I3C dynamic address before the DAA takes place (so + that other devices on the bus can't take this dynamic address). + - When the I3C device requires SETAASA for its discovery and uses a + pre-defined static address. =20 "#size-cells": const: 0 @@ -145,7 +147,31 @@ patternProperties: Dynamic address to be assigned to this device. In case static ad= dress is present (first cell of the reg property !=3D 0), this address is= assigned through SETDASA. If static address is not present, this address = is assigned - through SETNEWDA after assigning a temporary address via ENTDAA. + through SETNEWDA after assigning a temporary address via ENTDAA.= If + SETAASA is used, this property is not used, and the static addre= ss itself + becomes the dynamic address. + + mipi-i3c-static-method: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0x1 + maximum: 0x7 + default: 1 + description: | + Bitmap describing which methods of Dynamic Address Assignment fr= om a + static address are supported by this I3C Target. For each define= d bit + position, a set bit indicates support for that method and a clea= red + bit indicates lack of support. + + Bit 0: SETDASA CCC (Direct) + Bit 1: SETAASA CCC (Broadcast) + Bit 2: Other CCC (vendor / standards extension) + All other bits are reserved. + + This property follows the MIPI I3C specification. The primary use + of this property is to indicate support for SETAASA, i.e Bit 1, = but + will allow other values mentioned in the specification so that it + mirrors the specification. SETDASA will remain as the default me= thod + even if this property is not present. =20 required: - reg diff --git a/include/dt-bindings/i3c/i3c.h b/include/dt-bindings/i3c/i3c.h index 373439218bba..78b8c634aad8 100644 --- a/include/dt-bindings/i3c/i3c.h +++ b/include/dt-bindings/i3c/i3c.h @@ -13,4 +13,8 @@ #define I2C_NO_FILTER_HIGH_FREQUENCY (1 << 5) #define I2C_NO_FILTER_LOW_FREQUENCY (2 << 5) =20 +#define I3C_ADDR_METHOD_SETDASA (1 << 0) +#define I3C_ADDR_METHOD_SETAASA (1 << 1) +#define I3C_ADDR_METHOD_VENDOR (1 << 2) + #endif --=20 2.43.0 From nobody Wed Jun 17 06:04:21 2026 Received: from SA9PR02CU001.outbound.protection.outlook.com (mail-southcentralusazon11013037.outbound.protection.outlook.com [40.93.196.37]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A06363B5846; Tue, 16 Jun 2026 09:55:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.93.196.37 ARC-Seal: i=2; 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charset="utf-8" Replace all OF-specific functions with unified device property functions as a prerequisite to support both ACPI and device tree. Reviewed-by: Frank Li Signed-off-by: Akhil R --- drivers/i3c/master.c | 78 +++++++++++++++++++++----------------- include/linux/i3c/master.h | 5 ++- 2 files changed, 47 insertions(+), 36 deletions(-) diff --git a/drivers/i3c/master.c b/drivers/i3c/master.c index 109aa50eb1f8..3b19a5e8f46d 100644 --- a/drivers/i3c/master.c +++ b/drivers/i3c/master.c @@ -13,10 +13,12 @@ #include #include #include +#include #include #include #include #include +#include #include #include #include @@ -491,7 +493,7 @@ static void i3c_bus_cleanup(struct i3c_bus *i3cbus) mutex_unlock(&i3c_core_lock); } =20 -static int i3c_bus_init(struct i3c_bus *i3cbus, struct device_node *np) +static int i3c_bus_init(struct i3c_bus *i3cbus, struct fwnode_handle *fwno= de) { int ret, start, end, id =3D -1; =20 @@ -501,8 +503,8 @@ static int i3c_bus_init(struct i3c_bus *i3cbus, struct = device_node *np) i3c_bus_init_addrslots(i3cbus); i3cbus->mode =3D I3C_BUS_MODE_PURE; =20 - if (np) - id =3D of_alias_get_id(np, "i3c"); + if (fwnode && is_of_node(fwnode)) + id =3D of_alias_get_id(to_of_node(fwnode), "i3c"); =20 mutex_lock(&i3c_core_lock); if (id >=3D 0) { @@ -827,7 +829,7 @@ static void i3c_masterdev_release(struct device *dev) WARN_ON(!list_empty(&bus->devs.i2c) || !list_empty(&bus->devs.i3c)); i3c_bus_cleanup(bus); =20 - of_node_put(dev->of_node); + fwnode_handle_put(dev->fwnode); } =20 static const struct device_type i3c_masterdev_type =3D { @@ -1034,7 +1036,7 @@ static void i3c_device_release(struct device *dev) =20 WARN_ON(i3cdev->desc); =20 - of_node_put(i3cdev->dev.of_node); + fwnode_handle_put(dev->fwnode); kfree(i3cdev); } =20 @@ -1902,7 +1904,8 @@ i3c_master_register_new_i3c_devs(struct i3c_master_co= ntroller *master) desc->info.pid); =20 if (desc->boardinfo) - desc->dev->dev.of_node =3D desc->boardinfo->of_node; + device_set_node(&desc->dev->dev, + fwnode_handle_get(desc->boardinfo->fwnode)); =20 ret =3D device_register(&desc->dev->dev); if (ret) { @@ -2594,8 +2597,8 @@ EXPORT_SYMBOL_GPL(i3c_master_do_daa); #define OF_I3C_REG1_IS_I2C_DEV BIT(31) =20 static int -of_i3c_master_add_i2c_boardinfo(struct i3c_master_controller *master, - struct device_node *node, u32 *reg) +i3c_master_add_i2c_boardinfo(struct i3c_master_controller *master, + struct fwnode_handle *fwnode, u32 *reg) { struct i2c_dev_boardinfo *boardinfo; struct device *dev =3D &master->dev; @@ -2605,9 +2608,13 @@ of_i3c_master_add_i2c_boardinfo(struct i3c_master_co= ntroller *master, if (!boardinfo) return -ENOMEM; =20 - ret =3D of_i2c_get_board_info(dev, node, &boardinfo->base); - if (ret) - return ret; + if (is_of_node(fwnode)) { + ret =3D of_i2c_get_board_info(dev, to_of_node(fwnode), &boardinfo->base); + if (ret) + return ret; + } else { + return -EINVAL; + } =20 /* * The I3C Specification does not clearly say I2C devices with 10-bit @@ -2623,14 +2630,14 @@ of_i3c_master_add_i2c_boardinfo(struct i3c_master_c= ontroller *master, boardinfo->lvr =3D reg[2]; =20 list_add_tail(&boardinfo->node, &master->boardinfo.i2c); - of_node_get(node); + fwnode_handle_get(fwnode); =20 return 0; } =20 static int -of_i3c_master_add_i3c_boardinfo(struct i3c_master_controller *master, - struct device_node *node, u32 *reg) +i3c_master_add_i3c_boardinfo(struct i3c_master_controller *master, + struct fwnode_handle *fwnode, u32 *reg) { struct i3c_dev_boardinfo *boardinfo; struct device *dev =3D &master->dev; @@ -2653,7 +2660,7 @@ of_i3c_master_add_i3c_boardinfo(struct i3c_master_con= troller *master, =20 boardinfo->static_addr =3D reg[0]; =20 - if (!of_property_read_u32(node, "assigned-address", &init_dyn_addr)) { + if (!fwnode_property_read_u32(fwnode, "assigned-address", &init_dyn_addr)= ) { if (init_dyn_addr > I3C_MAX_ADDR) return -EINVAL; =20 @@ -2670,14 +2677,14 @@ of_i3c_master_add_i3c_boardinfo(struct i3c_master_c= ontroller *master, return -EINVAL; =20 boardinfo->init_dyn_addr =3D init_dyn_addr; - boardinfo->of_node =3D of_node_get(node); + boardinfo->fwnode =3D fwnode_handle_get(fwnode); list_add_tail(&boardinfo->node, &master->boardinfo.i3c); =20 return 0; } =20 -static int of_i3c_master_add_dev(struct i3c_master_controller *master, - struct device_node *node) +static int i3c_master_add_dev(struct i3c_master_controller *master, + struct fwnode_handle *fwnode) { u32 reg[3]; int ret; @@ -2685,7 +2692,7 @@ static int of_i3c_master_add_dev(struct i3c_master_co= ntroller *master, if (!master) return -EINVAL; =20 - ret =3D of_property_read_u32_array(node, "reg", reg, ARRAY_SIZE(reg)); + ret =3D fwnode_property_read_u32_array(fwnode, "reg", reg, ARRAY_SIZE(reg= )); if (ret) return ret; =20 @@ -2694,25 +2701,25 @@ static int of_i3c_master_add_dev(struct i3c_master_= controller *master, * dealing with an I2C device. */ if (!reg[1]) - ret =3D of_i3c_master_add_i2c_boardinfo(master, node, reg); + ret =3D i3c_master_add_i2c_boardinfo(master, fwnode, reg); else - ret =3D of_i3c_master_add_i3c_boardinfo(master, node, reg); + ret =3D i3c_master_add_i3c_boardinfo(master, fwnode, reg); =20 return ret; } =20 -static int of_populate_i3c_bus(struct i3c_master_controller *master) +static int fwnode_populate_i3c_bus(struct i3c_master_controller *master) { struct device *dev =3D &master->dev; - struct device_node *i3cbus_np =3D dev->of_node; + struct fwnode_handle *fwnode =3D dev_fwnode(dev); int ret; u32 val; =20 - if (!i3cbus_np) + if (!fwnode) return 0; =20 - for_each_available_child_of_node_scoped(i3cbus_np, node) { - ret =3D of_i3c_master_add_dev(master, node); + fwnode_for_each_available_child_node_scoped(fwnode, child) { + ret =3D i3c_master_add_dev(master, child); if (ret) return ret; } @@ -2722,10 +2729,10 @@ static int of_populate_i3c_bus(struct i3c_master_co= ntroller *master) * on the bus are not supporting typical rates, or if the bus topology * prevents it from using max possible rate. */ - if (!of_property_read_u32(i3cbus_np, "i2c-scl-hz", &val)) + if (!device_property_read_u32(dev, "i2c-scl-hz", &val)) master->bus.scl_rate.i2c =3D val; =20 - if (!of_property_read_u32(i3cbus_np, "i3c-scl-hz", &val)) + if (!device_property_read_u32(dev, "i3c-scl-hz", &val)) master->bus.scl_rate.i3c =3D val; =20 return 0; @@ -2780,7 +2787,7 @@ static u8 i3c_master_i2c_get_lvr(struct i2c_client *c= lient) u8 lvr =3D I3C_LVR_I2C_INDEX(2) | I3C_LVR_I2C_FM_MODE; u32 reg[3]; =20 - if (!of_property_read_u32_array(client->dev.of_node, "reg", reg, ARRAY_SI= ZE(reg))) + if (!fwnode_property_read_u32_array(client->dev.fwnode, "reg", reg, ARRAY= _SIZE(reg))) lvr =3D reg[2]; =20 return lvr; @@ -2899,7 +2906,8 @@ static int i3c_master_i2c_adapter_init(struct i3c_mas= ter_controller *master) struct i2c_adapter *adap =3D i3c_master_to_i2c_adapter(master); struct i2c_dev_desc *i2cdev; struct i2c_dev_boardinfo *i2cboardinfo; - int ret, id; + struct fwnode_handle *fwnode =3D dev_fwnode(&master->dev); + int ret, id =3D -1; =20 adap->dev.parent =3D master->dev.parent; adap->owner =3D master->dev.parent->driver->owner; @@ -2908,7 +2916,9 @@ static int i3c_master_i2c_adapter_init(struct i3c_mas= ter_controller *master) adap->timeout =3D HZ; adap->retries =3D 3; =20 - id =3D of_alias_get_id(master->dev.of_node, "i2c"); + if (fwnode && is_of_node(fwnode)) + id =3D of_alias_get_id(to_of_node(fwnode), "i2c"); + if (id >=3D 0) { adap->nr =3D id; ret =3D i2c_add_numbered_adapter(adap); @@ -3209,7 +3219,7 @@ int i3c_master_register(struct i3c_master_controller = *master, return ret; =20 master->dev.parent =3D parent; - master->dev.of_node =3D of_node_get(parent->of_node); + device_set_node(&master->dev, fwnode_handle_get(dev_fwnode(parent))); master->dev.bus =3D &i3c_bus_type; master->dev.type =3D &i3c_masterdev_type; master->dev.release =3D i3c_masterdev_release; @@ -3228,13 +3238,13 @@ int i3c_master_register(struct i3c_master_controlle= r *master, master->dev.coherent_dma_mask =3D parent->coherent_dma_mask; master->dev.dma_parms =3D parent->dma_parms; =20 - ret =3D i3c_bus_init(i3cbus, master->dev.of_node); + ret =3D i3c_bus_init(i3cbus, dev_fwnode(&master->dev)); if (ret) goto err_put_dev; =20 dev_set_name(&master->dev, "i3c-%d", i3cbus->id); =20 - ret =3D of_populate_i3c_bus(master); + ret =3D fwnode_populate_i3c_bus(master); if (ret) goto err_put_dev; =20 diff --git a/include/linux/i3c/master.h b/include/linux/i3c/master.h index f73cede87d36..22b10cff476c 100644 --- a/include/linux/i3c/master.h +++ b/include/linux/i3c/master.h @@ -177,7 +177,8 @@ struct i3c_device_ibi_info { * @pid: I3C Provisioned ID exposed by the device. This is a unique identi= fier * that may be used to attach boardinfo to i3c_dev_desc when the device * does not have a static address - * @of_node: optional DT node in case the device has been described in the= DT + * @fwnode: Firmware node (DT or ACPI) in case the device has been + * described in firmware * * This structure is used to attach board-level information to an I3C devi= ce. * Not all I3C devices connected on the bus will have a boardinfo. It's on= ly @@ -189,7 +190,7 @@ struct i3c_dev_boardinfo { u8 init_dyn_addr; u8 static_addr; u64 pid; - struct device_node *of_node; + struct fwnode_handle *fwnode; }; =20 /** --=20 2.43.0 From nobody Wed Jun 17 06:04:21 2026 Received: from BYAPR05CU005.outbound.protection.outlook.com (mail-westusazon11010021.outbound.protection.outlook.com [52.101.85.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7E406423A79; Tue, 16 Jun 2026 09:55:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.85.21 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781603750; cv=fail; b=Gptqp3Va0UQRN13J1vFt7eXu4fAR3H9ksO13pwry2f1rYzUn0gcff1unks57vvipe610UR17k95ho/1AhDdhozKZQAVjdfiP2xuzh2J/iN/5qJOr1039afch+0u2meAFMGrgiUxJXYOO7v4KWnSamkEKN5ncruHX0YCXT5d2G/s= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; 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charset="utf-8" Although the existing subsystem allows host controllers to register through the ACPI table, it was not possible to describe I3C or I2C devices when using ACPI. This is because the driver relied on the reg property to retrieve the PID, static address, etc., whereas ACPI uses _ADR or serial resources to describe such devices. Read _ADR and LVR from ACPI resources and extract the data as per the ACPI specification for an I3C bus. Also read mipi-i3c-static-address as per the MIPI DISCO specifications [1] to get the static address to be used. Enable describing I3C or I2C devices in the ACPI table. This is required if the device uses a static address or if it needs device-specific properties. [1] https://www.mipi.org/mipi-disco-for-i3c-download Signed-off-by: Akhil R --- drivers/i3c/master.c | 149 ++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 141 insertions(+), 8 deletions(-) diff --git a/drivers/i3c/master.c b/drivers/i3c/master.c index 3b19a5e8f46d..f0e05bcac26d 100644 --- a/drivers/i3c/master.c +++ b/drivers/i3c/master.c @@ -5,6 +5,7 @@ * Author: Boris Brezillon */ =20 +#include #include #include #include @@ -2596,6 +2597,55 @@ EXPORT_SYMBOL_GPL(i3c_master_do_daa); =20 #define OF_I3C_REG1_IS_I2C_DEV BIT(31) =20 +#ifdef CONFIG_ACPI +static int i3c_acpi_get_i2c_resource(struct acpi_resource *ares, void *dat= a) +{ + struct i2c_dev_boardinfo *boardinfo =3D data; + struct acpi_resource_i2c_serialbus *sb; + + if (boardinfo->base.addr || !i2c_acpi_get_i2c_resource(ares, &sb)) + return 1; + + boardinfo->base.addr =3D sb->slave_address; + if (sb->access_mode =3D=3D ACPI_I2C_10BIT_MODE) + boardinfo->base.flags |=3D I2C_CLIENT_TEN; + + boardinfo->lvr =3D sb->lvr; + + return 1; +} + +static int i3c_acpi_add_i2c_boardinfo(struct i2c_dev_boardinfo *boardinfo, + struct fwnode_handle *fwnode) +{ + struct acpi_device *adev =3D to_acpi_device_node(fwnode); + LIST_HEAD(resources); + int ret; + + boardinfo->base.fwnode =3D acpi_fwnode_handle(adev); + acpi_set_modalias(adev, dev_name(&adev->dev), boardinfo->base.type, + sizeof(boardinfo->base.type)); + + ret =3D acpi_dev_get_resources(adev, &resources, + i3c_acpi_get_i2c_resource, boardinfo); + if (ret < 0) + return ret; + + acpi_dev_free_resource_list(&resources); + + if (!boardinfo->base.addr) + return -ENODEV; + + return 0; +} +#else +static inline int i3c_acpi_add_i2c_boardinfo(struct i2c_dev_boardinfo *boa= rdinfo, + struct fwnode_handle *fwnode) +{ + return -ENODEV; +} +#endif + static int i3c_master_add_i2c_boardinfo(struct i3c_master_controller *master, struct fwnode_handle *fwnode, u32 *reg) @@ -2612,6 +2662,13 @@ i3c_master_add_i2c_boardinfo(struct i3c_master_contr= oller *master, ret =3D of_i2c_get_board_info(dev, to_of_node(fwnode), &boardinfo->base); if (ret) return ret; + + /* LVR is encoded in reg[2] for Device Tree. */ + boardinfo->lvr =3D reg[2]; + } else if (is_acpi_device_node(fwnode)) { + ret =3D i3c_acpi_add_i2c_boardinfo(boardinfo, fwnode); + if (ret) + return ret; } else { return -EINVAL; } @@ -2626,9 +2683,6 @@ i3c_master_add_i2c_boardinfo(struct i3c_master_contro= ller *master, return -EOPNOTSUPP; } =20 - /* LVR is encoded in reg[2]. */ - boardinfo->lvr =3D reg[2]; - list_add_tail(&boardinfo->node, &master->boardinfo.i2c); fwnode_handle_get(fwnode); =20 @@ -2683,8 +2737,8 @@ i3c_master_add_i3c_boardinfo(struct i3c_master_contro= ller *master, return 0; } =20 -static int i3c_master_add_dev(struct i3c_master_controller *master, - struct fwnode_handle *fwnode) +static int i3c_master_add_of_dev(struct i3c_master_controller *master, + struct fwnode_handle *fwnode) { u32 reg[3]; int ret; @@ -2708,6 +2762,74 @@ static int i3c_master_add_dev(struct i3c_master_cont= roller *master, return ret; } =20 +#ifdef CONFIG_ACPI +static int i3c_master_add_acpi_dev(struct i3c_master_controller *master, + struct fwnode_handle *fwnode) +{ + struct acpi_device *adev =3D to_acpi_device_node(fwnode); + acpi_bus_address adr; + u32 reg[3] =3D { 0 }; + int ret; + + /* + * If the ACPI table entry has _ADR method, it's an I3C device. + * Otherwise it may be an I2C device described by an I2cSerialBus + * resource. If no I2cSerialBus resource is found, ignore the entry. + */ + if (!acpi_has_method(adev->handle, "_ADR")) { + ret =3D i3c_master_add_i2c_boardinfo(master, fwnode, reg); + if (ret =3D=3D -ENODEV) + return 0; + + return ret; + } + + adr =3D acpi_device_adr(adev); + + /* For I3C devices, _ADR will have the 48 bit PID of the device */ + reg[1] =3D upper_32_bits(adr); + reg[2] =3D lower_32_bits(adr); + + fwnode_property_read_u32(fwnode, "mipi-i3c-static-address", ®[0]); + + return i3c_master_add_i3c_boardinfo(master, fwnode, reg); +} + +static u8 i3c_acpi_i2c_get_lvr(struct i2c_client *client) +{ + struct acpi_device *adev =3D to_acpi_device_node(client->dev.fwnode); + struct i2c_dev_boardinfo boardinfo =3D {}; + LIST_HEAD(resources); + int ret; + u8 lvr; + + lvr =3D I3C_LVR_I2C_INDEX(2) | I3C_LVR_I2C_FM_MODE; + + ret =3D acpi_dev_get_resources(adev, &resources, + i3c_acpi_get_i2c_resource, &boardinfo); + if (ret < 0) + return lvr; + + if (boardinfo.base.addr) + lvr =3D boardinfo.lvr; + + acpi_dev_free_resource_list(&resources); + + return lvr; +} +#else +static inline int i3c_master_add_acpi_dev(struct i3c_master_controller *ma= ster, + struct fwnode_handle *fwnode) +{ + return -ENODEV; +} + +static inline u8 i3c_acpi_i2c_get_lvr(struct i2c_client *client) +{ + return I3C_LVR_I2C_INDEX(2) | I3C_LVR_I2C_FM_MODE; +} +#endif + static int fwnode_populate_i3c_bus(struct i3c_master_controller *master) { struct device *dev =3D &master->dev; @@ -2719,7 +2841,13 @@ static int fwnode_populate_i3c_bus(struct i3c_master= _controller *master) return 0; =20 fwnode_for_each_available_child_node_scoped(fwnode, child) { - ret =3D i3c_master_add_dev(master, child); + if (is_of_node(child)) + ret =3D i3c_master_add_of_dev(master, child); + else if (is_acpi_device_node(child)) + ret =3D i3c_master_add_acpi_dev(master, child); + else + continue; + if (ret) return ret; } @@ -2787,8 +2915,13 @@ static u8 i3c_master_i2c_get_lvr(struct i2c_client *= client) u8 lvr =3D I3C_LVR_I2C_INDEX(2) | I3C_LVR_I2C_FM_MODE; u32 reg[3]; =20 - if (!fwnode_property_read_u32_array(client->dev.fwnode, "reg", reg, ARRAY= _SIZE(reg))) - lvr =3D reg[2]; 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charset="utf-8" Add support for devices using SETAASA, such as SPD5118 and SPD5108 attached to DDR5 memory modules that do not support ENTDAA. Follow the guidelines proposed by the MIPI Discovery and Configuration Specification [1] for discovering such devices. SETAASA (Set All Addresses to Static Address) differs from standard I3C address assignment that uses ENTDAA or SETDASA to assign dynamic addresses. Devices using SETAASA assign their pre-defined static addresses as their dynamic addresses during DAA, and it is not mandatory for these devices to implement standard CCC commands like GETPID, GETDCR, or GETBCR. For such devices, it is generally recommended to issue SETHID (specified by JEDEC JESD300) as a prerequisite for SETAASA to stop HID bit flipping. [1] https://www.mipi.org/mipi-disco-for-i3c-download Signed-off-by: Akhil R --- drivers/i3c/master.c | 83 +++++++++++++++++++++++++++++++++++++- include/linux/i3c/ccc.h | 1 + include/linux/i3c/master.h | 15 +++++++ 3 files changed, 97 insertions(+), 2 deletions(-) diff --git a/drivers/i3c/master.c b/drivers/i3c/master.c index f0e05bcac26d..557332d93257 100644 --- a/drivers/i3c/master.c +++ b/drivers/i3c/master.c @@ -5,6 +5,7 @@ * Author: Boris Brezillon */ =20 +#include #include #include #include @@ -1092,6 +1093,51 @@ static int i3c_master_rstdaa_locked(struct i3c_maste= r_controller *master, return ret; } =20 +/** + * i3c_master_setaasa_locked() - start a SETAASA procedure (Set All Addres= ses to Static Address) + * @master: I3C master object + * + * Send a SETAASA CCC command to set all attached I3C devices' dynamic add= resses to + * their static address. + * + * This function must be called with the bus lock held in write mode. + * + * First, the SETHID CCC command is sent, followed by the SETAASA CCC. + * + * Return: 0 in case of success, a positive I3C error code if the error is + * one of the official Mx error codes, and a negative error code otherwise. + */ +static int i3c_master_setaasa_locked(struct i3c_master_controller *master) +{ + struct i3c_ccc_cmd_dest dest; + struct i3c_ccc_cmd cmd; + int ret; + + /* + * Send SETHID CCC command. Though it is a standard CCC command specified + * in JESD300-5, we are not defining a separate macro to be explicit that + * the value falls under the vendor specific range. + */ + i3c_ccc_cmd_dest_init(&dest, I3C_BROADCAST_ADDR, 0); + i3c_ccc_cmd_init(&cmd, false, I3C_CCC_VENDOR(0, true), &dest, 1); + ret =3D i3c_master_send_ccc_cmd_locked(master, &cmd); + i3c_ccc_cmd_dest_cleanup(&dest); + if (ret && cmd.err =3D=3D I3C_ERROR_M2) + ret =3D 0; + if (ret) + return ret; + + /* Send SETAASA CCC command */ + i3c_ccc_cmd_dest_init(&dest, I3C_BROADCAST_ADDR, 0); + i3c_ccc_cmd_init(&cmd, false, I3C_CCC_SETAASA, &dest, 1); + ret =3D i3c_master_send_ccc_cmd_locked(master, &cmd); + i3c_ccc_cmd_dest_cleanup(&dest); + if (ret && cmd.err =3D=3D I3C_ERROR_M2) + ret =3D 0; + + return ret; +} + /** * i3c_master_entdaa_locked() - start a DAA (Dynamic Address Assignment) * procedure @@ -1852,6 +1898,22 @@ static int i3c_master_early_i3c_dev_add(struct i3c_m= aster_controller *master, if (ret) goto err_free_dev; =20 + /* + * For devices using SETAASA instead of ENTDAA, the address is statically + * assigned. Update the dynamic address to the provided static address. + * Reattach the I3C device after updating the dynamic address with the sa= me + * static address. It is not mandatory for such devices to implement CCC + * commands like GETPID, GETDCR etc. Hence, we can return after reattachi= ng. + */ + if (i3cdev->boardinfo->static_addr_method & I3C_ADDR_METHOD_SETAASA) { + i3cdev->info.dyn_addr =3D i3cdev->boardinfo->static_addr; + ret =3D i3c_master_reattach_i3c_dev(i3cdev, 0); + if (ret) + goto err_detach_dev; + + return 0; + } + ret =3D i3c_master_setdasa_locked(master, i3cdev->info.static_addr, i3cdev->boardinfo->init_dyn_addr); if (ret) @@ -2206,6 +2268,12 @@ static int i3c_master_bus_init(struct i3c_master_con= troller *master) if (ret) goto err_bus_cleanup; =20 + if (master->addr_method & I3C_ADDR_METHOD_SETAASA) { + ret =3D i3c_master_setaasa_locked(master); + if (ret) + goto err_bus_cleanup; + } + /* * Reserve init_dyn_addr first, and then try to pre-assign dynamic * address and retrieve device information if needed. @@ -2696,7 +2764,7 @@ i3c_master_add_i3c_boardinfo(struct i3c_master_contro= ller *master, struct i3c_dev_boardinfo *boardinfo; struct device *dev =3D &master->dev; enum i3c_addr_slot_status addrstatus; - u32 init_dyn_addr =3D 0; + u32 init_dyn_addr =3D 0, static_addr_method =3D 0; =20 boardinfo =3D devm_kzalloc(dev, sizeof(*boardinfo), GFP_KERNEL); if (!boardinfo) @@ -2714,7 +2782,14 @@ i3c_master_add_i3c_boardinfo(struct i3c_master_contr= oller *master, =20 boardinfo->static_addr =3D reg[0]; =20 - if (!fwnode_property_read_u32(fwnode, "assigned-address", &init_dyn_addr)= ) { + if (!fwnode_property_read_u32(fwnode, "mipi-i3c-static-method", &static_a= ddr_method)) + boardinfo->static_addr_method =3D static_addr_method & + (I3C_ADDR_METHOD_SETDASA | I3C_ADDR_METHOD_SETAASA); + + if (boardinfo->static_addr_method & I3C_ADDR_METHOD_SETAASA) { + /* For SETAASA, static address is taken as the dynamic address. */ + init_dyn_addr =3D boardinfo->static_addr; + } else if (!fwnode_property_read_u32(fwnode, "assigned-address", &init_dy= n_addr)) { if (init_dyn_addr > I3C_MAX_ADDR) return -EINVAL; =20 @@ -2724,6 +2799,9 @@ i3c_master_add_i3c_boardinfo(struct i3c_master_contro= ller *master, return -EINVAL; } =20 + /* Update the address methods required for device discovery */ + master->addr_method |=3D boardinfo->static_addr_method; + boardinfo->pid =3D ((u64)reg[1] << 32) | reg[2]; =20 if ((boardinfo->pid & GENMASK_ULL(63, 48)) || @@ -3358,6 +3436,7 @@ int i3c_master_register(struct i3c_master_controller = *master, master->dev.release =3D i3c_masterdev_release; master->ops =3D ops; master->secondary =3D secondary; + master->addr_method =3D I3C_ADDR_METHOD_SETDASA; INIT_LIST_HEAD(&master->boardinfo.i2c); INIT_LIST_HEAD(&master->boardinfo.i3c); =20 diff --git a/include/linux/i3c/ccc.h b/include/linux/i3c/ccc.h index ad59a4ae60d1..a145d766ab6f 100644 --- a/include/linux/i3c/ccc.h +++ b/include/linux/i3c/ccc.h @@ -32,6 +32,7 @@ #define I3C_CCC_DEFSLVS I3C_CCC_ID(0x8, true) #define I3C_CCC_ENTTM I3C_CCC_ID(0xb, true) #define I3C_CCC_ENTHDR(x) I3C_CCC_ID(0x20 + (x), true) +#define I3C_CCC_SETAASA I3C_CCC_ID(0x29, true) =20 /* Unicast-only commands */ #define I3C_CCC_SETDASA I3C_CCC_ID(0x7, false) diff --git a/include/linux/i3c/master.h b/include/linux/i3c/master.h index 22b10cff476c..9323b6af051c 100644 --- a/include/linux/i3c/master.h +++ b/include/linux/i3c/master.h @@ -174,6 +174,14 @@ struct i3c_device_ibi_info { * assigned a dynamic address by the master. Will be used during * bus initialization to assign it a specific dynamic address * before starting DAA (Dynamic Address Assignment) + * @static_addr_method: Bitmap describing which methods of Dynamic Address + * Assignment from a Static Address are supported by this I3C Target. + * A value of 1 in a bit position indicates that the I3C target + * supports that method, and a value of 0 indicates that the I3C + * target does not support that method. + * Bit 0: SETDASA + * Bit 1: SETAASA + * All other bits are reserved. * @pid: I3C Provisioned ID exposed by the device. This is a unique identi= fier * that may be used to attach boardinfo to i3c_dev_desc when the device * does not have a static address @@ -189,6 +197,7 @@ struct i3c_dev_boardinfo { struct list_head node; u8 init_dyn_addr; u8 static_addr; + u8 static_addr_method; u64 pid; struct fwnode_handle *fwnode; }; @@ -517,6 +526,11 @@ struct i3c_master_controller_ops { * @boardinfo.i2c: list of I2C boardinfo objects * @boardinfo: board-level information attached to devices connected on th= e bus * @bus: I3C bus exposed by this master + * @addr_method: Bitmap describing which methods of Address Assignment req= uired + * to be run for discovering all the devices on the bus. + * Bit 0: SETDASA + * Bit 1: SETAASA + * All other bits are reserved. * @wq: freezable workqueue which can be used by master * drivers if they need to postpone operations that need to take place * in a thread context. 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charset="utf-8" Devices using SETAASA for address assignment are not required to have a 48-bit PID according to the I3C specification. Allow such devices to register and use the static address where PID was required. Reviewed-by: Frank Li Signed-off-by: Akhil R --- drivers/i3c/master.c | 51 ++++++++++++++++++++++++++++++++++---------- 1 file changed, 40 insertions(+), 11 deletions(-) diff --git a/drivers/i3c/master.c b/drivers/i3c/master.c index 557332d93257..bcc9c2d29c34 100644 --- a/drivers/i3c/master.c +++ b/drivers/i3c/master.c @@ -1963,8 +1963,17 @@ i3c_master_register_new_i3c_devs(struct i3c_master_c= ontroller *master) desc->dev->dev.type =3D &i3c_device_type; desc->dev->dev.bus =3D &i3c_bus_type; desc->dev->dev.release =3D i3c_device_release; - dev_set_name(&desc->dev->dev, "%d-%llx", master->bus.id, - desc->info.pid); + + /* + * For devices without PID (e.g., SETAASA devices), use + * static address for naming instead. + */ + if (desc->info.pid) + dev_set_name(&desc->dev->dev, "%d-%llx", master->bus.id, + desc->info.pid); + else + dev_set_name(&desc->dev->dev, "%d-%02x", master->bus.id, + desc->info.static_addr); =20 if (desc->boardinfo) device_set_node(&desc->dev->dev, @@ -2357,8 +2366,18 @@ static void i3c_master_attach_boardinfo(struct i3c_d= ev_desc *i3cdev) struct i3c_dev_boardinfo *i3cboardinfo; =20 list_for_each_entry(i3cboardinfo, &master->boardinfo.i3c, node) { - if (i3cdev->info.pid !=3D i3cboardinfo->pid) - continue; + /* + * For devices without PID (e.g., SETAASA devices), match by + * static address. For devices with PID, match by PID. + */ + if (i3cboardinfo->pid) { + if (i3cdev->info.pid !=3D i3cboardinfo->pid) + continue; + } else { + if (!i3cboardinfo->static_addr || + i3cdev->info.static_addr !=3D i3cboardinfo->static_addr) + continue; + } =20 i3cdev->boardinfo =3D i3cboardinfo; i3cdev->info.static_addr =3D i3cboardinfo->static_addr; @@ -2372,8 +2391,12 @@ i3c_master_search_i3c_dev_duplicate(struct i3c_dev_d= esc *refdev) struct i3c_master_controller *master =3D i3c_dev_get_master(refdev); struct i3c_dev_desc *i3cdev; =20 + if (!refdev->info.pid) + return NULL; + i3c_bus_for_each_i3cdev(&master->bus, i3cdev) { - if (i3cdev !=3D refdev && i3cdev->info.pid =3D=3D refdev->info.pid) + if (i3cdev !=3D refdev && i3cdev->info.pid && + i3cdev->info.pid =3D=3D refdev->info.pid) return i3cdev; } =20 @@ -2804,9 +2827,15 @@ i3c_master_add_i3c_boardinfo(struct i3c_master_contr= oller *master, =20 boardinfo->pid =3D ((u64)reg[1] << 32) | reg[2]; =20 - if ((boardinfo->pid & GENMASK_ULL(63, 48)) || - I3C_PID_RND_LOWER_32BITS(boardinfo->pid)) - return -EINVAL; + /* For SETAASA devices, validate the static address instead of PID */ + if (boardinfo->static_addr_method & I3C_ADDR_METHOD_SETAASA) { + if (!boardinfo->static_addr) + return -EINVAL; + } else { + if ((boardinfo->pid & GENMASK_ULL(63, 48)) || + I3C_PID_RND_LOWER_32BITS(boardinfo->pid)) + return -EINVAL; + } =20 boardinfo->init_dyn_addr =3D init_dyn_addr; boardinfo->fwnode =3D fwnode_handle_get(fwnode); @@ -2829,10 +2858,10 @@ static int i3c_master_add_of_dev(struct i3c_master_= controller *master, return ret; =20 /* - * The manufacturer ID can't be 0. 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charset="utf-8" SETAASA-based devices cannot always be identified by PID or DCR; the standard I3C id_table matching may not be applicable. Allow such devices to be matched through Device Tree or ACPI. Reviewed-by: Frank Li Signed-off-by: Akhil R --- drivers/i3c/master.c | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/drivers/i3c/master.c b/drivers/i3c/master.c index bcc9c2d29c34..1bd545447b81 100644 --- a/drivers/i3c/master.c +++ b/drivers/i3c/master.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -345,15 +346,32 @@ static int i3c_device_match(struct device *dev, const= struct device_driver *drv) { struct i3c_device *i3cdev; const struct i3c_driver *i3cdrv; + u8 static_addr_method =3D 0; =20 if (dev->type !=3D &i3c_device_type) return 0; =20 i3cdev =3D dev_to_i3cdev(dev); i3cdrv =3D drv_to_i3cdrv(drv); - if (i3c_device_match_id(i3cdev, i3cdrv->id_table)) + + if (i3cdev->desc && i3cdev->desc->boardinfo) + static_addr_method =3D i3cdev->desc->boardinfo->static_addr_method; + + /* + * SETAASA-based devices need not always have a matching ID since + * it is not mandatory for such devices to implement deviceinfo + * CCC commands. Allow them to register through DT or ACPI. + */ + if (i3cdrv->id_table && i3c_device_match_id(i3cdev, i3cdrv->id_table)) return 1; =20 + if (static_addr_method & I3C_ADDR_METHOD_SETAASA) { + if (of_driver_match_device(dev, drv)) + return 1; + if (acpi_driver_match_device(dev, drv)) + return 1; + } + return 0; } =20 --=20 2.43.0 From nobody Wed Jun 17 06:04:21 2026 Received: from DM1PR04CU001.outbound.protection.outlook.com (mail-centralusazon11010058.outbound.protection.outlook.com [52.101.61.58]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7C546423A78; Tue, 16 Jun 2026 09:56:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.61.58 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781603802; cv=fail; b=M5ARL1Wgxv9k+UVc9Q8qZcXeN8IgCTwjKB5mj9dfhRNgy7vLYS1L8CrLo/CnbCSqa8ggc9rt4uOZI/PSuUomEVvthPFqxs+me296Wby8bODF4eB7pKIYhlC+Iv0Z0w/oAXVmdlenPWhQZbYEsojUKF3+rnx47nIBHno/BAN0pCA= ARC-Message-Signature: i=2; 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charset="utf-8" Add SETAASA and SETHID to the supported list of CCC commands for DesignWare I3C host controller. SETAASA is a broadcast command that assigns predefined static addresses to all I3C devices on the bus. SETHID is to stop HID bit flipping by the SPD Hub to which the SPD devices are connected. It is a prerequisite command to be sent before SETAASA as recommended by JESD300-5 and JESD403 sideband bus specifications. Signed-off-by: Akhil R --- drivers/i3c/master/dw-i3c-master.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/i3c/master/dw-i3c-master.c b/drivers/i3c/master/dw-i3c= -master.c index 971b429b76bc..3e510fddf06c 100644 --- a/drivers/i3c/master/dw-i3c-master.c +++ b/drivers/i3c/master/dw-i3c-master.c @@ -309,6 +309,8 @@ static bool dw_i3c_master_supports_ccc_cmd(struct i3c_m= aster_controller *m, case I3C_CCC_GETSTATUS: case I3C_CCC_GETMXDS: case I3C_CCC_GETHDRCAP: + case I3C_CCC_SETAASA: + case I3C_CCC_VENDOR(0, true): /* SETHID */ return true; default: return false; --=20 2.43.0 From nobody Wed Jun 17 06:04:21 2026 Received: from CH5PR02CU005.outbound.protection.outlook.com (mail-northcentralusazon11012016.outbound.protection.outlook.com [40.107.200.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 63BE8423A7B; Tue, 16 Jun 2026 09:56:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" Some ACPI-enumerated devices like Tegra410 do not have clock and reset resources exposed via the clk/reset frameworks. Unlike device tree, ACPI on Arm does not model such provider functions. The hardware is expected to be brought out of reset and have its clocks enabled by the firmware before the OS takes over. Any data to be shared with the OS is passed using the _DSD property. Add match data for such devices to skip acquiring clock and reset controls during probe and read the clock rate from the "clock-frequency" _DSD property. Note that the "clock-frequency" here is the controller's core clock and not the bus speed. I3C specifies the bus speed separately using "i3c-scl-hz" and "i2c-scl-hz" and hence this should not cause any conflict. Also, move match data parsing before clock/reset acquisition so the quirk is available early enough. Signed-off-by: Akhil R --- drivers/i3c/master/dw-i3c-master.c | 66 ++++++++++++++++++++---------- 1 file changed, 44 insertions(+), 22 deletions(-) diff --git a/drivers/i3c/master/dw-i3c-master.c b/drivers/i3c/master/dw-i3c= -master.c index 3e510fddf06c..a2a4b88c2017 100644 --- a/drivers/i3c/master/dw-i3c-master.c +++ b/drivers/i3c/master/dw-i3c-master.c @@ -242,6 +242,7 @@ /* List of quirks */ #define AMD_I3C_OD_PP_TIMING BIT(1) #define DW_I3C_DISABLE_RUNTIME_PM_QUIRK BIT(2) +#define DW_I3C_ACPI_SKIP_CLK_RST BIT(3) =20 struct dw_i3c_cmd { u32 cmd_lo; @@ -556,13 +557,28 @@ static void dw_i3c_master_set_intr_regs(struct dw_i3c= _master *master) writel(IBI_REQ_REJECT_ALL, master->regs + IBI_MR_REQ_REJECT); } =20 +static unsigned long dw_i3c_master_get_core_rate(struct dw_i3c_master *mas= ter) +{ + unsigned int core_rate_prop; + + if (!(master->quirks & DW_I3C_ACPI_SKIP_CLK_RST)) + return clk_get_rate(master->core_clk); + + if (device_property_read_u32(master->dev, "clock-frequency", &core_rate_p= rop)) { + dev_err(master->dev, "missing clock-frequency property\n"); + return 0; + } + + return core_rate_prop; +} + static int dw_i3c_clk_cfg(struct dw_i3c_master *master) { unsigned long core_rate, core_period; u32 scl_timing; u8 hcnt, lcnt; =20 - core_rate =3D clk_get_rate(master->core_clk); + core_rate =3D dw_i3c_master_get_core_rate(master); if (!core_rate) return -EINVAL; =20 @@ -615,7 +631,7 @@ static int dw_i2c_clk_cfg(struct dw_i3c_master *master) u16 hcnt, lcnt; u32 scl_timing; =20 - core_rate =3D clk_get_rate(master->core_clk); + core_rate =3D dw_i3c_master_get_core_rate(master); if (!core_rate) return -EINVAL; =20 @@ -1577,18 +1593,33 @@ int dw_i3c_common_probe(struct dw_i3c_master *maste= r, if (IS_ERR(master->regs)) return PTR_ERR(master->regs); =20 - master->core_clk =3D devm_clk_get_enabled(&pdev->dev, NULL); - if (IS_ERR(master->core_clk)) - return PTR_ERR(master->core_clk); - - master->pclk =3D devm_clk_get_optional_enabled(&pdev->dev, "pclk"); - if (IS_ERR(master->pclk)) - return PTR_ERR(master->pclk); + if (has_acpi_companion(&pdev->dev)) { + quirks =3D (unsigned long)device_get_match_data(&pdev->dev); + } else if (pdev->dev.of_node) { + drvdata =3D device_get_match_data(&pdev->dev); + if (drvdata) + quirks =3D drvdata->flags; + } + master->quirks =3D quirks; =20 - master->core_rst =3D devm_reset_control_get_optional_exclusive_deasserted= (&pdev->dev, - "core_rst"); - if (IS_ERR(master->core_rst)) - return PTR_ERR(master->core_rst); + if (master->quirks & DW_I3C_ACPI_SKIP_CLK_RST) { + master->core_clk =3D NULL; + master->pclk =3D NULL; + master->core_rst =3D NULL; + } else { + master->core_clk =3D devm_clk_get_enabled(&pdev->dev, NULL); + if (IS_ERR(master->core_clk)) + return PTR_ERR(master->core_clk); + + master->pclk =3D devm_clk_get_optional_enabled(&pdev->dev, "pclk"); + if (IS_ERR(master->pclk)) + return PTR_ERR(master->pclk); + + master->core_rst =3D devm_reset_control_get_optional_exclusive_deasserte= d(&pdev->dev, + "core_rst"); + if (IS_ERR(master->core_rst)) + return PTR_ERR(master->core_rst); + } =20 spin_lock_init(&master->xferqueue.lock); INIT_LIST_HEAD(&master->xferqueue.list); @@ -1636,15 +1667,6 @@ int dw_i3c_common_probe(struct dw_i3c_master *master, master->has_ibi_data =3D true; writel(thld_ctrl, master->regs + QUEUE_THLD_CTRL); =20 - if (has_acpi_companion(&pdev->dev)) { - quirks =3D (unsigned long)device_get_match_data(&pdev->dev); - } else if (pdev->dev.of_node) { - drvdata =3D device_get_match_data(&pdev->dev); - if (drvdata) - quirks =3D drvdata->flags; - } - master->quirks =3D quirks; - /* Keep controller enabled by preventing runtime suspend */ if (master->quirks & DW_I3C_DISABLE_RUNTIME_PM_QUIRK) pm_runtime_get_noresume(&pdev->dev); --=20 2.43.0 From nobody Wed Jun 17 06:04:21 2026 Received: from DM1PR04CU001.outbound.protection.outlook.com (mail-centralusazon11010055.outbound.protection.outlook.com [52.101.61.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 10CA5423A9B; Tue, 16 Jun 2026 09:57:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" Update variable names to generic names and add Tegra410 ACPI ID to support the I3C controller in Tegra410, which is a DesignWare I3C host controller. Reviewed-by: Frank Li Signed-off-by: Akhil R --- drivers/i3c/master/dw-i3c-master.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/i3c/master/dw-i3c-master.c b/drivers/i3c/master/dw-i3c= -master.c index a2a4b88c2017..fbe8dca22f07 100644 --- a/drivers/i3c/master/dw-i3c-master.c +++ b/drivers/i3c/master/dw-i3c-master.c @@ -1856,11 +1856,12 @@ static const struct of_device_id dw_i3c_master_of_m= atch[] =3D { }; MODULE_DEVICE_TABLE(of, dw_i3c_master_of_match); =20 -static const struct acpi_device_id amd_i3c_device_match[] =3D { +static const struct acpi_device_id dw_i3c_master_acpi_match[] =3D { { "AMDI0015", AMD_I3C_OD_PP_TIMING }, + { "NVDA2018", DW_I3C_ACPI_SKIP_CLK_RST }, { } }; -MODULE_DEVICE_TABLE(acpi, amd_i3c_device_match); +MODULE_DEVICE_TABLE(acpi, dw_i3c_master_acpi_match); =20 static struct platform_driver dw_i3c_driver =3D { .probe =3D dw_i3c_probe, @@ -1869,7 +1870,7 @@ static struct platform_driver dw_i3c_driver =3D { .driver =3D { .name =3D "dw-i3c-master", .of_match_table =3D dw_i3c_master_of_match, - .acpi_match_table =3D amd_i3c_device_match, + .acpi_match_table =3D dw_i3c_master_acpi_match, .pm =3D &dw_i3c_pm_ops, }, }; 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Tue, 16 Jun 2026 02:57:01 -0700 From: Akhil R To: Alexandre Belloni CC: Frank Li , Miquel Raynal , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Guenter Roeck , Philipp Zabel , Jon Hunter , Thierry Reding , , , , , , Akhil R Subject: [PATCH v4 10/12] hwmon: spd5118: Remove 16-bit addressing Date: Tue, 16 Jun 2026 09:54:24 +0000 Message-ID: <20260616095429.3947205-11-akhilrajeev@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260616095429.3947205-1-akhilrajeev@nvidia.com> References: <20260616095429.3947205-1-akhilrajeev@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF00026369:EE_|MW6PR12MB8898:EE_ X-MS-Office365-Filtering-Correlation-Id: 9e5572fc-7c12-4356-e6e1-08decb8da6b5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|36860700016|376014|82310400026|23010399003|1800799024|11063799006|56012099006|22082099003|18002099003|6133799003; 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charset="utf-8" The intent of introducing 16-bit addressing was to support I3C, but it turns out that I3C does not require reading the Legacy Mode register, nor any specific encoding for page translation. The testing of 16-bit code was limited and there are no known users for this feature. Remove the sections that support 16-bit addressing and prepare the driver to support I3C appropriately. Suggested-by: Guenter Roeck Acked-by: Guenter Roeck Signed-off-by: Akhil R --- drivers/hwmon/spd5118.c | 79 +++-------------------------------------- 1 file changed, 5 insertions(+), 74 deletions(-) diff --git a/drivers/hwmon/spd5118.c b/drivers/hwmon/spd5118.c index cc40661cab21..6ba37a719300 100644 --- a/drivers/hwmon/spd5118.c +++ b/drivers/hwmon/spd5118.c @@ -66,9 +66,6 @@ static const unsigned short normal_i2c[] =3D { #define SPD5118_EEPROM_BASE 0x80 #define SPD5118_EEPROM_SIZE (SPD5118_PAGE_SIZE * SPD5118_NUM_PAGES) =20 -#define PAGE_ADDR0(page) (((page) & BIT(0)) << 6) -#define PAGE_ADDR1_4(page) (((page) & GENMASK(4, 1)) >> 1) - /* Temperature unit in millicelsius */ #define SPD5118_TEMP_UNIT (MILLIDEGREE_PER_DEGREE / 4) /* Representable temperature range in millicelsius */ @@ -78,7 +75,6 @@ static const unsigned short normal_i2c[] =3D { struct spd5118_data { struct regmap *regmap; struct mutex nvmem_lock; - bool is_16bit; }; =20 /* hwmon */ @@ -348,12 +344,7 @@ static ssize_t spd5118_nvmem_read_page(struct spd5118_= data *data, char *buf, if (offset + count > SPD5118_PAGE_SIZE) count =3D SPD5118_PAGE_SIZE - offset; =20 - if (data->is_16bit) { - addr =3D SPD5118_EEPROM_BASE | PAGE_ADDR0(page) | - (PAGE_ADDR1_4(page) << 8); - } else { - addr =3D page * 0x100 + SPD5118_EEPROM_BASE; - } + addr =3D page * 0x100 + SPD5118_EEPROM_BASE; err =3D regmap_bulk_read(regmap, addr + offset, buf, count); if (err) return err; @@ -473,15 +464,6 @@ static const struct regmap_config spd5118_regmap8_conf= ig =3D { .num_ranges =3D ARRAY_SIZE(spd5118_i2c_regmap_range_cfg), }; =20 -static const struct regmap_config spd5118_regmap16_config =3D { - .reg_bits =3D 16, - .val_bits =3D 8, - .max_register =3D 0x7ff, - .writeable_reg =3D spd5118_writeable_reg, - .volatile_reg =3D spd5118_volatile_reg, - .cache_type =3D REGCACHE_MAPLE, -}; - static int spd5118_suspend(struct device *dev) { struct spd5118_data *data =3D dev_get_drvdata(dev); @@ -519,8 +501,7 @@ static int spd5118_resume(struct device *dev) =20 static DEFINE_SIMPLE_DEV_PM_OPS(spd5118_pm_ops, spd5118_suspend, spd5118_r= esume); =20 -static int spd5118_common_probe(struct device *dev, struct regmap *regmap, - bool is_16bit) +static int spd5118_common_probe(struct device *dev, struct regmap *regmap) { unsigned int capability, revision, vendor, bank; struct spd5118_data *data; @@ -537,8 +518,6 @@ static int spd5118_common_probe(struct device *dev, str= uct regmap *regmap, if (!(capability & SPD5118_CAP_TS_SUPPORT)) return -ENODEV; =20 - data->is_16bit =3D is_16bit; - err =3D regmap_read(regmap, SPD5118_REG_REVISION, &revision); if (err) return err; @@ -680,69 +659,21 @@ static int spd5118_i2c_init(struct i2c_client *client) return 0; } =20 -/* - * 16-bit addressing note: - * - * If I2C_FUNC_I2C is not supported by an I2C adapter driver, regmap uses - * SMBus operations as alternative. To simulate a read operation with a 16= -bit - * address, it writes the address using i2c_smbus_write_byte_data(), follo= wed - * by one or more calls to i2c_smbus_read_byte() to read the data. - * Per spd5118 standard, a read operation after writing the address must s= tart - * with (Repeat Start). However, a SMBus read byte operation starts w= ith - * (Start). This resets the register address in the spd5118 chip. As r= esult, - * i2c_smbus_read_byte() always returns data from register address 0x00. - * - * A working alternative to access chips with 16-bit register addresses in= the - * absence of I2C_FUNC_I2C support is not known. - * - * For this reason, 16-bit addressing can only be supported with I2C if the - * adapter supports I2C_FUNC_I2C. - * - * For I2C, the addressing mode selected by the BIOS must not be changed. - * Experiments show that at least some PC BIOS versions will not change the - * addressing mode on a soft reboot and end up in setup, claiming that some - * configuration change happened. This will happen again after a power cyc= le, - * which does reset the addressing mode. To prevent this from happening, - * detect if 16-bit addressing is enabled and always use the currently - * configured addressing mode. - */ - static int spd5118_i2c_probe(struct i2c_client *client) { - const struct regmap_config *config; struct device *dev =3D &client->dev; struct regmap *regmap; - int err, mode; - bool is_16bit; + int err; =20 err =3D spd5118_i2c_init(client); if (err) return err; =20 - mode =3D i2c_smbus_read_byte_data(client, SPD5118_REG_I2C_LEGACY_MODE); - if (mode < 0) - return mode; - - is_16bit =3D mode & SPD5118_LEGACY_MODE_ADDR; - if (is_16bit) { - /* - * See 16-bit addressing note above explaining why it is - * necessary to check for I2C_FUNC_I2C support here. - */ - if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) { - dev_err(dev, "Adapter does not support 16-bit register addresses\n"); - return -ENODEV; - } - config =3D &spd5118_regmap16_config; - } else { - config =3D &spd5118_regmap8_config; - } - - regmap =3D devm_regmap_init_i2c(client, config); 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On an I3C bus, SPD5118 devices are enumerated via SETAASA and always require an ACPI or device tree entry. Device matching is hence through the OF match tables only and does not need an I3C class match table. The device identity is verified in the type registers before proceeding to the common probe function. Acked-by: Guenter Roeck Signed-off-by: Akhil R --- drivers/hwmon/Kconfig | 9 ++++--- drivers/hwmon/spd5118.c | 56 ++++++++++++++++++++++++++++++++++++++++- 2 files changed, 61 insertions(+), 4 deletions(-) diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig index 5c2d3ff5fce8..c4bf5475fcb3 100644 --- a/drivers/hwmon/Kconfig +++ b/drivers/hwmon/Kconfig @@ -2354,12 +2354,15 @@ config SENSORS_INA3221 =20 config SENSORS_SPD5118 tristate "SPD5118 Compliant Temperature Sensors" - depends on I2C + depends on I3C_OR_I2C select REGMAP_I2C + select REGMAP_I3C if I3C help If you say yes here you get support for SPD5118 (JEDEC JESD300) - compliant temperature sensors. Such sensors are found on DDR5 memory - modules. + compliant temperature sensors using I2C or I3C bus interface. + Such sensors are found on DDR5 memory modules. + + This driver supports both I2C and I3C interfaces. =20 This driver can also be built as a module. If so, the module will be called spd5118. diff --git a/drivers/hwmon/spd5118.c b/drivers/hwmon/spd5118.c index 6ba37a719300..9724cf70b61d 100644 --- a/drivers/hwmon/spd5118.c +++ b/drivers/hwmon/spd5118.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -464,6 +465,27 @@ static const struct regmap_config spd5118_regmap8_conf= ig =3D { .num_ranges =3D ARRAY_SIZE(spd5118_i2c_regmap_range_cfg), }; =20 +/* + * SPD5118 2-byte register address format (JESD300-5, Tables 7 & 20): + * Byte 1 (on wire first): MemReg | BlkAddr[0] | Address[5:0] + * Byte 2 (on wire second): 0000 | BlkAddr[4:1] + * + * The address byte (with MemReg and lower address bits) must be sent firs= t, + * followed by the upper block address byte. With regmap 16-bit register + * format, this maps to little-endian: the low byte of the 16-bit value is + * transmitted first. No range config is needed since I3C does not use MR11 + * page switching. + */ +static const struct regmap_config spd5118_regmap_i3c_config =3D { + .reg_bits =3D 16, + .val_bits =3D 8, + .max_register =3D 0x7ff, + .reg_format_endian =3D REGMAP_ENDIAN_LITTLE, + .writeable_reg =3D spd5118_writeable_reg, + .volatile_reg =3D spd5118_volatile_reg, + .cache_type =3D REGCACHE_MAPLE, +}; + static int spd5118_suspend(struct device *dev) { struct spd5118_data *data =3D dev_get_drvdata(dev); @@ -701,7 +723,39 @@ static struct i2c_driver spd5118_i2c_driver =3D { .address_list =3D IS_ENABLED(CONFIG_SENSORS_SPD5118_DETECT) ? normal_i2c = : NULL, }; =20 -module_i2c_driver(spd5118_i2c_driver); +/* I3C */ + +static int spd5118_i3c_probe(struct i3c_device *i3cdev) +{ + struct device *dev =3D i3cdev_to_dev(i3cdev); + struct regmap *regmap; + u8 regval[2]; + int err; + + regmap =3D devm_regmap_init_i3c(i3cdev, &spd5118_regmap_i3c_config); + if (IS_ERR(regmap)) + return dev_err_probe(dev, PTR_ERR(regmap), "regmap init failed\n"); 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charset="utf-8" Enable I3C subsystem (I3C), Synopsys DesignWare I3C master controller (DW_I3C_MASTER), and SPD5118 hwmon temperature sensor (SENSORS_SPD5118) as modules. The NVIDIA Vera CPU uses SOCAMM LPDDR5X memory module, which contains SPD5118 (JEDEC JESD300) compliant temperature sensor. This sensor is accessible over the I3C bus through the DesignWare I3C controller present on the SoC. Enabling these configs allows monitoring memory module temperatures on platforms such as Vera Rubin. Vera is an ACPI-based platform and does not use device tree. Signed-off-by: Akhil R --- arch/arm64/configs/defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index f2e6ae93e533..65d9eb56e978 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -640,6 +640,8 @@ CONFIG_I2C_UNIPHIER_F=3Dy CONFIG_I2C_XILINX=3Dm CONFIG_I2C_RCAR=3Dy CONFIG_I2C_CROS_EC_TUNNEL=3Dy +CONFIG_I3C=3Dm +CONFIG_DW_I3C_MASTER=3Dm CONFIG_SPI=3Dy CONFIG_SPI_APPLE=3Dm CONFIG_SPI_ARMADA_3700=3Dy @@ -769,6 +771,7 @@ CONFIG_SENSORS_SL28CPLD=3Dm CONFIG_SENSORS_AMC6821=3Dm CONFIG_SENSORS_INA2XX=3Dm CONFIG_SENSORS_INA3221=3Dm +CONFIG_SENSORS_SPD5118=3Dm CONFIG_SENSORS_TMP102=3Dm CONFIG_THERMAL_GOV_POWER_ALLOCATOR=3Dy CONFIG_CPU_THERMAL=3Dy --=20 2.43.0