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These registers are organized in H/W as below on various SoCs. +---------------------------------------------------------------+ | SM8350, SM8450 | SM8550, Hamoa | SM8650, SM8750 | |---------------------------------------------------------------| | v2.7 | v3.0 | v3.2 | |---------------------------------------------------------------| | IRQ_ENABLE_BANK | IRQ_ENABLE_BANK | NA | |---------------------------------------------------------------| | IRQ_CFG | IRQ_CFG | IRQ_CFG | | | | | | | | [31:6] Unused | | | [31:5] Unused | [5] GPIO_STATUS | | | [4] GPIO_STATUS| [4] GPIO_MASK | | [31:3] Unused | [3] GPIO_MASK | [3] IRQ_ENABLE | | [0:2] Type | [0:2] Type | [0:2] Type | +---------------------------------------------------------------| All SoCs PDC irqchip supports "pass through mode" in which all interrupts are forwarded to the GIC without any latching at PDC H/W. So far irqchip did not utilize GPIO_STATUS and GPIO_MASK from IRQ_CFG register for v3.0 and v3.2 since they are only needed to be configured when PDC runs in specific mode named "second level interrupt controller" where it can latch the GPIO interrupts in GPIO_STATUS and forward GPIO interrupts to GIC as LEVEL_HIGH type SPI interrupt. All the SoCs defaulted to pass through mode with the exception of some x1e. x1e PDC may be set to secondary controller mode for builds on CRD boards whereas it may be set to pass through mode for IoT-EVK boards. Restructure in preparation to add the second level interrupt controller mode utilizing GPIO_STATUS and GPIO_MASK bits which changed the bit positions between v3.0 and v3.2. No functional impact with the change. Signed-off-by: Maulik Shah Reviewed-by: Konrad Dybcio --- drivers/irqchip/qcom-pdc.c | 207 ++++++++++++++++++++++++++++++++---------= ---- 1 file changed, 149 insertions(+), 58 deletions(-) diff --git a/drivers/irqchip/qcom-pdc.c b/drivers/irqchip/qcom-pdc.c index 2014dbb0bc43..23276325211d 100644 --- a/drivers/irqchip/qcom-pdc.c +++ b/drivers/irqchip/qcom-pdc.c @@ -21,21 +21,12 @@ #include #include =20 -#define PDC_MAX_GPIO_IRQS 256 -#define PDC_DRV_SIZE 0x10000 - -/* Valid only on HW version < 3.2 */ -#define IRQ_ENABLE_BANK 0x10 -#define IRQ_ENABLE_BANK_MAX (IRQ_ENABLE_BANK + BITS_TO_BYTES(PDC_MAX_GPIO_= IRQS)) +#define PDC_MAX_IRQS 256 +#define IRQ_ENABLE_BANK_MAX BITS_TO_BYTES(PDC_MAX_IRQS) #define IRQ_ENABLE_BANK_INDEX_MASK GENMASK(31, 5) #define IRQ_ENABLE_BANK_BIT_MASK GENMASK(4, 0) -#define IRQ_i_CFG 0x110 - -/* Valid only on HW version >=3D 3.2 */ -#define IRQ_i_CFG_IRQ_ENABLE 3 - -#define IRQ_i_CFG_TYPE_MASK GENMASK(2, 0) =20 +#define PDC_DRV_SIZE 0x10000 #define PDC_VERSION_REG 0x1000 #define PDC_VERSION_MAJOR GENMASK(23, 16) #define PDC_VERSION_MINOR GENMASK(15, 8) @@ -46,6 +37,98 @@ =20 /* Notable PDC versions */ #define PDC_VERSION_3_2 PDC_VERSION(3, 2, 0) +#define PDC_VERSION_3_0 PDC_VERSION(3, 0, 0) +#define PDC_VERSION_2_7 PDC_VERSION(2, 7, 0) + +/* + * PDC H/W registers layout per version: + * + * IRQ_ENABLE_BANK[b], b =3D 0....BITS_TO_BYTES(PDC_MAX_IRQS) + * IRQ_CFG[n], n =3D 0....PDC_MAX_IRQS + * + * +---------------------------------------------------------------+ + * | v2.7 | v3.0 | v3.2 | + * |---------------------------------------------------------------| + * | BASE | BASE | BASE | + * |---------------------------------------------------------------| + * | | + * | IRQ_ENABLE_BANK | IRQ_ENABLE_BANK | NA | + * |---------------------------------------------------------------| + * | IRQ_CFG | IRQ_CFG | IRQ_CFG | + * | | | | + * | | | [31:6] Unused | + * | | [31:5] Unused | [5] GPIO_STATUS | + * | | [4] GPIO_STATUS| [4] GPIO_MASK | + * | [31:3] Unused | [3] GPIO_MASK | [3] IRQ_ENABLE | + * | [0:2] Type | [0:2] Type | [0:2] Type | + * +---------------------------------------------------------------+ + */ + +/** + * struct pdc_regs: PDC registers location + * + * @irq_en_reg: IRQ_ENABLE_BANK register location + * @irq_cfg_reg: IRQ_CFG register location + */ +struct pdc_regs { + u32 irq_en_reg; + u32 irq_cfg_reg; +}; + +/** + * struct pdc_irq_cfg: bit fields for PDC IRQ_CFG register + * + * @irq_enable: bit number for IRQ_ENABLE field + * @irq_type: GENMASK for IRQ_TYPE field + */ +struct pdc_irq_cfg { + u32 irq_enable; + u32 irq_type; +}; + +/** + * struct pdc_desc: PDC driver state + * + * @base: PDC base register for DRV2 / HLOS + * @prev_base: PDC DRV1 base, applicable only for x1e RTL bug. + * @version: PDC version + * @regs: PDC regs (IRQ_ENABLE_BANK and IRQ_CFG) + * @cfg_fields: Fields of IRQ_CFG reg + */ +struct pdc_desc { + void __iomem *base; + void __iomem *prev_base; + u32 version; + const struct pdc_regs *regs; + const struct pdc_irq_cfg *cfg_fields; +}; + +static const struct pdc_regs pdc_v3_2 =3D { + .irq_cfg_reg =3D 0x110, +}; + +static const struct pdc_irq_cfg pdc_cfg_v3_2 =3D { + .irq_enable =3D 3, + .irq_type =3D GENMASK(2, 0), +}; + +static const struct pdc_regs pdc_v3_0 =3D { + .irq_en_reg =3D 0x10, + .irq_cfg_reg =3D 0x110, +}; + +static const struct pdc_irq_cfg pdc_cfg_v3_0 =3D { + .irq_type =3D GENMASK(2, 0), +}; + +static const struct pdc_regs pdc_v2_7 =3D { + .irq_en_reg =3D 0x10, + .irq_cfg_reg =3D 0x110, +}; + +static const struct pdc_irq_cfg pdc_cfg_v2_7 =3D { + .irq_type =3D GENMASK(2, 0), +}; =20 struct pdc_pin_region { u32 pin_base; @@ -56,12 +139,11 @@ struct pdc_pin_region { #define pin_to_hwirq(r, p) ((r)->parent_base + (p) - (r)->pin_base) =20 static DEFINE_RAW_SPINLOCK(pdc_lock); -static void __iomem *pdc_base; -static void __iomem *pdc_prev_base; static struct pdc_pin_region *pdc_region; static int pdc_region_cnt; static unsigned int pdc_version; static bool pdc_x1e_quirk; +static struct pdc_desc *pdc; =20 static void pdc_base_reg_write(void __iomem *base, int reg, u32 i, u32 val) { @@ -70,12 +152,12 @@ static void pdc_base_reg_write(void __iomem *base, int= reg, u32 i, u32 val) =20 static void pdc_reg_write(int reg, u32 i, u32 val) { - pdc_base_reg_write(pdc_base, reg, i, val); + pdc_base_reg_write(pdc->base, reg, i, val); } =20 static u32 pdc_reg_read(int reg, u32 i) { - return readl_relaxed(pdc_base + reg + i * sizeof(u32)); + return readl_relaxed(pdc->base + reg + i * sizeof(u32)); } =20 static void pdc_x1e_irq_enable_write(u32 bank, u32 enable) @@ -86,24 +168,24 @@ static void pdc_x1e_irq_enable_write(u32 bank, u32 ena= ble) switch (bank) { case 0 ... 1: /* Use previous DRV (client) region and shift to bank 3-4 */ - base =3D pdc_prev_base; + base =3D pdc->prev_base; bank +=3D 3; break; case 2 ... 4: /* Use our own region and shift to bank 0-2 */ - base =3D pdc_base; + base =3D pdc->base; bank -=3D 2; break; case 5: /* No fixup required for bank 5 */ - base =3D pdc_base; + base =3D pdc->base; break; default: WARN_ON(1); return; } =20 - pdc_base_reg_write(base, IRQ_ENABLE_BANK, bank, enable); + pdc_base_reg_write(base, pdc->regs->irq_en_reg, bank, enable); } =20 static void pdc_enable_intr_bank(int pin_out, bool on) @@ -114,21 +196,21 @@ static void pdc_enable_intr_bank(int pin_out, bool on) index =3D FIELD_GET(IRQ_ENABLE_BANK_INDEX_MASK, pin_out); mask =3D FIELD_GET(IRQ_ENABLE_BANK_BIT_MASK, pin_out); =20 - enable =3D pdc_reg_read(IRQ_ENABLE_BANK, index); + enable =3D pdc_reg_read(pdc->regs->irq_en_reg, index); __assign_bit(mask, &enable, on); =20 if (pdc_x1e_quirk) pdc_x1e_irq_enable_write(index, enable); else - pdc_reg_write(IRQ_ENABLE_BANK, index, enable); + pdc_reg_write(pdc->regs->irq_en_reg, index, enable); } =20 static void pdc_enable_intr_cfg(int pin_out, bool on) { - unsigned long enable =3D pdc_reg_read(IRQ_i_CFG, pin_out); + unsigned long enable =3D pdc_reg_read(pdc->regs->irq_cfg_reg, pin_out); =20 - __assign_bit(IRQ_i_CFG_IRQ_ENABLE, &enable, on); - pdc_reg_write(IRQ_i_CFG, pin_out, enable); + __assign_bit(pdc->cfg_fields->irq_enable, &enable, on); + pdc_reg_write(pdc->regs->irq_cfg_reg, pin_out, enable); } =20 static void __pdc_enable_intr(int pin_out, bool on) @@ -224,9 +306,9 @@ static int qcom_pdc_gic_set_type(struct irq_data *d, un= signed int type) return -EINVAL; } =20 - old_pdc_type =3D pdc_reg_read(IRQ_i_CFG, d->hwirq); - pdc_type |=3D (old_pdc_type & ~IRQ_i_CFG_TYPE_MASK); - pdc_reg_write(IRQ_i_CFG, d->hwirq, pdc_type); + old_pdc_type =3D pdc_reg_read(pdc->regs->irq_cfg_reg, d->hwirq); + pdc_type |=3D (old_pdc_type & ~pdc->cfg_fields->irq_type); + pdc_reg_write(pdc->regs->irq_cfg_reg, d->hwirq, pdc_type); =20 ret =3D irq_chip_set_type_parent(d, type); if (ret) @@ -327,7 +409,7 @@ static const struct irq_domain_ops qcom_pdc_ops =3D { .free =3D irq_domain_free_irqs_common, }; =20 -static int pdc_setup_pin_mapping(struct device_node *np) +static int pdc_setup_pin_mapping(struct device *dev, struct device_node *n= p) { int ret, n, i; =20 @@ -336,7 +418,8 @@ static int pdc_setup_pin_mapping(struct device_node *np) return -EINVAL; =20 pdc_region_cnt =3D n / 3; - pdc_region =3D kzalloc_objs(*pdc_region, pdc_region_cnt); + pdc_region =3D devm_kcalloc(dev, pdc_region_cnt, sizeof(*pdc_region), + GFP_KERNEL); if (!pdc_region) { pdc_region_cnt =3D 0; return -ENOMEM; @@ -366,11 +449,11 @@ static int pdc_setup_pin_mapping(struct device_node *= np) return 0; } =20 - static int qcom_pdc_probe(struct platform_device *pdev, struct device_node= *parent) { struct irq_domain *parent_domain, *pdc_domain; struct device_node *node =3D pdev->dev.of_node; + struct device *dev =3D &pdev->dev; resource_size_t res_size; struct resource res; int ret; @@ -383,6 +466,30 @@ static int qcom_pdc_probe(struct platform_device *pdev= , struct device_node *pare if (res_size > resource_size(&res)) pr_warn("%pOF: invalid reg size, please fix DT\n", node); =20 + pdc =3D devm_kzalloc(dev, sizeof(*pdc), GFP_KERNEL); + if (!pdc) + return -ENOMEM; + + pdc->base =3D devm_ioremap(dev, res.start, res_size); + if (!pdc->base) { + pr_err("%pOF: unable to map PDC registers\n", node); + return -ENXIO; + } + + pdc->version =3D pdc_reg_read(PDC_VERSION_REG, 0); + + if (pdc->version >=3D PDC_VERSION_3_2) { + pdc->cfg_fields =3D &pdc_cfg_v3_2; + pdc->regs =3D &pdc_v3_2; + } else if (pdc->version < PDC_VERSION_3_2 && + pdc->version >=3D PDC_VERSION_3_0) { + pdc->cfg_fields =3D &pdc_cfg_v3_0; + pdc->regs =3D &pdc_v3_0; + } else { + pdc->cfg_fields =3D &pdc_cfg_v2_7; + pdc->regs =3D &pdc_v2_7; + } + /* * PDC has multiple DRV regions, each one provides the same set of * registers for a particular client in the system. Due to a hardware @@ -392,8 +499,9 @@ static int qcom_pdc_probe(struct platform_device *pdev,= struct device_node *pare * region with the expected offset to preserve support for old DTs. */ if (of_device_is_compatible(node, "qcom,x1e80100-pdc")) { - pdc_prev_base =3D ioremap(res.start - PDC_DRV_SIZE, IRQ_ENABLE_BANK_MAX); - if (!pdc_prev_base) { + pdc->prev_base =3D devm_ioremap(dev, res.start - PDC_DRV_SIZE, + pdc->regs->irq_en_reg + IRQ_ENABLE_BANK_MAX); + if (!pdc->prev_base) { pr_err("%pOF: unable to map previous PDC DRV region\n", node); return -ENXIO; } @@ -401,48 +509,31 @@ static int qcom_pdc_probe(struct platform_device *pde= v, struct device_node *pare pdc_x1e_quirk =3D true; } =20 - pdc_base =3D ioremap(res.start, res_size); - if (!pdc_base) { - pr_err("%pOF: unable to map PDC registers\n", node); - ret =3D -ENXIO; - goto fail; - } - - pdc_version =3D pdc_reg_read(PDC_VERSION_REG, 0); - parent_domain =3D irq_find_host(parent); if (!parent_domain) { pr_err("%pOF: unable to find PDC's parent domain\n", node); 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Move all to struct pdc_desc to better align with versioning support. Document them. No functional impact. Signed-off-by: Maulik Shah --- drivers/irqchip/qcom-pdc.c | 77 ++++++++++++++++++++++++------------------= ---- 1 file changed, 40 insertions(+), 37 deletions(-) diff --git a/drivers/irqchip/qcom-pdc.c b/drivers/irqchip/qcom-pdc.c index 23276325211d..b9acb0f25c9c 100644 --- a/drivers/irqchip/qcom-pdc.c +++ b/drivers/irqchip/qcom-pdc.c @@ -92,15 +92,30 @@ struct pdc_irq_cfg { * @base: PDC base register for DRV2 / HLOS * @prev_base: PDC DRV1 base, applicable only for x1e RTL bug. * @version: PDC version + * @region: PDC interrupt continuous range + * @region_cnt: Total PDC ranges + * @x1e_quirk: x1e H/W Bug handling + * @lock: lock for IRQ_ENABLE_BANK protection * @regs: PDC regs (IRQ_ENABLE_BANK and IRQ_CFG) * @cfg_fields: Fields of IRQ_CFG reg + * @enable_intr: pointer to enable function based on PDC version */ struct pdc_desc { void __iomem *base; void __iomem *prev_base; u32 version; + + struct pdc_pin_region *region; + int region_cnt; + + bool x1e_quirk; + + raw_spinlock_t lock; + const struct pdc_regs *regs; const struct pdc_irq_cfg *cfg_fields; + + void (*enable_intr)(int pin_out, bool on); }; =20 static const struct pdc_regs pdc_v3_2 =3D { @@ -138,11 +153,6 @@ struct pdc_pin_region { =20 #define pin_to_hwirq(r, p) ((r)->parent_base + (p) - (r)->pin_base) =20 -static DEFINE_RAW_SPINLOCK(pdc_lock); -static struct pdc_pin_region *pdc_region; -static int pdc_region_cnt; -static unsigned int pdc_version; -static bool pdc_x1e_quirk; static struct pdc_desc *pdc; =20 static void pdc_base_reg_write(void __iomem *base, int reg, u32 i, u32 val) @@ -199,7 +209,7 @@ static void pdc_enable_intr_bank(int pin_out, bool on) enable =3D pdc_reg_read(pdc->regs->irq_en_reg, index); __assign_bit(mask, &enable, on); =20 - if (pdc_x1e_quirk) + if (pdc->x1e_quirk) pdc_x1e_irq_enable_write(index, enable); else pdc_reg_write(pdc->regs->irq_en_reg, index, enable); @@ -213,21 +223,11 @@ static void pdc_enable_intr_cfg(int pin_out, bool on) pdc_reg_write(pdc->regs->irq_cfg_reg, pin_out, enable); } =20 -static void __pdc_enable_intr(int pin_out, bool on) -{ - if (pdc_version < PDC_VERSION_3_2) - pdc_enable_intr_bank(pin_out, on); - else - pdc_enable_intr_cfg(pin_out, on); -} - static void pdc_enable_intr(struct irq_data *d, bool on) { - unsigned long flags; + guard(raw_spinlock)(&pdc->lock); =20 - raw_spin_lock_irqsave(&pdc_lock, flags); - __pdc_enable_intr(d->hwirq, on); - raw_spin_unlock_irqrestore(&pdc_lock, flags); + pdc->enable_intr(d->hwirq, on); } =20 static void qcom_pdc_gic_disable(struct irq_data *d) @@ -350,12 +350,10 @@ static struct irq_chip qcom_pdc_gic_chip =3D { =20 static struct pdc_pin_region *get_pin_region(int pin) { - int i; - - for (i =3D 0; i < pdc_region_cnt; i++) { - if (pin >=3D pdc_region[i].pin_base && - pin < pdc_region[i].pin_base + pdc_region[i].cnt) - return &pdc_region[i]; + for (int i =3D 0; i < pdc->region_cnt; i++) { + if (pin >=3D pdc->region[i].pin_base && + pin < pdc->region[i].pin_base + pdc->region[i].cnt) + return &pdc->region[i]; } =20 return NULL; @@ -411,39 +409,39 @@ static const struct irq_domain_ops qcom_pdc_ops =3D { =20 static int pdc_setup_pin_mapping(struct device *dev, struct device_node *n= p) { - int ret, n, i; + int ret, n; =20 n =3D of_property_count_elems_of_size(np, "qcom,pdc-ranges", sizeof(u32)); if (n <=3D 0 || n % 3) return -EINVAL; =20 - pdc_region_cnt =3D n / 3; - pdc_region =3D devm_kcalloc(dev, pdc_region_cnt, sizeof(*pdc_region), - GFP_KERNEL); - if (!pdc_region) { - pdc_region_cnt =3D 0; + pdc->region_cnt =3D n / 3; + pdc->region =3D devm_kcalloc(dev, pdc->region_cnt, sizeof(*pdc->region), + GFP_KERNEL); + if (!pdc->region) { + pdc->region_cnt =3D 0; return -ENOMEM; } =20 - for (n =3D 0; n < pdc_region_cnt; n++) { + for (n =3D 0; n < pdc->region_cnt; n++) { ret =3D of_property_read_u32_index(np, "qcom,pdc-ranges", n * 3 + 0, - &pdc_region[n].pin_base); + &pdc->region[n].pin_base); if (ret) return ret; ret =3D of_property_read_u32_index(np, "qcom,pdc-ranges", n * 3 + 1, - &pdc_region[n].parent_base); + &pdc->region[n].parent_base); if (ret) return ret; ret =3D of_property_read_u32_index(np, "qcom,pdc-ranges", n * 3 + 2, - &pdc_region[n].cnt); + &pdc->region[n].cnt); if (ret) return ret; =20 - for (i =3D 0; i < pdc_region[n].cnt; i++) - __pdc_enable_intr(i + pdc_region[n].pin_base, 0); + for (int i =3D 0; i < pdc->region[n].cnt; i++) + pdc->enable_intr(i + pdc->region[n].pin_base, 0); } =20 return 0; @@ -481,13 +479,16 @@ static int qcom_pdc_probe(struct platform_device *pde= v, struct device_node *pare if (pdc->version >=3D PDC_VERSION_3_2) { pdc->cfg_fields =3D &pdc_cfg_v3_2; pdc->regs =3D &pdc_v3_2; + pdc->enable_intr =3D pdc_enable_intr_cfg; } else if (pdc->version < PDC_VERSION_3_2 && pdc->version >=3D PDC_VERSION_3_0) { pdc->cfg_fields =3D &pdc_cfg_v3_0; pdc->regs =3D &pdc_v3_0; + pdc->enable_intr =3D pdc_enable_intr_bank; } else { pdc->cfg_fields =3D &pdc_cfg_v2_7; pdc->regs =3D &pdc_v2_7; + pdc->enable_intr =3D pdc_enable_intr_bank; } =20 /* @@ -506,7 +507,7 @@ static int qcom_pdc_probe(struct platform_device *pdev,= struct device_node *pare return -ENXIO; } =20 - pdc_x1e_quirk =3D true; + pdc->x1e_quirk =3D true; } =20 parent_domain =3D irq_find_host(parent); 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Remove the wrapper and invoke pdc->enable_intr() from caller. Locking in pdc_enable_intr() applies lock to all pdc->enable_intr() however its only required for pdc_enable_intr_bank() which uses a shared bank across all interrupts. pdc_enable_intr_cfg() do not required locking as IRQ_CFG registers are one per interrupt. Move locking accordingly. Signed-off-by: Maulik Shah --- drivers/irqchip/qcom-pdc.c | 13 ++++--------- 1 file changed, 4 insertions(+), 9 deletions(-) diff --git a/drivers/irqchip/qcom-pdc.c b/drivers/irqchip/qcom-pdc.c index b9acb0f25c9c..6c556464d37c 100644 --- a/drivers/irqchip/qcom-pdc.c +++ b/drivers/irqchip/qcom-pdc.c @@ -206,6 +206,8 @@ static void pdc_enable_intr_bank(int pin_out, bool on) index =3D FIELD_GET(IRQ_ENABLE_BANK_INDEX_MASK, pin_out); mask =3D FIELD_GET(IRQ_ENABLE_BANK_BIT_MASK, pin_out); =20 + guard(raw_spinlock)(&pdc->lock); + enable =3D pdc_reg_read(pdc->regs->irq_en_reg, index); __assign_bit(mask, &enable, on); =20 @@ -223,22 +225,15 @@ static void pdc_enable_intr_cfg(int pin_out, bool on) pdc_reg_write(pdc->regs->irq_cfg_reg, pin_out, enable); } =20 -static void pdc_enable_intr(struct irq_data *d, bool on) -{ - guard(raw_spinlock)(&pdc->lock); - - pdc->enable_intr(d->hwirq, on); -} - static void qcom_pdc_gic_disable(struct irq_data *d) { - pdc_enable_intr(d, false); + pdc->enable_intr(d->hwirq, false); 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Separate domains can be useful in case irqchip want to differentiate both of them. Since commit unified both the domains there is no way to differentiate. In preparation to add the second level interrupt controller support where GPIO interrupts get latched at PDC (but not direct SPIs) there is a need to differentiate between SPIs and GPIOs as SPIs. Reverting above commit do not seem a good option either which leads to waste of resources. PDC HW have the IRQ_PARAM register telling number of direct SPIs and number of GPIOs as SPIs. Further PDC allocates direct SPIs at the beginning and all GPIOs as SPIs are allocated at the end. This information can be used in driver to differentiate them. Add the support to read this register and keep this information in struct pdc_desc. Later change utilizes same. Signed-off-by: Maulik Shah --- drivers/irqchip/qcom-pdc.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/irqchip/qcom-pdc.c b/drivers/irqchip/qcom-pdc.c index 6c556464d37c..1aa6be42307c 100644 --- a/drivers/irqchip/qcom-pdc.c +++ b/drivers/irqchip/qcom-pdc.c @@ -61,6 +61,11 @@ * | | [4] GPIO_STATUS| [4] GPIO_MASK | * | [31:3] Unused | [3] GPIO_MASK | [3] IRQ_ENABLE | * | [0:2] Type | [0:2] Type | [0:2] Type | + * |---------------------------------------------------------------| + * | IRQ_PARAM | IRQ_PARAM | IRQ_PARAM | + * | | | + * | [15:8] NUM_GPIO | [15:8] NUM_GPIO | [15:8] NUM_GPIO | + * | [7:0] NUM_SPI | [7:0] NUM_SPI | [7:0] NUM_SPI | * +---------------------------------------------------------------+ */ =20 @@ -69,10 +74,12 @@ * * @irq_en_reg: IRQ_ENABLE_BANK register location * @irq_cfg_reg: IRQ_CFG register location + * @irq_param_reg: IRQ_PARAM register location */ struct pdc_regs { u32 irq_en_reg; u32 irq_cfg_reg; + u32 irq_param_reg; }; =20 /** @@ -92,6 +99,8 @@ struct pdc_irq_cfg { * @base: PDC base register for DRV2 / HLOS * @prev_base: PDC DRV1 base, applicable only for x1e RTL bug. * @version: PDC version + * @num_spis: Total number of direct SPI interrupts + * @num_gpios: Total number of GPIOs forwarded as SPI interrupts * @region: PDC interrupt continuous range * @region_cnt: Total PDC ranges * @x1e_quirk: x1e H/W Bug handling @@ -104,6 +113,8 @@ struct pdc_desc { void __iomem *base; void __iomem *prev_base; u32 version; + u32 num_spis; + u32 num_gpios; =20 struct pdc_pin_region *region; int region_cnt; @@ -120,6 +131,7 @@ struct pdc_desc { =20 static const struct pdc_regs pdc_v3_2 =3D { .irq_cfg_reg =3D 0x110, + .irq_param_reg =3D 0x100c, }; =20 static const struct pdc_irq_cfg pdc_cfg_v3_2 =3D { @@ -130,6 +142,7 @@ static const struct pdc_irq_cfg pdc_cfg_v3_2 =3D { static const struct pdc_regs pdc_v3_0 =3D { .irq_en_reg =3D 0x10, .irq_cfg_reg =3D 0x110, + .irq_param_reg =3D 0x100c, }; =20 static const struct pdc_irq_cfg pdc_cfg_v3_0 =3D { @@ -139,6 +152,7 @@ static const struct pdc_irq_cfg pdc_cfg_v3_0 =3D { static const struct pdc_regs pdc_v2_7 =3D { .irq_en_reg =3D 0x10, .irq_cfg_reg =3D 0x110, + .irq_param_reg =3D 0x100c, }; =20 static const struct pdc_irq_cfg pdc_cfg_v2_7 =3D { @@ -449,6 +463,7 @@ static int qcom_pdc_probe(struct platform_device *pdev,= struct device_node *pare struct device *dev =3D &pdev->dev; resource_size_t res_size; struct resource res; + u32 irq_param; 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Newer PDCs (v3.0 onwards) also support additional secondary controller mode where PDC latches GPIO IRQs and sends to GIC as level type IRQ. Direct SPIs still works same as pass through mode without latching at PDC even in secondary controller mode. All the SoCs so far default uses pass through mode with the exception of x1e. x1e PDC may be set to secondary controller mode for builds on CRD boards whereas it may be set to pass through mode for IoT-EVK boards. The mode configuration is done in firmware and initially shipped windows firmware did not have SCM interface to read or modify the PDC mode. Later only write access is opened up for non secure world. Using the write access available add changes to modify the PDC mode to pass through mode via SCM write. When the write fails (on older firmware) assume to work in secondary mode. In secondary mode set the separate irqchip for the GPIOs to perform additional operations only for the GPIO irqs. Co-developed-by: Sneh Mankad Signed-off-by: Sneh Mankad Signed-off-by: Maulik Shah --- drivers/irqchip/qcom-pdc.c | 220 +++++++++++++++++++++++++++++++++++++++++= +--- 1 file changed, 208 insertions(+), 12 deletions(-) diff --git a/drivers/irqchip/qcom-pdc.c b/drivers/irqchip/qcom-pdc.c index 1aa6be42307c..c6f2935ff788 100644 --- a/drivers/irqchip/qcom-pdc.c +++ b/drivers/irqchip/qcom-pdc.c @@ -20,12 +20,18 @@ #include #include #include +#include =20 #define PDC_MAX_IRQS 256 #define IRQ_ENABLE_BANK_MAX BITS_TO_BYTES(PDC_MAX_IRQS) #define IRQ_ENABLE_BANK_INDEX_MASK GENMASK(31, 5) #define IRQ_ENABLE_BANK_BIT_MASK GENMASK(4, 0) =20 +/* Secure DRV register to configure the PDC mode via qcom_scm_io_writel() = */ +#define PDC_GPIO_INT_CTL_ENABLE 0xb2045e8 +#define PDC_PASS_THROUGH_MODE 0x0 +#define PDC_SECONDARY_MODE 0x1 + #define PDC_DRV_SIZE 0x10000 #define PDC_VERSION_REG 0x1000 #define PDC_VERSION_MAJOR GENMASK(23, 16) @@ -85,10 +91,14 @@ struct pdc_regs { /** * struct pdc_irq_cfg: bit fields for PDC IRQ_CFG register * + * @gpio_irq_sts: bit number for GPIO_STATUS field + * @gpio_irq_mask: bit number for GPIO_MASK field * @irq_enable: bit number for IRQ_ENABLE field * @irq_type: GENMASK for IRQ_TYPE field */ struct pdc_irq_cfg { + u32 gpio_irq_sts; + u32 gpio_irq_mask; u32 irq_enable; u32 irq_type; }; @@ -103,11 +113,14 @@ struct pdc_irq_cfg { * @num_gpios: Total number of GPIOs forwarded as SPI interrupts * @region: PDC interrupt continuous range * @region_cnt: Total PDC ranges + * @mode: PDC_PASS_THROUGH_MODE or PDC_SECONDARY_MODE * @x1e_quirk: x1e H/W Bug handling * @lock: lock for IRQ_ENABLE_BANK protection * @regs: PDC regs (IRQ_ENABLE_BANK and IRQ_CFG) * @cfg_fields: Fields of IRQ_CFG reg * @enable_intr: pointer to enable function based on PDC version + * @unmask_gpio: pointer to GPIO irq unmask function + * @clear_gpio: pointer to GPIO irq clear function */ struct pdc_desc { void __iomem *base; @@ -119,6 +132,7 @@ struct pdc_desc { struct pdc_pin_region *region; int region_cnt; =20 + u8 mode; bool x1e_quirk; =20 raw_spinlock_t lock; @@ -127,6 +141,8 @@ struct pdc_desc { const struct pdc_irq_cfg *cfg_fields; =20 void (*enable_intr)(int pin_out, bool on); + void (*unmask_gpio)(int pin_out, bool on); + void (*clear_gpio)(int pin_out); }; =20 static const struct pdc_regs pdc_v3_2 =3D { @@ -135,6 +151,8 @@ static const struct pdc_regs pdc_v3_2 =3D { }; =20 static const struct pdc_irq_cfg pdc_cfg_v3_2 =3D { + .gpio_irq_sts =3D 5, + .gpio_irq_mask =3D 4, .irq_enable =3D 3, .irq_type =3D GENMASK(2, 0), }; @@ -146,6 +164,8 @@ static const struct pdc_regs pdc_v3_0 =3D { }; =20 static const struct pdc_irq_cfg pdc_cfg_v3_0 =3D { + .gpio_irq_sts =3D 4, + .gpio_irq_mask =3D 3, .irq_type =3D GENMASK(2, 0), }; =20 @@ -184,6 +204,15 @@ static u32 pdc_reg_read(int reg, u32 i) return readl_relaxed(pdc->base + reg + i * sizeof(u32)); } =20 +static inline bool pdc_pin_is_gpio(int pin_out) +{ + /* + * PDC allocates direct SPIs at the beginning and + * all GPIOs as SPIs are allocated after direct SPIs. + */ + return pin_out >=3D pdc->num_spis; +} + static void pdc_x1e_irq_enable_write(u32 bank, u32 enable) { void __iomem *base; @@ -231,6 +260,30 @@ static void pdc_enable_intr_bank(int pin_out, bool on) pdc_reg_write(pdc->regs->irq_en_reg, index, enable); } =20 +static void pdc_clear_gpio_cfg(int pin_out) +{ + unsigned long gpio_sts; + + if (pdc->version < PDC_VERSION_3_0) + return; + + gpio_sts =3D pdc_reg_read(pdc->regs->irq_cfg_reg, pin_out); + __clear_bit(pdc->cfg_fields->gpio_irq_sts, &gpio_sts); + pdc_reg_write(pdc->regs->irq_cfg_reg, pin_out, gpio_sts); +} + +static void pdc_unmask_gpio_cfg(int pin_out, bool unmask) +{ + unsigned long gpio_mask; + + if (pdc->version < PDC_VERSION_3_0) + return; + + gpio_mask =3D pdc_reg_read(pdc->regs->irq_cfg_reg, pin_out); + __assign_bit(pdc->cfg_fields->gpio_irq_mask, &gpio_mask, !unmask); + pdc_reg_write(pdc->regs->irq_cfg_reg, pin_out, gpio_mask); +} + static void pdc_enable_intr_cfg(int pin_out, bool on) { unsigned long enable =3D pdc_reg_read(pdc->regs->irq_cfg_reg, pin_out); @@ -245,12 +298,40 @@ static void qcom_pdc_gic_disable(struct irq_data *d) irq_chip_disable_parent(d); } =20 +static void qcom_pdc_gic_secondary_disable(struct irq_data *d) +{ + pdc->enable_intr(d->hwirq, false); + pdc->unmask_gpio(d->hwirq, false); + irq_chip_disable_parent(d); +} + static void qcom_pdc_gic_enable(struct irq_data *d) { pdc->enable_intr(d->hwirq, true); irq_chip_enable_parent(d); } =20 +static void qcom_pdc_gic_secondary_enable(struct irq_data *d) +{ + pdc->enable_intr(d->hwirq, true); + pdc->unmask_gpio(d->hwirq, true); + irq_chip_enable_parent(d); +} + +static void qcom_pdc_secondary_ack(struct irq_data *d) +{ + if (!irqd_is_level_type(d)) + pdc->clear_gpio(d->hwirq); +} + +static void qcom_pdc_gic_secondary_eoi(struct irq_data *d) +{ + if (irqd_is_level_type(d)) + pdc->clear_gpio(d->hwirq); + + irq_chip_eoi_parent(d); +} + /* * GIC does not handle falling edge or active low. To allow falling edge a= nd * active low interrupts to be handled at GIC, PDC has an inverter that in= verts @@ -338,6 +419,67 @@ static int qcom_pdc_gic_set_type(struct irq_data *d, u= nsigned int type) return 0; } =20 +/** + * qcom_pdc_gic_set_type: Configure PDC for the interrupt + * + * @d: the interrupt data + * @type: the interrupt type + * + * All @type are forwarded as Level type to parent GIC + */ +static int qcom_pdc_gic_secondary_set_type(struct irq_data *d, unsigned in= t type) +{ + enum pdc_irq_config_bits pdc_type; + enum pdc_irq_config_bits old_pdc_type; + int ret; + + switch (type) { + case IRQ_TYPE_EDGE_RISING: + pdc_type =3D PDC_EDGE_RISING; + break; + case IRQ_TYPE_EDGE_FALLING: + pdc_type =3D PDC_EDGE_FALLING; + break; + case IRQ_TYPE_EDGE_BOTH: + pdc_type =3D PDC_EDGE_DUAL; + break; + case IRQ_TYPE_LEVEL_HIGH: + pdc_type =3D PDC_LEVEL_HIGH; + break; + case IRQ_TYPE_LEVEL_LOW: + pdc_type =3D PDC_LEVEL_LOW; + break; + default: + WARN_ON(1); + return -EINVAL; + } + + old_pdc_type =3D pdc_reg_read(pdc->regs->irq_cfg_reg, d->hwirq); + pdc_type |=3D (old_pdc_type & ~pdc->cfg_fields->irq_type); + pdc_reg_write(pdc->regs->irq_cfg_reg, d->hwirq, pdc_type); + + type =3D IRQ_TYPE_LEVEL_HIGH; + pdc->clear_gpio(d->hwirq); + + ret =3D irq_chip_set_type_parent(d, type); + if (ret) + return ret; + + /* + * When we change types the PDC can give a phantom interrupt. + * Clear it. Specifically the phantom shows up when reconfiguring + * polarity of interrupt without changing the state of the signal + * but let's be consistent and clear it always. + * + * Doing this works because we have IRQCHIP_SET_TYPE_MASKED so the + * interrupt will be cleared before the rest of the system sees it. + */ + if (old_pdc_type !=3D pdc_type) + irq_chip_set_parent_state(d, IRQCHIP_STATE_PENDING, false); + + return 0; +} + static struct irq_chip qcom_pdc_gic_chip =3D { .name =3D "PDC", .irq_eoi =3D irq_chip_eoi_parent, @@ -357,6 +499,26 @@ static struct irq_chip qcom_pdc_gic_chip =3D { .irq_set_affinity =3D irq_chip_set_affinity_parent, }; =20 +static struct irq_chip qcom_pdc_gic_secondary_chip =3D { + .name =3D "PDC", + .irq_ack =3D qcom_pdc_secondary_ack, + .irq_eoi =3D qcom_pdc_gic_secondary_eoi, + .irq_mask =3D irq_chip_mask_parent, + .irq_unmask =3D irq_chip_unmask_parent, + .irq_disable =3D qcom_pdc_gic_secondary_disable, + .irq_enable =3D qcom_pdc_gic_secondary_enable, + .irq_get_irqchip_state =3D irq_chip_get_parent_state, + .irq_set_irqchip_state =3D irq_chip_set_parent_state, + .irq_retrigger =3D irq_chip_retrigger_hierarchy, + .irq_set_type =3D qcom_pdc_gic_secondary_set_type, + .flags =3D IRQCHIP_MASK_ON_SUSPEND | + IRQCHIP_SET_TYPE_MASKED | + IRQCHIP_SKIP_SET_WAKE | + IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND, + .irq_set_vcpu_affinity =3D irq_chip_set_vcpu_affinity_parent, + .irq_set_affinity =3D irq_chip_set_affinity_parent, +}; + static struct pdc_pin_region *get_pin_region(int pin) { for (int i =3D 0; i < pdc->region_cnt; i++) { @@ -385,20 +547,37 @@ static int qcom_pdc_alloc(struct irq_domain *domain, = unsigned int virq, if (hwirq =3D=3D GPIO_NO_WAKE_IRQ) return irq_domain_disconnect_hierarchy(domain, virq); =20 - ret =3D irq_domain_set_hwirq_and_chip(domain, virq, hwirq, - &qcom_pdc_gic_chip, NULL); - if (ret) - return ret; + /* + * PDC secondary chip is only set for the GPIO interrupts as SPIs. + * Direct SPI interrupts are still in pass through mode (no latching + * at PDC). + */ + if (pdc->mode =3D=3D PDC_PASS_THROUGH_MODE || !pdc_pin_is_gpio(hwirq)) { + ret =3D irq_domain_set_hwirq_and_chip(domain, virq, hwirq, + &qcom_pdc_gic_chip, + NULL); + if (ret) + return ret; =20 - region =3D get_pin_region(hwirq); - if (!region) - return irq_domain_disconnect_hierarchy(domain->parent, virq); + if (type & IRQ_TYPE_EDGE_BOTH) + type =3D IRQ_TYPE_EDGE_RISING; =20 - if (type & IRQ_TYPE_EDGE_BOTH) - type =3D IRQ_TYPE_EDGE_RISING; + if (type & IRQ_TYPE_LEVEL_MASK) + type =3D IRQ_TYPE_LEVEL_HIGH; + } else { + ret =3D irq_domain_set_hwirq_and_chip(domain, virq, hwirq, + &qcom_pdc_gic_secondary_chip, + NULL); + if (ret) + return ret; =20 - if (type & IRQ_TYPE_LEVEL_MASK) + /* Secondary mode converts all interrupts to LEVEL HIGH type */ type =3D IRQ_TYPE_LEVEL_HIGH; + } + + region =3D get_pin_region(hwirq); + if (!region) + return irq_domain_disconnect_hierarchy(domain->parent, virq); =20 parent_fwspec.fwnode =3D domain->parent->fwnode; parent_fwspec.param_count =3D 3; @@ -449,8 +628,13 @@ static int pdc_setup_pin_mapping(struct device *dev, s= truct device_node *np) if (ret) return ret; =20 - for (int i =3D 0; i < pdc->region[n].cnt; i++) - pdc->enable_intr(i + pdc->region[n].pin_base, 0); + for (int i =3D 0; i < pdc->region[n].cnt; i++) { + if (pdc_pin_is_gpio(i + pdc->region[n].pin_base) && + pdc->mode =3D=3D PDC_SECONDARY_MODE) + pdc->clear_gpio(i + pdc->region[n].pin_base); + + pdc->enable_intr(i + pdc->region[n].pin_base, false); + } } =20 return 0; @@ -501,6 +685,8 @@ static int qcom_pdc_probe(struct platform_device *pdev,= struct device_node *pare pdc->enable_intr =3D pdc_enable_intr_bank; } =20 + pdc->mode =3D PDC_PASS_THROUGH_MODE; + /* * PDC has multiple DRV regions, each one provides the same set of * registers for a particular client in the system. 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For level-triggered IRQs this happens automatically in irq_eoi() but for edge-triggered IRQs this needs to happen as early as possible in the IRQ handler. Implement this by using handle_fasteoi_ack_irq() as IRQ handler in this situation and forward the irq_ack() callback to the parent IRQ chip. Signed-off-by: Stephan Gerhold Signed-off-by: Maulik Shah --- drivers/pinctrl/qcom/pinctrl-msm.c | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinc= trl-msm.c index 11db6564c44d..17665e1a9dbc 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -995,6 +995,16 @@ static void msm_gpio_irq_ack(struct irq_data *d) if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) { if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) msm_gpio_update_dual_edge_parent(d); + + /* + * During early initialization of the IRQ hierarchy, + * irq_ack() is called by __irq_set_handler() before + * the parent IRQ chip has been set up. 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PDC interrupts no more break GPIOs PDC irqchip is updated to work for pass through or secondary mode. Update nwakeirq_map to reflect the GPIO to PDC irq map size. Signed-off-by: Maulik Shah --- drivers/pinctrl/qcom/pinctrl-x1e80100.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-x1e80100.c b/drivers/pinctrl/qcom= /pinctrl-x1e80100.c index 8d2b8246170b..e4c0abcd95b9 100644 --- a/drivers/pinctrl/qcom/pinctrl-x1e80100.c +++ b/drivers/pinctrl/qcom/pinctrl-x1e80100.c @@ -1836,9 +1836,7 @@ static const struct msm_pinctrl_soc_data x1e80100_pin= ctrl =3D { .ngroups =3D ARRAY_SIZE(x1e80100_groups), .ngpios =3D 239, .wakeirq_map =3D x1e80100_pdc_map, - /* TODO: Enabling PDC currently breaks GPIO interrupts */ - .nwakeirq_map =3D 0, - /* .nwakeirq_map =3D ARRAY_SIZE(x1e80100_pdc_map), */ + .nwakeirq_map =3D ARRAY_SIZE(x1e80100_pdc_map), .egpio_func =3D 9, }; =20 --=20 2.43.0 From nobody Wed Jun 24 23:24:22 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 06A91423A77 for ; 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Signed-off-by: Maulik Shah --- arch/arm64/boot/dts/qcom/hamoa.dtsi | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom= /hamoa.dtsi index 4ba751a65142..47e425003028 100644 --- a/arch/arm64/boot/dts/qcom/hamoa.dtsi +++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi @@ -302,6 +302,14 @@ cluster_cl5: cluster-sleep-1 { exit-latency-us =3D <4000>; min-residency-us =3D <7000>; }; + + domain_ss3: domain-sleep-0 { + compatible =3D "domain-idle-state"; + arm,psci-suspend-param =3D <0x0200c354>; + entry-latency-us =3D <2800>; + exit-latency-us =3D <4400>; + min-residency-us =3D <9000>; + }; }; }; =20 @@ -460,7 +468,7 @@ cluster_pd2: power-domain-cpu-cluster2 { =20 system_pd: power-domain-system { #power-domain-cells =3D <0>; - /* TODO: system-wide idle states */ + domain-idle-states =3D <&domain_ss3>; }; }; =20 --=20 2.43.0