From nobody Wed Jun 17 07:26:08 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1A1DA3BED44; Mon, 15 Jun 2026 23:10:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781565010; cv=none; b=XjsQ0r6cHiHUWfwojpNVSdZoqx/7CMxY4TmIgcuFTJBHBF7r44luM+YLxtPlxCFVYqT/BM9xfCAuyyLWC69fYbMLknTArHTPnTbR/mfe9n+1OdzIk+b6ugiiensyOzTrcVl75IcMZHmQJo9LXmL5W/5Cay4aiMn8Er4ONpJwrK0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781565010; c=relaxed/simple; bh=uu0OcTgn3CPKXcF0xjMO0RfY0krvnzHgkkThexzDjvs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=M8bbAkRkyGxyha6atCtwXUa0QpDaO1OJVCiVpako/x3SD/v/9WmLA2s+DibjVsscL7XG1AmGhHfxvEgj4qqvfezglhs8FoPuvjNZfKYepy8tSQoHw73f7bmaakYKWHAh7mBtzxxQPzZpJmNVug7jzOCEiCLu7fC2VhZYrEGgTiY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=FZT+uCZD; arc=none smtp.client-ip=198.175.65.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="FZT+uCZD" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1781565010; x=1813101010; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=uu0OcTgn3CPKXcF0xjMO0RfY0krvnzHgkkThexzDjvs=; b=FZT+uCZD5Vo8wwowbepknD4PvecqZWlrtNS7Tonvw5YCRx25Hxi2GaDc eGWxkD0O6eUOjTYjbw88JaC7OwOjErwnWCRsKVCjdiGmiqoOkAzcn/F+c 1sDnFaOCypCIxszXU+spNxHgb2ewFb66aoUuz93B/MEXajrGXZFY9U/lo 8frQ4/T0fkqWix0ro4ydczIF7+MXsvXY3pYT2dWZvh9aUz/9FSY4xCj9g Fwfny3WglfoWZs3IN8zLdYMxreIQHvbsesgCB4r2G+9TI6ldoH3Yj7gn0 Q/g2nYyibC32AyTqlwaOG5uv45NwpytO4QOlSCYR66ACsWlwRqdQ5Xi+Y A==; X-CSE-ConnectionGUID: u6PiyQhTRKyW5cKM+6Vsgg== X-CSE-MsgGUID: C/Ilpt4DQgimyO3ZNf7v1A== X-IronPort-AV: E=McAfee;i="6800,10657,11818"; a="99738593" X-IronPort-AV: E=Sophos;i="6.24,207,1774335600"; d="scan'208";a="99738593" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Jun 2026 16:10:08 -0700 X-CSE-ConnectionGUID: MRZGq3RCQKSK0Awlr3KY7g== X-CSE-MsgGUID: pINr62ocR7eYnN8FGdsidA== X-ExtLoop1: 1 Received: from 9cc2c43eec6b.jf.intel.com ([10.54.77.29]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Jun 2026 16:10:06 -0700 From: Zide Chen To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Jim Mattson , Mingwei Zhang , Zide Chen , Das Sandipan , Shukla Manali , Dapeng Mi , Falcon Thomas , Xudong Hao Subject: [PATCH V3 1/4] KVM: x86/pmu: Do not map fixed counters >= 3 to generic perf events Date: Mon, 15 Jun 2026 16:01:15 -0700 Message-ID: <20260615230118.50718-2-zide.chen@intel.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260615230118.50718-1-zide.chen@intel.com> References: <20260615230118.50718-1-zide.chen@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Only fixed counters 0..2 have matching generic cross-platform hardware perf events (INSTRUCTIONS, CPU_CYCLES, REF_CPU_CYCLES). Therefore, perf_get_hw_event_config() is only applicable to these counters. KVM does not intend to emulate fixed counters >=3D 3 on legacy (non-mediated) vPMU, while for mediated vPMU, KVM does not care what the fixed counter event mappings are. Therefore, return 0 for their eventsel. Also remove __always_inline as BUILD_BUG_ON() is no longer needed. Signed-off-by: Zide Chen --- v2: - Replace 3 in "if (index < 3)" with ARRAY_SIZE(fixed_pmc_perf_ids). --- arch/x86/kvm/vmx/pmu_intel.c | 26 ++++++++++++++------------ 1 file changed, 14 insertions(+), 12 deletions(-) diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c index a73a9515d96c..59b7a90c79e1 100644 --- a/arch/x86/kvm/vmx/pmu_intel.c +++ b/arch/x86/kvm/vmx/pmu_intel.c @@ -464,28 +464,30 @@ static int intel_pmu_set_msr(struct kvm_vcpu *vcpu, s= truct msr_data *msr_info) * different perf_event is already utilizing the requested counter, but th= e end * result is the same (ignoring the fact that using a general purpose coun= ter * will likely exacerbate counter contention). - * - * Forcibly inlined to allow asserting on @index at build time, and there = should - * never be more than one user. */ -static __always_inline u64 intel_get_fixed_pmc_eventsel(unsigned int index) +static u64 intel_get_fixed_pmc_eventsel(unsigned int index) { const enum perf_hw_id fixed_pmc_perf_ids[] =3D { [0] =3D PERF_COUNT_HW_INSTRUCTIONS, [1] =3D PERF_COUNT_HW_CPU_CYCLES, [2] =3D PERF_COUNT_HW_REF_CPU_CYCLES, }; - u64 eventsel; - - BUILD_BUG_ON(ARRAY_SIZE(fixed_pmc_perf_ids) !=3D KVM_MAX_NR_INTEL_FIXED_C= OUNTERS); - BUILD_BUG_ON(index >=3D KVM_MAX_NR_INTEL_FIXED_COUNTERS); + u64 eventsel =3D 0; =20 /* - * Yell if perf reports support for a fixed counter but perf doesn't - * have a known encoding for the associated general purpose event. + * Fixed counters 3 and above don't have corresponding generic hardware + * perf event, and KVM does not intend to emulate them on non-mediated + * vPMU. */ - eventsel =3D perf_get_hw_event_config(fixed_pmc_perf_ids[index]); - WARN_ON_ONCE(!eventsel && index < kvm_pmu_cap.num_counters_fixed); + if (index < ARRAY_SIZE(fixed_pmc_perf_ids)) { + /* + * Yell if perf reports support for a fixed counter but perf + * doesn't have a known encoding for the associated general + * purpose event. + */ + eventsel =3D perf_get_hw_event_config(fixed_pmc_perf_ids[index]); + WARN_ON_ONCE(!eventsel && index < kvm_pmu_cap.num_counters_fixed); + } return eventsel; } =20 --=20 2.54.0 From nobody Wed Jun 17 07:26:08 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 77F5E3BED76; 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a="99738599" X-IronPort-AV: E=Sophos;i="6.24,207,1774335600"; d="scan'208";a="99738599" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Jun 2026 16:10:08 -0700 X-CSE-ConnectionGUID: Ya6c8gf5TR2286HHK1dNcQ== X-CSE-MsgGUID: wlQR33UITV+MQI92+lx63w== X-ExtLoop1: 1 Received: from 9cc2c43eec6b.jf.intel.com ([10.54.77.29]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Jun 2026 16:10:06 -0700 From: Zide Chen To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Jim Mattson , Mingwei Zhang , Zide Chen , Das Sandipan , Shukla Manali , Dapeng Mi , Falcon Thomas , Xudong Hao Subject: [PATCH V3 2/4] KVM: x86/pmu: Support Intel fixed counter 3 on mediated vPMU Date: Mon, 15 Jun 2026 16:01:16 -0700 Message-ID: <20260615230118.50718-3-zide.chen@intel.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260615230118.50718-1-zide.chen@intel.com> References: <20260615230118.50718-1-zide.chen@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Dapeng Mi Starting with Ice Lake, Intel introduced fixed counter 3, which counts TOPDOWN.SLOTS - the number of available slots for an unhalted logical processor. It serves as the denominator for top-level metrics in the Top-down Microarchitecture Analysis method. Emulating this counter on legacy vPMU would require introducing a new generic perf encoding for the Intel-specific TOPDOWN.SLOTS event in order to call perf_get_hw_event_config(). This is undesirable as it would pollute the generic perf event encoding. Moreover, KVM does not intend to emulate IA32_PERF_METRICS in the legacy vPMU model, and without IA32_PERF_METRICS, emulating this counter has little practical value. Therefore, expose fixed counter 3 to guests only when mediated vPMU is enabled. Signed-off-by: Dapeng Mi Co-developed-by: Zide Chen Signed-off-by: Zide Chen --- v3: - Move the non-contiguous counter filter code to pmu.c v2: - Don't advertise fixed counter 3 to userspace if the host doesn't support it. --- arch/x86/include/asm/kvm_host.h | 2 +- arch/x86/kvm/pmu.c | 18 ++++++++++++++++++ arch/x86/kvm/x86.c | 4 ++-- 3 files changed, 21 insertions(+), 3 deletions(-) diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_hos= t.h index 3886b536c8a5..754103e7ab4d 100644 --- a/arch/x86/include/asm/kvm_host.h +++ b/arch/x86/include/asm/kvm_host.h @@ -577,7 +577,7 @@ struct kvm_pmc { #define KVM_MAX_NR_GP_COUNTERS KVM_MAX(KVM_MAX_NR_INTEL_GP_COUNTERS, \ KVM_MAX_NR_AMD_GP_COUNTERS) =20 -#define KVM_MAX_NR_INTEL_FIXED_COUNTERS 3 +#define KVM_MAX_NR_INTEL_FIXED_COUNTERS 4 #define KVM_MAX_NR_AMD_FIXED_COUNTERS 0 #define KVM_MAX_NR_FIXED_COUNTERS KVM_MAX(KVM_MAX_NR_INTEL_FIXED_COUNTERS,= \ KVM_MAX_NR_AMD_FIXED_COUNTERS) diff --git a/arch/x86/kvm/pmu.c b/arch/x86/kvm/pmu.c index b92dd2e58335..0faf580782d5 100644 --- a/arch/x86/kvm/pmu.c +++ b/arch/x86/kvm/pmu.c @@ -122,6 +122,8 @@ void kvm_init_pmu_capability(struct kvm_pmu_ops *pmu_op= s) { bool is_intel =3D boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_INTEL; int min_nr_gp_ctrs =3D pmu_ops->MIN_NR_GP_COUNTERS; + union cpuid10_edx edx; + u32 eax, ebx, ecx; =20 /* * Hybrid PMUs don't play nice with virtualization without careful @@ -169,6 +171,22 @@ void kvm_init_pmu_capability(struct kvm_pmu_ops *pmu_o= ps) kvm_pmu_cap.num_counters_fixed =3D min(kvm_pmu_cap.num_counters_fixed, KVM_MAX_NR_FIXED_COUNTERS); =20 + /* + * Intel platforms may support non-contiguous fixed counters, e.g., some + * E-core based server processors don't implement fixed counter 3. + * + * Before KVM supports non-contiguous fixed counters, make sure only + * contiguous ones are retained in kvm_pmu_cap. + */ + if (kvm_host_pmu.version >=3D 5) { + cpuid(10, &eax, &ebx, &ecx, &edx.full); + if (kvm_pmu_cap.num_counters_fixed > edx.split.num_counters_fixed) + kvm_pmu_cap.num_counters_fixed =3D edx.split.num_counters_fixed; + } + + if (!enable_mediated_pmu && kvm_pmu_cap.num_counters_fixed > 3) + kvm_pmu_cap.num_counters_fixed =3D 3; + kvm_pmu_eventsel.INSTRUCTIONS_RETIRED =3D perf_get_hw_event_config(PERF_COUNT_HW_INSTRUCTIONS); kvm_pmu_eventsel.BRANCH_INSTRUCTIONS_RETIRED =3D diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index cf122b8c3210..b9cca855bc10 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -350,7 +350,7 @@ static const u32 msrs_to_save_base[] =3D { =20 static const u32 msrs_to_save_pmu[] =3D { MSR_ARCH_PERFMON_FIXED_CTR0, MSR_ARCH_PERFMON_FIXED_CTR1, - MSR_ARCH_PERFMON_FIXED_CTR0 + 2, + MSR_ARCH_PERFMON_FIXED_CTR2, MSR_ARCH_PERFMON_FIXED_CTR3, MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_CORE_PERF_GLOBAL_STATUS, MSR_CORE_PERF_GLOBAL_CTRL, MSR_IA32_PEBS_ENABLE, MSR_IA32_DS_AREA, MSR_PEBS_DATA_CFG, @@ -7742,7 +7742,7 @@ static void kvm_init_msr_lists(void) { unsigned i; =20 - BUILD_BUG_ON_MSG(KVM_MAX_NR_FIXED_COUNTERS !=3D 3, + BUILD_BUG_ON_MSG(KVM_MAX_NR_FIXED_COUNTERS !=3D 4, "Please update the fixed PMCs in msrs_to_save_pmu[]"); =20 num_msrs_to_save =3D 0; --=20 2.54.0 From nobody Wed Jun 17 07:26:08 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 39BE53BFE38; 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a="99738603" X-IronPort-AV: E=Sophos;i="6.24,207,1774335600"; d="scan'208";a="99738603" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Jun 2026 16:10:08 -0700 X-CSE-ConnectionGUID: U9BGZOccQRyMD1JqWS5O+g== X-CSE-MsgGUID: wFCCThigQJWnbgtE0BANRw== X-ExtLoop1: 1 Received: from 9cc2c43eec6b.jf.intel.com ([10.54.77.29]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Jun 2026 16:10:07 -0700 From: Zide Chen To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Jim Mattson , Mingwei Zhang , Zide Chen , Das Sandipan , Shukla Manali , Dapeng Mi , Falcon Thomas , Xudong Hao Subject: [PATCH V3 3/4] KVM: x86/pmu: Support PERF_METRICS MSR in mediated vPMU Date: Mon, 15 Jun 2026 16:01:17 -0700 Message-ID: <20260615230118.50718-4-zide.chen@intel.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260615230118.50718-1-zide.chen@intel.com> References: <20260615230118.50718-1-zide.chen@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Dapeng Mi Bit 15 in IA32_PERF_CAPABILITIES indicates that the CPU provides built-in support for Topdown Microarchitecture Analysis (TMA) L1 metrics via the IA32_PERF_METRICS MSR. Expose this capability only when mediated vPMU is enabled, as emulating IA32_PERF_METRICS in the legacy vPMU model is impractical. Pass IA32_PERF_METRICS through to the guest only when mediated vPMU is enabled and bit 15 is set in guest IA32_PERF_CAPABILITIES. Allow kvm_pmu_{get,set}_msr() to handle this MSR for host accesses. Save and restore this MSR on host/guest PMU context switches so that host PMU activity does not clobber the guest value, and guest state is not leaked into the host. Signed-off-by: Dapeng Mi Signed-off-by: Zide Chen --- v3: - Replace WARN_ON() with WARN_ON_ONCE(). (Dapeng) - Add comments to explain why don't validate writes on PERF_METRICS. --- arch/x86/include/asm/kvm_host.h | 1 + arch/x86/include/asm/msr-index.h | 1 + arch/x86/include/asm/perf_event.h | 1 + arch/x86/kvm/vmx/pmu_intel.c | 36 +++++++++++++++++++++++++++++++ arch/x86/kvm/vmx/pmu_intel.h | 5 +++++ arch/x86/kvm/vmx/vmx.c | 6 ++++++ arch/x86/kvm/x86.c | 6 +++++- 7 files changed, 55 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_hos= t.h index 754103e7ab4d..9b03475843f3 100644 --- a/arch/x86/include/asm/kvm_host.h +++ b/arch/x86/include/asm/kvm_host.h @@ -597,6 +597,7 @@ struct kvm_pmu { u64 global_status_rsvd; u64 reserved_bits; u64 raw_event_mask; + u64 perf_metrics; struct kvm_pmc gp_counters[KVM_MAX_NR_GP_COUNTERS]; struct kvm_pmc fixed_counters[KVM_MAX_NR_FIXED_COUNTERS]; =20 diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-in= dex.h index 18c4be75e927..fdcaeb6c8352 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -331,6 +331,7 @@ #define PERF_CAP_PEBS_FORMAT 0xf00 #define PERF_CAP_FW_WRITES BIT_ULL(13) #define PERF_CAP_PEBS_BASELINE BIT_ULL(14) +#define PERF_CAP_PERF_METRICS BIT_ULL(15) #define PERF_CAP_PEBS_TIMING_INFO BIT_ULL(17) #define PERF_CAP_PEBS_MASK (PERF_CAP_PEBS_TRAP | PERF_CAP_ARCH_REG | \ PERF_CAP_PEBS_FORMAT | PERF_CAP_PEBS_BASELINE | \ diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_= event.h index 1eb13673e889..bc2e1cbcd9b9 100644 --- a/arch/x86/include/asm/perf_event.h +++ b/arch/x86/include/asm/perf_event.h @@ -447,6 +447,7 @@ static inline bool is_topdown_idx(int idx) #define GLOBAL_STATUS_ARCH_PEBS_THRESHOLD_BIT 54 #define GLOBAL_STATUS_ARCH_PEBS_THRESHOLD BIT_ULL(GLOBAL_STATUS_ARCH_PEBS_= THRESHOLD_BIT) #define GLOBAL_STATUS_PERF_METRICS_OVF_BIT 48 +#define GLOBAL_STATUS_PERF_METRICS_OVF BIT_ULL(GLOBAL_STATUS_PERF_METRICS= _OVF_BIT) =20 #define GLOBAL_CTRL_EN_PERF_METRICS BIT_ULL(48) /* diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c index 59b7a90c79e1..19daee29b731 100644 --- a/arch/x86/kvm/vmx/pmu_intel.c +++ b/arch/x86/kvm/vmx/pmu_intel.c @@ -188,6 +188,8 @@ static bool intel_is_valid_msr(struct kvm_vcpu *vcpu, u= 32 msr) switch (msr) { case MSR_CORE_PERF_FIXED_CTR_CTRL: return kvm_pmu_has_perf_global_ctrl(pmu); + case MSR_PERF_METRICS: + return vcpu_has_perf_metrics(vcpu); case MSR_IA32_PEBS_ENABLE: ret =3D vcpu_get_perf_capabilities(vcpu) & PERF_CAP_PEBS_FORMAT; break; @@ -345,6 +347,10 @@ static int intel_pmu_get_msr(struct kvm_vcpu *vcpu, st= ruct msr_data *msr_info) case MSR_CORE_PERF_FIXED_CTR_CTRL: msr_info->data =3D pmu->fixed_ctr_ctrl; break; + case MSR_PERF_METRICS: + WARN_ON_ONCE(!msr_info->host_initiated); + msr_info->data =3D pmu->perf_metrics; + break; case MSR_IA32_PEBS_ENABLE: msr_info->data =3D pmu->pebs_enable; break; @@ -394,6 +400,15 @@ static int intel_pmu_set_msr(struct kvm_vcpu *vcpu, st= ruct msr_data *msr_info) if (pmu->fixed_ctr_ctrl !=3D data) reprogram_fixed_counters(pmu, data); break; + case MSR_PERF_METRICS: + WARN_ON_ONCE(!msr_info->host_initiated); + + /* + * If TMA level 2 is not supported, bits [63:32] are reserved + * and ignored on write, so no validation is needed here. + */ + pmu->perf_metrics =3D data; + break; case MSR_IA32_PEBS_ENABLE: if (data & pmu->pebs_enable_rsvd) return 1; @@ -589,6 +604,11 @@ static void intel_pmu_refresh(struct kvm_vcpu *vcpu) pmu->global_status_rsvd &=3D ~MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI; =20 + if (perf_capabilities & PERF_CAP_PERF_METRICS) { + pmu->global_ctrl_rsvd &=3D ~GLOBAL_CTRL_EN_PERF_METRICS; + pmu->global_status_rsvd &=3D ~GLOBAL_STATUS_PERF_METRICS_OVF; + } + if (perf_capabilities & PERF_CAP_PEBS_FORMAT) { if (perf_capabilities & PERF_CAP_PEBS_BASELINE) { pmu->pebs_enable_rsvd =3D counter_rsvd; @@ -632,6 +652,9 @@ static void intel_pmu_init(struct kvm_vcpu *vcpu) =20 static void intel_pmu_reset(struct kvm_vcpu *vcpu) { + struct kvm_pmu *pmu =3D vcpu_to_pmu(vcpu); + + pmu->perf_metrics =3D 0; intel_pmu_release_guest_lbr_event(vcpu); } =20 @@ -803,6 +826,13 @@ static void intel_mediated_pmu_load(struct kvm_vcpu *v= cpu) struct kvm_pmu *pmu =3D vcpu_to_pmu(vcpu); u64 global_status, toggle; =20 + /* + * PERF_METRICS MSR must be restored closely after fixed counter 3 + * (kvm_pmu_load_guest_pmcs()). + */ + if (vcpu_has_perf_metrics(vcpu)) + wrmsrq(MSR_PERF_METRICS, pmu->perf_metrics); + rdmsrq(MSR_CORE_PERF_GLOBAL_STATUS, global_status); toggle =3D pmu->global_status ^ global_status; if (global_status & toggle) @@ -831,6 +861,12 @@ static void intel_mediated_pmu_put(struct kvm_vcpu *vc= pu) */ if (pmu->fixed_ctr_ctrl_hw) wrmsrq(MSR_CORE_PERF_FIXED_CTR_CTRL, 0); + + if (vcpu_has_perf_metrics(vcpu)) { + pmu->perf_metrics =3D rdpmc(INTEL_PMC_FIXED_RDPMC_METRICS); + if (pmu->perf_metrics) + wrmsrq(MSR_PERF_METRICS, 0); + } } =20 struct kvm_pmu_ops intel_pmu_ops __initdata =3D { diff --git a/arch/x86/kvm/vmx/pmu_intel.h b/arch/x86/kvm/vmx/pmu_intel.h index 5d9357640aa1..2ec547223b09 100644 --- a/arch/x86/kvm/vmx/pmu_intel.h +++ b/arch/x86/kvm/vmx/pmu_intel.h @@ -40,4 +40,9 @@ struct lbr_desc { =20 extern struct x86_pmu_lbr vmx_lbr_caps; =20 +static inline bool vcpu_has_perf_metrics(struct kvm_vcpu *vcpu) +{ + return !!(vcpu_get_perf_capabilities(vcpu) & PERF_CAP_PERF_METRICS); +} + #endif /* __KVM_X86_VMX_PMU_INTEL_H */ diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index c548f22375ad..7cffe1619a1f 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -4264,6 +4264,9 @@ static void vmx_recalc_pmu_msr_intercepts(struct kvm_= vcpu *vcpu) MSR_TYPE_RW, intercept); vmx_set_intercept_for_msr(vcpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, MSR_TYPE_RW, intercept); + + vmx_set_intercept_for_msr(vcpu, MSR_PERF_METRICS, MSR_TYPE_RW, + !vcpu_has_perf_metrics(vcpu)); } =20 static void vmx_recalc_msr_intercepts(struct kvm_vcpu *vcpu) @@ -8088,6 +8091,9 @@ static __init u64 vmx_get_perf_capabilities(void) perf_cap &=3D ~PERF_CAP_PEBS_BASELINE; } =20 + if (enable_mediated_pmu) + perf_cap |=3D host_perf_cap & PERF_CAP_PERF_METRICS; + return perf_cap; } =20 diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index b9cca855bc10..2ac297ba3598 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -352,7 +352,7 @@ static const u32 msrs_to_save_pmu[] =3D { MSR_ARCH_PERFMON_FIXED_CTR0, MSR_ARCH_PERFMON_FIXED_CTR1, MSR_ARCH_PERFMON_FIXED_CTR2, MSR_ARCH_PERFMON_FIXED_CTR3, MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_CORE_PERF_GLOBAL_STATUS, - MSR_CORE_PERF_GLOBAL_CTRL, + MSR_CORE_PERF_GLOBAL_CTRL, MSR_PERF_METRICS, MSR_IA32_PEBS_ENABLE, MSR_IA32_DS_AREA, MSR_PEBS_DATA_CFG, =20 /* This part of MSRs should match KVM_MAX_NR_INTEL_GP_COUNTERS. */ @@ -7679,6 +7679,10 @@ static void kvm_probe_msr_to_save(u32 msr_index) intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2)) return; break; + case MSR_PERF_METRICS: + if (!(kvm_caps.supported_perf_cap & PERF_CAP_PERF_METRICS)) + return; + break; case MSR_ARCH_PERFMON_PERFCTR0 ... MSR_ARCH_PERFMON_PERFCTR0 + KVM_MAX_NR_GP_COUNTERS - 1: if (msr_index - MSR_ARCH_PERFMON_PERFCTR0 >=3D --=20 2.54.0 From nobody Wed Jun 17 07:26:08 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 39C7F3BFE3A; Mon, 15 Jun 2026 23:10:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781565016; cv=none; b=LDn8WCbKvrkpA8yaF7KrdZ9FmMaG9oReuEqHyikBw2GMthbJZelqPd5MOwDf1W9NIzWuxSiCM1K68u7uj3rHwtxj21npPlV16WhZyBnHfCDMV+DyanHHm8syMaAcCa/x1sI9Zu31x2nzKNzSkpEmKa06c1ENKLjlkblVfLytrXM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781565016; c=relaxed/simple; bh=Hx7BNwD2GIEFBYxeKQ5msWLCZhL6lQHoZdWJ0g1xYmM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=fwPnyV3Fjzvgpx5QxZKWXfia+Bie5UJFJL1MN0FOLYc5rOXjU5YLCw6lwS6FRRGzfBpdpdxZnDPj22OTpodm5IjKAOkMraTGuPKz2xsMhihU237JvkH+fAFN4vNueYfSMV2UuLnK/IvI0WDiO/YSIWdZ6NsmhMhbHIPEXg4zn/s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=IvYNcJNz; arc=none smtp.client-ip=198.175.65.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="IvYNcJNz" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1781565012; x=1813101012; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Hx7BNwD2GIEFBYxeKQ5msWLCZhL6lQHoZdWJ0g1xYmM=; b=IvYNcJNzlxgQAk1fRbdnKuXjcB5AO7gTwlV+/6z6413umaMa7VmbI+3D JYfML4VsV8MmTjYWIOP3n6wdRFOmaA24kjJU/51+tb/ah/2Hj4zE0dlvC oZrv1zO+Mce9eCCOb9h4Qg8XizTwGh3mqBZR6MvC8sbnSpQjb8aLkkP/r xyrHA24COvX+GFdVsP9cwtIWIO2ePb9xi0C282bAIa1lSxybtufWjRVnC K17iZKJPRtPGyh8jEKu76oIqB+zVDewmleyKNOn958z3gNV+ZSxq7wHmh 0nqEW/TqsowSSEYFtDry2gjviuRqx5JvpCr837PZmOFpmDZvQKi2jMf2O g==; X-CSE-ConnectionGUID: CpeLAbwTQ8y4PVwr6jmtWA== X-CSE-MsgGUID: r/naJvBFSOyU4V1YXehemg== X-IronPort-AV: E=McAfee;i="6800,10657,11818"; a="99738608" X-IronPort-AV: E=Sophos;i="6.24,207,1774335600"; d="scan'208";a="99738608" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Jun 2026 16:10:08 -0700 X-CSE-ConnectionGUID: 7KbJBpeVTuC3RQAqCPi0Sw== X-CSE-MsgGUID: 2lFOpIyyRoCtBW7uR+7rQw== X-ExtLoop1: 1 Received: from 9cc2c43eec6b.jf.intel.com ([10.54.77.29]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Jun 2026 16:10:07 -0700 From: Zide Chen To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Jim Mattson , Mingwei Zhang , Zide Chen , Das Sandipan , Shukla Manali , Dapeng Mi , Falcon Thomas , Xudong Hao Subject: [PATCH V3 4/4] KVM: selftests: Add perf_metrics and fixed counter 3 tests Date: Mon, 15 Jun 2026 16:01:18 -0700 Message-ID: <20260615230118.50718-5-zide.chen@intel.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260615230118.50718-1-zide.chen@intel.com> References: <20260615230118.50718-1-zide.chen@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a selftest to exercise IA32_PERF_METRICS, i.e. architectural support for Topdown (TMA) Level 1 metrics, enumerated by IA32_PERF_CAPABILITIES[15]. Only check for non-zero metrics, as they are derived and depend on the workload, CPU model, and host scheduling, making precise expectations fragile. Extend the PMU selftest to cover Intel fixed counter 3 by bumping MAX_NR_FIXED_COUNTERS to 4 and validating basic functionality. Signed-off-by: Zide Chen --- v3: - Slightly reword comment to explain the sum of topdown metrics is close to 100%. - Change abs() with explicit bounds (sum >=3D 0xfd && sum <=3D 0x102) for better readability. v2: - New patch. --- --- tools/arch/x86/include/asm/msr-index.h | 1 + tools/testing/selftests/kvm/include/x86/pmu.h | 3 + .../selftests/kvm/x86/pmu_counters_test.c | 72 +++++++++++++++++-- 3 files changed, 71 insertions(+), 5 deletions(-) diff --git a/tools/arch/x86/include/asm/msr-index.h b/tools/arch/x86/includ= e/asm/msr-index.h index eff29645719b..e7745e2cd543 100644 --- a/tools/arch/x86/include/asm/msr-index.h +++ b/tools/arch/x86/include/asm/msr-index.h @@ -331,6 +331,7 @@ #define PERF_CAP_PEBS_FORMAT 0xf00 #define PERF_CAP_FW_WRITES BIT_ULL(13) #define PERF_CAP_PEBS_BASELINE BIT_ULL(14) +#define PERF_CAP_PERF_METRICS BIT_ULL(15) #define PERF_CAP_PEBS_TIMING_INFO BIT_ULL(17) #define PERF_CAP_PEBS_MASK (PERF_CAP_PEBS_TRAP | PERF_CAP_ARCH_REG | \ PERF_CAP_PEBS_FORMAT | PERF_CAP_PEBS_BASELINE | \ diff --git a/tools/testing/selftests/kvm/include/x86/pmu.h b/tools/testing/= selftests/kvm/include/x86/pmu.h index 608ed83d7c6a..6c19503e0bb7 100644 --- a/tools/testing/selftests/kvm/include/x86/pmu.h +++ b/tools/testing/selftests/kvm/include/x86/pmu.h @@ -52,6 +52,9 @@ /* Fixed PMC controls, Intel only. */ #define FIXED_PMC_GLOBAL_CTRL_ENABLE(_idx) BIT_ULL((32 + (_idx))) =20 +/* PERF_METRICS enable, Intel only. */ +#define PERF_METRICS_GLOBAL_CTRL_ENABLE BIT_ULL(48) + #define FIXED_PMC_KERNEL BIT_ULL(0) #define FIXED_PMC_USER BIT_ULL(1) #define FIXED_PMC_ANYTHREAD BIT_ULL(2) diff --git a/tools/testing/selftests/kvm/x86/pmu_counters_test.c b/tools/te= sting/selftests/kvm/x86/pmu_counters_test.c index dc6afac3aa91..d4688a7d1e55 100644 --- a/tools/testing/selftests/kvm/x86/pmu_counters_test.c +++ b/tools/testing/selftests/kvm/x86/pmu_counters_test.c @@ -6,6 +6,7 @@ =20 #include "pmu.h" #include "processor.h" +#include =20 /* Number of iterations of the loop for the guest measurement payload. */ #define NUM_LOOPS 10 @@ -241,17 +242,20 @@ do { \ ); \ } while (0) =20 -#define GUEST_TEST_EVENT(_idx, _pmc, _pmc_msr, _ctrl_msr, _value, FEP) \ +#define GUEST_RUN_PAYLOAD(_ctrl_msr, _value, FEP) \ do { \ - wrmsr(_pmc_msr, 0); \ - \ if (this_cpu_has(X86_FEATURE_CLFLUSHOPT)) \ GUEST_MEASURE_EVENT(_ctrl_msr, _value, "clflushopt %[m]", FEP); \ else if (this_cpu_has(X86_FEATURE_CLFLUSH)) \ GUEST_MEASURE_EVENT(_ctrl_msr, _value, "clflush %[m]", FEP); \ else \ GUEST_MEASURE_EVENT(_ctrl_msr, _value, "nop", FEP); \ - \ +} while (0) + +#define GUEST_TEST_EVENT(_idx, _pmc, _pmc_msr, _ctrl_msr, _value, FEP) \ +do { \ + wrmsr(_pmc_msr, 0); \ + GUEST_RUN_PAYLOAD(_ctrl_msr, _value, FEP); \ guest_assert_event_count(_idx, _pmc, _pmc_msr); \ } while (0) =20 @@ -318,6 +322,56 @@ static void guest_test_arch_event(u8 idx) FIXED_PMC_GLOBAL_CTRL_ENABLE(i)); } =20 +static void guest_test_perf_metrics(void) +{ + int retiring, bad_spec, fe_bound, be_bound, sum; + u64 global_ctrl, metrics; + + if ((guest_get_pmu_version() < 2) || /* Does guest have GLOBAL_CTRL? */ + !this_cpu_has(X86_FEATURE_PDCM) || + !(rdmsr(MSR_IA32_PERF_CAPABILITIES) & PERF_CAP_PERF_METRICS)) + return; + + wrmsr(MSR_CORE_PERF_GLOBAL_CTRL, 0); + wrmsr(MSR_CORE_PERF_FIXED_CTR3, 0); + wrmsr(MSR_PERF_METRICS, 0); + + /* Enable fixed ctr3 (TOPDOWN.SLOTS) and PERF_METRICS. */ + wrmsr(MSR_CORE_PERF_FIXED_CTR_CTRL, FIXED_PMC_CTRL(3, FIXED_PMC_KERNEL)); + global_ctrl =3D FIXED_PMC_GLOBAL_CTRL_ENABLE(3) | + PERF_METRICS_GLOBAL_CTRL_ENABLE; + + GUEST_RUN_PAYLOAD(MSR_CORE_PERF_GLOBAL_CTRL, global_ctrl, ""); + + /* Check test results. */ + metrics =3D rdmsr(MSR_PERF_METRICS); + retiring =3D FIELD_GET(GENMASK_ULL(7, 0), metrics); + bad_spec =3D FIELD_GET(GENMASK_ULL(15, 8), metrics); + fe_bound =3D FIELD_GET(GENMASK_ULL(23, 16), metrics); + be_bound =3D FIELD_GET(GENMASK_ULL(31, 24), metrics); + + /* + * Be conservative: the measured payload definitely retires work, so + * Retiring should be non-zero. + */ + GUEST_ASSERT_NE(metrics, 0ULL); + GUEST_ASSERT_NE(retiring, 0ULL); + + /* + * The sum of the 4 level-1 topdown metrics should be close to 100%. + * 3 is chosen as a loose sanity check. + */ + sum =3D retiring + bad_spec + fe_bound + be_bound; + GUEST_ASSERT(sum >=3D 0xfd && sum <=3D 0x102); + + /* Sanity check after PERF_METRICS disabled. */ + __asm__ __volatile__("loop ." : "+c"((int){NUM_LOOPS})); + GUEST_ASSERT_EQ(rdmsr(MSR_PERF_METRICS), metrics); + wrmsr(MSR_PERF_METRICS, 0xdeaddead); + + GUEST_ASSERT_EQ(rdmsr(MSR_PERF_METRICS), 0xdeaddead); +} + static void guest_test_arch_events(void) { u8 i; @@ -325,6 +379,8 @@ static void guest_test_arch_events(void) for (i =3D 0; i < NR_INTEL_ARCH_EVENTS; i++) guest_test_arch_event(i); =20 + guest_test_perf_metrics(); + GUEST_DONE(); } =20 @@ -361,7 +417,7 @@ static void test_arch_events(u8 pmu_version, u64 perf_c= apabilities, * other than PMCs in the future. */ #define MAX_NR_GP_COUNTERS 8 -#define MAX_NR_FIXED_COUNTERS 3 +#define MAX_NR_FIXED_COUNTERS 4 =20 #define GUEST_ASSERT_PMC_MSR_ACCESS(insn, msr, expect_gp, vector) \ __GUEST_ASSERT(expect_gp ? vector =3D=3D GP_VECTOR : !vector, \ @@ -585,6 +641,7 @@ static void test_intel_counters(void) u8 nr_fixed_counters =3D kvm_cpu_property(X86_PROPERTY_PMU_NR_FIXED_COUNT= ERS); u8 nr_gp_counters =3D kvm_cpu_property(X86_PROPERTY_PMU_NR_GP_COUNTERS); u8 pmu_version =3D kvm_cpu_property(X86_PROPERTY_PMU_VERSION); + u64 advertised_perf_caps =3D kvm_get_feature_msr(MSR_IA32_PERF_CAPABILITI= ES); unsigned int i; u8 v, j; u32 k; @@ -592,6 +649,7 @@ static void test_intel_counters(void) const u64 perf_caps[] =3D { 0, PMU_CAP_FW_WRITES, + PERF_CAP_PERF_METRICS, }; =20 /* @@ -649,6 +707,10 @@ static void test_intel_counters(void) if (!kvm_has_perf_caps && perf_caps[i]) continue; =20 + /* Ignore unsupported features. */ + if (perf_caps[i] & ~advertised_perf_caps) + continue; + pr_info("Testing arch events, PMU version %u, perf_caps =3D %lx\n", v, perf_caps[i]); =20 --=20 2.54.0