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Mon, 15 Jun 2026 09:49:00 -0700 (PDT) From: Neil Armstrong Date: Mon, 15 Jun 2026 18:48:56 +0200 Subject: [PATCH v3 1/3] arm64: dts: qcom: sm8650: update the cpus capacity-dmips-mhz Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260615-topic-sm8650-upstream-cpu-props-v3-1-eeb6e9fa7581@linaro.org> References: <20260615-topic-sm8650-upstream-cpu-props-v3-0-eeb6e9fa7581@linaro.org> In-Reply-To: <20260615-topic-sm8650-upstream-cpu-props-v3-0-eeb6e9fa7581@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong , Konrad Dybcio X-Mailer: b4 0.15.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=2456; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=4HjNMydN5tW67EpwgcKq0bJylrgzUaRgs8yaNRqheFs=; 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Reviewed-by: Konrad Dybcio Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qco= m/sm8650.dtsi index 160ead25ecf7..e8e43ddc3032 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -153,7 +153,7 @@ cpu2: cpu@200 { =20 enable-method =3D "psci"; next-level-cache =3D <&l2_200>; - capacity-dmips-mhz =3D <1792>; + capacity-dmips-mhz =3D <2909>; dynamic-power-coefficient =3D <238>; =20 qcom,freq-domain =3D <&cpufreq_hw 3>; @@ -189,7 +189,7 @@ cpu3: cpu@300 { =20 enable-method =3D "psci"; next-level-cache =3D <&l2_300>; - capacity-dmips-mhz =3D <1792>; + capacity-dmips-mhz =3D <2909>; dynamic-power-coefficient =3D <238>; =20 qcom,freq-domain =3D <&cpufreq_hw 3>; @@ -225,7 +225,7 @@ cpu4: cpu@400 { =20 enable-method =3D "psci"; next-level-cache =3D <&l2_400>; - capacity-dmips-mhz =3D <1792>; + capacity-dmips-mhz =3D <2909>; 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Mon, 15 Jun 2026 09:49:02 -0700 (PDT) Received: from arrakeen.starnux.net ([2a01:e0a:106d:1080:52eb:f6ff:feb3:451a]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4922fa58f80sm5670735e9.11.2026.06.15.09.49.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Jun 2026 09:49:01 -0700 (PDT) From: Neil Armstrong Date: Mon, 15 Jun 2026 18:48:57 +0200 Subject: [PATCH v3 2/3] arm64: dts: qcom: sm8650: add CPU cache size properties Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260615-topic-sm8650-upstream-cpu-props-v3-2-eeb6e9fa7581@linaro.org> References: <20260615-topic-sm8650-upstream-cpu-props-v3-0-eeb6e9fa7581@linaro.org> In-Reply-To: <20260615-topic-sm8650-upstream-cpu-props-v3-0-eeb6e9fa7581@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong , Konrad Dybcio X-Mailer: b4 0.15.1 X-Developer-Signature: v=1; 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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Add the L1 cache size and its line size (cache-size and cache-line-size) with the corresponding L1-I cache and L1-D cache. L1 cache is unified, but clidr_el1 register (get_cache_type) tells that L1 cache is separated (CACHE_TYPE_SEPARATE), add i-cache-line-size and d-cache-line-size and cache-line-size of L3 cache is specified. All cache line sizes were confirmed by checking ccsidr_el1. Reviewed-by: Konrad Dybcio Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 56 ++++++++++++++++++++++++++++++++= ++++ 1 file changed, 56 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qco= m/sm8650.dtsi index e8e43ddc3032..090a4739ebc1 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -75,6 +75,11 @@ cpu0: cpu@0 { compatible =3D "arm,cortex-a520"; reg =3D <0 0>; =20 + i-cache-size =3D <65536>; + i-cache-line-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-line-size =3D <64>; + clocks =3D <&cpufreq_hw 0>; =20 power-domains =3D <&cpu_pd0>; @@ -103,11 +108,15 @@ l2_0: l2-cache { cache-level =3D <2>; cache-unified; next-level-cache =3D <&l3_0>; + cache-size =3D <524288>; + cache-line-size =3D <64>; =20 l3_0: l3-cache { compatible =3D "cache"; cache-level =3D <3>; cache-unified; + cache-size =3D <12582912>; + cache-line-size =3D <64>; }; }; }; @@ -117,6 +126,11 @@ cpu1: cpu@100 { compatible =3D "arm,cortex-a520"; reg =3D <0 0x100>; =20 + i-cache-size =3D <65536>; + i-cache-line-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-line-size =3D <64>; + clocks =3D <&cpufreq_hw 0>; =20 power-domains =3D <&cpu_pd1>; @@ -146,6 +160,11 @@ cpu2: cpu@200 { compatible =3D "arm,cortex-a720"; reg =3D <0 0x200>; =20 + i-cache-size =3D <65536>; + i-cache-line-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-line-size =3D <64>; + clocks =3D <&cpufreq_hw 3>; =20 power-domains =3D <&cpu_pd2>; @@ -174,6 +193,8 @@ l2_200: l2-cache { cache-level =3D <2>; cache-unified; next-level-cache =3D <&l3_0>; + cache-size =3D <524288>; + cache-line-size =3D <64>; }; }; =20 @@ -182,6 +203,11 @@ cpu3: cpu@300 { compatible =3D "arm,cortex-a720"; reg =3D <0 0x300>; =20 + i-cache-size =3D <65536>; + i-cache-line-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-line-size =3D <64>; + clocks =3D <&cpufreq_hw 3>; =20 power-domains =3D <&cpu_pd3>; @@ -210,6 +236,8 @@ l2_300: l2-cache { cache-level =3D <2>; cache-unified; next-level-cache =3D <&l3_0>; + cache-size =3D <524288>; + cache-line-size =3D <64>; }; }; =20 @@ -218,6 +246,11 @@ cpu4: cpu@400 { compatible =3D "arm,cortex-a720"; reg =3D <0 0x400>; =20 + i-cache-size =3D <65536>; + i-cache-line-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-line-size =3D <64>; + clocks =3D <&cpufreq_hw 3>; =20 power-domains =3D <&cpu_pd4>; @@ -246,6 +279,8 @@ l2_400: l2-cache { cache-level =3D <2>; cache-unified; next-level-cache =3D <&l3_0>; + cache-size =3D <524288>; + cache-line-size =3D <64>; }; }; =20 @@ -254,6 +289,11 @@ cpu5: cpu@500 { compatible =3D "arm,cortex-a720"; reg =3D <0 0x500>; =20 + i-cache-size =3D <65536>; + i-cache-line-size =3D <64>; + d-cache-size =3D <65536>; + d-cache-line-size =3D <64>; + clocks =3D <&cpufreq_hw 1>; =20 power-domains =3D <&cpu_pd5>; @@ -282,6 +322,8 @@ l2_500: l2-cache { cache-level =3D <2>; cache-unified; next-level-cache =3D <&l3_0>; + cache-size =3D <524288>; + cache-line-size =3D <64>; }; }; =20 @@ -290,6 +332,11 @@ cpu6: cpu@600 { compatible =3D "arm,cortex-a720"; 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Mon, 15 Jun 2026 09:49:02 -0700 (PDT) Received: from arrakeen.starnux.net ([2a01:e0a:106d:1080:52eb:f6ff:feb3:451a]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4922fa58f80sm5670735e9.11.2026.06.15.09.49.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Jun 2026 09:49:02 -0700 (PDT) From: Neil Armstrong Date: Mon, 15 Jun 2026 18:48:58 +0200 Subject: [PATCH v3 3/3] arm64: dts: qcom: sm8650: fix soundwire ports properties Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260615-topic-sm8650-upstream-cpu-props-v3-3-eeb6e9fa7581@linaro.org> References: <20260615-topic-sm8650-upstream-cpu-props-v3-0-eeb6e9fa7581@linaro.org> In-Reply-To: <20260615-topic-sm8650-upstream-cpu-props-v3-0-eeb6e9fa7581@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong , Krzysztof Kozlowski X-Mailer: b4 0.15.1 X-Developer-Signature: v=1; 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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Since commit 9e53a66a2f2f ("soundwire: qcom: deprecate qcom,din/out-ports"), the ports are checked against the actul hardware configuration, leading to: qcom-soundwire 6ad0000.soundwire: din-ports (0) mismatch with controller (1) qcom-soundwire 6d30000.soundwire: dout-ports (0) mismatch with controller (= 1) Fix the ports count and properties of the corresponding soundwire controllers. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 42 ++++++++++++++++++--------------= ---- 1 file changed, 21 insertions(+), 21 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qco= m/sm8650.dtsi index 090a4739ebc1..b1293fdb1481 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -4734,18 +4734,18 @@ swr1: soundwire@6ad0000 { pinctrl-0 =3D <&rx_swr_active>; pinctrl-names =3D "default"; =20 - qcom,din-ports =3D <0>; + qcom,din-ports =3D <1>; qcom,dout-ports =3D <11>; =20 - qcom,ports-sinterval =3D /bits/ 16 <0x03 0x1f 0x1f 0x07 0x03 0xff 0xff= 0x31 0xff 0xff 0xff>; - qcom,ports-offset1 =3D /bits/ 8 <0x00 0x00 0x0b 0x09 0x01 0xff 0xff 0x= 00 0xff 0xff 0xff>; - qcom,ports-offset2 =3D /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0xff 0xff 0x= 00 0xff 0xff 0xff>; - qcom,ports-hstart =3D /bits/ 8 <0xff 0x03 0xff 0xff 0xff 0xff 0xff 0x0= 0 0xff 0xff 0xff>; - qcom,ports-hstop =3D /bits/ 8 <0xff 0x06 0xff 0xff 0xff 0xff 0xff 0x0f= 0xff 0xff 0xff>; - qcom,ports-word-length =3D /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0xff 0xff= 0x18 0xff 0xff 0xff>; - qcom,ports-block-pack-mode =3D /bits/ 8 <0xff 0x00 0x01 0xff 0xff 0xff = 0xff 0x01 0xff 0xff 0xff>; - qcom,ports-block-group-count =3D /bits/ 8 <0xff 0xff 0xff 0x01 0x03 0xf= f 0xff 0x00 0xff 0xff 0xff>; - qcom,ports-lane-control =3D /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0xff 0xf= f 0x01 0xff 0xff 0xff>; + qcom,ports-sinterval =3D /bits/ 16 <0x03 0x1f 0x1f 0x07 0x03 0xff 0xff= 0x31 0xff 0xff 0xff 0xff>; + qcom,ports-offset1 =3D /bits/ 8 <0x00 0x00 0x0b 0x09 0x01 0xff 0xff 0x= 00 0xff 0xff 0xff 0xff>; + qcom,ports-offset2 =3D /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0xff 0xff 0x= 00 0xff 0xff 0xff 0xff>; + qcom,ports-hstart =3D /bits/ 8 <0xff 0x03 0xff 0xff 0xff 0xff 0xff 0x0= 0 0xff 0xff 0xff 0xff>; + qcom,ports-hstop =3D /bits/ 8 <0xff 0x06 0xff 0xff 0xff 0xff 0xff 0x0f= 0xff 0xff 0xff 0xff>; + qcom,ports-word-length =3D /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0xff 0xff= 0x18 0xff 0xff 0xff 0xff>; + qcom,ports-block-pack-mode =3D /bits/ 8 <0xff 0x00 0x01 0xff 0xff 0xff = 0xff 0x01 0xff 0xff 0xff 0xff>; + qcom,ports-block-group-count =3D /bits/ 8 <0xff 0xff 0xff 0x01 0x03 0xf= f 0xff 0x00 0xff 0xff 0xff 0xff>; + qcom,ports-lane-control =3D /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0xff 0xf= f 0x01 0xff 0xff 0xff 0xff>; =20 #address-cells =3D <2>; #size-cells =3D <0>; @@ -4831,17 +4831,17 @@ swr2: soundwire@6d30000 { pinctrl-names =3D "default"; =20 qcom,din-ports =3D <4>; - qcom,dout-ports =3D <0>; - - qcom,ports-sinterval-low =3D /bits/ 8 <0x01 0x01 0x03 0x03>; - qcom,ports-offset1 =3D /bits/ 8 <0x00 0x00 0x01 0x01>; - qcom,ports-offset2 =3D /bits/ 8 <0x00 0x00 0x00 0x00>; - qcom,ports-hstart =3D /bits/ 8 <0xff 0xff 0xff 0xff>; - qcom,ports-hstop =3D /bits/ 8 <0xff 0xff 0xff 0xff>; - qcom,ports-word-length =3D /bits/ 8 <0xff 0xff 0xff 0xff>; - qcom,ports-block-pack-mode =3D /bits/ 8 <0xff 0xff 0xff 0xff>; - qcom,ports-block-group-count =3D /bits/ 8 <0xff 0xff 0xff 0xff>; - qcom,ports-lane-control =3D /bits/ 8 <0x01 0x02 0x00 0x00>; + qcom,dout-ports =3D <1>; + + qcom,ports-sinterval-low =3D /bits/ 8 <0x00 0x01 0x01 0x03 0x03>; + qcom,ports-offset1 =3D /bits/ 8 <0x00 0x00 0x00 0x01 0x01>; + qcom,ports-offset2 =3D /bits/ 8 <0x00 0x00 0x00 0x00 0x00>; + qcom,ports-hstart =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; + qcom,ports-hstop =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; + qcom,ports-word-length =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; + qcom,ports-block-pack-mode =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; + qcom,ports-block-group-count =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; + qcom,ports-lane-control =3D /bits/ 8 <0xff 0x01 0x02 0x00 0x00>; =20 #address-cells =3D <2>; #size-cells =3D <0>; --=20 2.34.1