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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-8434b03fd0bsm9968393b3a.50.2026.06.15.05.33.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Jun 2026 05:33:09 -0700 (PDT) From: Yingchao Deng Date: Mon, 15 Jun 2026 20:32:29 +0800 Subject: [PATCH v10 1/5] coresight: cti: Convert trigger usage fields to dynamic Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260615-extended_cti-v10-1-1c1694b6d8ed@oss.qualcomm.com> References: <20260615-extended_cti-v10-0-1c1694b6d8ed@oss.qualcomm.com> In-Reply-To: <20260615-extended_cti-v10-0-1c1694b6d8ed@oss.qualcomm.com> To: Suzuki K Poulose , Mike Leach , James Clark , Leo Yan , Alexander Shishkin Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, quic_yingdeng@quicinc.com, tingwei.zhang@oss.qualcomm.com, Jinlong Mao , jie.gan@oss.qualcomm.com, Yingchao Deng X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1781526782; l=12354; i=yingchao.deng@oss.qualcomm.com; s=20260611; h=from:subject:message-id; bh=TAOMHPwZ/2RDPjN7qrbBuJn2lZJcCG9fJ4QI233NyUI=; b=VHCzRSuqfbFvWtVe5AcdjRQlCzVjmpVG5VrCy1cejDmCXWkgaagQBiARuQs+cbtJLfZw+A3C/ 2L3ZOGVqO5xDdtv6p+EDJJ2dVQg9Ek+YiGTGVfIV+eBpMezTP/3oYf2 X-Developer-Key: i=yingchao.deng@oss.qualcomm.com; a=ed25519; pk=+y3U2mIt7mf0C+x6qBUD670cd9S2QV+yl5015bUYMgs= X-Proofpoint-Spam-Info: AW1haW4tMjYwNjE1MDEzMiBTYWx0ZWRfX+PWO0QtQXEkQ HfLOyG5NiD7VAy7XqXp8HvyrQsz0AR5FPRxz7aH9MMytmcRrDa3OLb74I2N1gEYf5yBjST9EQWP wvI16gLNXU7IiQ4p7JETGeqmbDdQ98Q= X-Proofpoint-GUID: kbNlz-mmWUEp3xgTI19_POcVVw77s6SH X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjE1MDEzMiBTYWx0ZWRfX5GYo/A1MQZUH j6OqhDrXoTK0roGmHDHft3eVe7IE0pEkMCG9a9yzuwo+XdNzAwEj6kRHCnyr4MpHHpEDsMiHMQq ZpWp5nqbuAHvrmEfabDjc1cJf7NocyCk2YUxkBojN8kGK+M/79j3BGlZTkui92LBrwW3JIdwG0X GMBTxBAJV8thPQyBxUi/kpS0GZCpHHQODQbztz7cGK6uIwchbx395j9lg0Q0UShp4F+RK+K2lP7 Mbk+RW8UUwhOkDe6ZF41hAyGqk/VLOyKAruEr1lZJzs4tQ8m7HSxVJHycnWA6sjQXTonpqsqJoP CVUObUAa7VISndACf3Pm7eT7SeECtFUPHdoAhMs88qvq1Eyta3IN5mnmOJuQQuI6xv6tyeErm6c 3foiT6KMWC06oVpEpr5rmhVCFHS/W2QliqqxImMKAFRGD6MLS7f9JwtWLPnkb+n6IPLeisO41kr h6E6s5GYEO4ja81Kdwg== X-Authority-Analysis: v=2.4 cv=F4tnsKhN c=1 sm=1 tr=0 ts=6a2ff107 cx=c_pps a=m5Vt/hrsBiPMCU0y4gIsQw==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=7CQSdrXTAAAA:8 a=EUspDBNiAAAA:8 a=RZ9YlW45n8Y3xjBI2tUA:9 a=QEXdDO2ut3YA:10 a=IoOABgeZipijB_acs4fv:22 a=a-qgeE7W1pNrGK8U0ZQC:22 X-Proofpoint-ORIG-GUID: kbNlz-mmWUEp3xgTI19_POcVVw77s6SH X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-15_03,2026-06-15_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 bulkscore=0 clxscore=1015 impostorscore=0 spamscore=0 adultscore=0 lowpriorityscore=0 priorityscore=1501 suspectscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606040000 definitions=main-2606150132 Replace the fixed-size u32 fields in the cti_config and cti_trig_grp structure with dynamically allocated bitmaps and arrays. This allows memory to be allocated based on the actual number of triggers during probe time, reducing memory footprint and improving scalability for platforms with varying trigger counts. Also add a bounds check in cti_allocate_trig_con() to ensure the caller does not pass in/out signal counts larger than nr_trig_max. Reviewed-by: Leo Yan Signed-off-by: Yingchao Deng --- drivers/hwtracing/coresight/coresight-cti-core.c | 70 +++++++++++++++++-= ---- .../hwtracing/coresight/coresight-cti-platform.c | 26 +++++--- drivers/hwtracing/coresight/coresight-cti-sysfs.c | 14 ++--- drivers/hwtracing/coresight/coresight-cti.h | 12 ++-- 4 files changed, 87 insertions(+), 35 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-cti-core.c b/drivers/hwt= racing/coresight/coresight-cti-core.c index b2c9a4db13b4..572798ab504c 100644 --- a/drivers/hwtracing/coresight/coresight-cti-core.c +++ b/drivers/hwtracing/coresight/coresight-cti-core.c @@ -161,8 +161,8 @@ void cti_write_intack(struct device *dev, u32 ackval) /* DEVID[19:16] - number of CTM channels */ #define CTI_DEVID_CTMCHANNELS(devid_val) ((int) BMVAL(devid_val, 16, 19)) =20 -static void cti_set_default_config(struct device *dev, - struct cti_drvdata *drvdata) +static int cti_set_default_config(struct device *dev, + struct cti_drvdata *drvdata) { struct cti_config *config =3D &drvdata->config; u32 devid; @@ -181,6 +181,31 @@ static void cti_set_default_config(struct device *dev, config->nr_trig_max =3D CTIINOUTEN_MAX; } =20 + config->trig_in_use =3D devm_bitmap_zalloc(dev, config->nr_trig_max, + GFP_KERNEL); + if (!config->trig_in_use) + return -ENOMEM; + + config->trig_out_use =3D devm_bitmap_zalloc(dev, config->nr_trig_max, + GFP_KERNEL); + if (!config->trig_out_use) + return -ENOMEM; + + config->trig_out_filter =3D devm_bitmap_zalloc(dev, config->nr_trig_max, + GFP_KERNEL); + if (!config->trig_out_filter) + return -ENOMEM; + + config->ctiinen =3D devm_kcalloc(dev, config->nr_trig_max, sizeof(u32), + GFP_KERNEL); + if (!config->ctiinen) + return -ENOMEM; + + config->ctiouten =3D devm_kcalloc(dev, config->nr_trig_max, sizeof(u32), + GFP_KERNEL); + if (!config->ctiouten) + return -ENOMEM; + config->nr_ctm_channels =3D CTI_DEVID_CTMCHANNELS(devid); =20 /* Most regs default to 0 as zalloc'ed except...*/ @@ -189,6 +214,7 @@ static void cti_set_default_config(struct device *dev, config->enable_req_count =3D 0; =20 config->asicctl_impl =3D !!FIELD_GET(GENMASK(4, 0), devid); + return 0; } =20 /* @@ -219,8 +245,10 @@ int cti_add_connection_entry(struct device *dev, struc= t cti_drvdata *drvdata, cti_dev->nr_trig_con++; =20 /* add connection usage bit info to overall info */ - drvdata->config.trig_in_use |=3D tc->con_in->used_mask; - drvdata->config.trig_out_use |=3D tc->con_out->used_mask; + bitmap_or(drvdata->config.trig_in_use, drvdata->config.trig_in_use, + tc->con_in->used_mask, drvdata->config.nr_trig_max); + bitmap_or(drvdata->config.trig_out_use, drvdata->config.trig_out_use, + tc->con_out->used_mask, drvdata->config.nr_trig_max); =20 return 0; } @@ -231,6 +259,14 @@ struct cti_trig_con *cti_allocate_trig_con(struct devi= ce *dev, int in_sigs, { struct cti_trig_con *tc =3D NULL; struct cti_trig_grp *in =3D NULL, *out =3D NULL; + struct cti_drvdata *drvdata =3D dev_get_drvdata(dev); + int n_trigs =3D drvdata->config.nr_trig_max; + + if (in_sigs > n_trigs || out_sigs > n_trigs) { + dev_err(dev, "trigger signal is out of range: in=3D%d out=3D%d nr_max=3D= %d\n", + in_sigs, out_sigs, n_trigs); + return NULL; + } =20 tc =3D devm_kzalloc(dev, sizeof(struct cti_trig_con), GFP_KERNEL); if (!tc) @@ -242,12 +278,20 @@ struct cti_trig_con *cti_allocate_trig_con(struct dev= ice *dev, int in_sigs, if (!in) return NULL; =20 + in->used_mask =3D devm_bitmap_zalloc(dev, n_trigs, GFP_KERNEL); + if (!in->used_mask) + return NULL; + out =3D devm_kzalloc(dev, offsetof(struct cti_trig_grp, sig_types[out_sigs]), GFP_KERNEL); if (!out) return NULL; =20 + out->used_mask =3D devm_bitmap_zalloc(dev, n_trigs, GFP_KERNEL); + if (!out->used_mask) + return NULL; + tc->con_in =3D in; tc->con_out =3D out; tc->con_in->nr_sigs =3D in_sigs; @@ -263,7 +307,6 @@ int cti_add_default_connection(struct device *dev, stru= ct cti_drvdata *drvdata) { int ret =3D 0; int n_trigs =3D drvdata->config.nr_trig_max; - u32 n_trig_mask =3D GENMASK(n_trigs - 1, 0); struct cti_trig_con *tc =3D NULL; =20 /* @@ -274,8 +317,8 @@ int cti_add_default_connection(struct device *dev, stru= ct cti_drvdata *drvdata) if (!tc) return -ENOMEM; =20 - tc->con_in->used_mask =3D n_trig_mask; - tc->con_out->used_mask =3D n_trig_mask; + bitmap_fill(tc->con_in->used_mask, n_trigs); + bitmap_fill(tc->con_out->used_mask, n_trigs); ret =3D cti_add_connection_entry(dev, drvdata, tc, NULL, "default"); return ret; } @@ -288,7 +331,6 @@ int cti_channel_trig_op(struct device *dev, enum cti_ch= an_op op, { struct cti_drvdata *drvdata =3D dev_get_drvdata(dev->parent); struct cti_config *config =3D &drvdata->config; - u32 trig_bitmask; u32 chan_bitmask; u32 reg_value; int reg_offset; @@ -298,18 +340,16 @@ int cti_channel_trig_op(struct device *dev, enum cti_= chan_op op, (trigger_idx >=3D config->nr_trig_max)) return -EINVAL; =20 - trig_bitmask =3D BIT(trigger_idx); - /* ensure registered triggers and not out filtered */ if (direction =3D=3D CTI_TRIG_IN) { - if (!(trig_bitmask & config->trig_in_use)) + if (!(test_bit(trigger_idx, config->trig_in_use))) return -EINVAL; } else { - if (!(trig_bitmask & config->trig_out_use)) + if (!(test_bit(trigger_idx, config->trig_out_use))) return -EINVAL; =20 if ((config->trig_filter_enable) && - (config->trig_out_filter & trig_bitmask)) + test_bit(trigger_idx, config->trig_out_filter)) return -EINVAL; } =20 @@ -687,7 +727,9 @@ static int cti_probe(struct amba_device *adev, const st= ruct amba_id *id) raw_spin_lock_init(&drvdata->spinlock); =20 /* initialise CTI driver config values */ - cti_set_default_config(dev, drvdata); + ret =3D cti_set_default_config(dev, drvdata); + if (ret) + return ret; =20 pdata =3D coresight_cti_get_platform_data(dev); if (IS_ERR(pdata)) { diff --git a/drivers/hwtracing/coresight/coresight-cti-platform.c b/drivers= /hwtracing/coresight/coresight-cti-platform.c index d6d5388705c3..ba5a7e4b6bff 100644 --- a/drivers/hwtracing/coresight/coresight-cti-platform.c +++ b/drivers/hwtracing/coresight/coresight-cti-platform.c @@ -136,8 +136,8 @@ static int cti_plat_create_v8_etm_connection(struct dev= ice *dev, goto create_v8_etm_out; =20 /* build connection data */ - tc->con_in->used_mask =3D 0xF0; /* sigs <4,5,6,7> */ - tc->con_out->used_mask =3D 0xF0; /* sigs <4,5,6,7> */ + bitmap_set(tc->con_in->used_mask, 4, 4); /* sigs <4,5,6,7> */ + bitmap_set(tc->con_out->used_mask, 4, 4); /* sigs <4,5,6,7> */ =20 /* * The EXTOUT type signals from the ETM are connected to a set of input @@ -194,10 +194,10 @@ static int cti_plat_create_v8_connections(struct devi= ce *dev, goto of_create_v8_out; =20 /* Set the v8 PE CTI connection data */ - tc->con_in->used_mask =3D 0x3; /* sigs <0 1> */ + bitmap_set(tc->con_in->used_mask, 0, 2); /* sigs <0 1> */ tc->con_in->sig_types[0] =3D PE_DBGTRIGGER; tc->con_in->sig_types[1] =3D PE_PMUIRQ; - tc->con_out->used_mask =3D 0x7; /* sigs <0 1 2 > */ + bitmap_set(tc->con_out->used_mask, 0, 3); /* sigs <0 1 2 > */ tc->con_out->sig_types[0] =3D PE_EDBGREQ; tc->con_out->sig_types[1] =3D PE_DBGRESTART; tc->con_out->sig_types[2] =3D PE_CTIIRQ; @@ -213,7 +213,7 @@ static int cti_plat_create_v8_connections(struct device= *dev, goto of_create_v8_out; =20 /* filter pe_edbgreq - PE trigout sig <0> */ - drvdata->config.trig_out_filter |=3D 0x1; + set_bit(0, drvdata->config.trig_out_filter); =20 of_create_v8_out: return ret; @@ -257,7 +257,7 @@ static int cti_plat_read_trig_group(struct cti_trig_grp= *tgrp, if (!err) { /* set the signal usage mask */ for (idx =3D 0; idx < tgrp->nr_sigs; idx++) - tgrp->used_mask |=3D BIT(values[idx]); + set_bit(values[idx], tgrp->used_mask); } =20 kfree(values); @@ -316,24 +316,34 @@ static int cti_plat_process_filter_sigs(struct cti_dr= vdata *drvdata, { struct cti_trig_grp *tg =3D NULL; int err =3D 0, nr_filter_sigs; + int nr_trigs =3D drvdata->config.nr_trig_max; =20 nr_filter_sigs =3D cti_plat_count_sig_elements(fwnode, CTI_DT_FILTER_OUT_SIGS); if (nr_filter_sigs =3D=3D 0) return 0; =20 - if (nr_filter_sigs > drvdata->config.nr_trig_max) + if (nr_filter_sigs > nr_trigs) return -EINVAL; =20 tg =3D kzalloc_obj(*tg); if (!tg) return -ENOMEM; =20 + tg->used_mask =3D bitmap_zalloc(nr_trigs, GFP_KERNEL); + if (!tg->used_mask) { + kfree(tg); + return -ENOMEM; + } + tg->nr_sigs =3D nr_filter_sigs; err =3D cti_plat_read_trig_group(tg, fwnode, CTI_DT_FILTER_OUT_SIGS); if (!err) - drvdata->config.trig_out_filter |=3D tg->used_mask; + bitmap_or(drvdata->config.trig_out_filter, + drvdata->config.trig_out_filter, + tg->used_mask, nr_trigs); =20 + bitmap_free(tg->used_mask); kfree(tg); return err; } diff --git a/drivers/hwtracing/coresight/coresight-cti-sysfs.c b/drivers/hw= tracing/coresight/coresight-cti-sysfs.c index 3fe2c916d228..2bbfa405cb6b 100644 --- a/drivers/hwtracing/coresight/coresight-cti-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-cti-sysfs.c @@ -719,12 +719,12 @@ static ssize_t trigout_filtered_show(struct device *d= ev, struct cti_drvdata *drvdata =3D dev_get_drvdata(dev->parent); struct cti_config *cfg =3D &drvdata->config; int nr_trig_max =3D cfg->nr_trig_max; - unsigned long mask =3D cfg->trig_out_filter; + unsigned long *mask =3D cfg->trig_out_filter; =20 - if (mask =3D=3D 0) + if (bitmap_empty(mask, nr_trig_max)) return 0; =20 - return sysfs_emit(buf, "%*pbl\n", nr_trig_max, &mask); + return sysfs_emit(buf, "%*pbl\n", nr_trig_max, mask); } static DEVICE_ATTR_RO(trigout_filtered); =20 @@ -931,9 +931,9 @@ static ssize_t trigin_sig_show(struct device *dev, struct cti_trig_con *con =3D (struct cti_trig_con *)ext_attr->var; struct cti_drvdata *drvdata =3D dev_get_drvdata(dev->parent); struct cti_config *cfg =3D &drvdata->config; - unsigned long mask =3D con->con_in->used_mask; + unsigned long *mask =3D con->con_in->used_mask; =20 - return sysfs_emit(buf, "%*pbl\n", cfg->nr_trig_max, &mask); + return sysfs_emit(buf, "%*pbl\n", cfg->nr_trig_max, mask); } =20 static ssize_t trigout_sig_show(struct device *dev, @@ -945,9 +945,9 @@ static ssize_t trigout_sig_show(struct device *dev, struct cti_trig_con *con =3D (struct cti_trig_con *)ext_attr->var; struct cti_drvdata *drvdata =3D dev_get_drvdata(dev->parent); struct cti_config *cfg =3D &drvdata->config; - unsigned long mask =3D con->con_out->used_mask; + unsigned long *mask =3D con->con_out->used_mask; =20 - return sysfs_emit(buf, "%*pbl\n", cfg->nr_trig_max, &mask); + return sysfs_emit(buf, "%*pbl\n", cfg->nr_trig_max, mask); } =20 /* convert a sig type id to a name */ diff --git a/drivers/hwtracing/coresight/coresight-cti.h b/drivers/hwtracin= g/coresight/coresight-cti.h index c5f9e79fabc6..ef079fc18b72 100644 --- a/drivers/hwtracing/coresight/coresight-cti.h +++ b/drivers/hwtracing/coresight/coresight-cti.h @@ -68,7 +68,7 @@ struct fwnode_handle; */ struct cti_trig_grp { int nr_sigs; - u32 used_mask; + unsigned long *used_mask; int sig_types[]; }; =20 @@ -145,17 +145,17 @@ struct cti_config { int enable_req_count; =20 /* registered triggers and filtering */ - u32 trig_in_use; - u32 trig_out_use; - u32 trig_out_filter; + unsigned long *trig_in_use; + unsigned long *trig_out_use; + unsigned long *trig_out_filter; bool trig_filter_enable; u8 xtrig_rchan_sel; =20 /* cti cross trig programmable regs */ u32 ctiappset; u8 ctiinout_sel; - u32 ctiinen[CTIINOUTEN_MAX]; - u32 ctiouten[CTIINOUTEN_MAX]; + u32 *ctiinen; + u32 *ctiouten; u32 ctigate; u32 asicctl; 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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-8434b03fd0bsm9968393b3a.50.2026.06.15.05.33.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Jun 2026 05:33:12 -0700 (PDT) From: Yingchao Deng Date: Mon, 15 Jun 2026 20:32:30 +0800 Subject: [PATCH v10 2/5] coresight: cti: use __reg_addr() helper for register access Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260615-extended_cti-v10-2-1c1694b6d8ed@oss.qualcomm.com> References: <20260615-extended_cti-v10-0-1c1694b6d8ed@oss.qualcomm.com> In-Reply-To: <20260615-extended_cti-v10-0-1c1694b6d8ed@oss.qualcomm.com> To: Suzuki K Poulose , Mike Leach , James Clark , Leo Yan , Alexander Shishkin Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, quic_yingdeng@quicinc.com, tingwei.zhang@oss.qualcomm.com, Jinlong Mao , jie.gan@oss.qualcomm.com, Yingchao Deng X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1781526782; l=10380; i=yingchao.deng@oss.qualcomm.com; s=20260611; h=from:subject:message-id; bh=wIWFmWKXaUOYZmGF72r5cp1d/iTRLSZHqeXR8U6HAKU=; b=oKoFZXfqqzQ5B4qXkwS1d5b32jbxDCcr+4CRT76qY8Z/leTtADcFEHzQYyrg3F6MrGiGzRT7R MZHH1zEewG5AgAoEp2DMqbVffjU+HyQeW8/lh8ni0K91UjR8UnSTn6E X-Developer-Key: i=yingchao.deng@oss.qualcomm.com; a=ed25519; pk=+y3U2mIt7mf0C+x6qBUD670cd9S2QV+yl5015bUYMgs= X-Proofpoint-Spam-Info: AW1haW4tMjYwNjE1MDEzMiBTYWx0ZWRfX0up1vO5hrl7i 3Phduyf4zT28FF47vSwG6R45RQcWYCvUUeYT7b4E1l7GO0RAMwmaFIwABKJRdVBz0Oleodz+1az aghoJgdAHv0WwutfxDzW07n0fLpton8= X-Authority-Analysis: v=2.4 cv=Zqnd7d7G c=1 sm=1 tr=0 ts=6a2ff10a cx=c_pps a=WW5sKcV1LcKqjgzy2JUPuA==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=EUspDBNiAAAA:8 a=xqws7DasADjwqOAWw1EA:9 a=QEXdDO2ut3YA:10 a=OpyuDcXvxspvyRM73sMx:22 X-Proofpoint-GUID: mo0bryC4_fAtUg-csMWeWo22AdncQzki X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjE1MDEzMiBTYWx0ZWRfX60KwVJjA/fV0 olZlBA3vr7FqPkhT4Po0MrSvzBRlaj+i19zLs3d90ppGdmuvDYh/Ll742s5NRDxFewiTr4gjFCh DnTLfrEmODywe4AKNItD9rNYMyGu8s4unSj+dOF0AuNsHblCa+bpPMCfhr+dnA1te1d47sS5VQd tUV14kAf0NJr1cKv7Y9VZB60foLNBmiI6hhC5fB7rIcKXVQl9/ED/YiYcKmCoHcPX2anrwiEWPq C43ve+EduNgGEjf5A0kO7QeMaze06KOOPG3S45JaaXdspFvCRio7nK4Eko47yGcn0uC4K6Pc+5l sbZld+4W3iKSBl4eg5Q0oqoqzdqQkN20uh/Y0MFguwUjURaZIipRIwBiZAWjuGPtl5dJxokYN5Y vSRC6OvEftK/l8neblC7eh+VjJdS2UnK91cA4mu4URZbUzNkiCAC3Z/bUc+Wn9aFmZawRT+op0X sMGn2Zt+Bk1o+H6jxdA== X-Proofpoint-ORIG-GUID: mo0bryC4_fAtUg-csMWeWo22AdncQzki X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-15_03,2026-06-15_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 spamscore=0 priorityscore=1501 suspectscore=0 lowpriorityscore=0 adultscore=0 malwarescore=0 clxscore=1015 impostorscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606040000 definitions=main-2606150132 Introduce a static inline __reg_addr(drvdata, off, index) helper in coresight-cti.h to compute MMIO addresses from a base offset and a per-trigger index, replacing the function-like CTIINEN(n)/CTIOUTEN(n) macros with base offsets and explicit index arithmetic. Add reg_addr and reg_index_addr convenience macros for zero-index and indexed access respectively. Convert cti_read_single_reg() and cti_write_single_reg() to static inline wrappers in coresight-cti.h, and add indexed variants cti_read_single_reg_index() / cti_write_single_reg_index() for callers that need explicit bank selection. Extend cs_off_attribute with a u32 index field and update coresight_cti_reg_show/store to use the attribute's index field directly. Co-developed-by: Jinlong Mao Signed-off-by: Jinlong Mao Signed-off-by: Yingchao Deng drivers/hwtracing/coresight/coresight-cti-core.c | 45 ++++++++++++++-----= ---- drivers/hwtracing/coresight/coresight-cti-sysfs.c | 25 +++++++------ drivers/hwtracing/coresight/coresight-cti.h | 9 +++-- drivers/hwtracing/coresight/coresight-priv.h | 4 +- 4 files changed, 50 insertions(+), 33 deletions(-) --- drivers/hwtracing/coresight/coresight-cti-core.c | 36 +++++------------- drivers/hwtracing/coresight/coresight-cti-sysfs.c | 17 +++++---- drivers/hwtracing/coresight/coresight-cti.h | 46 +++++++++++++++++++= ++-- drivers/hwtracing/coresight/coresight-priv.h | 4 +- 4 files changed, 64 insertions(+), 39 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-cti-core.c b/drivers/hwt= racing/coresight/coresight-cti-core.c index 572798ab504c..fa758c535ccb 100644 --- a/drivers/hwtracing/coresight/coresight-cti-core.c +++ b/drivers/hwtracing/coresight/coresight-cti-core.c @@ -55,16 +55,17 @@ void cti_write_all_hw_regs(struct cti_drvdata *drvdata) =20 /* write the CTI trigger registers */ for (i =3D 0; i < config->nr_trig_max; i++) { - writel_relaxed(config->ctiinen[i], drvdata->base + CTIINEN(i)); + writel_relaxed(config->ctiinen[i], + reg_index_addr(drvdata, CTIINEN, i)); writel_relaxed(config->ctiouten[i], - drvdata->base + CTIOUTEN(i)); + reg_index_addr(drvdata, CTIOUTEN, i)); } =20 /* other regs */ - writel_relaxed(config->ctigate, drvdata->base + CTIGATE); + writel_relaxed(config->ctigate, reg_addr(drvdata, CTIGATE)); if (config->asicctl_impl) - writel_relaxed(config->asicctl, drvdata->base + ASICCTL); - writel_relaxed(config->ctiappset, drvdata->base + CTIAPPSET); + writel_relaxed(config->asicctl, reg_addr(drvdata, ASICCTL)); + writel_relaxed(config->ctiappset, reg_addr(drvdata, CTIAPPSET)); =20 /* re-enable CTI */ writel_relaxed(1, drvdata->base + CTICONTROL); @@ -122,24 +123,6 @@ static int cti_disable_hw(struct cti_drvdata *drvdata) return 0; } =20 -u32 cti_read_single_reg(struct cti_drvdata *drvdata, int offset) -{ - int val; - - CS_UNLOCK(drvdata->base); - val =3D readl_relaxed(drvdata->base + offset); - CS_LOCK(drvdata->base); - - return val; -} - -void cti_write_single_reg(struct cti_drvdata *drvdata, int offset, u32 val= ue) -{ - CS_UNLOCK(drvdata->base); - writel_relaxed(value, drvdata->base + offset); - CS_LOCK(drvdata->base); -} - void cti_write_intack(struct device *dev, u32 ackval) { struct cti_drvdata *drvdata =3D dev_get_drvdata(dev->parent); @@ -333,7 +316,7 @@ int cti_channel_trig_op(struct device *dev, enum cti_ch= an_op op, struct cti_config *config =3D &drvdata->config; u32 chan_bitmask; u32 reg_value; - int reg_offset; + u32 reg_offset; =20 /* ensure indexes in range */ if ((channel_idx >=3D config->nr_ctm_channels) || @@ -355,8 +338,7 @@ int cti_channel_trig_op(struct device *dev, enum cti_ch= an_op op, =20 /* update the local register values */ chan_bitmask =3D BIT(channel_idx); - reg_offset =3D (direction =3D=3D CTI_TRIG_IN ? CTIINEN(trigger_idx) : - CTIOUTEN(trigger_idx)); + reg_offset =3D (direction =3D=3D CTI_TRIG_IN ? CTIINEN : CTIOUTEN); =20 guard(raw_spinlock_irqsave)(&drvdata->spinlock); =20 @@ -376,7 +358,7 @@ int cti_channel_trig_op(struct device *dev, enum cti_ch= an_op op, =20 /* write through if enabled */ if (cti_is_active(config)) - cti_write_single_reg(drvdata, reg_offset, reg_value); + cti_write_single_reg_index(drvdata, reg_offset, trigger_idx, reg_value); =20 return 0; } diff --git a/drivers/hwtracing/coresight/coresight-cti-sysfs.c b/drivers/hw= tracing/coresight/coresight-cti-sysfs.c index 2bbfa405cb6b..6165866eaefe 100644 --- a/drivers/hwtracing/coresight/coresight-cti-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-cti-sysfs.c @@ -171,7 +171,7 @@ static ssize_t coresight_cti_reg_show(struct device *de= v, pm_runtime_get_sync(dev->parent); =20 scoped_guard(raw_spinlock_irqsave, &drvdata->spinlock) - val =3D cti_read_single_reg(drvdata, cti_attr->off); + val =3D cti_read_single_reg_index(drvdata, cti_attr->off, cti_attr->inde= x); =20 pm_runtime_put_sync(dev->parent); return sysfs_emit(buf, "0x%x\n", val); @@ -192,7 +192,7 @@ static __maybe_unused ssize_t coresight_cti_reg_store(s= truct device *dev, pm_runtime_get_sync(dev->parent); =20 scoped_guard(raw_spinlock_irqsave, &drvdata->spinlock) - cti_write_single_reg(drvdata, cti_attr->off, val); + cti_write_single_reg_index(drvdata, cti_attr->off, cti_attr->index, val); =20 pm_runtime_put_sync(dev->parent); return size; @@ -202,7 +202,8 @@ static __maybe_unused ssize_t coresight_cti_reg_store(s= truct device *dev, (&((struct cs_off_attribute[]) { \ { \ __ATTR(name, 0444, coresight_cti_reg_show, NULL), \ - offset \ + offset, \ + 0 \ } \ })[0].attr.attr) =20 @@ -211,7 +212,8 @@ static __maybe_unused ssize_t coresight_cti_reg_store(s= truct device *dev, { \ __ATTR(name, 0644, coresight_cti_reg_show, \ coresight_cti_reg_store), \ - offset \ + offset, \ + 0 \ } \ })[0].attr.attr) =20 @@ -219,7 +221,8 @@ static __maybe_unused ssize_t coresight_cti_reg_store(s= truct device *dev, (&((struct cs_off_attribute[]) { \ { \ __ATTR(name, 0200, NULL, coresight_cti_reg_store), \ - offset \ + offset, \ + 0 \ } \ })[0].attr.attr) =20 @@ -386,7 +389,7 @@ static ssize_t inen_store(struct device *dev, =20 /* write through if enabled */ if (cti_is_active(config)) - cti_write_single_reg(drvdata, CTIINEN(index), val); + cti_write_single_reg_index(drvdata, CTIINEN, index, val); =20 return size; } @@ -427,7 +430,7 @@ static ssize_t outen_store(struct device *dev, =20 /* write through if enabled */ if (cti_is_active(config)) - cti_write_single_reg(drvdata, CTIOUTEN(index), val); + cti_write_single_reg_index(drvdata, CTIOUTEN, index, val); =20 return size; } diff --git a/drivers/hwtracing/coresight/coresight-cti.h b/drivers/hwtracin= g/coresight/coresight-cti.h index ef079fc18b72..634bdce5cdfd 100644 --- a/drivers/hwtracing/coresight/coresight-cti.h +++ b/drivers/hwtracing/coresight/coresight-cti.h @@ -30,8 +30,8 @@ struct fwnode_handle; #define CTIAPPSET 0x014 #define CTIAPPCLEAR 0x018 #define CTIAPPPULSE 0x01C -#define CTIINEN(n) (0x020 + (4 * n)) -#define CTIOUTEN(n) (0x0A0 + (4 * n)) +#define CTIINEN 0x020 +#define CTIOUTEN 0x0A0 #define CTITRIGINSTATUS 0x130 #define CTITRIGOUTSTATUS 0x134 #define CTICHINSTATUS 0x138 @@ -217,8 +217,6 @@ int cti_enable(struct coresight_device *csdev, enum cs_= mode mode, int cti_disable(struct coresight_device *csdev, struct coresight_path *pat= h); void cti_write_all_hw_regs(struct cti_drvdata *drvdata); void cti_write_intack(struct device *dev, u32 ackval); -void cti_write_single_reg(struct cti_drvdata *drvdata, int offset, u32 val= ue); -u32 cti_read_single_reg(struct cti_drvdata *drvdata, int offset); int cti_channel_trig_op(struct device *dev, enum cti_chan_op op, enum cti_trig_dir direction, u32 channel_idx, u32 trigger_idx); @@ -231,6 +229,46 @@ struct coresight_platform_data * coresight_cti_get_platform_data(struct device *dev); const char *cti_plat_get_node_name(struct fwnode_handle *fwnode); =20 +static inline void __iomem *__reg_addr(struct cti_drvdata *drvdata, + u32 off, u32 index) +{ + return drvdata->base + off + index * sizeof(u32); +} + +#define reg_addr(drvdata, off) __reg_addr((drvdata), (off), 0) +#define reg_index_addr(drvdata, off, i) __reg_addr((drvdata), (off), (i)) + +static inline u32 cti_read_single_reg_index(struct cti_drvdata *drvdata, + u32 off, u32 index) +{ + u32 val; + + CS_UNLOCK(drvdata->base); + val =3D readl_relaxed(reg_index_addr(drvdata, off, index)); + CS_LOCK(drvdata->base); + + return val; +} + +static inline u32 cti_read_single_reg(struct cti_drvdata *drvdata, u32 off) +{ + return cti_read_single_reg_index(drvdata, off, 0); +} + +static inline void cti_write_single_reg_index(struct cti_drvdata *drvdata, + u32 off, u32 index, u32 value) +{ + CS_UNLOCK(drvdata->base); + writel_relaxed(value, reg_index_addr(drvdata, off, index)); + CS_LOCK(drvdata->base); +} + +static inline void cti_write_single_reg(struct cti_drvdata *drvdata, + u32 off, u32 value) +{ + cti_write_single_reg_index(drvdata, off, 0, value); +} + /* Check if a cti device is enabled */ static inline bool cti_is_active(struct cti_config *cfg) { diff --git a/drivers/hwtracing/coresight/coresight-priv.h b/drivers/hwtraci= ng/coresight/coresight-priv.h index dddac946659f..cb4736324c04 100644 --- a/drivers/hwtracing/coresight/coresight-priv.h +++ b/drivers/hwtracing/coresight/coresight-priv.h @@ -58,6 +58,7 @@ struct cs_pair_attribute { struct cs_off_attribute { struct device_attribute attr; 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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-8434b03fd0bsm9968393b3a.50.2026.06.15.05.33.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Jun 2026 05:33:16 -0700 (PDT) From: Yingchao Deng Date: Mon, 15 Jun 2026 20:32:31 +0800 Subject: [PATCH v10 3/5] coresight: cti: add Qualcomm extended CTI identification and quirks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260615-extended_cti-v10-3-1c1694b6d8ed@oss.qualcomm.com> References: <20260615-extended_cti-v10-0-1c1694b6d8ed@oss.qualcomm.com> In-Reply-To: <20260615-extended_cti-v10-0-1c1694b6d8ed@oss.qualcomm.com> To: Suzuki K Poulose , Mike Leach , James Clark , Leo Yan , Alexander Shishkin Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, quic_yingdeng@quicinc.com, tingwei.zhang@oss.qualcomm.com, Jinlong Mao , jie.gan@oss.qualcomm.com, Yingchao Deng X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1781526782; l=8792; i=yingchao.deng@oss.qualcomm.com; s=20260611; h=from:subject:message-id; bh=lODQpixgMjeh3XaPxg7whs4SFcFhY0krJnrZZurdwgY=; b=hTOJCGiFRo4kRJIKulKIAU9giNFMQhIjh0gUp7W5oMvJjfvr53d2zE5P/2Sj/GlmAR6EFemXL ZR995QsmeyCCpazUo3+0wHFjNMSbudyfriu35GtXdn+I82ViV1z+dMG X-Developer-Key: i=yingchao.deng@oss.qualcomm.com; a=ed25519; pk=+y3U2mIt7mf0C+x6qBUD670cd9S2QV+yl5015bUYMgs= X-Proofpoint-Spam-Info: AW1haW4tMjYwNjE1MDEzMiBTYWx0ZWRfX7DT2TFo71MBy XKRNfMc/N0A8QVjETePinGBbcw/WNYbXmpb3y6eAbhQTdNOoC6RyeTvtm5dwCN7Nu7yuxLQmMqL E6JfQTWUmMMK5jsRGTwO7TigfEzwblo= X-Authority-Analysis: v=2.4 cv=Zqnd7d7G c=1 sm=1 tr=0 ts=6a2ff10e cx=c_pps a=mDZGXZTwRPZaeRUbqKGCBw==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=EUspDBNiAAAA:8 a=beW-1tIARaYxa11sNzUA:9 a=QEXdDO2ut3YA:10 a=zc0IvFSfCIW2DFIPzwfm:22 X-Proofpoint-GUID: XYcAgXDWSFJMr45jW03w7Hgqlr1y0pWP X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjE1MDEzMiBTYWx0ZWRfXxahbXF1vHTsT 6lPCrw9KIUwD6uTSmo4BiAuQPOJPJC0fQBeCfA4VkU0sd6ueNSVifAiX4gV1BlOYueIazCnHghY jCC9/tduubiWtCGLcZWO7VdSF+LGLTG1h5jdM9SPDhihPZoPplwB15+XhptrHXcObj9miIfKCVI FvMlw2Tg64BPdXYmM+tUD8FNClb9qOlzgmZfHb6e25SsD71V/MfR31+mRwLwM+n2xUbDm/Tgnwx c5SqbFqeYZ3T0N7Wo2cT48+4WkBFhVixsjoGrQ6DO9AtfwfV3y89knzCIl3Kp0T0jYNrVhwlrmB JBflsZUlKwDfild12wyUqV/EWs65Mmoe206Oqr9P7UpvyF4/fuusaomv/MhBXSWXuIfWvG8NG97 twdMuqNo/IZk5hX6zgfIPNt62PAxRCUqPTeB+jLbkrsNBtX60zn2SPon9V5JpMqdTOfq/H2qUFS cDCrdB8vIHedId1aVEw== X-Proofpoint-ORIG-GUID: XYcAgXDWSFJMr45jW03w7Hgqlr1y0pWP X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-15_03,2026-06-15_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 spamscore=0 priorityscore=1501 suspectscore=0 lowpriorityscore=0 adultscore=0 malwarescore=0 clxscore=1015 impostorscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606040000 definitions=main-2606150132 Qualcomm implements an extended variant of the ARM CoreSight CTI with a different register layout and vendor-specific behavior. While the programming model remains largely compatible, the register offsets differ from the standard ARM CTI and require explicit handling. Detect Qualcomm CTIs via the DEVARCH register and record this in the CTI driver data. Introduce a small mapping layer to translate standard CTI register offsets to Qualcomm-specific offsets, allowing the rest of the driver to use a common register access path. Additionally, handle a Qualcomm-specific quirk where the hardware does not implement the CoreSight Claim tag protocol. Instead of clearing the CLAIMSET register at probe time, bypass the claim/disclaim operations entirely for Qualcomm CTIs by wrapping coresight_claim_device(), coresight_disclaim_device_unlocked() and coresight_clear_self_claim_tag() in thin helpers that early-return when is_qcom_cti is set. No functional change is intended for standard ARM CTI devices. Co-developed-by: Jinlong Mao Signed-off-by: Jinlong Mao Signed-off-by: Yingchao Deng --- drivers/hwtracing/coresight/coresight-cti-core.c | 47 +++++++++++++++-- drivers/hwtracing/coresight/coresight-cti.h | 64 ++++++++++++++++++++= +++- 2 files changed, 105 insertions(+), 6 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-cti-core.c b/drivers/hwt= racing/coresight/coresight-cti-core.c index fa758c535ccb..5b83dd4e603b 100644 --- a/drivers/hwtracing/coresight/coresight-cti-core.c +++ b/drivers/hwtracing/coresight/coresight-cti-core.c @@ -73,6 +73,35 @@ void cti_write_all_hw_regs(struct cti_drvdata *drvdata) CS_LOCK(drvdata->base); } =20 +/* + * Qualcomm CTIs do not implement the CoreSight Claim tag protocol, so + * bypass coresight_clear_self_claim_tag() for them. + */ +static void cti_clear_self_claim_tag(struct cti_drvdata *drvdata, + struct csdev_access *csa) +{ + if (drvdata->is_qcom_cti) + return; + + coresight_clear_self_claim_tag(csa); +} + +static int cti_claim_device(struct cti_drvdata *drvdata) +{ + if (drvdata->is_qcom_cti) + return 0; + + return coresight_claim_device(drvdata->csdev); +} + +static void cti_unclaim_device_unlocked(struct cti_drvdata *drvdata) +{ + if (drvdata->is_qcom_cti) + return; + + coresight_disclaim_device_unlocked(drvdata->csdev); +} + /* write regs to hardware and enable */ static int cti_enable_hw(struct cti_drvdata *drvdata) { @@ -86,7 +115,7 @@ static int cti_enable_hw(struct cti_drvdata *drvdata) goto cti_state_unchanged; =20 /* claim the device */ - rc =3D coresight_claim_device(drvdata->csdev); + rc =3D cti_claim_device(drvdata); if (rc) return rc; =20 @@ -101,7 +130,6 @@ static int cti_enable_hw(struct cti_drvdata *drvdata) static int cti_disable_hw(struct cti_drvdata *drvdata) { struct cti_config *config =3D &drvdata->config; - struct coresight_device *csdev =3D drvdata->csdev; =20 guard(raw_spinlock_irqsave)(&drvdata->spinlock); =20 @@ -118,7 +146,7 @@ static int cti_disable_hw(struct cti_drvdata *drvdata) /* disable CTI */ writel_relaxed(0, drvdata->base + CTICONTROL); =20 - coresight_disclaim_device_unlocked(csdev); + cti_unclaim_device_unlocked(drvdata); CS_LOCK(drvdata->base); return 0; } @@ -144,6 +172,9 @@ void cti_write_intack(struct device *dev, u32 ackval) /* DEVID[19:16] - number of CTM channels */ #define CTI_DEVID_CTMCHANNELS(devid_val) ((int) BMVAL(devid_val, 16, 19)) =20 +/* DEVARCH[31:21] - ARCHITECT */ +#define CTI_DEVARCH_ARCHITECT(devarch_val) ((int)BMVAL(devarch_val, 21, 31= )) + static int cti_set_default_config(struct device *dev, struct cti_drvdata *drvdata) { @@ -684,6 +715,7 @@ static int cti_probe(struct amba_device *adev, const st= ruct amba_id *id) struct coresight_desc cti_desc =3D { 0 }; struct coresight_platform_data *pdata =3D NULL; struct resource *res =3D &adev->res; + u32 devarch; =20 /* driver data*/ drvdata =3D devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); @@ -708,6 +740,10 @@ static int cti_probe(struct amba_device *adev, const s= truct amba_id *id) =20 raw_spin_lock_init(&drvdata->spinlock); =20 + devarch =3D readl_relaxed(drvdata->base + CORESIGHT_DEVARCH); + if (CTI_DEVARCH_ARCHITECT(devarch) =3D=3D QCOM_ARCHITECT) + drvdata->is_qcom_cti =3D true; + /* initialise CTI driver config values */ ret =3D cti_set_default_config(dev, drvdata); if (ret) @@ -753,7 +789,7 @@ static int cti_probe(struct amba_device *adev, const st= ruct amba_id *id) cti_desc.groups =3D drvdata->ctidev.con_groups; cti_desc.dev =3D dev; =20 - coresight_clear_self_claim_tag(&cti_desc.access); + cti_clear_self_claim_tag(drvdata, &cti_desc.access); drvdata->csdev =3D coresight_register(&cti_desc); if (IS_ERR(drvdata->csdev)) return PTR_ERR(drvdata->csdev); @@ -767,7 +803,8 @@ static int cti_probe(struct amba_device *adev, const st= ruct amba_id *id) =20 /* all done - dec pm refcount */ pm_runtime_put(&adev->dev); - dev_info(&drvdata->csdev->dev, "CTI initialized\n"); + dev_info(&drvdata->csdev->dev, + "%sCTI initialized\n", drvdata->is_qcom_cti ? "QCOM " : ""); return 0; } =20 diff --git a/drivers/hwtracing/coresight/coresight-cti.h b/drivers/hwtracin= g/coresight/coresight-cti.h index 634bdce5cdfd..4b6fd6b55114 100644 --- a/drivers/hwtracing/coresight/coresight-cti.h +++ b/drivers/hwtracing/coresight/coresight-cti.h @@ -54,10 +54,36 @@ struct fwnode_handle; /* * CTI CSSoc 600 has a max of 32 trigger signals per direction. * CTI CSSoc 400 has 8 IO triggers - other CTIs can be impl def. + * QCOM CTI support up to 128 trigger signals per direction. * Max of in and out defined in the DEVID register. * - pick up actual number used from .dts parameters if present. */ -#define CTIINOUTEN_MAX 32 +#define CTIINOUTEN_MAX 128 + +/* QCOM CTI extension */ +#define QCOM_ARCHITECT 0x477 + +#define QCOM_CTIINTACK 0x020 +#define QCOM_CTIAPPSET 0x004 +#define QCOM_CTIAPPCLEAR 0x008 +#define QCOM_CTIAPPPULSE 0x00C +#define QCOM_CTIINEN 0x400 +#define QCOM_CTIOUTEN 0x800 +#define QCOM_CTITRIGINSTATUS 0x040 +#define QCOM_CTITRIGOUTSTATUS 0x060 +#define QCOM_CTICHINSTATUS 0x080 +#define QCOM_CTICHOUTSTATUS 0x084 +#define QCOM_CTIGATE 0x088 +#define QCOM_ASICCTL 0x08C +/* Integration test registers */ +#define QCOM_ITCHINACK 0xE70 +#define QCOM_ITTRIGINACK 0xE80 +#define QCOM_ITCHOUT 0xE74 +#define QCOM_ITTRIGOUT 0xEA0 +#define QCOM_ITCHOUTACK 0xE78 +#define QCOM_ITTRIGOUTACK 0xEC0 +#define QCOM_ITCHIN 0xE7C +#define QCOM_ITTRIGIN 0xEE0 =20 /** * Group of related trigger signals @@ -168,6 +194,9 @@ struct cti_config { * @spinlock: Control data access to one at a time. * @config: Configuration data for this CTI device. * @node: List entry of this device in the list of CTI devices. + * @is_qcom_cti: True if this CTI is a Qualcomm vendor-specific + * variant that requires register offset translation + * via cti_qcom_reg_off(). */ struct cti_drvdata { void __iomem *base; @@ -176,6 +205,7 @@ struct cti_drvdata { raw_spinlock_t spinlock; struct cti_config config; struct list_head node; + bool is_qcom_cti; }; =20 /* @@ -229,9 +259,41 @@ struct coresight_platform_data * coresight_cti_get_platform_data(struct device *dev); const char *cti_plat_get_node_name(struct fwnode_handle *fwnode); =20 +static inline u32 cti_qcom_reg_off(u32 offset) +{ + switch (offset) { + case CTIINTACK: return QCOM_CTIINTACK; + case CTIAPPSET: return QCOM_CTIAPPSET; + case CTIAPPCLEAR: return QCOM_CTIAPPCLEAR; + case CTIAPPPULSE: return QCOM_CTIAPPPULSE; + case CTIINEN: return QCOM_CTIINEN; + case CTIOUTEN: return QCOM_CTIOUTEN; + case CTITRIGINSTATUS: return QCOM_CTITRIGINSTATUS; + case CTITRIGOUTSTATUS: return QCOM_CTITRIGOUTSTATUS; + case CTICHINSTATUS: return QCOM_CTICHINSTATUS; + case CTICHOUTSTATUS: return QCOM_CTICHOUTSTATUS; + case CTIGATE: return QCOM_CTIGATE; + case ASICCTL: return QCOM_ASICCTL; + case ITCHINACK: return QCOM_ITCHINACK; + case ITTRIGINACK: return QCOM_ITTRIGINACK; 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Multiple instances of these registers are required to expose the full trigger space. Add coresight_cti_reg_index(), coresight_cti_reg_rw_index(), and coresight_cti_reg_wo_index() macros that carry the bank index in the cs_off_attribute.index field, keeping the base offset and index separate rather than encoding them together. Add static sysfs entries for the banked CTI registers and control their visibility based on the underlying hardware configuration. Visibility is determined by comparing the attribute's index against the number of banks implied by nr_trig_max (32 triggers per bank). Registers beyond the hardware capacity are hidden, preserving the existing ABI on standard ARM CTIs while exposing the full register set on Qualcomm CTIs. Reviewed-by: Leo Yan Signed-off-by: Yingchao Deng --- drivers/hwtracing/coresight/coresight-cti-sysfs.c | 58 +++++++++++++++++++= ++++ 1 file changed, 58 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-cti-sysfs.c b/drivers/hw= tracing/coresight/coresight-cti-sysfs.c index 6165866eaefe..175f20d69232 100644 --- a/drivers/hwtracing/coresight/coresight-cti-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-cti-sysfs.c @@ -207,6 +207,15 @@ static __maybe_unused ssize_t coresight_cti_reg_store(= struct device *dev, } \ })[0].attr.attr) =20 +#define coresight_cti_reg_index(name, offset, idx) \ + (&((struct cs_off_attribute[]) { \ + { \ + __ATTR(name, 0444, coresight_cti_reg_show, NULL), \ + offset, \ + idx \ + } \ + })[0].attr.attr) + #define coresight_cti_reg_rw(name, offset) \ (&((struct cs_off_attribute[]) { \ { \ @@ -217,6 +226,16 @@ static __maybe_unused ssize_t coresight_cti_reg_store(= struct device *dev, } \ })[0].attr.attr) =20 +#define coresight_cti_reg_rw_index(name, offset, idx) \ + (&((struct cs_off_attribute[]) { \ + { \ + __ATTR(name, 0644, coresight_cti_reg_show, \ + coresight_cti_reg_store), \ + offset, \ + idx \ + } \ + })[0].attr.attr) + #define coresight_cti_reg_wo(name, offset) \ (&((struct cs_off_attribute[]) { \ { \ @@ -226,6 +245,15 @@ static __maybe_unused ssize_t coresight_cti_reg_store(= struct device *dev, } \ })[0].attr.attr) =20 +#define coresight_cti_reg_wo_index(name, offset, idx) \ + (&((struct cs_off_attribute[]) { \ + { \ + __ATTR(name, 0200, NULL, coresight_cti_reg_store), \ + offset, \ + idx \ + } \ + })[0].attr.attr) + /* coresight management registers */ static struct attribute *coresight_cti_mgmt_attrs[] =3D { coresight_cti_reg(devaff0, CTIDEVAFF0), @@ -515,18 +543,36 @@ static struct attribute *coresight_cti_regs_attrs[] = =3D { &dev_attr_appclear.attr, &dev_attr_apppulse.attr, coresight_cti_reg(triginstatus, CTITRIGINSTATUS), + coresight_cti_reg_index(triginstatus1, CTITRIGINSTATUS, 1), + coresight_cti_reg_index(triginstatus2, CTITRIGINSTATUS, 2), + coresight_cti_reg_index(triginstatus3, CTITRIGINSTATUS, 3), coresight_cti_reg(trigoutstatus, CTITRIGOUTSTATUS), + coresight_cti_reg_index(trigoutstatus1, CTITRIGOUTSTATUS, 1), + coresight_cti_reg_index(trigoutstatus2, CTITRIGOUTSTATUS, 2), + coresight_cti_reg_index(trigoutstatus3, CTITRIGOUTSTATUS, 3), coresight_cti_reg(chinstatus, CTICHINSTATUS), coresight_cti_reg(choutstatus, CTICHOUTSTATUS), #ifdef CONFIG_CORESIGHT_CTI_INTEGRATION_REGS coresight_cti_reg_rw(itctrl, CORESIGHT_ITCTRL), coresight_cti_reg(ittrigin, ITTRIGIN), + coresight_cti_reg_index(ittrigin1, ITTRIGIN, 1), + coresight_cti_reg_index(ittrigin2, ITTRIGIN, 2), + coresight_cti_reg_index(ittrigin3, ITTRIGIN, 3), coresight_cti_reg(itchin, ITCHIN), coresight_cti_reg_rw(ittrigout, ITTRIGOUT), + coresight_cti_reg_rw_index(ittrigout1, ITTRIGOUT, 1), + coresight_cti_reg_rw_index(ittrigout2, ITTRIGOUT, 2), + coresight_cti_reg_rw_index(ittrigout3, ITTRIGOUT, 3), coresight_cti_reg_rw(itchout, ITCHOUT), coresight_cti_reg(itchoutack, ITCHOUTACK), coresight_cti_reg(ittrigoutack, ITTRIGOUTACK), + coresight_cti_reg_index(ittrigoutack1, ITTRIGOUTACK, 1), + coresight_cti_reg_index(ittrigoutack2, ITTRIGOUTACK, 2), + coresight_cti_reg_index(ittrigoutack3, ITTRIGOUTACK, 3), coresight_cti_reg_wo(ittriginack, ITTRIGINACK), + coresight_cti_reg_wo_index(ittriginack1, ITTRIGINACK, 1), + coresight_cti_reg_wo_index(ittriginack2, ITTRIGINACK, 2), + coresight_cti_reg_wo_index(ittriginack3, ITTRIGINACK, 3), coresight_cti_reg_wo(itchinack, ITCHINACK), #endif NULL, @@ -537,10 +583,22 @@ static umode_t coresight_cti_regs_is_visible(struct k= object *kobj, { struct device *dev =3D kobj_to_dev(kobj); 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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-8434b03fd0bsm9968393b3a.50.2026.06.15.05.33.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Jun 2026 05:33:22 -0700 (PDT) From: Yingchao Deng Date: Mon, 15 Jun 2026 20:32:33 +0800 Subject: [PATCH v10 5/5] coresight: cti: document banked and missing base CTI sysfs registers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260615-extended_cti-v10-5-1c1694b6d8ed@oss.qualcomm.com> References: <20260615-extended_cti-v10-0-1c1694b6d8ed@oss.qualcomm.com> In-Reply-To: <20260615-extended_cti-v10-0-1c1694b6d8ed@oss.qualcomm.com> To: Suzuki K Poulose , Mike Leach , James Clark , Leo Yan , Alexander Shishkin Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, quic_yingdeng@quicinc.com, tingwei.zhang@oss.qualcomm.com, Jinlong Mao , jie.gan@oss.qualcomm.com, Yingchao Deng X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1781526782; l=4728; i=yingchao.deng@oss.qualcomm.com; s=20260611; h=from:subject:message-id; bh=sVNEsaKI0s3R6oPe1epN5ZwL+HwElnwD/2wqBgGhWsc=; b=xrjzXq+0FweLFMAZP6AFuQu+4WYGHuaVkvve5aDJ9J4hda+bhLUMZE3XQOwes46WyedpL9P34 yq3JNirfcD4AaZ+Zaj2JLxOo9yCEP2ml2BAz1gpbGpZ8fG/wQq7xtet X-Developer-Key: i=yingchao.deng@oss.qualcomm.com; a=ed25519; pk=+y3U2mIt7mf0C+x6qBUD670cd9S2QV+yl5015bUYMgs= X-Proofpoint-Spam-Info: AW1haW4tMjYwNjE1MDEzMiBTYWx0ZWRfXzvqL+umlO+Hr +bx4oRCpyWZ/4ELAm1H6YRPzCL8sywot06MjllE0a02z2LZiDcljZD8lmz/AS5XNmnFflpnN9uT icDu7ZbETQD+pMMPOP48T30A2t9oFL4= X-Authority-Analysis: v=2.4 cv=Zqnd7d7G c=1 sm=1 tr=0 ts=6a2ff114 cx=c_pps a=mDZGXZTwRPZaeRUbqKGCBw==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=EUspDBNiAAAA:8 a=KKAkSRfTAAAA:8 a=ZlVeDcQYEk3IPcOgC64A:9 a=QEXdDO2ut3YA:10 a=zc0IvFSfCIW2DFIPzwfm:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-GUID: 1me3rQVdrVglZt3pPL0m0bo1vGVJnx9K X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjE1MDEzMiBTYWx0ZWRfXxZmXRrjce7PP uJo8xsRq9Evtb6HyDsmmN0VRFLf1DeYNo0jghFIf78g4nPNNdsOyNtfWo2wbFRE959CnKFCW2Fo OsmWomgDhYqiBIr/tU6b7gk/m5/kl/CYD8Q+Fjz9FzS4v9fhHKJP0/jIC/m/C0BmsxxVXI9J2GQ JXdUb+nChiRfuuLVGk2PFOgVkBgI/iol1Udk+p5Ji5dfBwYu6hh7p6fPq1+DF2Wnk4c/uUqfNpa reDx4cixiksNy9yWQGC6i/7sX59/gPTryc075SlHUN3UHd8fTJFONtxwmBaFnJBGIG20H9RSKKZ Z5Z8DxLSN5Pth3O5EFUd05uD8KJsG8Q2hYIOWCIyepBIGwkymEi5ejW9aTGlmnB60GGhGD4yATn Ke+B73cGqQA1eQDXkcmffj8+G4TIPv+jEPAWBANGZNXzaUTfTA/R5wyf8tZZNl3PEcktDEq4IuI dqSMwnhloUMCYo9DYXg== X-Proofpoint-ORIG-GUID: 1me3rQVdrVglZt3pPL0m0bo1vGVJnx9K X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-15_03,2026-06-15_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 spamscore=0 priorityscore=1501 suspectscore=0 lowpriorityscore=0 adultscore=0 malwarescore=0 clxscore=1015 impostorscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606040000 definitions=main-2606150132 Document the new sysfs entries triginstatus[1-3], trigoutstatus[1-3], ittrigin[1-3], ittrigout[1-3], ittrigoutack[1-3] and ittriginack[1-3] in the coresight-cti ABI documentation. Also document the previously undocumented base integration test registers itctrl, itchin, itchinack, ittrigin, ittriginack, itchout, itchoutack, ittrigout and ittrigoutack, which were introduced in kernel version 5.7. Signed-off-by: Yingchao Deng --- .../ABI/testing/sysfs-bus-coresight-devices-cti | 90 ++++++++++++++++++= ++++ 1 file changed, 90 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-cti b/Do= cumentation/ABI/testing/sysfs-bus-coresight-devices-cti index a2aef7f5a6d7..9d7831ac455b 100644 --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-cti +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-cti @@ -128,12 +128,102 @@ KernelVersion: 5.7 Contact: Mike Leach or Mathieu Poirier Description: (Read) read current status of input trigger signals =20 +What: /sys/bus/coresight/devices//regs/triginstatus[1-3] +Date: June 2026 +KernelVersion: 7.3 +Contact: Jinlong Mao +Description: (Read) read current status of QCOM extended input trigger sig= nals. + What: /sys/bus/coresight/devices//regs/trigoutstatus Date: March 2020 KernelVersion: 5.7 Contact: Mike Leach or Mathieu Poirier Description: (Read) read current status of output trigger signals. =20 +What: /sys/bus/coresight/devices//regs/trigoutstatus[1-3] +Date: June 2026 +KernelVersion: 7.3 +Contact: Jinlong Mao +Description: (Read) read current status of QCOM extended output trigger si= gnals. + +What: /sys/bus/coresight/devices//regs/itctrl +Date: March 2020 +KernelVersion: 5.7 +Contact: coresight@lists.linaro.org +Description: (RW) Control integration mode. + +What: /sys/bus/coresight/devices//regs/itchin +Date: March 2020 +KernelVersion: 5.7 +Contact: coresight@lists.linaro.org +Description: (Read) Read the values of the CTCHIN inputs. + +What: /sys/bus/coresight/devices//regs/itchinack +Date: March 2020 +KernelVersion: 5.7 +Contact: coresight@lists.linaro.org +Description: (Write) Write the value of the CTCHINACK input. + +What: /sys/bus/coresight/devices//regs/ittrigin +Date: March 2020 +KernelVersion: 5.7 +Contact: coresight@lists.linaro.org +Description: (Read) Read the values of the CTTRIGIN inputs. + +What: /sys/bus/coresight/devices//regs/ittrigin[1-3] +Date: June 2026 +KernelVersion: 7.3 +Contact: Jinlong Mao +Description: (Read) Read the values of the QCOM extended CTTRIGIN inputs. + +What: /sys/bus/coresight/devices//regs/ittriginack +Date: March 2020 +KernelVersion: 5.7 +Contact: coresight@lists.linaro.org +Description: (Write) Write the value of the CTTRIGINACK input. + +What: /sys/bus/coresight/devices//regs/ittriginack[1-3] +Date: June 2026 +KernelVersion: 7.3 +Contact: Jinlong Mao +Description: (Write) Write the value of the QCOM extended CTTRIGINACK inpu= t. + +What: /sys/bus/coresight/devices//regs/itchout +Date: March 2020 +KernelVersion: 5.7 +Contact: coresight@lists.linaro.org +Description: (RW) Read or write the value of the CTCHOUT outputs. + +What: /sys/bus/coresight/devices//regs/itchoutack +Date: March 2020 +KernelVersion: 5.7 +Contact: coresight@lists.linaro.org +Description: (Read) Read the value of the CTCHOUTACK input. + +What: /sys/bus/coresight/devices//regs/ittrigout +Date: March 2020 +KernelVersion: 5.7 +Contact: coresight@lists.linaro.org +Description: (RW) Read or write the value of the CTTRIGOUT outputs. + +What: /sys/bus/coresight/devices//regs/ittrigout[1-3] +Date: June 2026 +KernelVersion: 7.3 +Contact: Jinlong Mao +Description: (RW) Read or write the value of the QCOM extended CTTRIGOUT o= utputs. + +What: /sys/bus/coresight/devices//regs/ittrigoutack +Date: March 2020 +KernelVersion: 5.7 +Contact: coresight@lists.linaro.org +Description: (Read) Read the value of the CTTRIGOUTACK input. + +What: /sys/bus/coresight/devices//regs/ittrigoutack[1-3] +Date: June 2026 +KernelVersion: 7.3 +Contact: Jinlong Mao +Description: (Read) Read the value of the QCOM extended CTTRIGOUTACK input. + What: /sys/bus/coresight/devices//channels/trigin_attach Date: March 2020 KernelVersion: 5.7 --=20 2.43.0