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The SoM integrates the Shikra SoC, PMICs, and essential passives, and is designed to be mounted on carrier boards. Three eSoM variant are introduced: - CQM: retail variant with integrated modem (PM4125 and PM8005 PMIC) - CQS: retail variant without modem (PM4125 and PM8005 PMIC) - IQS: industrial-grade variant without modem (PM8150 PMIC) Each SoM variant pairs with a common EVK carrier board provides debug UART, USB, and other peripheral interfaces. Add compatible strings for the CQ2390M, CQ2390S, IQ2390S SoM variant and its corresponding EVK boards. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Komal Bajaj --- Documentation/devicetree/bindings/arm/qcom.yaml | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentatio= n/devicetree/bindings/arm/qcom.yaml index 50cc18a6ec5e..cf7d241f8107 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -989,6 +989,24 @@ properties: - xiaomi,polaris - const: qcom,sdm845 =20 + - items: + - enum: + - qcom,shikra-cqm-evk + - const: qcom,shikra-cqm-som + - const: qcom,shikra + + - items: + - enum: + - qcom,shikra-cqs-evk + - const: qcom,shikra-cqs-som + - const: qcom,shikra + + - items: + - enum: + - qcom,shikra-iqs-evk + - const: qcom,shikra-iqs-som + - const: qcom,shikra + - items: - enum: - oneplus,billie2 --=20 2.34.1 From nobody Fri Jun 12 22:51:12 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D5C3B33BBBA for ; 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Fri, 12 Jun 2026 10:28:00 -0700 (PDT) Received: from [10.213.101.118] ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2c4327acae2sm24278105ad.52.2026.06.12.10.27.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 12 Jun 2026 10:28:00 -0700 (PDT) From: Komal Bajaj Date: Fri, 12 Jun 2026 22:57:38 +0530 Subject: [PATCH v6 2/5] arm64: dts: qcom: Introduce Shikra SoC base dtsi Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260612-shikra-dt-v6-2-6b6cb58db477@oss.qualcomm.com> References: <20260612-shikra-dt-v6-0-6b6cb58db477@oss.qualcomm.com> In-Reply-To: <20260612-shikra-dt-v6-0-6b6cb58db477@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Vinod Koul , Neil Armstrong , Wesley Cheng , Ulf Hansson Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-mmc@vger.kernel.org, monish.chunara@oss.qualcomm.com, Komal Bajaj , Imran Shaik , Monish Chunara , Rakesh Kota , Raviteja Laggyshetty , Sneh Mankad , Vishnu Santhosh , Xueyao An , Konrad Dybcio X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; 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Enable support for the following peripherals: - CPU nodes - Global Clock Controller (GCC) - RPM-based clock controller (RPMCC) and power domains (RPMPD) - Interrupt controller - Top Level Mode Multiplexer (TLMM) - Debug UART - eMMC host controller - System timer and watchdog Co-developed-by: Imran Shaik Signed-off-by: Imran Shaik Co-developed-by: Monish Chunara Signed-off-by: Monish Chunara Co-developed-by: Rakesh Kota Signed-off-by: Rakesh Kota Co-developed-by: Raviteja Laggyshetty Signed-off-by: Raviteja Laggyshetty Co-developed-by: Sneh Mankad Signed-off-by: Sneh Mankad Co-developed-by: Vishnu Santhosh Signed-off-by: Vishnu Santhosh Co-developed-by: Xueyao An Signed-off-by: Xueyao An Reviewed-by: Konrad Dybcio Signed-off-by: Komal Bajaj --- arch/arm64/boot/dts/qcom/shikra.dtsi | 842 +++++++++++++++++++++++++++++++= ++++ 1 file changed, 842 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qco= m/shikra.dtsi new file mode 100644 index 000000000000..4e5bc9e17c8e --- /dev/null +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -0,0 +1,842 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include +#include +#include + +/ { + interrupt-parent =3D <&intc>; + + #address-cells =3D <2>; + #size-cells =3D <2>; + + clocks { + xo_board: xo-board { + compatible =3D "fixed-clock"; + clock-frequency =3D <38400000>; + #clock-cells =3D <0>; + }; + + sleep_clk: sleep-clk { + compatible =3D "fixed-clock"; + clock-frequency =3D <32764>; + #clock-cells =3D <0>; + }; + }; + + cpus { + #address-cells =3D <2>; + #size-cells =3D <0>; + + cpu0: cpu@0 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x0 0x0>; + enable-method =3D "psci"; + next-level-cache =3D <&l3>; + capacity-dmips-mhz =3D <1024>; + dynamic-power-coefficient =3D <100>; + }; + + cpu1: cpu@100 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x0 0x100>; + enable-method =3D "psci"; + next-level-cache =3D <&l3>; + capacity-dmips-mhz =3D <1024>; + dynamic-power-coefficient =3D <100>; + }; + + cpu2: cpu@200 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a55"; + reg =3D <0x0 0x200>; + enable-method =3D "psci"; + next-level-cache =3D <&l3>; + capacity-dmips-mhz =3D <1024>; + dynamic-power-coefficient =3D <100>; + }; + + cpu3: cpu@300 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a78c"; + reg =3D <0x0 0x300>; + enable-method =3D "psci"; + next-level-cache =3D <&l2_3>; + capacity-dmips-mhz =3D <1946>; + dynamic-power-coefficient =3D <489>; + + l2_3: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3>; + cache-size =3D <0x40000>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu =3D <&cpu0>; + }; + + core1 { + cpu =3D <&cpu1>; + }; + + core2 { + cpu =3D <&cpu2>; + }; + }; + + cluster1 { + core0 { + cpu =3D <&cpu3>; + }; + }; + }; + + l3: l3-cache { + compatible =3D "cache"; + cache-level =3D <3>; + cache-unified; + cache-size =3D <0x80000>; + }; + }; + + firmware { + scm { + compatible =3D "qcom,scm-shikra", "qcom,scm"; + clocks =3D <&rpmcc RPM_SMD_CE1_CLK>; + clock-names =3D "core"; + qcom,dload-mode =3D <&tcsr_regs 0x13000>; + #reset-cells =3D <1>; + interconnects =3D <&system_noc MASTER_CRYPTO_CORE0 RPM_ALWAYS_TAG + &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; + }; + }; + + memory@80000000 { + device_type =3D "memory"; + /* We expect the bootloader to fill in the size */ + reg =3D <0x0 0x80000000 0x0 0x0>; + }; + + pmu-a55 { + compatible =3D "arm,cortex-a55-pmu"; + interrupts =3D ; + }; + + pmu-a78c { + compatible =3D "arm,cortex-a78-pmu"; + interrupts =3D ; + }; + + psci { + compatible =3D "arm,psci-1.0"; + method =3D "smc"; + }; + + rpm: remoteproc { + compatible =3D "qcom,shikra-rpm-proc", "qcom,rpm-proc"; + + glink-edge { + compatible =3D "qcom,glink-rpm"; + interrupts =3D ; + qcom,rpm-msg-ram =3D <&rpm_msg_ram>; + mboxes =3D <&apcs_glb 0>; + + rpm_requests: rpm-requests { + compatible =3D "qcom,rpm-shikra", "qcom,glink-smd-rpm"; + qcom,glink-channels =3D "rpm_requests"; + + rpmcc: clock-controller { + compatible =3D "qcom,rpmcc-shikra", "qcom,rpmcc-qcm2290", "qcom,rpmcc= "; + clocks =3D <&xo_board>; + clock-names =3D "xo"; + #clock-cells =3D <1>; + }; + + rpmpd: power-controller { + compatible =3D "qcom,shikra-rpmpd"; + #power-domain-cells =3D <1>; + operating-points-v2 =3D <&rpmpd_opp_table>; + + rpmpd_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + rpmpd_opp_min_svs: opp1 { + opp-level =3D ; + }; + + rpmpd_opp_low_svs: opp2 { + opp-level =3D ; + }; + + rpmpd_opp_svs: opp3 { + opp-level =3D ; + }; + + rpmpd_opp_svs_plus: opp4 { + opp-level =3D ; + }; + + rpmpd_opp_nom: opp5 { + opp-level =3D ; + }; + + rpmpd_opp_nom_plus: opp6 { + opp-level =3D ; + }; + + rpmpd_opp_turbo: opp7 { + opp-level =3D ; + }; + + rpmpd_opp_turbo_plus: opp8 { + opp-level =3D ; + }; + }; + }; + }; + }; + + mpm: interrupt-controller { + compatible =3D "qcom,mpm"; + qcom,rpm-msg-ram =3D <&apss_mpm>; + interrupts =3D ; + mboxes =3D <&apcs_glb 1>; + interrupt-controller; + #interrupt-cells =3D <2>; + #power-domain-cells =3D <0>; + interrupt-parent =3D <&intc>; + qcom,mpm-pin-count =3D <96>; + qcom,mpm-pin-map =3D <2 275>, /* TSENS0 uplow */ + <12 422>, /* DWC3 ss_phy_irq */ + <58 272>, /* QUSB2_PHY dmse_hv_vddmx */ + <59 273>, /* QUSB2_PHY dpse_hv_vddmx */ + <86 183>, /* MPM wake, SPMI */ + <90 157>, /* QUSB2_PHY DM */ + <91 158>; /* QUSB2_PHY DP */ + }; + }; + + reserved_memory: reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + hyp_mem: hyp@80000000 { + reg =3D <0x0 0x80000000 0x0 0x1600000>; + no-map; + }; + + xblboot_mem: xblboot@85e00000 { + reg =3D <0x0 0x85e00000 0x0 0x100000>; + no-map; + }; + + secdata_apss_mem: secdata-apss@85fff000 { + reg =3D <0x0 0x85fff000 0x0 0x1000>; + no-map; + }; + + smem_mem: smem@86000000 { + compatible =3D "qcom,smem"; + reg =3D <0x0 0x86000000 0x0 0x200000>; + no-map; + + hwlocks =3D <&tcsr_mutex 3>; + }; + + audio_heap_mem: audio-heap@86200000 { + reg =3D <0x0 0x86200000 0x0 0x100000>; + no-map; + }; + + tz_stat_mem: tz-stat@a0000000 { + reg =3D <0x0 0xa0000000 0x0 0x100000>; + no-map; + }; + + qtee_mem: qtee@a1300000 { + reg =3D <0x0 0xa1300000 0x0 0x500000>; + no-map; + }; + + tz_apps_mem: tz-apps@a1800000 { + reg =3D <0x0 0xa1800000 0x0 0x2100000>; + no-map; + }; + + mpss_wlan_mem: mpss-wlan@ab000000 { + reg =3D <0x0 0xab000000 0x0 0x6e00000>; + no-map; + }; + + wlan_mem: wlan@b2300000 { + reg =3D <0x0 0xb2300000 0x0 0x100000>; + no-map; + }; + + cdsp_mem: cdsp@b2400000 { + reg =3D <0x0 0xb2400000 0x0 0x1900000>; + no-map; + }; + + gpu_micro_code_mem: gpu-micro-code@b3d00000 { + reg =3D <0x0 0xb3d00000 0x0 0x2000>; + no-map; + }; + + video_mem: video@b3d02000 { + reg =3D <0x0 0xb3d02000 0x0 0x700000>; + no-map; + }; + + lmcu_mem: lmcu@b4402000 { + reg =3D <0x0 0xb4402000 0x0 0x300000>; + no-map; + }; + + lmcu_dtb_mem: lmcu-dtb@b4702000 { + reg =3D <0x0 0xb4702000 0x0 0x40000>; + no-map; + }; + }; + + soc: soc@0 { + compatible =3D "simple-bus"; + + #address-cells =3D <2>; + #size-cells =3D <2>; + dma-ranges =3D <0x0 0x0 0x0 0x0 0x10 0x0>; + ranges =3D <0x0 0x0 0x0 0x0 0x10 0x0>; + + tcsr_mutex: syscon@340000 { + compatible =3D "qcom,tcsr-mutex"; + reg =3D <0x0 0x00340000 0x0 0x20000>; + #hwlock-cells =3D <1>; + }; + + tcsr_regs: syscon@3c0000 { + compatible =3D "qcom,shikra-tcsr", "syscon"; + reg =3D <0x0 0x003c0000 0x0 0x40000>; + }; + + tlmm: pinctrl@500000 { + compatible =3D "qcom,shikra-tlmm"; + reg =3D <0x0 0x00500000 0x0 0x700000>; + + interrupts =3D ; + + gpio-controller; + #gpio-cells =3D <2>; + + interrupt-controller; + #interrupt-cells =3D <2>; + + gpio-ranges =3D <&tlmm 0 0 165>; + wakeup-parent =3D <&mpm>; + + qup_uart0_default: qup-uart0-default-state { + pins =3D "gpio0", "gpio1"; + function =3D "qup0_se0"; + drive-strength =3D <2>; + bias-disable; + }; + + sdc1_state_on: sdc1-on-state { + clk-pins { + pins =3D "sdc1_clk"; + drive-strength =3D <6>; + bias-disable; + }; + + cmd-pins { + pins =3D "sdc1_cmd"; + drive-strength =3D <6>; + bias-pull-up; + }; + + data-pins { + pins =3D "sdc1_data"; + drive-strength =3D <6>; + bias-pull-up; + }; + + rclk-pins { + pins =3D "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc1_state_off: sdc1-off-state { + clk-pins { + pins =3D "sdc1_clk"; + drive-strength =3D <2>; + bias-bus-hold; + }; + + cmd-pins { + pins =3D "sdc1_cmd"; + drive-strength =3D <2>; + bias-bus-hold; + }; + + data-pins { + pins =3D "sdc1_data"; + drive-strength =3D <2>; + bias-bus-hold; + }; + + rclk-pins { + pins =3D "sdc1_rclk"; + bias-bus-hold; + }; + }; + }; + + mem_noc: interconnect@d00000 { + compatible =3D "qcom,shikra-mem-noc-core"; + reg =3D <0x0 0x00d00000 0x0 0x43080>; + clocks =3D <&gcc GCC_DDRSS_GPU_AXI_CLK>; + clock-names =3D "gpu_axi"; + #interconnect-cells =3D <2>; + }; + + llcc: system-cache-controller@e00000 { + compatible =3D "qcom,shikra-llcc"; + reg =3D <0x0 0x00e00000 0x0 0x80000>, + <0x0 0x00f00000 0x0 0x80000>, + <0x0 0x01000000 0x0 0x80000>; + reg-names =3D "llcc0_base", + "llcc1_base", + "llcc_broadcast_base"; + interrupts =3D ; + }; + + gcc: clock-controller@1400000 { + compatible =3D "qcom,shikra-gcc"; + reg =3D <0x0 0x01400000 0x0 0x1f0000>; + clocks =3D <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&sleep_clk>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>; + power-domains =3D <&rpmpd RPMPD_VDDCX>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + + system_noc: interconnect@1880000 { + compatible =3D "qcom,shikra-sys-noc"; + reg =3D <0x0 0x01880000 0x0 0x6a080>; + clocks =3D <&gcc GCC_EMAC0_AXI_SYS_NOC_CLK>, + <&gcc GCC_EMAC1_AXI_SYS_NOC_CLK>, + <&gcc GCC_SYS_NOC_USB2_PRIM_AXI_CLK>, + <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>; + clock-names =3D "emac0_axi", + "emac1_axi", + "usb2_axi", + "usb3_axi"; + #interconnect-cells =3D <2>; + + clk_virt: interconnect-clk { + compatible =3D "qcom,shikra-clk-virt"; + #interconnect-cells =3D <2>; + }; + + mc_virt: interconnect-mc { + compatible =3D "qcom,shikra-mc-virt"; + #interconnect-cells =3D <2>; + }; + + mmrt_virt: interconnect-mmrt { + compatible =3D "qcom,shikra-mmrt-virt"; + #interconnect-cells =3D <2>; + }; + + mmnrt_virt: interconnect-mmnrt { + compatible =3D "qcom,shikra-mmnrt-virt"; + #interconnect-cells =3D <2>; + }; + }; + + config_noc: interconnect@1900000 { + compatible =3D "qcom,shikra-config-noc"; + reg =3D <0x0 0x01900000 0x0 0x8080>; + #interconnect-cells =3D <2>; + }; + + qfprom: efuse@1b44000 { + compatible =3D "qcom,shikra-qfprom", "qcom,qfprom"; + reg =3D <0x0 0x01b44000 0x0 0x3000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + qusb2_hstx_trim_1: hstx-trim@25b { + reg =3D <0x25b 0x1>; + bits =3D <1 4>; + }; + + gpu_speed_bin: gpu-speed-bin@2006 { + reg =3D <0x2006 0x2>; + bits =3D <5 8>; + }; + }; + + spmi_bus: spmi@1c40000 { + compatible =3D "qcom,spmi-pmic-arb"; + reg =3D <0x0 0x01c40000 0x0 0x1100>, + <0x0 0x01e00000 0x0 0x2000000>, + <0x0 0x03e00000 0x0 0x100000>, + <0x0 0x03f00000 0x0 0xa0000>, + <0x0 0x01c0a000 0x0 0x26000>; + reg-names =3D "core", + "chnls", + "obsrvr", + "intr", + "cnfg"; + interrupts-extended =3D <&mpm 86 IRQ_TYPE_EDGE_RISING>; + interrupt-names =3D "periph_irq"; + interrupt-controller; + #interrupt-cells =3D <4>; + #address-cells =3D <2>; + #size-cells =3D <0>; + qcom,channel =3D <0>; + qcom,ee =3D <0>; + }; + + rpm_msg_ram: sram@45f0000 { + compatible =3D "qcom,rpm-msg-ram", "mmio-sram"; + reg =3D <0x0 0x045f0000 0x0 0x7000>; + + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x0 0x0 0x045f0000 0x7000>; + + apss_mpm: sram@1b8 { + reg =3D <0x1b8 0x48>; + }; + }; + + sram@4690000 { + compatible =3D "qcom,rpm-stats"; + reg =3D <0x0 0x04690000 0x0 0x14000>; + }; + + sdhc_1: mmc@4744000 { + compatible =3D "qcom,shikra-sdhci", "qcom,sdhci-msm-v5"; + + reg =3D <0x0 0x04744000 0x0 0x1000>, + <0x0 0x04745000 0x0 0x1000>; + reg-names =3D "hc", + "cqhci"; + + iommus =3D <&apps_smmu 0xc0 0x0>; + + interrupts =3D , + ; + interrupt-names =3D "hc_irq", + "pwr_irq"; + + clocks =3D <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names =3D "iface", + "core", + "xo"; + + interconnects =3D <&system_noc MASTER_SDCC_1 RPM_ALWAYS_TAG + &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ACTIVE_TAG + &config_noc SLAVE_SDCC_1 RPM_ACTIVE_TAG>; + interconnect-names =3D "sdhc-ddr", + "cpu-sdhc"; + + power-domains =3D <&rpmpd RPMPD_VDDCX>; + operating-points-v2 =3D <&sdhc1_opp_table>; + + qcom,dll-config =3D <0x000f642c>; + qcom,ddr-config =3D <0x80040868>; + + bus-width =3D <8>; + + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + + resets =3D <&gcc GCC_SDCC1_BCR>; + + status =3D "disabled"; + + sdhc1_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-100000000 { + opp-hz =3D /bits/ 64 <100000000>; + required-opps =3D <&rpmpd_opp_low_svs>; + opp-peak-kBps =3D <250000 133320>; + opp-avg-kBps =3D <104000 0>; + }; + + opp-384000000 { + opp-hz =3D /bits/ 64 <384000000>; + required-opps =3D <&rpmpd_opp_nom>; + opp-peak-kBps =3D <800000 300000>; + opp-avg-kBps =3D <400000 0>; + }; + }; + }; + + qupv3_0: geniqup@4ac0000 { + compatible =3D "qcom,geni-se-qup"; + reg =3D <0x0 0x04ac0000 0x0 0x2000>; + + clocks =3D <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + clock-names =3D "m-ahb", + "s-ahb"; + + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + uart0: serial@4a80000 { + compatible =3D "qcom,geni-debug-uart"; + reg =3D <0x0 0x04a80000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; + interconnect-names =3D "qup-core", + "qup-config"; + + pinctrl-0 =3D <&qup_uart0_default>; + pinctrl-names =3D "default"; + + status =3D "disabled"; + }; + }; + + sram@c11e000 { + compatible =3D "qcom,shikra-imem", "mmio-sram"; + reg =3D <0x0 0x0c11e000 0x0 0x1000>; + ranges =3D <0x0 0x0 0x0c11e000 0x1000>; + + no-memory-wc; + + #address-cells =3D <1>; + #size-cells =3D <1>; + + pil-sram@94c { + compatible =3D "qcom,pil-reloc-info"; + reg =3D <0x94c 0xc8>; + }; + }; + + apps_smmu: iommu@c600000 { + compatible =3D "qcom,shikra-smmu-500", "qcom,smmu-500", "arm,mmu-500"; + reg =3D <0x0 0x0c600000 0x0 0x80000>; + #iommu-cells =3D <2>; + #global-interrupts =3D <1>; + + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + intc: interrupt-controller@f200000 { + compatible =3D "arm,gic-v3"; + reg =3D <0x0 0xf200000 0x0 0x10000>, + <0x0 0xf240000 0x0 0x80000>; + + interrupts =3D ; + + #interrupt-cells =3D <4>; + interrupt-controller; + + #redistributor-regions =3D <1>; + redistributor-stride =3D <0x0 0x20000>; + + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + ppi-partitions { + ppi_cluster0: interrupt-partition-0 { + affinity =3D <&cpu0 &cpu1 &cpu2>; + }; + + ppi_cluster1: interrupt-partition-1 { + affinity =3D <&cpu3>; + }; + }; + }; + + apcs_glb: mailbox@f400000 { + compatible =3D "qcom,shikra-apss-shared", "qcom,sdm845-apss-shared"; + reg =3D <0x0 0x0f400000 0x0 0x1000>; + #mbox-cells =3D <1>; + }; + + watchdog@f410000 { + compatible =3D "qcom,apss-wdt-shikra", "qcom,kpss-wdt"; + reg =3D <0x0 0x0f410000 0x0 0x1000>; + interrupts =3D , + ; + clocks =3D <&sleep_clk>; + }; + + timer@f420000 { + compatible =3D "arm,armv7-timer-mem"; + reg =3D <0x0 0x0f420000 0x0 0x1000>; + + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x0 0x0 0x0 0x10000000>; + + frame@f421000 { + reg =3D <0x0f421000 0x1000>, + <0x0f422000 0x1000>; + frame-number =3D <0>; + interrupts =3D , + ; + }; + + frame@f423000 { + reg =3D <0x0f423000 0x1000>; + frame-number =3D <1>; + interrupts =3D ; + status =3D "disabled"; + }; + + frame@f425000 { + reg =3D <0x0f425000 0x1000>; + frame-number =3D <2>; + interrupts =3D ; + status =3D "disabled"; + }; + + frame@f427000 { + reg =3D <0x0f427000 0x1000>; + frame-number =3D <3>; + interrupts =3D ; + status =3D "disabled"; + }; + + frame@f429000 { + reg =3D <0x0f429000 0x1000>; + frame-number =3D <4>; + interrupts =3D ; + status =3D "disabled"; + }; + + frame@f42b000 { + reg =3D <0x0f42b000 0x1000>; + frame-number =3D <5>; + interrupts =3D ; + status =3D "disabled"; + }; + + frame@f42d000 { + reg =3D <0x0f42d000 0x1000>; + frame-number =3D <6>; + interrupts =3D ; + status =3D "disabled"; + }; + }; + }; + + timer { + compatible =3D "arm,armv8-timer"; + + interrupts =3D , + , + , + ; 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Since PM8005 regulators are controlled by rpmpd, so disabling the pm8005 regulators. Co-developed-by: Rakesh Kota Signed-off-by: Rakesh Kota Reviewed-by: Dmitry Baryshkov Signed-off-by: Komal Bajaj --- arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi | 156 +++++++++++++++++++++++= ++++ 1 file changed, 156 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi b/arch/arm64/boot= /dts/qcom/shikra-cqm-som.dtsi new file mode 100644 index 000000000000..dc3861489f64 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi @@ -0,0 +1,156 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include + +#include "shikra.dtsi" +#include "pm4125.dtsi" +#include "pm8005.dtsi" + +/ { + gpio-keys { + compatible =3D "gpio-keys"; + label =3D "gpio-keys"; + pinctrl-0 =3D <&vol_up_n>; + pinctrl-names =3D "default"; + + key-volume-up { + label =3D "Volume Up"; + gpios =3D <&pm4125_gpios 9 GPIO_ACTIVE_LOW>; + linux,input-type =3D <1>; + linux,code =3D ; + wakeup-source; + debounce-interval =3D <15>; + linux,can-disable; + }; + }; +}; + +&pm4125_gpios { + vol_up_n: vol-up-n-state { + pins =3D "gpio9"; + function =3D PMIC_GPIO_FUNC_NORMAL; + input-enable; + bias-pull-up; + power-source =3D <0>; + }; +}; + +&pm4125_resin { + linux,code =3D ; + + status =3D "okay"; +}; + +&pm8005_regulators { + status =3D "disabled"; +}; + +&rpm_requests { + regulators { + compatible =3D "qcom,rpm-pm2250-regulators"; + + pm4125_s2: s2 { + regulator-min-microvolt =3D <1000000>; + regulator-max-microvolt =3D <1200000>; + }; + + pm4125_l3: l3 { + regulator-min-microvolt =3D <624000>; + regulator-max-microvolt =3D <650000>; + }; + + pm4125_l4: l4 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <2960000>; + }; + + pm4125_l5: l5 { + regulator-min-microvolt =3D <1232000>; + regulator-max-microvolt =3D <1304000>; + }; + + pm4125_l6: l6 { + regulator-min-microvolt =3D <788000>; + regulator-max-microvolt =3D <1050000>; + }; + + pm4125_l7: l7 { + regulator-min-microvolt =3D <664000>; + regulator-max-microvolt =3D <664000>; + }; + + pm4125_l8: l8 { + regulator-min-microvolt =3D <928000>; + regulator-max-microvolt =3D <1000000>; + }; + + pm4125_l9: l9 { + regulator-min-microvolt =3D <875000>; + regulator-max-microvolt =3D <1000000>; + }; + + pm4125_l10: l10 { + regulator-min-microvolt =3D <1304000>; + regulator-max-microvolt =3D <1304000>; + }; + + pm4125_l12: l12 { + regulator-min-microvolt =3D <928000>; + regulator-max-microvolt =3D <975000>; + }; + + pm4125_l13: l13 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + }; + + pm4125_l14: l14 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + }; + + pm4125_l15: l15 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + }; + + pm4125_l16: l16 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + }; + + pm4125_l17: l17 { + regulator-min-microvolt =3D <3000000>; + regulator-max-microvolt =3D <3544000>; + }; + + pm4125_l18: l18 { + regulator-min-microvolt =3D <1800000>; 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Reviewed-by: Dmitry Baryshkov Signed-off-by: Komal Bajaj --- arch/arm64/boot/dts/qcom/shikra-iqs-som.dtsi | 170 +++++++++++++++++++++++= ++++ 1 file changed, 170 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra-iqs-som.dtsi b/arch/arm64/boot= /dts/qcom/shikra-iqs-som.dtsi new file mode 100644 index 000000000000..73945bf42112 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/shikra-iqs-som.dtsi @@ -0,0 +1,170 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include + +#include "shikra.dtsi" +#include "pm8150.dtsi" + +/ { + gpio-key { + compatible =3D "gpio-keys"; + label =3D "gpio-keys"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&vol_up_n>; + + key-volume-up { + label =3D "Volume Up"; + gpios =3D <&pm8150_gpios 6 GPIO_ACTIVE_LOW>; + linux,input-type =3D <1>; + linux,code =3D ; + wakeup-source; + debounce-interval =3D <15>; + linux,can-disable; + }; + }; +}; + +&pm8150_gpios { + vol_up_n: vol-up-n-state { + pins =3D "gpio6"; + function =3D PMIC_GPIO_FUNC_NORMAL; + input-enable; + bias-pull-up; + power-source =3D <0>; + }; + +}; + +&pon_pwrkey { + status =3D "okay"; +}; + +&pon_resin { + linux,code =3D ; + status =3D "okay"; +}; + +&rpm_requests { + regulators { + compatible =3D "qcom,rpm-pm8150-regulators"; + + pm8150_s4: s4 { + regulator-min-microvolt =3D <1080000>; + regulator-max-microvolt =3D <2040000>; + }; + + pm8150_s5: s5 { + regulator-min-microvolt =3D <1574000>; + regulator-max-microvolt =3D <2040000>; + }; + + pm8150_s6: s6 { + regulator-min-microvolt =3D <382000>; + regulator-max-microvolt =3D <1352000>; + }; + + pm8150_s7: s7 { + regulator-min-microvolt =3D <1000000>; + regulator-max-microvolt =3D <1200000>; + }; + + pm8150_s8: s8 { + regulator-min-microvolt =3D <570000>; + regulator-max-microvolt =3D <650000>; + }; + + pm8150_l1: l1 { + regulator-min-microvolt =3D <312000>; + regulator-max-microvolt =3D <1304000>; + }; + + pm8150_l2: l2 { + regulator-min-microvolt =3D <1650000>; + regulator-max-microvolt =3D <3300000>; + }; + + pm8150_l3: l3 { + regulator-min-microvolt =3D <312000>; + regulator-max-microvolt =3D <1304000>; + }; + + pm8150_l4: l4 { + regulator-min-microvolt =3D <875000>; + regulator-max-microvolt =3D <975000>; + }; + + pm8150_l5: l5 { + regulator-min-microvolt =3D <788000>; + regulator-max-microvolt =3D <1050000>; + }; + + pm8150_l6: l6 { + regulator-min-microvolt =3D <875000>; + regulator-max-microvolt =3D <1000000>; + }; + + pm8150_l7: l7 { + regulator-min-microvolt =3D <1504000>; + regulator-max-microvolt =3D <2000000>; + }; + + pm8150_l8: l8 { + regulator-min-microvolt =3D <1150000>; + regulator-max-microvolt =3D <1304000>; + }; + + pm8150_l9: l9 { + regulator-min-microvolt =3D <875000>; + regulator-max-microvolt =3D <1000000>; + }; + + pm8150_l10: l10 { + regulator-min-microvolt =3D <2700000>; + regulator-max-microvolt =3D <3544000>; + }; + + pm8150_l11: l11 { + regulator-min-microvolt =3D <1100000>; + regulator-max-microvolt =3D <1304000>; + }; + + pm8150_l12: l12 { + regulator-min-microvolt =3D <1650000>; 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Three EVK boards are introduced: - shikra-cqm-evk.dts: pairs with CQ2390M SoM (retail, with modem) - shikra-cqs-evk.dts: pairs with CQ2390S SoM (retail, without modem) - shikra-iqs-evk.dts: pairs with IQ2390S SoM (industrial, without modem) Also add shikra-evk.dtsi, it represents the common carrier-board and daughter-card configuration shared across all Shikra EVK variants. Co-developed-by: Imran Shaik Signed-off-by: Imran Shaik Co-developed-by: Monish Chunara Signed-off-by: Monish Chunara Co-developed-by: Rakesh Kota Signed-off-by: Rakesh Kota Co-developed-by: Raviteja Laggyshetty Signed-off-by: Raviteja Laggyshetty Co-developed-by: Sneh Mankad Signed-off-by: Sneh Mankad Co-developed-by: Vishnu Santhosh Signed-off-by: Vishnu Santhosh Co-developed-by: Xueyao An Signed-off-by: Xueyao An Reviewed-by: Konrad Dybcio Signed-off-by: Komal Bajaj --- arch/arm64/boot/dts/qcom/Makefile | 3 +++ arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts | 40 +++++++++++++++++++++++++= ++++ arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts | 40 +++++++++++++++++++++++++= ++++ arch/arm64/boot/dts/qcom/shikra-evk.dtsi | 15 +++++++++++ arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts | 40 +++++++++++++++++++++++++= ++++ 5 files changed, 138 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index 6f33c4e2f09c..a9e9d829fb96 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -334,6 +334,9 @@ dtb-$(CONFIG_ARCH_QCOM) +=3D sdm850-huawei-matebook-e-2= 019.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sdm850-lenovo-yoga-c630.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sdm850-samsung-w737.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sdx75-idp.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D shikra-cqm-evk.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D shikra-cqs-evk.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D shikra-iqs-evk.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sm4250-oneplus-billie2.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sm4450-qrd.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D sm6115-fxtec-pro1x.dtb diff --git a/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts b/arch/arm64/boot/= dts/qcom/shikra-cqm-evk.dts new file mode 100644 index 000000000000..0a52ab9b7a4c --- /dev/null +++ b/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; + +#include "shikra-cqm-som.dtsi" +#include "shikra-evk.dtsi" + +/ { + model =3D "Qualcomm Technologies, Inc. Shikra CQM EVK"; + compatible =3D "qcom,shikra-cqm-evk", "qcom,shikra-cqm-som", "qcom,shikra= "; + chassis-type =3D "embedded"; + + aliases { + mmc0 =3D &sdhc_1; + serial0 =3D &uart0; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; +}; + +&sdhc_1 { + vmmc-supply =3D <&pm4125_l20>; + vqmmc-supply =3D <&pm4125_l14>; + + pinctrl-0 =3D <&sdc1_state_on>; + pinctrl-1 =3D <&sdc1_state_off>; + pinctrl-names =3D "default", "sleep"; + + non-removable; + supports-cqe; + no-sdio; + no-sd; + + status =3D "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts b/arch/arm64/boot/= dts/qcom/shikra-cqs-evk.dts new file mode 100644 index 000000000000..b3f19a64d7ae --- /dev/null +++ b/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; + +#include "shikra-cqm-som.dtsi" +#include "shikra-evk.dtsi" + +/ { + model =3D "Qualcomm Technologies, Inc. Shikra CQS EVK"; + compatible =3D "qcom,shikra-cqs-evk", "qcom,shikra-cqs-som", "qcom,shikra= "; + chassis-type =3D "embedded"; + + aliases { + mmc0 =3D &sdhc_1; + serial0 =3D &uart0; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; +}; + +&sdhc_1 { + vmmc-supply =3D <&pm4125_l20>; + vqmmc-supply =3D <&pm4125_l14>; + + pinctrl-0 =3D <&sdc1_state_on>; + pinctrl-1 =3D <&sdc1_state_off>; + pinctrl-names =3D "default", "sleep"; + + non-removable; + supports-cqe; + no-sdio; + no-sd; + + status =3D "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/shikra-evk.dtsi b/arch/arm64/boot/dts= /qcom/shikra-evk.dtsi new file mode 100644 index 000000000000..d0c48bad704c --- /dev/null +++ b/arch/arm64/boot/dts/qcom/shikra-evk.dtsi @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +&qupv3_0 { + firmware-name =3D "qcom/shikra/qupv3fw.elf"; + + status =3D "okay"; +}; + +&uart0 { + status =3D "okay"; +}; + diff --git a/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts b/arch/arm64/boot/= dts/qcom/shikra-iqs-evk.dts new file mode 100644 index 000000000000..3003a47bd759 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; + +#include "shikra-iqs-som.dtsi" +#include "shikra-evk.dtsi" + +/ { + model =3D "Qualcomm Technologies, Inc. Shikra IQS EVK"; + compatible =3D "qcom,shikra-iqs-evk", "qcom,shikra-iqs-som", "qcom,shikra= "; + chassis-type =3D "embedded"; + + aliases { + mmc0 =3D &sdhc_1; + serial0 =3D &uart0; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; +}; + +&sdhc_1 { + vmmc-supply =3D <&pm8150_l17>; + vqmmc-supply =3D <&pm8150_s4>; + + pinctrl-0 =3D <&sdc1_state_on>; + pinctrl-1 =3D <&sdc1_state_off>; + pinctrl-names =3D "default", "sleep"; + + non-removable; + supports-cqe; + no-sdio; + no-sd; + + status =3D "okay"; +}; --=20 2.34.1