From nobody Sat Jun 20 20:54:45 2026 Received: from mout-p-101.mailbox.org (mout-p-101.mailbox.org [80.241.56.151]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5728F3AB5AC; Fri, 12 Jun 2026 09:51:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=80.241.56.151 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781257912; cv=none; b=QH3hRxFo4nzWiTrvDIYmO62ImH0bepH+NDLIYKRH/S7tKtcaTnG14Irrq1KYve9kQphUj9x5Gw5r2y5jAAEqbtOd0yKiIM0WFzaXFeUZXZLsmg/DAIa6iwbdnY/J+bHXPOwnkst0rnA1bzyVdQEzVL5Z/xaKHiX5Cuq+6r3uQEk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781257912; c=relaxed/simple; bh=7fTCUHMih1u47whNSbXGHQdUnbbg9iDC23xen06vPas=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=nJOYa00SrBYDoLhVXot/rHnIKgyg/UdDpn5eOMVWTQMc53i/eRM2RqIO1nJ/zhKHeklqwc/piW4NomHW2DdAFpI5qTMxvwhA3oaq5B9Ul4W2H4vQgHugsn4V17nH7/WZEhw6QDt7CsEE5MJ6y0V6yFA3lmZ1cSgey7JzjPciusI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=mailbox.org; spf=pass smtp.mailfrom=mailbox.org; dkim=pass (2048-bit key) header.d=mailbox.org header.i=@mailbox.org header.b=gDPiFq9q; dkim=pass (2048-bit key) header.d=mailbox.org header.i=@mailbox.org header.b=oDCtrU0w; arc=none smtp.client-ip=80.241.56.151 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=mailbox.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mailbox.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=mailbox.org header.i=@mailbox.org header.b="gDPiFq9q"; dkim=pass (2048-bit key) header.d=mailbox.org header.i=@mailbox.org header.b="oDCtrU0w" Received: from smtp2.mailbox.org (smtp2.mailbox.org [IPv6:2001:67c:2050:b231:465::2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mout-p-101.mailbox.org (Postfix) with ESMTPS id 4gcFCk3YkVz9v1L; Fri, 12 Jun 2026 11:51:46 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mailbox.org; s=mail20150812; t=1781257906; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Vf7zdrO8nx9luF+ZUjyGUDc8D9p7LPr06wHVS5hvGZc=; b=gDPiFq9qrGwl6b3sF5ZyP0ojy+jnlIyl9wT+kPk1tTV8kAeUhfl6KFheJ8gf6prcTLJGeV v0YiWHL7ive7HkmhrDSoL+sMiPRfWK8ISoCdhqk4WATyx6NKqtmVxu3XQPdIydAbAtbP5V GqKCZqyj5tWIljtUZ+xTh0RdH+j+lf2rU5MYbFZRjVvupY1FmRAreCBQwbDvH91CeT4e6T ohsssOKQy0WCa/zUMOT7eWs9nVfo6H/9mXP2k1LmxXJcAVKqPuystCAFzv+NwCVG7xsOQ4 /6hs/RIQrXb5TL4WgOoLl6JTJhnBvaFoAu08ZmHyDBKrETPVLXcxANNtmve5HA== Authentication-Results: outgoing_mbo_mout; dkim=pass header.d=mailbox.org header.s=mail20150812 header.b=oDCtrU0w; spf=pass (outgoing_mbo_mout: domain of shuwei.wu@mailbox.org designates 2001:67c:2050:b231:465::2 as permitted sender) smtp.mailfrom=shuwei.wu@mailbox.org From: Shuwei Wu DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mailbox.org; s=mail20150812; t=1781257905; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Vf7zdrO8nx9luF+ZUjyGUDc8D9p7LPr06wHVS5hvGZc=; b=oDCtrU0wBd8mpv/KzQ9vbr7YLeFGObtphORsgLE8DrGC22DciIBaFGyzBZ7CtprMy6GiIp EDcckGqZBRyWHtYQAJ54pVhb+nwGDZqH3jkTE+234PNxI0r45f7TiIQryf0T6EwThJCUnJ FnGUUqbH5N/ira+td5PBtTOGfiKwBrLjcVkfr+QSMBdT0Zwwu3OGd1fKMgQ+b181SjZqmA 02PXQKdMYHdiuGvQU5Zcv5XHLH+TMEEkZb9U27U2LtkCBn8ymq9pddP76qh20l5uEglJut G/UYddwmg4AS6PKEXOxqoAafbCm15wyRkFy0CKM6unjXY1mqXffU+Q0OzLC/RQ== Date: Fri, 12 Jun 2026 17:51:01 +0800 Subject: [PATCH v3 1/2] cpufreq: spacemit: Add K1 cpufreq driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260612-shadow-deps-v3-1-2f3ba88611ff@mailbox.org> References: <20260612-shadow-deps-v3-0-2f3ba88611ff@mailbox.org> In-Reply-To: <20260612-shadow-deps-v3-0-2f3ba88611ff@mailbox.org> To: "Rafael J. Wysocki" , Viresh Kumar , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Yixun Lan , Yixun Lan Cc: linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, devicetree@vger.kernel.org, Shuwei Wu X-Developer-Signature: v=1; a=ed25519-sha256; t=1781257883; l=10241; i=shuwei.wu@mailbox.org; s=20251125; h=from:subject:message-id; bh=7fTCUHMih1u47whNSbXGHQdUnbbg9iDC23xen06vPas=; b=mtlmsI5jctAx4FbvxWXQtLMRo7mBCr6r5JvPHNy3Zimp3086kWaXyxUVr5MFm+ggmOTZDFbYi P4MakYc7yZOCMMBIPDk4Ro1NzwbtGlsNfdJcjS2zfB2qXxf8iToozNo X-Developer-Key: i=shuwei.wu@mailbox.org; a=ed25519; pk=qZs6i2UZnXkmjUrwO5HJxcfpCvgSNrR4dcU5cjtfTSk= X-MBO-RS-ID: 88c836974a72c62c2e2 X-MBO-RS-META: b1bbb5spo1badixip3e6nhrisumg5ie5 X-Rspamd-Queue-Id: 4gcFCk3YkVz9v1L K1 has two CPU cluster clocks but one shared CPU voltage rail. Use one cpufreq policy for all CPUs, let the OPP core handle the shared regulator and the cluster0 clock, and update the cluster1 clock explicitly. Block spacemit,k1 from cpufreq-dt probing when OPP v2 nodes are present, as K1 needs the dedicated driver for safe transitions. Signed-off-by: Shuwei Wu Tested-by: Gong Shuai # OrangePi-RV2 Tested-by: Vincent Legoll # OrangePi-RV2 --- Changes in v3: - Add a K1-specific cpufreq driver for the shared-rail, dual-clock topology - Add spacemit,k1 to the cpufreq-dt blocklist --- drivers/cpufreq/Kconfig | 4 + drivers/cpufreq/Kconfig.riscv | 15 ++ drivers/cpufreq/Makefile | 3 + drivers/cpufreq/cpufreq-dt-platdev.c | 2 + drivers/cpufreq/spacemit-k1-cpufreq.c | 251 ++++++++++++++++++++++++++++++= ++++ 5 files changed, 275 insertions(+) diff --git a/drivers/cpufreq/Kconfig b/drivers/cpufreq/Kconfig index 78702a08364f..19bbd1bd2f36 100644 --- a/drivers/cpufreq/Kconfig +++ b/drivers/cpufreq/Kconfig @@ -259,6 +259,10 @@ endif =20 source "drivers/cpufreq/Kconfig.arm" =20 +if RISCV +source "drivers/cpufreq/Kconfig.riscv" +endif + if PPC32 || PPC64 source "drivers/cpufreq/Kconfig.powerpc" endif diff --git a/drivers/cpufreq/Kconfig.riscv b/drivers/cpufreq/Kconfig.riscv new file mode 100644 index 000000000000..3d5b59fbcd4c --- /dev/null +++ b/drivers/cpufreq/Kconfig.riscv @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# RISC-V CPU Frequency scaling drivers +# + +config RISCV_SPACEMIT_K1_CPUFREQ + tristate "SpacemiT K1 CPUFreq driver" + depends on ARCH_SPACEMIT || COMPILE_TEST + depends on OF && COMMON_CLK + select PM_OPP + help + Enable CPU frequency scaling for SpacemiT K1 SoC. + K1 has two CPU cluster clocks and one shared CPU voltage rail. + The driver keeps all CPUs in one policy and updates both cluster + clocks with the shared OPP transition. diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile index 385c9fcc65c6..9680f420e824 100644 --- a/drivers/cpufreq/Makefile +++ b/drivers/cpufreq/Makefile @@ -89,6 +89,9 @@ obj-$(CONFIG_ARM_TEGRA194_CPUFREQ) +=3D tegra194-cpufreq.o obj-$(CONFIG_ARM_TI_CPUFREQ) +=3D ti-cpufreq.o obj-$(CONFIG_ARM_VEXPRESS_SPC_CPUFREQ) +=3D vexpress-spc-cpufreq.o =20 +##########################################################################= ######## +# RISC-V SoC drivers +obj-$(CONFIG_RISCV_SPACEMIT_K1_CPUFREQ) +=3D spacemit-k1-cpufreq.o =20 ##########################################################################= ######## # PowerPC platform drivers diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq= -dt-platdev.c index 25fd3b191b7e..69bbe739a627 100644 --- a/drivers/cpufreq/cpufreq-dt-platdev.c +++ b/drivers/cpufreq/cpufreq-dt-platdev.c @@ -185,6 +185,8 @@ static const struct of_device_id blocklist[] __initcons= t =3D { { .compatible =3D "qcom,sm8550", }, { .compatible =3D "qcom,sm8650", }, =20 + { .compatible =3D "spacemit,k1", }, + { .compatible =3D "st,stih407", }, { .compatible =3D "st,stih410", }, { .compatible =3D "st,stih418", }, diff --git a/drivers/cpufreq/spacemit-k1-cpufreq.c b/drivers/cpufreq/spacem= it-k1-cpufreq.c new file mode 100644 index 000000000000..631897eb8022 --- /dev/null +++ b/drivers/cpufreq/spacemit-k1-cpufreq.c @@ -0,0 +1,251 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * CPU frequency scaling driver for SpacemiT K1 SoC. + * + * Copyright (c) 2026 Shuwei Wu + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct k1_cpufreq_priv { + struct device *cpu_dev; + struct clk *cluster0_clk; + struct clk *cluster1_clk; + struct cpufreq_frequency_table *freq_table; + cpumask_var_t cpus; + int opp_token; +}; + +static struct platform_device *k1_cpufreq_pdev; + +static int k1_cpufreq_set_target(struct cpufreq_policy *policy, + unsigned int index) +{ + struct k1_cpufreq_priv *priv =3D policy->driver_data; + unsigned long old_freq =3D policy->cur * 1000UL; + unsigned long new_freq =3D policy->freq_table[index].frequency * 1000UL; + int ret; + + if (!old_freq) + old_freq =3D clk_get_rate(priv->cluster0_clk); + + if (new_freq > old_freq) { + ret =3D dev_pm_opp_set_rate(priv->cpu_dev, new_freq); + if (ret) + return ret; + + ret =3D clk_set_rate(priv->cluster1_clk, new_freq); + if (ret) + dev_pm_opp_set_rate(priv->cpu_dev, old_freq); + + return ret; + } + + ret =3D clk_set_rate(priv->cluster1_clk, new_freq); + if (ret) + return ret; + + ret =3D dev_pm_opp_set_rate(priv->cpu_dev, new_freq); + if (ret) + clk_set_rate(priv->cluster1_clk, old_freq); + + return ret; +} + +static int k1_cpufreq_init_policy(struct cpufreq_policy *policy) +{ + struct k1_cpufreq_priv *priv =3D cpufreq_get_driver_data(); + unsigned int transition_latency; + + cpumask_copy(policy->cpus, priv->cpus); + policy->clk =3D priv->cluster0_clk; + policy->freq_table =3D priv->freq_table; + policy->driver_data =3D priv; + policy->dvfs_possible_from_any_cpu =3D true; + + transition_latency =3D dev_pm_opp_get_max_transition_latency(priv->cpu_de= v); + if (!transition_latency) + transition_latency =3D CPUFREQ_DEFAULT_TRANSITION_LATENCY_NS; + policy->cpuinfo.transition_latency =3D transition_latency; + + return 0; +} + +static struct cpufreq_driver k1_cpufreq_driver =3D { + .flags =3D CPUFREQ_NEED_INITIAL_FREQ_CHECK | CPUFREQ_IS_COOLING_DEV, + .verify =3D cpufreq_generic_frequency_table_verify, + .target_index =3D k1_cpufreq_set_target, + .get =3D cpufreq_generic_get, + .init =3D k1_cpufreq_init_policy, + .register_em =3D cpufreq_register_em_with_opp, + .name =3D "k1-cpufreq", +}; + +static int k1_cpufreq_probe(struct platform_device *pdev) +{ + struct k1_cpufreq_priv *priv; + struct device *cpu4_dev; + static const char * const reg_names[] =3D { "cpu", NULL }; + int cpu, ret; + + priv =3D kzalloc_obj(*priv); + if (!priv) + return -ENOMEM; + + if (!zalloc_cpumask_var(&priv->cpus, GFP_KERNEL)) { + ret =3D -ENOMEM; + goto free_data; + } + + priv->cpu_dev =3D get_cpu_device(0); + cpu4_dev =3D get_cpu_device(4); + if (!priv->cpu_dev || !cpu4_dev) { + ret =3D -EPROBE_DEFER; + goto free_cpumask; + } + + for_each_present_cpu(cpu) + cpumask_set_cpu(cpu, priv->cpus); + + priv->cluster0_clk =3D clk_get(priv->cpu_dev, NULL); + if (IS_ERR(priv->cluster0_clk)) { + ret =3D PTR_ERR(priv->cluster0_clk); + dev_err_probe(priv->cpu_dev, ret, "failed to get cluster0 clock\n"); + goto free_cpumask; + } + + priv->cluster1_clk =3D clk_get(cpu4_dev, NULL); + if (IS_ERR(priv->cluster1_clk)) { + ret =3D PTR_ERR(priv->cluster1_clk); + dev_err_probe(cpu4_dev, ret, "failed to get cluster1 clock\n"); + goto put_clk_c0; + } + + priv->opp_token =3D dev_pm_opp_set_regulators(priv->cpu_dev, reg_names); + if (priv->opp_token < 0) { + ret =3D priv->opp_token; + dev_err_probe(priv->cpu_dev, ret, "failed to set regulators\n"); + goto put_clk_c1; + } + + ret =3D dev_pm_opp_of_cpumask_add_table(priv->cpus); + if (ret) { + dev_err_probe(priv->cpu_dev, ret, "failed to add OPP table\n"); + goto put_opp_regulators; + } + + ret =3D dev_pm_opp_get_opp_count(priv->cpu_dev); + if (ret <=3D 0) { + dev_err(priv->cpu_dev, "OPP table can't be empty\n"); + ret =3D -ENODEV; + goto remove_opp_table; + } + + ret =3D dev_pm_opp_init_cpufreq_table(priv->cpu_dev, &priv->freq_table); + if (ret) { + dev_err(priv->cpu_dev, "failed to init cpufreq table: %d\n", ret); + goto remove_opp_table; + } + + k1_cpufreq_driver.driver_data =3D priv; + ret =3D cpufreq_register_driver(&k1_cpufreq_driver); + if (ret) + goto free_freq_table; + + platform_set_drvdata(pdev, priv); + + return 0; + +free_freq_table: + k1_cpufreq_driver.driver_data =3D NULL; + dev_pm_opp_free_cpufreq_table(priv->cpu_dev, &priv->freq_table); +remove_opp_table: + dev_pm_opp_of_cpumask_remove_table(priv->cpus); +put_opp_regulators: + dev_pm_opp_put_regulators(priv->opp_token); +put_clk_c1: + clk_put(priv->cluster1_clk); +put_clk_c0: + clk_put(priv->cluster0_clk); +free_cpumask: + free_cpumask_var(priv->cpus); +free_data: + kfree(priv); + + return ret; +} + +static void k1_cpufreq_remove(struct platform_device *pdev) +{ + struct k1_cpufreq_priv *priv =3D platform_get_drvdata(pdev); + + if (!priv) + return; + + cpufreq_unregister_driver(&k1_cpufreq_driver); + k1_cpufreq_driver.driver_data =3D NULL; + dev_pm_opp_free_cpufreq_table(priv->cpu_dev, &priv->freq_table); + dev_pm_opp_of_cpumask_remove_table(priv->cpus); + dev_pm_opp_put_regulators(priv->opp_token); + clk_put(priv->cluster1_clk); + clk_put(priv->cluster0_clk); + free_cpumask_var(priv->cpus); + kfree(priv); +} + +static struct platform_driver k1_cpufreq_platdrv =3D { + .probe =3D k1_cpufreq_probe, + .remove =3D k1_cpufreq_remove, + .driver =3D { + .name =3D "spacemit-k1-cpufreq", + }, +}; + +static const struct of_device_id k1_cpufreq_match_list[] __initconst =3D { + { .compatible =3D "spacemit,k1" }, + { } +}; +MODULE_DEVICE_TABLE(of, k1_cpufreq_match_list); + +/* + * K1 has no dedicated cpufreq controller device. Register a logical platf= orm + * device so clock/regulator dependencies can defer probe. + */ +static int __init k1_cpufreq_init(void) +{ + int ret; + + if (!of_machine_device_match(k1_cpufreq_match_list)) + return -ENODEV; + + ret =3D platform_driver_register(&k1_cpufreq_platdrv); + if (ret) + return ret; + + k1_cpufreq_pdev =3D platform_device_register_simple("spacemit-k1-cpufreq"= , -1, NULL, 0); + ret =3D PTR_ERR_OR_ZERO(k1_cpufreq_pdev); + if (ret) + platform_driver_unregister(&k1_cpufreq_platdrv); + + return ret; +} +module_init(k1_cpufreq_init); + +static void __exit k1_cpufreq_exit(void) +{ + platform_device_unregister(k1_cpufreq_pdev); + platform_driver_unregister(&k1_cpufreq_platdrv); +} +module_exit(k1_cpufreq_exit); + +MODULE_DESCRIPTION("SpacemiT K1 CPUFreq driver"); +MODULE_AUTHOR("Shuwei Wu "); +MODULE_LICENSE("GPL"); --=20 2.53.0 From nobody Sat Jun 20 20:54:45 2026 Received: from mout-p-101.mailbox.org (mout-p-101.mailbox.org [80.241.56.151]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6467F3D649C; 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t=1781257914; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Zfe/dJqFfrMrhmEzQiIVU+r4LtnZx/69uLFhmgVm3jQ=; b=jrcr2scJwWan4crijrU3QtEOUNAKBSj15cGswWgFkGhHn2qsgEgvDoTKVw/vKuW4T4DFIb O70Xi8WJiiaXOnKShEueNLU5rydIcYGz2saxns0R/9mGVU311OZPL23XWLlBgspkShn5AF Y9Krr6nGqPCREasabZ7E8ZTXVwZ3JFi84Gyx4FaRLbEqUCbZqrnNc5aF6585PIajKzD4Y9 /uALLUL/s+/QQX1+VFsrmNgrtBfO0NUAPJq1fcRLNPF2RrMKHfREk89hQmqp6WeayfWmVf S477EQuFsIkJTMzOP2cz9z9XE8L+DS0ULaJQJj1omNoxwsVGQF7a00ZdaK3+cA== Date: Fri, 12 Jun 2026 17:51:02 +0800 Subject: [PATCH v3 2/2] riscv: dts: spacemit: Add cpu scaling for K1 SoC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260612-shadow-deps-v3-2-2f3ba88611ff@mailbox.org> References: <20260612-shadow-deps-v3-0-2f3ba88611ff@mailbox.org> In-Reply-To: <20260612-shadow-deps-v3-0-2f3ba88611ff@mailbox.org> To: "Rafael J. Wysocki" , Viresh Kumar , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Yixun Lan , Yixun Lan Cc: linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, devicetree@vger.kernel.org, Shuwei Wu X-Developer-Signature: v=1; a=ed25519-sha256; t=1781257883; l=7264; i=shuwei.wu@mailbox.org; s=20251125; h=from:subject:message-id; bh=kMk70jSxtb3MD3cA34JzN4CJWO0HzPs0M08gJr1gSr0=; b=R8lUg0Ck/5RNYU+5FwX9zIpHYKFMuRl28uMk31qF020V2HHOw5tMB/6X3/CDqkdrm7adyeLLH Lf4KOaLz98wBBs1pFM6Q8jVQFaNBidqxNl7UUcVvlrz6VfHdM42cQZP X-Developer-Key: i=shuwei.wu@mailbox.org; a=ed25519; pk=qZs6i2UZnXkmjUrwO5HJxcfpCvgSNrR4dcU5cjtfTSk= X-MBO-RS-META: pkdxdm4u4y1dubcmy3i5fjwcjecejtby X-MBO-RS-ID: 372acceaeecb71d3147 X-Rspamd-Queue-Id: 4gcFCw3RThz9tpN Use one shared CPU OPP table for all CPUs and add CPU clock properties for the two CPU clock clusters. Enable CPU DVFS on Banana Pi BPI-F3 by including the OPP table and wiring the CPU nodes to the CPU regulator supply. Signed-off-by: Shuwei Wu Tested-by: Gong Shuai # OrangePi-RV2 Tested-by: Vincent Legoll # OrangePi-RV2 --- Changes in v3: - Use one shared CPU OPP table for all CPUs Changes in v2: - Add k1-opp.dtsi with OPP tables for both CPU clusters - Assign CPU supplies and include OPP table for Banana Pi BPI-F3 --- arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 35 ++++++++++++- arch/riscv/boot/dts/spacemit/k1-opp.dtsi | 70 +++++++++++++++++++++= ++++ arch/riscv/boot/dts/spacemit/k1.dtsi | 8 +++ 3 files changed, 112 insertions(+), 1 deletion(-) diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/b= oot/dts/spacemit/k1-bananapi-f3.dts index 444c3b1e6f44..81ab5f70176b 100644 --- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts @@ -5,6 +5,7 @@ =20 #include "k1.dtsi" #include "k1-pinctrl.dtsi" +#include "k1-opp.dtsi" =20 / { model =3D "Banana Pi BPI-F3"; @@ -86,6 +87,38 @@ &combo_phy { status =3D "okay"; }; =20 +&cpu_0 { + cpu-supply =3D <&buck1_0v9>; +}; + +&cpu_1 { + cpu-supply =3D <&buck1_0v9>; +}; + +&cpu_2 { + cpu-supply =3D <&buck1_0v9>; +}; + +&cpu_3 { + cpu-supply =3D <&buck1_0v9>; +}; + +&cpu_4 { + cpu-supply =3D <&buck1_0v9>; +}; + +&cpu_5 { + cpu-supply =3D <&buck1_0v9>; +}; + +&cpu_6 { + cpu-supply =3D <&buck1_0v9>; +}; + +&cpu_7 { + cpu-supply =3D <&buck1_0v9>; +}; + &emmc { bus-width =3D <8>; mmc-hs400-1_8v; @@ -201,7 +234,7 @@ pmic@41 { dldoin2-supply =3D <&buck5>; =20 regulators { - buck1 { + buck1_0v9: buck1 { regulator-min-microvolt =3D <500000>; regulator-max-microvolt =3D <3450000>; regulator-ramp-delay =3D <5000>; diff --git a/arch/riscv/boot/dts/spacemit/k1-opp.dtsi b/arch/riscv/boot/dts= /spacemit/k1-opp.dtsi new file mode 100644 index 000000000000..3627812e1344 --- /dev/null +++ b/arch/riscv/boot/dts/spacemit/k1-opp.dtsi @@ -0,0 +1,70 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/ { + cpu_opp_table: opp-table-cpu { + compatible =3D "operating-points-v2"; + opp-shared; + + opp-614400000 { + opp-hz =3D /bits/ 64 <614400000>; + opp-microvolt =3D <950000>; + clock-latency-ns =3D <200000>; + }; + + opp-819000000 { + opp-hz =3D /bits/ 64 <819000000>; + opp-microvolt =3D <950000>; + clock-latency-ns =3D <200000>; + }; + + opp-1000000000 { + opp-hz =3D /bits/ 64 <1000000000>; + opp-microvolt =3D <950000>; + clock-latency-ns =3D <200000>; + }; + + opp-1228800000 { + opp-hz =3D /bits/ 64 <1228800000>; + opp-microvolt =3D <950000>; + clock-latency-ns =3D <200000>; + }; + + opp-1600000000 { + opp-hz =3D /bits/ 64 <1600000000>; + opp-microvolt =3D <1050000>; + clock-latency-ns =3D <200000>; + }; + }; +}; + +&cpu_0 { + operating-points-v2 =3D <&cpu_opp_table>; +}; + +&cpu_1 { + operating-points-v2 =3D <&cpu_opp_table>; +}; + +&cpu_2 { + operating-points-v2 =3D <&cpu_opp_table>; +}; + +&cpu_3 { + operating-points-v2 =3D <&cpu_opp_table>; +}; + +&cpu_4 { + operating-points-v2 =3D <&cpu_opp_table>; +}; + +&cpu_5 { + operating-points-v2 =3D <&cpu_opp_table>; +}; + +&cpu_6 { + operating-points-v2 =3D <&cpu_opp_table>; +}; + +&cpu_7 { + operating-points-v2 =3D <&cpu_opp_table>; +}; diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spa= cemit/k1.dtsi index 529ec68e9c23..bdd109b81730 100644 --- a/arch/riscv/boot/dts/spacemit/k1.dtsi +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi @@ -54,6 +54,7 @@ cpu_0: cpu@0 { compatible =3D "spacemit,x60", "riscv"; device_type =3D "cpu"; reg =3D <0>; + clocks =3D <&syscon_apmu CLK_CPU_C0_CORE>; riscv,isa =3D "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zi= fencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_sv= inval_svnapot_svpbmt"; riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "b", "v", "zicbo= m", @@ -84,6 +85,7 @@ cpu_1: cpu@1 { compatible =3D "spacemit,x60", "riscv"; device_type =3D "cpu"; reg =3D <1>; + clocks =3D <&syscon_apmu CLK_CPU_C0_CORE>; riscv,isa =3D "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zi= fencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_sv= inval_svnapot_svpbmt"; riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "b", "v", "zicbo= m", @@ -114,6 +116,7 @@ cpu_2: cpu@2 { compatible =3D "spacemit,x60", "riscv"; device_type =3D "cpu"; reg =3D <2>; + clocks =3D <&syscon_apmu CLK_CPU_C0_CORE>; riscv,isa =3D "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zi= fencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_sv= inval_svnapot_svpbmt"; riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "b", "v", "zicbo= m", @@ -144,6 +147,7 @@ cpu_3: cpu@3 { compatible =3D "spacemit,x60", "riscv"; device_type =3D "cpu"; reg =3D <3>; + clocks =3D <&syscon_apmu CLK_CPU_C0_CORE>; riscv,isa =3D "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zi= fencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_sv= inval_svnapot_svpbmt"; riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "b", "v", "zicbo= m", @@ -174,6 +178,7 @@ cpu_4: cpu@4 { compatible =3D "spacemit,x60", "riscv"; device_type =3D "cpu"; reg =3D <4>; + clocks =3D <&syscon_apmu CLK_CPU_C1_CORE>; riscv,isa =3D "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zi= fencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_sv= inval_svnapot_svpbmt"; riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "b", "v", "zicbo= m", @@ -204,6 +209,7 @@ cpu_5: cpu@5 { compatible =3D "spacemit,x60", "riscv"; device_type =3D "cpu"; reg =3D <5>; + clocks =3D <&syscon_apmu CLK_CPU_C1_CORE>; riscv,isa =3D "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zi= fencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_sv= inval_svnapot_svpbmt"; riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "b", "v", "zicbo= m", @@ -234,6 +240,7 @@ cpu_6: cpu@6 { compatible =3D "spacemit,x60", "riscv"; device_type =3D "cpu"; reg =3D <6>; + clocks =3D <&syscon_apmu CLK_CPU_C1_CORE>; riscv,isa =3D "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicond_zicsr_zi= fencei_zihintpause_zihpm_zfh_zba_zbb_zbc_zbs_zkt_zvfh_zvkt_sscofpmf_sstc_sv= inval_svnapot_svpbmt"; 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[89.182.129.114]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-4606f263923sm24756097f8f.2.2026.06.14.05.28.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Jun 2026 05:28:14 -0700 (PDT) From: Andre Heider To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Yixun Lan Cc: devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH] riscv: dts: spacemit: k1-musepi-pro: add cpu scaling Date: Sun, 14 Jun 2026 14:28:11 +0200 Message-ID: <20260614122812.2287506-1-a.heider@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260612-shadow-deps-v3-0-2f3ba88611ff@mailbox.org> References: <20260612-shadow-deps-v3-0-2f3ba88611ff@mailbox.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Enable CPU DVFS by including the OPP table and wiring the CPU nodes to the CPU regulator supply. Signed-off-by: Andre Heider Tested-by: Gong Shuai # OrangePi-RV2 Tested-by: Vincent Legoll # OrangePi-RV2 --- .../riscv/boot/dts/spacemit/k1-musepi-pro.dts | 35 ++++++++++++++++++- 1 file changed, 34 insertions(+), 1 deletion(-) diff --git a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts b/arch/riscv/bo= ot/dts/spacemit/k1-musepi-pro.dts index 0d809e4ad3b1..1b425011f123 100644 --- a/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts +++ b/arch/riscv/boot/dts/spacemit/k1-musepi-pro.dts @@ -9,6 +9,7 @@ =20 #include "k1.dtsi" #include "k1-pinctrl.dtsi" +#include "k1-opp.dtsi" =20 / { model =3D "SpacemiT MusePi Pro"; @@ -99,6 +100,38 @@ &combo_phy { status =3D "okay"; }; =20 +&cpu_0 { + cpu-supply =3D <&buck1_0v9>; +}; + +&cpu_1 { + cpu-supply =3D <&buck1_0v9>; +}; + +&cpu_2 { + cpu-supply =3D <&buck1_0v9>; +}; + +&cpu_3 { + cpu-supply =3D <&buck1_0v9>; +}; + +&cpu_4 { + cpu-supply =3D <&buck1_0v9>; +}; + +&cpu_5 { + cpu-supply =3D <&buck1_0v9>; +}; + +&cpu_6 { + cpu-supply =3D <&buck1_0v9>; +}; + +&cpu_7 { + cpu-supply =3D <&buck1_0v9>; +}; + ð0 { phy-handle =3D <&rgmii0>; phy-mode =3D "rgmii-id"; @@ -178,7 +211,7 @@ pmic@41 { dldoin2-supply =3D <&buck5>; =20 regulators { - buck1 { + buck1_0v9: buck1 { regulator-min-microvolt =3D <500000>; regulator-max-microvolt =3D <3450000>; regulator-ramp-delay =3D <5000>; --=20 2.53.0