From nobody Sat Jun 13 00:38:18 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 20D72389443 for ; Thu, 11 Jun 2026 23:45:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781221552; cv=none; b=ZAQ8P3vwaLOe/csGcOIzhr9/NMICjXicg+9wVivFjranipvNZVpK28/CD/xJrANO70DGRfwKxNr+RuVWAS4DbteGu0bXAj+IZev2kU2eJBeC4vHkQfOYl10Qsm8x3AKIdZAWf3JGNMfIEEC/nCDT+heKJvOq8osQrUOydhhubSc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781221552; c=relaxed/simple; bh=FLTlKYBwbpVpaUOCu6nlw+klwM1qmLmhO3wOq+k94VU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Hw8BWV1ZQjGpdq8umN6b83jgJzWqUo+/S0dJNWMaZZWqPaLEYXnqHA9if3PysG1deuE3W6RLa/MxgjYpqDwxkl6iNNVFylrfhgOn0X+63lov6Vuiv1d4Ya33lPgnmCFQ+azIWUDh9bYMryQ+kYcyoVtLitkNkALgoIpXq4gEy8Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=C4dijLUe; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="C4dijLUe" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1781221544; bh=FLTlKYBwbpVpaUOCu6nlw+klwM1qmLmhO3wOq+k94VU=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=C4dijLUezV6a7U7+JuezvIAAjPmeDtPDexXNIOPazkG7eGfAKgOSmUUtrWNLOLor8 LFhVVo0gTSpBIfq3WwMByx4+HhOf8Ckxgaas60TpDmxaD5HhovPGN6QS/sN4+D2UD2 +kThvY1B23D2eHgy+QkcIJI2sda6mOlz3J1elyGr9Sv8OCx5lJ3jvFWxqfVPvAbBAY wkF4JZUqd9CBo2fm7EBagEAj3rkmPgaSsNPi+lNEnNLXpSb0lfLLnwvdh8VlyiMIYz 8QsAIzwZHloaa12BBzCUf4G3zBmr9QqohDMcQg+anM3aiMIbI/HMb/yZzl3hy7B92P 5eURoHoiSl/Gg== Received: from localhost (unknown [100.64.0.241]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (prime256v1) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by bali.collaboradmins.com (Postfix) with ESMTPSA id 0322C17E091C; Fri, 12 Jun 2026 01:45:43 +0200 (CEST) From: Cristian Ciocaltea Date: Fri, 12 Jun 2026 02:45:20 +0300 Subject: [PATCH v4 1/8] phy: rockchip: samsung-hdptx: Fix rate recalculation for high bpc Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260612-hdptx-clk-fixes-v4-1-ce5e1d456cda@collabora.com> References: <20260612-hdptx-clk-fixes-v4-0-ce5e1d456cda@collabora.com> In-Reply-To: <20260612-hdptx-clk-fixes-v4-0-ce5e1d456cda@collabora.com> To: Vinod Koul , Neil Armstrong , Heiko Stuebner , Algea Cao , Dmitry Baryshkov Cc: kernel@collabora.com, linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, =?utf-8?q?Thomas_Niederpr=C3=BCm?= , Simon Wright X-Mailer: b4 0.15.2 The PHY PLL can be programmed by an external component, e.g. the bootloader, just before the recalc_rate() callback is invoked during devm_clk_hw_register() in the probe path. Therefore rk_hdptx_phy_clk_recalc_rate() finds the PLL enabled and attempts to compute the clock rate, while making use of the bpc value from the HDMI PHY configuration, which always defaults to 8 because phy_configure() was not run at that point. As a consequence, the (re)calculated rate is incorrect when the actual bpc was higher than 8. Do not rely on any of the hdmi_cfg members when computing the clock rate and, instead, read the required input data (i.e. bpc), directly from the hardware registers. Fixes: 3481fc04d969 ("phy: rockchip: samsung-hdptx: Compute clk rate from P= LL config") Tested-by: Thomas Niederpr=C3=BCm Tested-by: Simon Wright Signed-off-by: Cristian Ciocaltea --- drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 13 ++++--------- 1 file changed, 4 insertions(+), 9 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/ph= y/rockchip/phy-rockchip-samsung-hdptx.c index 2d973bc37f07..710603afff86 100644 --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c @@ -2168,7 +2168,7 @@ static u64 rk_hdptx_phy_clk_calc_rate_from_pll_cfg(st= ruct rk_hdptx_phy *hdptx) struct lcpll_config lcpll_hw; struct ropll_config ropll_hw; u64 fout, sdm; - u32 mode, val; + u32 mode, bpc, val; int ret, i; =20 ret =3D regmap_read(hdptx->regmap, CMN_REG(0008), &mode); @@ -2266,6 +2266,7 @@ static u64 rk_hdptx_phy_clk_calc_rate_from_pll_cfg(st= ruct rk_hdptx_phy *hdptx) if (ret) return 0; ropll_hw.pms_sdiv =3D ((val & PLL_PCG_POSTDIV_SEL_MASK) >> 4) + 1; + bpc =3D (FIELD_GET(PLL_PCG_CLK_SEL_MASK, val) << 1) + 8; =20 fout =3D PLL_REF_CLK * ropll_hw.pms_mdiv; if (ropll_hw.sdm_en) { @@ -2280,7 +2281,7 @@ static u64 rk_hdptx_phy_clk_calc_rate_from_pll_cfg(st= ruct rk_hdptx_phy *hdptx) fout =3D fout + sdm; } =20 - return div_u64(fout * 2, ropll_hw.pms_sdiv * 10); + return DIV_ROUND_CLOSEST_ULL(fout * 2 * 8, ropll_hw.pms_sdiv * 10 * bpc); } =20 static unsigned long rk_hdptx_phy_clk_recalc_rate(struct clk_hw *hw, @@ -2288,19 +2289,13 @@ static unsigned long rk_hdptx_phy_clk_recalc_rate(s= truct clk_hw *hw, { struct rk_hdptx_phy *hdptx =3D to_rk_hdptx_phy(hw); u32 status; - u64 rate; int ret; =20 ret =3D regmap_read(hdptx->grf, GRF_HDPTX_CON0, &status); if (ret || !(status & HDPTX_I_PLL_EN)) return 0; =20 - rate =3D rk_hdptx_phy_clk_calc_rate_from_pll_cfg(hdptx); - - if (hdptx->hdmi_cfg.mode =3D=3D PHY_HDMI_MODE_FRL) - return rate; - - return DIV_ROUND_CLOSEST_ULL(rate * 8, hdptx->hdmi_cfg.bpc); + return rk_hdptx_phy_clk_calc_rate_from_pll_cfg(hdptx); } =20 static int rk_hdptx_phy_clk_determine_rate(struct clk_hw *hw, --=20 2.54.0 From nobody Sat Jun 13 00:38:18 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B0AAB381AF1 for ; Thu, 11 Jun 2026 23:45:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781221551; cv=none; b=cfGsJrGPw9I/tFICL/8uX2eZqU5RLlbZBQVdAtmUlInxRYKVaajcvgvKTKBue73qqEY8nXb9lmHQJwH5S6OVp2DPMX952QCKUowevPM2ID+2qnrDsoF1MHyH/ikZMi/BhUSMbIM01grU3PgZiOty3e3r0oJaUJ3Z5MuXY7QFT6g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781221551; c=relaxed/simple; bh=O76zc6hZ3sZD7icHCi6nwGcYj5BUYZJBnFM55uK6B8A=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; 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Fri, 12 Jun 2026 01:45:44 +0200 (CEST) From: Cristian Ciocaltea Date: Fri, 12 Jun 2026 02:45:21 +0300 Subject: [PATCH v4 2/8] phy: rockchip: samsung-hdptx: Prevent divide-by-zero when computing clk rate Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260612-hdptx-clk-fixes-v4-2-ce5e1d456cda@collabora.com> References: <20260612-hdptx-clk-fixes-v4-0-ce5e1d456cda@collabora.com> In-Reply-To: <20260612-hdptx-clk-fixes-v4-0-ce5e1d456cda@collabora.com> To: Vinod Koul , Neil Armstrong , Heiko Stuebner , Algea Cao , Dmitry Baryshkov Cc: kernel@collabora.com, linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Sashiko X-Mailer: b4 0.15.2 Calculating 'sdm' fraction in rk_hdptx_phy_clk_calc_rate_from_pll_cfg() could trigger a divide-by-zero, as it uses div_u64() with a denominator read directly from hardware: the values ropll_hw.sdm_deno, ropll_hw.sdc_deno, ropll_hw.sdc_n, and ropll_hw.sdc_num are populated from PLL registers which, in theory, could be left by the bootloader uninitialized/misconfigured. Provide the necessary sanitization to avoid trusting the hardware state. Reported-by: Sashiko Closes: https://sashiko.dev/#/patchset/20260611-hdptx-clk-fixes-v3-0-67b1b0= c00e16@collabora.com?part=3D1 Fixes: 3481fc04d969 ("phy: rockchip: samsung-hdptx: Compute clk rate from P= LL config") Signed-off-by: Cristian Ciocaltea --- drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/ph= y/rockchip/phy-rockchip-samsung-hdptx.c index 710603afff86..8c044381b83a 100644 --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c @@ -2270,10 +2270,15 @@ static u64 rk_hdptx_phy_clk_calc_rate_from_pll_cfg(= struct rk_hdptx_phy *hdptx) =20 fout =3D PLL_REF_CLK * ropll_hw.pms_mdiv; if (ropll_hw.sdm_en) { + val =3D 16U * ropll_hw.sdm_deno * + (ropll_hw.sdc_deno * ropll_hw.sdc_n - ropll_hw.sdc_num); + if (!val) { + dev_dbg(hdptx->dev, "%s invalid ROPLL hw state\n", __func__); + return 0; + } + sdm =3D div_u64(PLL_REF_CLK * ropll_hw.sdc_deno * - ropll_hw.pms_mdiv * ropll_hw.sdm_num, - 16 * ropll_hw.sdm_deno * - (ropll_hw.sdc_deno * ropll_hw.sdc_n - ropll_hw.sdc_num)); + ropll_hw.pms_mdiv * ropll_hw.sdm_num, val); =20 if (ropll_hw.sdm_num_sign) fout =3D fout - sdm; --=20 2.54.0 From nobody Sat Jun 13 00:38:18 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6C7443D9DD3 for ; Thu, 11 Jun 2026 23:45:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781221552; cv=none; b=Nsdw0//7qu9lb0EGVSUqt7dx0bZgVgWWxKmMDTwOIsw4WNdteyJohL0Tcq20I7jac6cWQDtYALdFqKnfz84KuoQEUqtO0Uig47ydSWt/ZyAGsVeYD/kPpwqYwpaGl1wQavS+W8fwpjmhwYzv5PMHXcZUGaun1Fq7sfXDYQe1N/4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781221552; c=relaxed/simple; bh=mMmN5c98AYlSbEtpnRmRYuYBWUBFkWC7EXBgNfEYdGA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; 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Fri, 12 Jun 2026 01:45:45 +0200 (CEST) From: Cristian Ciocaltea Date: Fri, 12 Jun 2026 02:45:22 +0300 Subject: [PATCH v4 3/8] phy: rockchip: samsung-hdptx: Fix rate recalculation for 3.2GHz FRL Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260612-hdptx-clk-fixes-v4-3-ce5e1d456cda@collabora.com> References: <20260612-hdptx-clk-fixes-v4-0-ce5e1d456cda@collabora.com> In-Reply-To: <20260612-hdptx-clk-fixes-v4-0-ce5e1d456cda@collabora.com> To: Vinod Koul , Neil Armstrong , Heiko Stuebner , Algea Cao , Dmitry Baryshkov Cc: kernel@collabora.com, linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Sashiko X-Mailer: b4 0.15.2 rk_hdptx_phy_clk_calc_rate_from_pll_cfg() is currently unable to handle cascade mode for the 3.2GHz FRL operating mode, as it relies solely on LCPLL_LCVCO_MODE_EN_MASK to determinate the rate from the rk_hdptx_frl_lcpll_cfg array. Since there is no entry for this particular rate, the function returns 0. This is the only rate which requires LC_REF_CLK_SEL to be set in GRF_HDPTX_CON0, hence extend the FRL matching accordingly. Reported-by: Sashiko Closes: https://sashiko.dev/#/patchset/20260611-hdptx-clk-fixes-v3-0-67b1b0= c00e16@collabora.com?part=3D1 Fixes: de5dba833118 ("phy: rockchip: samsung-hdptx: Add HDMI 2.1 FRL suppor= t") Signed-off-by: Cristian Ciocaltea --- drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 33 ++++++++++++++++---= ---- 1 file changed, 24 insertions(+), 9 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/ph= y/rockchip/phy-rockchip-samsung-hdptx.c index 8c044381b83a..b210c1a88b25 100644 --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c @@ -2206,16 +2206,31 @@ static u64 rk_hdptx_phy_clk_calc_rate_from_pll_cfg(= struct rk_hdptx_phy *hdptx) return 0; lcpll_hw.sdc_n =3D (val & LCPLL_SDC_N_MASK) >> 1; =20 - for (i =3D 0; i < ARRAY_SIZE(rk_hdptx_frl_lcpll_cfg); i++) { - const struct lcpll_config *cfg =3D &rk_hdptx_frl_lcpll_cfg[i]; + ret =3D regmap_read(hdptx->grf, GRF_HDPTX_CON0, &val); + if (ret) + return 0; =20 - if (cfg->pms_mdiv =3D=3D lcpll_hw.pms_mdiv && - cfg->pms_sdiv =3D=3D lcpll_hw.pms_sdiv && - cfg->sdm_num_sign =3D=3D lcpll_hw.sdm_num_sign && - cfg->sdm_num =3D=3D lcpll_hw.sdm_num && - cfg->sdm_deno =3D=3D lcpll_hw.sdm_deno && - cfg->sdc_n =3D=3D lcpll_hw.sdc_n) - return cfg->rate; + if (val & LC_REF_CLK_SEL) { + if (lcpll_hw.pms_mdiv =3D=3D 0x6b && + lcpll_hw.sdm_num_sign =3D=3D 0x01 && + lcpll_hw.sdm_num =3D=3D 0x02 && + lcpll_hw.sdm_deno =3D=3D 0x09 && + lcpll_hw.sdc_n =3D=3D FIELD_GET(LCPLL_SDC_N_MASK, 0x02)) + return FRL_8G4L_RATE; + } else { + const struct lcpll_config *cfg; + + for (i =3D 0; i < ARRAY_SIZE(rk_hdptx_frl_lcpll_cfg); i++) { + cfg =3D &rk_hdptx_frl_lcpll_cfg[i]; + + if (cfg->pms_mdiv =3D=3D lcpll_hw.pms_mdiv && + cfg->pms_sdiv =3D=3D lcpll_hw.pms_sdiv && + cfg->sdm_num_sign =3D=3D lcpll_hw.sdm_num_sign && + cfg->sdm_num =3D=3D lcpll_hw.sdm_num && + cfg->sdm_deno =3D=3D lcpll_hw.sdm_deno && + cfg->sdc_n =3D=3D lcpll_hw.sdc_n) + return cfg->rate; + } } =20 dev_dbg(hdptx->dev, "%s no FRL match found\n", __func__); --=20 2.54.0 From nobody Sat Jun 13 00:38:18 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2CA9D3DB32E for ; Thu, 11 Jun 2026 23:45:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781221553; cv=none; b=XYvpBKktL5Szlaj1MAadhdFqDKKzHS63Q8qJLGjCwm6Se4U6IdTNZ7roBa8q5zIXqLbmVQS4GZvypXhAQ8tK6K/9L/Bg2uHnNMJMM+YXREpkA3q3Csb1yX1IMGFI4576XTbVJu/xZsOlIxYG8vxP41NVemfxNLutQ/nU3AOyWNo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781221553; c=relaxed/simple; bh=2kQesQNu3MuWE/xRuzdp6xMGi9TTCCje9qYNe5bbNus=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; 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Fri, 12 Jun 2026 01:45:46 +0200 (CEST) From: Cristian Ciocaltea Date: Fri, 12 Jun 2026 02:45:23 +0300 Subject: [PATCH v4 4/8] phy: rockchip: samsung-hdptx: Handle uncommitted PHY config changes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260612-hdptx-clk-fixes-v4-4-ce5e1d456cda@collabora.com> References: <20260612-hdptx-clk-fixes-v4-0-ce5e1d456cda@collabora.com> In-Reply-To: <20260612-hdptx-clk-fixes-v4-0-ce5e1d456cda@collabora.com> To: Vinod Koul , Neil Armstrong , Heiko Stuebner , Algea Cao , Dmitry Baryshkov Cc: kernel@collabora.com, linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, =?utf-8?q?Thomas_Niederpr=C3=BCm?= , Simon Wright X-Mailer: b4 0.15.2 Any changes to the PHY link rate and/or color depth done via the HDMI PHY configuration API are not immediately programmed into the hardware, but are delayed until the PHY usage count gets incremented from 0 to 1, that is when it is powered on or when the PLL clock exposed through the CCF API is prepared, whichever comes first. Since the clock might remain in prepared state after subsequent PHY config changes, the programming can also be triggered via clk_ops.set_rate(). However, from the clock consumer perspective (i.e. VOP2 display controller), the (pixel) clock rate doesn't vary with bpc, as that is handled internally by the PHY and reflected in the TDMS character rate only. As a consequence, changing the bpc while preserving the modeline may lead to out-of-sync issues between CCF and HDMI PHY config state, because the .set_rate() callback is not invoked when clock rate remains constant. This may also happen when the PHY PLL has been pre-programmed by an external entity, e.g. the bootloader, which is actually a regression introduced by the recent FRL patches. Introduce a pll_config_dirty flag to keep track of uncommitted PHY config changes and use it in clk_ops.determine_rate() to invalidate the current clock rate (as known by CCF) and, consequently, ensure those changes are programmed into hardware via clk_ops.set_rate(). Moreover, proceed with a similar fix in phy_ops.power_on() callback, to handle the scenario where the CCF API is not used due to operating in FRL mode, while the clock is still in a prepared state and thus preventing rk_hdptx_phy_consumer_get() to apply the updated PHY configuration. Fixes: de5dba833118 ("phy: rockchip: samsung-hdptx: Add HDMI 2.1 FRL suppor= t") Fixes: 9d0ec51d7c22 ("phy: rockchip: samsung-hdptx: Add high color depth ma= nagement") Tested-by: Thomas Niederpr=C3=BCm Tested-by: Simon Wright Signed-off-by: Cristian Ciocaltea --- drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 84 +++++++++++++------= ---- 1 file changed, 48 insertions(+), 36 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/ph= y/rockchip/phy-rockchip-samsung-hdptx.c index b210c1a88b25..25bd821cd039 100644 --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c @@ -413,6 +413,7 @@ struct rk_hdptx_phy { =20 /* clk provider */ struct clk_hw hw; + bool pll_config_dirty; bool restrict_rate_change; =20 atomic_t usage_count; @@ -1260,13 +1261,19 @@ static int rk_hdptx_tmds_ropll_cmn_config(struct rk= _hdptx_phy *hdptx) =20 static int rk_hdptx_pll_cmn_config(struct rk_hdptx_phy *hdptx) { + int ret; + if (hdptx->hdmi_cfg.rate <=3D HDMI20_MAX_RATE) - return rk_hdptx_tmds_ropll_cmn_config(hdptx); + ret =3D rk_hdptx_tmds_ropll_cmn_config(hdptx); + else if (hdptx->hdmi_cfg.rate =3D=3D FRL_8G4L_RATE) + ret =3D rk_hdptx_frl_lcpll_ropll_cmn_config(hdptx); + else + ret =3D rk_hdptx_frl_lcpll_cmn_config(hdptx); =20 - if (hdptx->hdmi_cfg.rate =3D=3D FRL_8G4L_RATE) - return rk_hdptx_frl_lcpll_ropll_cmn_config(hdptx); + if (!ret) + hdptx->pll_config_dirty =3D false; =20 - return rk_hdptx_frl_lcpll_cmn_config(hdptx); + return ret; } =20 static int rk_hdptx_frl_lcpll_mode_config(struct rk_hdptx_phy *hdptx) @@ -1347,25 +1354,22 @@ static int rk_hdptx_phy_consumer_get(struct rk_hdpt= x_phy *hdptx) return 0; =20 ret =3D regmap_read(hdptx->grf, GRF_HDPTX_STATUS, &status); - if (ret) - goto dec_usage; - - if (status & HDPTX_O_PLL_LOCK_DONE) - dev_warn(hdptx->dev, "PLL locked by unknown consumer!\n"); + if (ret) { + atomic_dec(&hdptx->usage_count); + return ret; + } =20 if (mode =3D=3D PHY_MODE_DP) { rk_hdptx_dp_reset(hdptx); } else { - ret =3D rk_hdptx_pll_cmn_config(hdptx); - if (ret) - goto dec_usage; + /* + * Ignore PLL config errors at this point as pll_config_dirty + * was not reset and, therefore, operation will be retried. + */ + rk_hdptx_pll_cmn_config(hdptx); } =20 return 0; - -dec_usage: - atomic_dec(&hdptx->usage_count); - return ret; } =20 static int rk_hdptx_phy_consumer_put(struct rk_hdptx_phy *hdptx, bool forc= e) @@ -1700,13 +1704,18 @@ static int rk_hdptx_phy_power_on(struct phy *phy) if (ret) rk_hdptx_phy_consumer_put(hdptx, true); } else { - regmap_write(hdptx->grf, GRF_HDPTX_CON0, - HDPTX_MODE_SEL << 16 | FIELD_PREP(HDPTX_MODE_SEL, 0x0)); + if (hdptx->pll_config_dirty) + ret =3D rk_hdptx_pll_cmn_config(hdptx); =20 - if (hdptx->hdmi_cfg.mode =3D=3D PHY_HDMI_MODE_FRL) - ret =3D rk_hdptx_frl_lcpll_mode_config(hdptx); - else - ret =3D rk_hdptx_tmds_ropll_mode_config(hdptx); + if (!ret) { + regmap_write(hdptx->grf, GRF_HDPTX_CON0, + HDPTX_MODE_SEL << 16 | FIELD_PREP(HDPTX_MODE_SEL, 0x0)); + + if (hdptx->hdmi_cfg.mode =3D=3D PHY_HDMI_MODE_FRL) + ret =3D rk_hdptx_frl_lcpll_mode_config(hdptx); + else + ret =3D rk_hdptx_tmds_ropll_mode_config(hdptx); + } =20 if (ret) rk_hdptx_phy_consumer_put(hdptx, true); @@ -2081,7 +2090,10 @@ static int rk_hdptx_phy_configure(struct phy *phy, u= nion phy_configure_opts *opt dev_err(hdptx->dev, "invalid hdmi params for phy configure\n"); } else { hdptx->restrict_rate_change =3D true; - dev_dbg(hdptx->dev, "%s rate=3D%llu bpc=3D%u\n", __func__, + hdptx->pll_config_dirty =3D true; + + dev_dbg(hdptx->dev, "%s %s rate=3D%llu bpc=3D%u\n", __func__, + hdptx->hdmi_cfg.mode ? "FRL" : "TMDS", hdptx->hdmi_cfg.rate, hdptx->hdmi_cfg.bpc); } =20 @@ -2323,8 +2335,19 @@ static int rk_hdptx_phy_clk_determine_rate(struct cl= k_hw *hw, { struct rk_hdptx_phy *hdptx =3D to_rk_hdptx_phy(hw); =20 - if (hdptx->hdmi_cfg.mode =3D=3D PHY_HDMI_MODE_FRL) - return hdptx->hdmi_cfg.rate; + /* + * Invalidate current clock rate to ensure rk_hdptx_phy_clk_set_rate() + * will be invoked to commit PLL configuration. + */ + if (hdptx->pll_config_dirty) { + req->rate =3D 0; + return 0; + } + + if (hdptx->hdmi_cfg.mode =3D=3D PHY_HDMI_MODE_FRL) { + req->rate =3D hdptx->hdmi_cfg.rate; + return 0; + } =20 /* * FIXME: Temporarily allow altering TMDS char rate via CCF. @@ -2356,17 +2379,6 @@ static int rk_hdptx_phy_clk_set_rate(struct clk_hw *= hw, unsigned long rate, unsigned long parent_rate) { struct rk_hdptx_phy *hdptx =3D to_rk_hdptx_phy(hw); - unsigned long long link_rate =3D rate; - - if (hdptx->hdmi_cfg.mode !=3D PHY_HDMI_MODE_FRL) - link_rate =3D DIV_ROUND_CLOSEST_ULL(rate * hdptx->hdmi_cfg.bpc, 8); - - /* Revert any unlikely link rate change since determine_rate() */ - if (hdptx->hdmi_cfg.rate !=3D link_rate) { - dev_warn(hdptx->dev, "Reverting unexpected rate change from %llu to %llu= \n", - link_rate, hdptx->hdmi_cfg.rate); - hdptx->hdmi_cfg.rate =3D link_rate; - } =20 /* * The link rate would be normally programmed in HW during --=20 2.54.0 From nobody Sat Jun 13 00:38:18 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1265E3DBD7F for ; Thu, 11 Jun 2026 23:45:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781221558; cv=none; b=bPwZVprK3jyCJ2J66N8GdmVLSG8zB7X66J7nvVME+//krdaotCUE7f8CnR8t432AOXu2Fu/PW4V1KdFpYEBXpfpUr9NRj1hcKgzullYfPlunBLYxvBqLf2VV/57TExEd9XMz+BuetwaQozDZtAcXy5VHQLevJYlZ972+AOsVJpA= ARC-Message-Signature: i=1; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260612-hdptx-clk-fixes-v4-5-ce5e1d456cda@collabora.com> References: <20260612-hdptx-clk-fixes-v4-0-ce5e1d456cda@collabora.com> In-Reply-To: <20260612-hdptx-clk-fixes-v4-0-ce5e1d456cda@collabora.com> To: Vinod Koul , Neil Armstrong , Heiko Stuebner , Algea Cao , Dmitry Baryshkov Cc: kernel@collabora.com, linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, =?utf-8?q?Thomas_Niederpr=C3=BCm?= , Simon Wright X-Mailer: b4 0.15.2 Since commit ba9c2fe18c17 ("drm/rockchip: dw_hdmi_qp: Switch to phy_configure()") the TMDS rate setup doesn't rely anymore on the unconventional usage of the bus width, instead it is managed exclusively through the HDMI PHY configuration API. Drop the now obsolete workaround to retrieve the TMDS character rate via phy_get_bus_width() during power_on(). While at it, get rid of the extra call to rk_hdptx_phy_consumer_put() by moving the statement at the end of the function. Tested-by: Thomas Niederpr=C3=BCm Tested-by: Simon Wright Signed-off-by: Cristian Ciocaltea --- drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 27 +++++--------------= ---- 1 file changed, 6 insertions(+), 21 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/ph= y/rockchip/phy-rockchip-samsung-hdptx.c index 25bd821cd039..35997087d61c 100644 --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c @@ -1660,22 +1660,6 @@ static int rk_hdptx_phy_power_on(struct phy *phy) enum phy_mode mode =3D phy_get_mode(phy); int ret, lane; =20 - if (mode !=3D PHY_MODE_DP) { - if (!hdptx->hdmi_cfg.rate && hdptx->hdmi_cfg.mode !=3D PHY_HDMI_MODE_FRL= ) { - /* - * FIXME: Temporary workaround to setup TMDS char rate - * from the RK DW HDMI QP bridge driver. - * Will be removed as soon the switch to the HDMI PHY - * configuration API has been completed on both ends. - */ - hdptx->hdmi_cfg.rate =3D phy_get_bus_width(hdptx->phy) & 0xfffffff; - hdptx->hdmi_cfg.rate *=3D 100; - } - - dev_dbg(hdptx->dev, "%s rate=3D%llu bpc=3D%u\n", __func__, - hdptx->hdmi_cfg.rate, hdptx->hdmi_cfg.bpc); - } - ret =3D rk_hdptx_phy_consumer_get(hdptx); if (ret) return ret; @@ -1701,9 +1685,10 @@ static int rk_hdptx_phy_power_on(struct phy *phy) rk_hdptx_dp_pll_init(hdptx); =20 ret =3D rk_hdptx_dp_aux_init(hdptx); - if (ret) - rk_hdptx_phy_consumer_put(hdptx, true); } else { + dev_dbg(hdptx->dev, "%s rate=3D%llu bpc=3D%u\n", __func__, + hdptx->hdmi_cfg.rate, hdptx->hdmi_cfg.bpc); + if (hdptx->pll_config_dirty) ret =3D rk_hdptx_pll_cmn_config(hdptx); =20 @@ -1716,11 +1701,11 @@ static int rk_hdptx_phy_power_on(struct phy *phy) else ret =3D rk_hdptx_tmds_ropll_mode_config(hdptx); } - - if (ret) - rk_hdptx_phy_consumer_put(hdptx, true); } =20 + if (ret) + rk_hdptx_phy_consumer_put(hdptx, true); + return ret; } =20 --=20 2.54.0 From nobody Sat Jun 13 00:38:18 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1252E3DBD77 for ; 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Fri, 12 Jun 2026 01:45:47 +0200 (CEST) From: Cristian Ciocaltea Date: Fri, 12 Jun 2026 02:45:25 +0300 Subject: [PATCH v4 6/8] phy: rockchip: samsung-hdptx: Drop restrict_rate_change handling Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260612-hdptx-clk-fixes-v4-6-ce5e1d456cda@collabora.com> References: <20260612-hdptx-clk-fixes-v4-0-ce5e1d456cda@collabora.com> In-Reply-To: <20260612-hdptx-clk-fixes-v4-0-ce5e1d456cda@collabora.com> To: Vinod Koul , Neil Armstrong , Heiko Stuebner , Algea Cao , Dmitry Baryshkov Cc: kernel@collabora.com, linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, =?utf-8?q?Thomas_Niederpr=C3=BCm?= , Simon Wright X-Mailer: b4 0.15.2 Since commit 6efbd0f46dd8 ("phy: rockchip: samsung-hdptx: Restrict altering TMDS char rate via CCF"), adjusting the rate via the Common Clock Framework API has been disallowed. To avoid breaking existing users until switching to the PHY config API, it introduced a temporary exception to the rule, controlled via the 'restrict_rate_change' flag. As the API transition completed, remove the now deprecated exception logic. Tested-by: Thomas Niederpr=C3=BCm Tested-by: Simon Wright Signed-off-by: Cristian Ciocaltea --- drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 42 +++++--------------= ---- 1 file changed, 8 insertions(+), 34 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/ph= y/rockchip/phy-rockchip-samsung-hdptx.c index 35997087d61c..b74a433c7e53 100644 --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c @@ -414,7 +414,6 @@ struct rk_hdptx_phy { /* clk provider */ struct clk_hw hw; bool pll_config_dirty; - bool restrict_rate_change; =20 atomic_t usage_count; =20 @@ -2074,7 +2073,6 @@ static int rk_hdptx_phy_configure(struct phy *phy, un= ion phy_configure_opts *opt if (ret) { dev_err(hdptx->dev, "invalid hdmi params for phy configure\n"); } else { - hdptx->restrict_rate_change =3D true; hdptx->pll_config_dirty =3D true; =20 dev_dbg(hdptx->dev, "%s %s rate=3D%llu bpc=3D%u\n", __func__, @@ -2321,41 +2319,17 @@ static int rk_hdptx_phy_clk_determine_rate(struct c= lk_hw *hw, struct rk_hdptx_phy *hdptx =3D to_rk_hdptx_phy(hw); =20 /* - * Invalidate current clock rate to ensure rk_hdptx_phy_clk_set_rate() - * will be invoked to commit PLL configuration. + * For uncommitted PLL configuration, invalidate the current clock rate + * to ensure rk_hdptx_phy_clk_set_rate() will be always invoked. + * Otherwise, restrict the rate according to the PHY link setup. */ - if (hdptx->pll_config_dirty) { + if (hdptx->pll_config_dirty) req->rate =3D 0; - return 0; - } - - if (hdptx->hdmi_cfg.mode =3D=3D PHY_HDMI_MODE_FRL) { + else if (hdptx->hdmi_cfg.mode =3D=3D PHY_HDMI_MODE_FRL) req->rate =3D hdptx->hdmi_cfg.rate; - return 0; - } - - /* - * FIXME: Temporarily allow altering TMDS char rate via CCF. - * To be dropped as soon as the RK DW HDMI QP bridge driver - * switches to make use of phy_configure(). - */ - if (!hdptx->restrict_rate_change && req->rate !=3D hdptx->hdmi_cfg.rate) { - struct phy_configure_opts_hdmi hdmi =3D { - .tmds_char_rate =3D req->rate, - }; - - int ret =3D rk_hdptx_phy_verify_hdmi_config(hdptx, &hdmi, &hdptx->hdmi_c= fg); - - if (ret) - return ret; - } - - /* - * The TMDS char rate shall be adjusted via phy_configure() only, - * hence ensure rk_hdptx_phy_clk_set_rate() won't be invoked with - * a different rate argument. - */ - req->rate =3D DIV_ROUND_CLOSEST_ULL(hdptx->hdmi_cfg.rate * 8, hdptx->hdmi= _cfg.bpc); + else + req->rate =3D DIV_ROUND_CLOSEST_ULL(hdptx->hdmi_cfg.rate * 8, + hdptx->hdmi_cfg.bpc); =20 return 0; } --=20 2.54.0 From nobody Sat Jun 13 00:38:18 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 09CF73DB99A for ; Thu, 11 Jun 2026 23:45:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781221559; cv=none; b=g0i6J98NcrjJSER8PFVEEZowvLl7aFdZK3C03ock/WhFKNjtTpi9RPI5ZWfsU/yYUCKX03hesWuUqctuy4ldj1/W1ABAL0PqwbwQBWT/N7VYFIiNbNVUDmvpvpwjTD4+FR1BGzZjm9W5rO6qPR81ib7eTM+biirAcyKF5Jk7ssU= ARC-Message-Signature: i=1; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260612-hdptx-clk-fixes-v4-7-ce5e1d456cda@collabora.com> References: <20260612-hdptx-clk-fixes-v4-0-ce5e1d456cda@collabora.com> In-Reply-To: <20260612-hdptx-clk-fixes-v4-0-ce5e1d456cda@collabora.com> To: Vinod Koul , Neil Armstrong , Heiko Stuebner , Algea Cao , Dmitry Baryshkov Cc: kernel@collabora.com, linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, =?utf-8?q?Thomas_Niederpr=C3=BCm?= , Simon Wright X-Mailer: b4 0.15.2 The 16 most significant bits of the general-purpose register (GRF) are used as a write-enable mask for the remaining 16 bits. Make use of the recently introduced FIELD_PREP_WM16() macro to avoid open-coding the bit shift operations and improve code readability. Tested-by: Thomas Niederpr=C3=BCm Tested-by: Simon Wright Signed-off-by: Cristian Ciocaltea --- drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 52 +++++++++++--------= ---- 1 file changed, 25 insertions(+), 27 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/ph= y/rockchip/phy-rockchip-samsung-hdptx.c index b74a433c7e53..88b48f5f946d 100644 --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (c) 2021-2022 Rockchip Electronics Co., Ltd. - * Copyright (c) 2024 Collabora Ltd. + * Copyright (c) 2024-2026 Collabora Ltd. * * Author: Algea Cao * Author: Cristian Ciocaltea @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -949,7 +950,9 @@ static void rk_hdptx_pre_power_up(struct rk_hdptx_phy *= hdptx) reset_control_assert(hdptx->rsts[RST_CMN].rstc); reset_control_assert(hdptx->rsts[RST_INIT].rstc); =20 - val =3D (HDPTX_I_PLL_EN | HDPTX_I_BIAS_EN | HDPTX_I_BGR_EN) << 16; + val =3D (FIELD_PREP_WM16(HDPTX_I_PLL_EN, 0) | + FIELD_PREP_WM16(HDPTX_I_BIAS_EN, 0) | + FIELD_PREP_WM16(HDPTX_I_BGR_EN, 0)); regmap_write(hdptx->grf, GRF_HDPTX_CON0, val); } =20 @@ -960,8 +963,8 @@ static int rk_hdptx_post_enable_lane(struct rk_hdptx_ph= y *hdptx) =20 reset_control_deassert(hdptx->rsts[RST_LANE].rstc); =20 - val =3D (HDPTX_I_BIAS_EN | HDPTX_I_BGR_EN) << 16 | - HDPTX_I_BIAS_EN | HDPTX_I_BGR_EN; + val =3D (FIELD_PREP_WM16(HDPTX_I_BIAS_EN, 1) | + FIELD_PREP_WM16(HDPTX_I_BGR_EN, 1)); regmap_write(hdptx->grf, GRF_HDPTX_CON0, val); =20 /* 3 lanes FRL mode */ @@ -990,16 +993,15 @@ static int rk_hdptx_post_enable_pll(struct rk_hdptx_p= hy *hdptx) u32 val; int ret; =20 - val =3D (HDPTX_I_BIAS_EN | HDPTX_I_BGR_EN) << 16 | - HDPTX_I_BIAS_EN | HDPTX_I_BGR_EN; + val =3D (FIELD_PREP_WM16(HDPTX_I_BIAS_EN, 1) | + FIELD_PREP_WM16(HDPTX_I_BGR_EN, 1)); regmap_write(hdptx->grf, GRF_HDPTX_CON0, val); =20 usleep_range(10, 15); reset_control_deassert(hdptx->rsts[RST_INIT].rstc); =20 usleep_range(10, 15); - val =3D HDPTX_I_PLL_EN << 16 | HDPTX_I_PLL_EN; - regmap_write(hdptx->grf, GRF_HDPTX_CON0, val); + regmap_write(hdptx->grf, GRF_HDPTX_CON0, FIELD_PREP_WM16(HDPTX_I_PLL_EN, = 1)); =20 usleep_range(10, 15); reset_control_deassert(hdptx->rsts[RST_CMN].rstc); @@ -1037,7 +1039,9 @@ static void rk_hdptx_phy_disable(struct rk_hdptx_phy = *hdptx) reset_control_assert(hdptx->rsts[RST_CMN].rstc); reset_control_assert(hdptx->rsts[RST_INIT].rstc); =20 - val =3D (HDPTX_I_PLL_EN | HDPTX_I_BIAS_EN | HDPTX_I_BGR_EN) << 16; + val =3D (FIELD_PREP_WM16(HDPTX_I_PLL_EN, 0) | + FIELD_PREP_WM16(HDPTX_I_BIAS_EN, 0) | + FIELD_PREP_WM16(HDPTX_I_BGR_EN, 0)); regmap_write(hdptx->grf, GRF_HDPTX_CON0, val); } =20 @@ -1135,7 +1139,7 @@ static int rk_hdptx_frl_lcpll_cmn_config(struct rk_hd= ptx_phy *hdptx) =20 rk_hdptx_pre_power_up(hdptx); =20 - regmap_write(hdptx->grf, GRF_HDPTX_CON0, LC_REF_CLK_SEL << 16); + regmap_write(hdptx->grf, GRF_HDPTX_CON0, FIELD_PREP_WM16(LC_REF_CLK_SEL, = 0)); =20 rk_hdptx_multi_reg_write(hdptx, rk_hdptx_common_cmn_init_seq); rk_hdptx_multi_reg_write(hdptx, rk_hdptx_frl_lcpll_cmn_init_seq); @@ -1178,8 +1182,7 @@ static int rk_hdptx_frl_lcpll_ropll_cmn_config(struct= rk_hdptx_phy *hdptx) rk_hdptx_pre_power_up(hdptx); =20 /* ROPLL input reference clock from LCPLL (cascade mode) */ - regmap_write(hdptx->grf, GRF_HDPTX_CON0, - (LC_REF_CLK_SEL << 16) | LC_REF_CLK_SEL); + regmap_write(hdptx->grf, GRF_HDPTX_CON0, FIELD_PREP_WM16(LC_REF_CLK_SEL, = 1)); =20 rk_hdptx_multi_reg_write(hdptx, rk_hdptx_common_cmn_init_seq); rk_hdptx_multi_reg_write(hdptx, rk_hdptx_frl_lcpll_ropll_cmn_init_seq); @@ -1218,7 +1221,7 @@ static int rk_hdptx_tmds_ropll_cmn_config(struct rk_h= dptx_phy *hdptx) =20 rk_hdptx_pre_power_up(hdptx); =20 - regmap_write(hdptx->grf, GRF_HDPTX_CON0, LC_REF_CLK_SEL << 16); + regmap_write(hdptx->grf, GRF_HDPTX_CON0, FIELD_PREP_WM16(LC_REF_CLK_SEL, = 0)); =20 rk_hdptx_multi_reg_write(hdptx, rk_hdptx_common_cmn_init_seq); rk_hdptx_multi_reg_write(hdptx, rk_hdptx_tmds_cmn_init_seq); @@ -1336,11 +1339,9 @@ static void rk_hdptx_dp_reset(struct rk_hdptx_phy *h= dptx) FIELD_PREP(LN_TX_DRV_EI_EN_MASK, 0)); =20 regmap_write(hdptx->grf, GRF_HDPTX_CON0, - HDPTX_I_PLL_EN << 16 | FIELD_PREP(HDPTX_I_PLL_EN, 0x0)); - regmap_write(hdptx->grf, GRF_HDPTX_CON0, - HDPTX_I_BIAS_EN << 16 | FIELD_PREP(HDPTX_I_BIAS_EN, 0x0)); - regmap_write(hdptx->grf, GRF_HDPTX_CON0, - HDPTX_I_BGR_EN << 16 | FIELD_PREP(HDPTX_I_BGR_EN, 0x0)); + FIELD_PREP_WM16(HDPTX_I_PLL_EN, 0) | + FIELD_PREP_WM16(HDPTX_I_BIAS_EN, 0) | + FIELD_PREP_WM16(HDPTX_I_BGR_EN, 0)); } =20 static int rk_hdptx_phy_consumer_get(struct rk_hdptx_phy *hdptx) @@ -1616,9 +1617,8 @@ static int rk_hdptx_dp_aux_init(struct rk_hdptx_phy *= hdptx) FIELD_PREP(OVRD_SB_VREG_EN_MASK, 0x1)); =20 regmap_write(hdptx->grf, GRF_HDPTX_CON0, - HDPTX_I_BGR_EN << 16 | FIELD_PREP(HDPTX_I_BGR_EN, 0x1)); - regmap_write(hdptx->grf, GRF_HDPTX_CON0, - HDPTX_I_BIAS_EN << 16 | FIELD_PREP(HDPTX_I_BIAS_EN, 0x1)); + FIELD_PREP_WM16(HDPTX_I_BGR_EN, 1) | + FIELD_PREP_WM16(HDPTX_I_BIAS_EN, 1)); usleep_range(20, 25); =20 reset_control_deassert(hdptx->rsts[RST_INIT].rstc); @@ -1665,7 +1665,7 @@ static int rk_hdptx_phy_power_on(struct phy *phy) =20 if (mode =3D=3D PHY_MODE_DP) { regmap_write(hdptx->grf, GRF_HDPTX_CON0, - HDPTX_MODE_SEL << 16 | FIELD_PREP(HDPTX_MODE_SEL, 0x1)); + FIELD_PREP_WM16(HDPTX_MODE_SEL, 1)); =20 for (lane =3D 0; lane < 4; lane++) { regmap_update_bits(hdptx->regmap, LANE_REG(031e) + 0x400 * lane, @@ -1693,7 +1693,7 @@ static int rk_hdptx_phy_power_on(struct phy *phy) =20 if (!ret) { regmap_write(hdptx->grf, GRF_HDPTX_CON0, - HDPTX_MODE_SEL << 16 | FIELD_PREP(HDPTX_MODE_SEL, 0x0)); + FIELD_PREP_WM16(HDPTX_MODE_SEL, 0)); =20 if (hdptx->hdmi_cfg.mode =3D=3D PHY_HDMI_MODE_FRL) ret =3D rk_hdptx_frl_lcpll_mode_config(hdptx); @@ -1828,8 +1828,7 @@ static int rk_hdptx_phy_set_rate(struct rk_hdptx_phy = *hdptx, u32 bw, status; int ret; =20 - regmap_write(hdptx->grf, GRF_HDPTX_CON0, - HDPTX_I_PLL_EN << 16 | FIELD_PREP(HDPTX_I_PLL_EN, 0x0)); + regmap_write(hdptx->grf, GRF_HDPTX_CON0, FIELD_PREP_WM16(HDPTX_I_PLL_EN, = 0)); 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Fri, 12 Jun 2026 01:45:49 +0200 (CEST) From: Cristian Ciocaltea Date: Fri, 12 Jun 2026 02:45:27 +0300 Subject: [PATCH v4 8/8] phy: rockchip: samsung-hdptx: Consistently use bitfield macros Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260612-hdptx-clk-fixes-v4-8-ce5e1d456cda@collabora.com> References: <20260612-hdptx-clk-fixes-v4-0-ce5e1d456cda@collabora.com> In-Reply-To: <20260612-hdptx-clk-fixes-v4-0-ce5e1d456cda@collabora.com> To: Vinod Koul , Neil Armstrong , Heiko Stuebner , Algea Cao , Dmitry Baryshkov Cc: kernel@collabora.com, linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, =?utf-8?q?Thomas_Niederpr=C3=BCm?= , Simon Wright X-Mailer: b4 0.15.2 Make the code more robust and improve readability by using the available bitfield macros (e.g. FIELD_PREP, FIELD_GET) whenever possible, instead of open coding the related bit operations. Tested-by: Thomas Niederpr=C3=BCm Tested-by: Simon Wright Signed-off-by: Cristian Ciocaltea --- drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 30 +++++++++++++++----= ---- 1 file changed, 20 insertions(+), 10 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/ph= y/rockchip/phy-rockchip-samsung-hdptx.c index 88b48f5f946d..d8646f24e05e 100644 --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c @@ -53,6 +53,12 @@ /* CMN_REG(001e) */ #define LCPLL_PI_EN_MASK BIT(5) #define LCPLL_100M_CLK_EN_MASK BIT(0) +/* CMN_REG(0022) */ +#define ANA_LCPLL_PMS_PDIV_MASK GENMASK(7, 4) +#define ANA_LCPLL_PMS_REFDIV_MASK GENMASK(3, 0) +/* CMN_REG(0023) */ +#define LCPLL_PMS_SDIV_RBR_MASK GENMASK(7, 4) +#define LCPLL_PMS_SDIV_HBR_MASK GENMASK(3, 0) /* CMN_REG(0025) */ #define LCPLL_PMS_IQDIV_RSTN_MASK BIT(4) /* CMN_REG(0028) */ @@ -1157,9 +1163,11 @@ static int rk_hdptx_frl_lcpll_cmn_config(struct rk_h= dptx_phy *hdptx) regmap_write(hdptx->regmap, CMN_REG(0020), cfg->pms_mdiv); regmap_write(hdptx->regmap, CMN_REG(0021), cfg->pms_mdiv_afc); regmap_write(hdptx->regmap, CMN_REG(0022), - (cfg->pms_pdiv << 4) | cfg->pms_refdiv); + FIELD_PREP(ANA_LCPLL_PMS_PDIV_MASK, cfg->pms_pdiv) | + FIELD_PREP(ANA_LCPLL_PMS_REFDIV_MASK, cfg->pms_refdiv)); regmap_write(hdptx->regmap, CMN_REG(0023), - (cfg->pms_sdiv << 4) | cfg->pms_sdiv); + FIELD_PREP(LCPLL_PMS_SDIV_RBR_MASK, cfg->pms_sdiv) | + FIELD_PREP(LCPLL_PMS_SDIV_HBR_MASK, cfg->pms_sdiv)); regmap_write(hdptx->regmap, CMN_REG(002a), cfg->sdm_deno); regmap_write(hdptx->regmap, CMN_REG(002b), cfg->sdm_num_sign); regmap_write(hdptx->regmap, CMN_REG(002c), cfg->sdm_num); @@ -1229,8 +1237,10 @@ static int rk_hdptx_tmds_ropll_cmn_config(struct rk_= hdptx_phy *hdptx) regmap_write(hdptx->regmap, CMN_REG(0051), cfg->pms_mdiv); regmap_write(hdptx->regmap, CMN_REG(0055), cfg->pms_mdiv_afc); regmap_write(hdptx->regmap, CMN_REG(0059), - (cfg->pms_pdiv << 4) | cfg->pms_refdiv); - regmap_write(hdptx->regmap, CMN_REG(005a), cfg->pms_sdiv << 4); + FIELD_PREP(ANA_ROPLL_PMS_PDIV_MASK, cfg->pms_pdiv) | + FIELD_PREP(ANA_ROPLL_PMS_REFDIV_MASK, cfg->pms_refdiv)); + regmap_write(hdptx->regmap, CMN_REG(005a), + FIELD_PREP(ROPLL_PMS_SDIV_RBR_MASK, cfg->pms_sdiv)); =20 regmap_update_bits(hdptx->regmap, CMN_REG(005e), ROPLL_SDM_EN_MASK, FIELD_PREP(ROPLL_SDM_EN_MASK, cfg->sdm_en)); @@ -2177,7 +2187,7 @@ static u64 rk_hdptx_phy_clk_calc_rate_from_pll_cfg(st= ruct rk_hdptx_phy *hdptx) ret =3D regmap_read(hdptx->regmap, CMN_REG(0023), &val); if (ret) return 0; - lcpll_hw.pms_sdiv =3D val & 0xf; + lcpll_hw.pms_sdiv =3D FIELD_GET(LCPLL_PMS_SDIV_HBR_MASK, val); =20 ret =3D regmap_read(hdptx->regmap, CMN_REG(002B), &val); if (ret) @@ -2197,7 +2207,7 @@ static u64 rk_hdptx_phy_clk_calc_rate_from_pll_cfg(st= ruct rk_hdptx_phy *hdptx) ret =3D regmap_read(hdptx->regmap, CMN_REG(002D), &val); if (ret) return 0; - lcpll_hw.sdc_n =3D (val & LCPLL_SDC_N_MASK) >> 1; + lcpll_hw.sdc_n =3D FIELD_GET(LCPLL_SDC_N_MASK, val); =20 ret =3D regmap_read(hdptx->grf, GRF_HDPTX_CON0, &val); if (ret) @@ -2238,12 +2248,12 @@ static u64 rk_hdptx_phy_clk_calc_rate_from_pll_cfg(= struct rk_hdptx_phy *hdptx) ret =3D regmap_read(hdptx->regmap, CMN_REG(005E), &val); if (ret) return 0; - ropll_hw.sdm_en =3D val & ROPLL_SDM_EN_MASK; + ropll_hw.sdm_en =3D FIELD_GET(ROPLL_SDM_EN_MASK, val); =20 ret =3D regmap_read(hdptx->regmap, CMN_REG(0064), &val); if (ret) return 0; - ropll_hw.sdm_num_sign =3D val & ROPLL_SDM_NUM_SIGN_RBR_MASK; + ropll_hw.sdm_num_sign =3D FIELD_GET(ROPLL_SDM_NUM_SIGN_RBR_MASK, val); =20 ret =3D regmap_read(hdptx->regmap, CMN_REG(0065), &val); if (ret) @@ -2258,7 +2268,7 @@ static u64 rk_hdptx_phy_clk_calc_rate_from_pll_cfg(st= ruct rk_hdptx_phy *hdptx) ret =3D regmap_read(hdptx->regmap, CMN_REG(0069), &val); if (ret) return 0; - ropll_hw.sdc_n =3D (val & ROPLL_SDC_N_RBR_MASK) + 3; + ropll_hw.sdc_n =3D FIELD_GET(ROPLL_SDC_N_RBR_MASK, val) + 3; =20 ret =3D regmap_read(hdptx->regmap, CMN_REG(006c), &val); if (ret) @@ -2273,7 +2283,7 @@ static u64 rk_hdptx_phy_clk_calc_rate_from_pll_cfg(st= ruct rk_hdptx_phy *hdptx) ret =3D regmap_read(hdptx->regmap, CMN_REG(0086), &val); if (ret) return 0; - ropll_hw.pms_sdiv =3D ((val & PLL_PCG_POSTDIV_SEL_MASK) >> 4) + 1; + ropll_hw.pms_sdiv =3D FIELD_GET(PLL_PCG_POSTDIV_SEL_MASK, val) + 1; bpc =3D (FIELD_GET(PLL_PCG_CLK_SEL_MASK, val) << 1) + 8; =20 fout =3D PLL_REF_CLK * ropll_hw.pms_mdiv; --=20 2.54.0