From nobody Fri Jun 12 20:17:38 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 29A37409636; Thu, 11 Jun 2026 16:09:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.19 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781194178; cv=none; b=dH5NroU9/lwlKYxKP6XorOcCQ0m9MAd4/eXpCiBdqgCOx7thscPORbO9H/eeyKK5J3jB4GoZL8ZJhHlbDDGcsnbYOKW+yN3iojNDsKfdDQLfiwnsDn3wbaETr2uH2Mg3DnJd70z48ex5vHzyTSuDFxpiUAHd1KqxNFWMScnzlos= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781194178; c=relaxed/simple; bh=Krnalm3gofcxrYqeJe2mgn6O2TBD/liaqN+jY92+f/k=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Lz7RoEoiawD1OzpBU0DRSoO6UcLGp5vGdkOiJeGF8piKCE7yjpIqNlHOYSSuNrZw6AGHiZcZHl70g+ThWpr5VSpZW5g68gU1ob1cqxwRDoMvuFV7j13Bf+BuG5w/lxRSkNh/51mf2R3J4YwZEvjbnLzjmBf89NM/lYrp1JuByLc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=OI23TyLx; arc=none smtp.client-ip=198.175.65.19 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="OI23TyLx" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1781194177; x=1812730177; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Krnalm3gofcxrYqeJe2mgn6O2TBD/liaqN+jY92+f/k=; b=OI23TyLx0t0CKF00aODzGlfMZvx3xmefd0//JVdVGTTwDtHGhBDgYGnA xvJZrG3I/YY85snwpp8W6m3h+O2YQqI+Txd4L5vtfl4cql3jcAVKFv439 LGNGCPWNDzSEjo2FYkUzuAUVaAJ0pFTKSh90f3kSCuV6h1rGdEJS4xMwz ZMpd3w2nSShBYadXf9yKFlGI/MZcb7PWavCvmmEDtq7AlclFUrXnZWjkm Lpio2YfTV31BYT647GvQJDwt9TtH8A6xUUerX56qcuIqJ/WtlHkURjRNh QxmpiebJDfFy9hnGsN7OPrUPnVq3YCyYaJKzzytmYXRKJViRTEs8y2yf9 w==; X-CSE-ConnectionGUID: D3nCQUq2SYuSSCugrRgoQA== X-CSE-MsgGUID: vEXftG2xTfuBi6tfxjxsQQ== X-IronPort-AV: E=McAfee;i="6800,10657,11813"; a="81994962" X-IronPort-AV: E=Sophos;i="6.24,199,1774335600"; d="scan'208";a="81994962" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Jun 2026 09:09:36 -0700 X-CSE-ConnectionGUID: WGKOPhP1STKcxMttKWCgjQ== X-CSE-MsgGUID: QSSquFLhRneHtbh5MudJog== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,199,1774335600"; d="scan'208";a="246403589" Received: from 9cc2c43eec6b.jf.intel.com ([10.54.77.29]) by orviesa008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Jun 2026 09:09:36 -0700 From: Zide Chen To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , Adrian Hunter , Alexander Shishkin , Andi Kleen , Eranian Stephane Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Dapeng Mi , Zide Chen Subject: [PATCH V3 1/8] perf/x86/intel/uncore: Fix PCI PMU cleanup on setup failure Date: Thu, 11 Jun 2026 09:00:26 -0700 Message-ID: <20260611160033.66760-2-zide.chen@intel.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260611160033.66760-1-zide.chen@intel.com> References: <20260611160033.66760-1-zide.chen@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When uncore_pci_pmu_register() fails, pmu->boxes[die] is set to NULL before returning. In the uncore_pci_remove() path, this causes uncore_pci_pmu_unregister() to be skipped entirely, leaking pmu->activeboxes. In the uncore_bus_notify() path, uncore_pci_pmu_unregister() may still be called and must exit early when pmu->boxes[die] is NULL to avoid a NULL pointer dereference, and to ensure activeboxes is only decremented for a previously active box. Additionally, since pci_get_drvdata() returns NULL on registration failure, uncore_pci_remove() can no longer treat NULL drvdata as an indicator of an auxiliary PCI device. Remove the associated WARN_ON_ONCE(). Link: https://sashiko.dev/#/patchset/20260512233048.9577-1-zide.chen@intel.= com?part=3D1 Reviewed-by: Dapeng Mi Signed-off-by: Zide Chen --- v3: Add Reviewed-by tag. v2: New patch. --- arch/x86/events/intel/uncore.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/x86/events/intel/uncore.c b/arch/x86/events/intel/uncore.c index 7857959c6e82..b69b6a21d46b 100644 --- a/arch/x86/events/intel/uncore.c +++ b/arch/x86/events/intel/uncore.c @@ -1183,6 +1183,7 @@ static int uncore_pci_pmu_register(struct pci_dev *pd= ev, /* First active box registers the pmu */ ret =3D uncore_pmu_register(pmu); if (ret) { + atomic_dec(&pmu->activeboxes); pmu->boxes[die] =3D NULL; uncore_box_exit(box); kfree(box); @@ -1248,6 +1249,9 @@ static void uncore_pci_pmu_unregister(struct intel_un= core_pmu *pmu, int die) { struct intel_uncore_box *box =3D pmu->boxes[die]; =20 + if (!box) + return; + pmu->boxes[die] =3D NULL; if (atomic_dec_return(&pmu->activeboxes) =3D=3D 0) uncore_pmu_unregister(pmu); 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11 Jun 2026 09:09:36 -0700 From: Zide Chen To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , Adrian Hunter , Alexander Shishkin , Andi Kleen , Eranian Stephane Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Dapeng Mi , Zide Chen Subject: [PATCH V3 2/8] perf/x86/intel/uncore: Fix refcnt and other cleanups Date: Thu, 11 Jun 2026 09:00:27 -0700 Message-ID: <20260611160033.66760-3-zide.chen@intel.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260611160033.66760-1-zide.chen@intel.com> References: <20260611160033.66760-1-zide.chen@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Fix typo UNCORE_BOX_FLAG_INITIATED to UNCORE_BOX_FLAG_INITIALIZED. Rename the 'id' parameter in uncore_box_{ref,unref}() to 'die' to reflect its actual meaning and be consistent with other functions. box->refcnt is incremented in the PCI PMU register path but has never been checked or decremented. Although for PCI PMUs box->refcnt effectively tracks only a single user, add atomic_dec_return() in the PCI PMU unregister path to make the reference counting complete and consistent. Signed-off-by: Zide Chen Reviewed-by: Dapeng Mi --- v3: - Instead of removing atomic_inc(&box->refcnt) in PMU register, add the corresponding atomic_dec_return(&box->refcnt) in PMU unregister. (Dapeng) v2: - Don't rename pmu->activeboxes and keep its semantics because in uncore_pci_remove() path, uncore_pci_pmu_unregister() won't be called for non-active boxes. - Since pmu->activeboxes keeps its name, don't need to rename box->refcnt to box->cpu_refcnt. --- arch/x86/events/intel/uncore.c | 16 +++++++++------- arch/x86/events/intel/uncore.h | 6 +++--- 2 files changed, 12 insertions(+), 10 deletions(-) diff --git a/arch/x86/events/intel/uncore.c b/arch/x86/events/intel/uncore.c index b69b6a21d46b..21c8ed1628cb 100644 --- a/arch/x86/events/intel/uncore.c +++ b/arch/x86/events/intel/uncore.c @@ -1255,8 +1255,10 @@ static void uncore_pci_pmu_unregister(struct intel_u= ncore_pmu *pmu, int die) pmu->boxes[die] =3D NULL; if (atomic_dec_return(&pmu->activeboxes) =3D=3D 0) uncore_pmu_unregister(pmu); - uncore_box_exit(box); - kfree(box); + if (atomic_dec_return(&box->refcnt) =3D=3D 0) { + uncore_box_exit(box); + kfree(box); + } } =20 static void uncore_pci_remove(struct pci_dev *pdev) @@ -1518,7 +1520,7 @@ static void uncore_change_context(struct intel_uncore= _type **uncores, uncore_change_type_ctx(*uncores, old_cpu, new_cpu); } =20 -static void uncore_box_unref(struct intel_uncore_type **types, int id) +static void uncore_box_unref(struct intel_uncore_type **types, int die) { struct intel_uncore_type *type; struct intel_uncore_pmu *pmu; @@ -1529,7 +1531,7 @@ static void uncore_box_unref(struct intel_uncore_type= **types, int id) type =3D *types; pmu =3D type->pmus; for (i =3D 0; i < type->num_boxes; i++, pmu++) { - box =3D pmu->boxes[id]; + box =3D pmu->boxes[die]; if (box && box->cpu >=3D 0 && atomic_dec_return(&box->refcnt) =3D=3D 0) uncore_box_exit(box); } @@ -1604,14 +1606,14 @@ static int allocate_boxes(struct intel_uncore_type = **types, } =20 static int uncore_box_ref(struct intel_uncore_type **types, - int id, unsigned int cpu) + int die, unsigned int cpu) { struct intel_uncore_type *type; struct intel_uncore_pmu *pmu; struct intel_uncore_box *box; int i, ret; =20 - ret =3D allocate_boxes(types, id, cpu); + ret =3D allocate_boxes(types, die, cpu); if (ret) return ret; =20 @@ -1619,7 +1621,7 @@ static int uncore_box_ref(struct intel_uncore_type **= types, type =3D *types; pmu =3D type->pmus; for (i =3D 0; i < type->num_boxes; i++, pmu++) { - box =3D pmu->boxes[id]; + box =3D pmu->boxes[die]; if (box && box->cpu >=3D 0 && atomic_inc_return(&box->refcnt) =3D=3D 1) uncore_box_init(box); } diff --git a/arch/x86/events/intel/uncore.h b/arch/x86/events/intel/uncore.h index c2e5ccb1d72c..bad5d8dec8e0 100644 --- a/arch/x86/events/intel/uncore.h +++ b/arch/x86/events/intel/uncore.h @@ -185,7 +185,7 @@ struct intel_uncore_box { #define CFL_UNC_CBO_7_PERFEVTSEL0 0xf70 #define CFL_UNC_CBO_7_PER_CTR0 0xf76 =20 -#define UNCORE_BOX_FLAG_INITIATED 0 +#define UNCORE_BOX_FLAG_INITIALIZED 0 /* event config registers are 8-byte apart */ #define UNCORE_BOX_FLAG_CTL_OFFS8 1 /* CFL 8th CBOX has different MSR space */ @@ -559,7 +559,7 @@ static inline u64 uncore_read_counter(struct intel_unco= re_box *box, =20 static inline void uncore_box_init(struct intel_uncore_box *box) { - if (!test_and_set_bit(UNCORE_BOX_FLAG_INITIATED, &box->flags)) { + if (!test_and_set_bit(UNCORE_BOX_FLAG_INITIALIZED, &box->flags)) { if (box->pmu->type->ops->init_box) box->pmu->type->ops->init_box(box); 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d="scan'208";a="246403595" Received: from 9cc2c43eec6b.jf.intel.com ([10.54.77.29]) by orviesa008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Jun 2026 09:09:36 -0700 From: Zide Chen To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , Adrian Hunter , Alexander Shishkin , Andi Kleen , Eranian Stephane Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Dapeng Mi , Zide Chen Subject: [PATCH V3 3/8] perf/x86/intel/uncore: Let init_box() callback report failures Date: Thu, 11 Jun 2026 09:00:28 -0700 Message-ID: <20260611160033.66760-4-zide.chen@intel.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260611160033.66760-1-zide.chen@intel.com> References: <20260611160033.66760-1-zide.chen@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The init_box() callback currently returns void, so initialization failures are silently ignored and the box is still marked initialized. Change the callback to return int so platform code can report errors back to the common uncore layer. Update uncore_box_init() to set the initialized flag only when init_box() succeeds. Because box->refcnt guarantees that at most one CPU calls uncore_box_init() for a given box at a time, plain __set_bit() is safe for the initialized flag without atomic overhead. Convert all init_box() implementations to return 0 on success or a negative error code on failure. This is a prerequisite for propagating initialization errors to the caller so they can be handled properly. Reviewed-by: Ian Rogers Reviewed-by: Dapeng Mi Signed-off-by: Zide Chen --- v3: Add Reviewed-by tag. --- arch/x86/events/intel/uncore.h | 16 +++-- arch/x86/events/intel/uncore_discovery.c | 21 ++++--- arch/x86/events/intel/uncore_discovery.h | 6 +- arch/x86/events/intel/uncore_nhmex.c | 3 +- arch/x86/events/intel/uncore_snb.c | 80 +++++++++++++++--------- arch/x86/events/intel/uncore_snbep.c | 77 ++++++++++++++--------- 6 files changed, 126 insertions(+), 77 deletions(-) diff --git a/arch/x86/events/intel/uncore.h b/arch/x86/events/intel/uncore.h index bad5d8dec8e0..d732b87be0a9 100644 --- a/arch/x86/events/intel/uncore.h +++ b/arch/x86/events/intel/uncore.h @@ -129,7 +129,7 @@ struct intel_uncore_type { #define events_group attr_groups[2] =20 struct intel_uncore_ops { - void (*init_box)(struct intel_uncore_box *); + int (*init_box)(struct intel_uncore_box *); void (*exit_box)(struct intel_uncore_box *); void (*disable_box)(struct intel_uncore_box *); void (*enable_box)(struct intel_uncore_box *); @@ -557,12 +557,18 @@ static inline u64 uncore_read_counter(struct intel_un= core_box *box, return box->pmu->type->ops->read_counter(box, event); } =20 -static inline void uncore_box_init(struct intel_uncore_box *box) +static inline int uncore_box_init(struct intel_uncore_box *box) { - if (!test_and_set_bit(UNCORE_BOX_FLAG_INITIALIZED, &box->flags)) { - if (box->pmu->type->ops->init_box) - box->pmu->type->ops->init_box(box); + int ret =3D 0; + + if (!test_bit(UNCORE_BOX_FLAG_INITIALIZED, &box->flags) && + box->pmu->type->ops->init_box) { + ret =3D box->pmu->type->ops->init_box(box); + if (!ret) + __set_bit(UNCORE_BOX_FLAG_INITIALIZED, &box->flags); } + + return ret; } =20 static inline void uncore_box_exit(struct intel_uncore_box *box) diff --git a/arch/x86/events/intel/uncore_discovery.c b/arch/x86/events/int= el/uncore_discovery.c index e50776222256..0a22edf4d509 100644 --- a/arch/x86/events/intel/uncore_discovery.c +++ b/arch/x86/events/intel/uncore_discovery.c @@ -489,14 +489,15 @@ static u64 intel_generic_uncore_box_ctl(struct intel_= uncore_box *box) return unit->addr; } =20 -void intel_generic_uncore_msr_init_box(struct intel_uncore_box *box) +int intel_generic_uncore_msr_init_box(struct intel_uncore_box *box) { u64 box_ctl =3D intel_generic_uncore_box_ctl(box); =20 if (!box_ctl) - return; + return -ENODEV; =20 wrmsrq(box_ctl, GENERIC_PMON_BOX_CTL_INT); + return 0; } =20 void intel_generic_uncore_msr_disable_box(struct intel_uncore_box *box) @@ -578,15 +579,16 @@ static inline int intel_pci_uncore_box_ctl(struct int= el_uncore_box *box) return UNCORE_DISCOVERY_PCI_BOX_CTRL(intel_generic_uncore_box_ctl(box)); } =20 -void intel_generic_uncore_pci_init_box(struct intel_uncore_box *box) +int intel_generic_uncore_pci_init_box(struct intel_uncore_box *box) { int box_ctl =3D intel_pci_uncore_box_ctl(box); =20 if (!box_ctl) - return; + return -ENODEV; =20 __set_bit(UNCORE_BOX_FLAG_CTL_OFFS8, &box->flags); - pci_write_config_dword(box->pci_dev, box_ctl, GENERIC_PMON_BOX_CTL_INT); + return pci_write_config_dword(box->pci_dev, box_ctl, + GENERIC_PMON_BOX_CTL_INT); } =20 void intel_generic_uncore_pci_disable_box(struct intel_uncore_box *box) @@ -648,7 +650,7 @@ static struct intel_uncore_ops generic_uncore_pci_ops = =3D { =20 #define UNCORE_GENERIC_MMIO_SIZE 0x4000 =20 -void intel_generic_uncore_mmio_init_box(struct intel_uncore_box *box) +int intel_generic_uncore_mmio_init_box(struct intel_uncore_box *box) { static struct intel_uncore_discovery_unit *unit; struct intel_uncore_type *type =3D box->pmu->type; @@ -658,13 +660,13 @@ void intel_generic_uncore_mmio_init_box(struct intel_= uncore_box *box) if (!unit) { pr_warn("Uncore type %d id %d: Cannot find box control address.\n", type->type_id, box->pmu->pmu_idx); - return; + return -ENODEV; } =20 if (!unit->addr) { pr_warn("Uncore type %d box %d: Invalid box control address.\n", type->type_id, unit->id); - return; + return -ENODEV; } =20 addr =3D unit->addr; @@ -672,10 +674,11 @@ void intel_generic_uncore_mmio_init_box(struct intel_= uncore_box *box) if (!box->io_addr) { pr_warn("Uncore type %d box %d: ioremap error for 0x%llx.\n", type->type_id, unit->id, (unsigned long long)addr); - return; + return -ENOMEM; } =20 writel(GENERIC_PMON_BOX_CTL_INT, box->io_addr); + return 0; } =20 void intel_generic_uncore_mmio_disable_box(struct intel_uncore_box *box) diff --git a/arch/x86/events/intel/uncore_discovery.h b/arch/x86/events/int= el/uncore_discovery.h index e1330342b92e..142e1b56cfc2 100644 --- a/arch/x86/events/intel/uncore_discovery.h +++ b/arch/x86/events/intel/uncore_discovery.h @@ -148,11 +148,11 @@ void intel_uncore_generic_uncore_cpu_init(void); int intel_uncore_generic_uncore_pci_init(void); void intel_uncore_generic_uncore_mmio_init(void); =20 -void intel_generic_uncore_msr_init_box(struct intel_uncore_box *box); +int intel_generic_uncore_msr_init_box(struct intel_uncore_box *box); void intel_generic_uncore_msr_disable_box(struct intel_uncore_box *box); void intel_generic_uncore_msr_enable_box(struct intel_uncore_box *box); =20 -void intel_generic_uncore_mmio_init_box(struct intel_uncore_box *box); +int intel_generic_uncore_mmio_init_box(struct intel_uncore_box *box); void intel_generic_uncore_mmio_disable_box(struct intel_uncore_box *box); void intel_generic_uncore_mmio_enable_box(struct intel_uncore_box *box); void intel_generic_uncore_mmio_disable_event(struct intel_uncore_box *box, @@ -160,7 +160,7 @@ void intel_generic_uncore_mmio_disable_event(struct int= el_uncore_box *box, void intel_generic_uncore_mmio_enable_event(struct intel_uncore_box *box, struct perf_event *event); =20 -void intel_generic_uncore_pci_init_box(struct intel_uncore_box *box); +int intel_generic_uncore_pci_init_box(struct intel_uncore_box *box); void intel_generic_uncore_pci_disable_box(struct intel_uncore_box *box); void intel_generic_uncore_pci_enable_box(struct intel_uncore_box *box); void intel_generic_uncore_pci_disable_event(struct intel_uncore_box *box, diff --git a/arch/x86/events/intel/uncore_nhmex.c b/arch/x86/events/intel/u= ncore_nhmex.c index 8962e7cb21e3..7a6855281102 100644 --- a/arch/x86/events/intel/uncore_nhmex.c +++ b/arch/x86/events/intel/uncore_nhmex.c @@ -199,9 +199,10 @@ DEFINE_UNCORE_FORMAT_ATTR(counter, counter, "config:6-= 7"); DEFINE_UNCORE_FORMAT_ATTR(match, match, "config1:0-63"); DEFINE_UNCORE_FORMAT_ATTR(mask, mask, "config2:0-63"); =20 -static void nhmex_uncore_msr_init_box(struct intel_uncore_box *box) +static int nhmex_uncore_msr_init_box(struct intel_uncore_box *box) { wrmsrq(NHMEX_U_MSR_PMON_GLOBAL_CTL, NHMEX_U_PMON_GLOBAL_EN_ALL); + return 0; } =20 static void nhmex_uncore_msr_exit_box(struct intel_uncore_box *box) diff --git a/arch/x86/events/intel/uncore_snb.c b/arch/x86/events/intel/unc= ore_snb.c index edddd4f9ab5f..c5347920541c 100644 --- a/arch/x86/events/intel/uncore_snb.c +++ b/arch/x86/events/intel/uncore_snb.c @@ -295,12 +295,14 @@ static void snb_uncore_msr_disable_event(struct intel= _uncore_box *box, struct pe wrmsrq(event->hw.config_base, 0); } =20 -static void snb_uncore_msr_init_box(struct intel_uncore_box *box) +static int snb_uncore_msr_init_box(struct intel_uncore_box *box) { if (box->pmu->pmu_idx =3D=3D 0) { wrmsrq(SNB_UNC_PERF_GLOBAL_CTL, SNB_UNC_GLOBAL_CTL_EN | SNB_UNC_GLOBAL_CTL_CORE_ALL); } + + return 0; } =20 static void snb_uncore_msr_enable_box(struct intel_uncore_box *box) @@ -394,7 +396,7 @@ void snb_uncore_cpu_init(void) snb_uncore_cbox.num_boxes =3D topology_num_cores_per_package(); } =20 -static void skl_uncore_msr_init_box(struct intel_uncore_box *box) +static int skl_uncore_msr_init_box(struct intel_uncore_box *box) { if (box->pmu->pmu_idx =3D=3D 0) { wrmsrq(SKL_UNC_PERF_GLOBAL_CTL, @@ -404,6 +406,8 @@ static void skl_uncore_msr_init_box(struct intel_uncore= _box *box) /* The 8th CBOX has different MSR space */ if (box->pmu->pmu_idx =3D=3D 7) __set_bit(UNCORE_BOX_FLAG_CFL8_CBOX_MSR_OFFS, &box->flags); + + return 0; } =20 static void skl_uncore_msr_enable_box(struct intel_uncore_box *box) @@ -547,10 +551,12 @@ static struct intel_uncore_type *tgl_msr_uncores[] = =3D { NULL, }; =20 -static void rkl_uncore_msr_init_box(struct intel_uncore_box *box) +static int rkl_uncore_msr_init_box(struct intel_uncore_box *box) { if (box->pmu->pmu_idx =3D=3D 0) wrmsrq(SKL_UNC_PERF_GLOBAL_CTL, SNB_UNC_GLOBAL_CTL_EN); + + return 0; } =20 void tgl_uncore_cpu_init(void) @@ -707,9 +713,10 @@ static struct intel_uncore_type mtl_uncore_hac_cbox = =3D { .format_group =3D &adl_uncore_format_group, }; =20 -static void mtl_uncore_msr_init_box(struct intel_uncore_box *box) +static int mtl_uncore_msr_init_box(struct intel_uncore_box *box) { wrmsrq(uncore_msr_box_ctl(box), SNB_UNC_GLOBAL_CTL_EN); + return 0; } =20 static struct intel_uncore_ops mtl_uncore_msr_ops =3D { @@ -773,10 +780,12 @@ static struct intel_uncore_type *lnl_msr_uncores[] = =3D { =20 #define LNL_UNC_MSR_GLOBAL_CTL 0x240e =20 -static void lnl_uncore_msr_init_box(struct intel_uncore_box *box) +static int lnl_uncore_msr_init_box(struct intel_uncore_box *box) { if (box->pmu->pmu_idx =3D=3D 0) wrmsrq(LNL_UNC_MSR_GLOBAL_CTL, SNB_UNC_GLOBAL_CTL_EN); + + return 0; } =20 static struct intel_uncore_ops lnl_uncore_msr_ops =3D { @@ -874,7 +883,7 @@ static const struct attribute_group snb_uncore_imc_form= at_group =3D { .attrs =3D snb_uncore_imc_formats_attr, }; =20 -static void snb_uncore_imc_init_box(struct intel_uncore_box *box) +static int snb_uncore_imc_init_box(struct intel_uncore_box *box) { struct intel_uncore_type *type =3D box->pmu->type; struct pci_dev *pdev =3D box->pci_dev; @@ -893,10 +902,13 @@ static void snb_uncore_imc_init_box(struct intel_unco= re_box *box) addr &=3D ~(PAGE_SIZE - 1); =20 box->io_addr =3D ioremap(addr, type->mmio_map_size); - if (!box->io_addr) + if (!box->io_addr) { pr_warn("perf uncore: Failed to ioremap for %s.\n", type->name); + return -ENOMEM; + } =20 box->hrtimer_duration =3D UNCORE_SNB_IMC_HRTIMER_INTERVAL; + return 0; } =20 static void snb_uncore_imc_enable_box(struct intel_uncore_box *box) @@ -1532,7 +1544,7 @@ static struct pci_dev *tgl_uncore_get_mc_dev(void) #define TGL_UNCORE_MMIO_IMC_MEM_OFFSET 0x10000 #define TGL_UNCORE_PCI_IMC_MAP_SIZE 0xe000 =20 -static void +static int uncore_get_box_mmio_addr(struct intel_uncore_box *box, unsigned int base_offset, int bar_offset, int step) @@ -1541,19 +1553,20 @@ uncore_get_box_mmio_addr(struct intel_uncore_box *b= ox, struct intel_uncore_pmu *pmu =3D box->pmu; struct intel_uncore_type *type =3D pmu->type; resource_size_t addr; + int ret =3D 0; u32 bar; =20 if (!pdev) { pr_warn("perf uncore: Cannot find matched IMC device.\n"); - return; + return -ENODEV; } =20 pci_read_config_dword(pdev, bar_offset, &bar); if (!(bar & BIT(0))) { pr_warn("perf uncore: BAR 0x%x is disabled. Failed to map %s counters.\n= ", bar_offset, type->name); - pci_dev_put(pdev); - return; + ret =3D -ENODEV; + goto out; } bar &=3D ~BIT(0); addr =3D (resource_size_t)(bar + step * pmu->pmu_idx); @@ -1565,23 +1578,26 @@ uncore_get_box_mmio_addr(struct intel_uncore_box *b= ox, =20 addr +=3D base_offset; box->io_addr =3D ioremap(addr, type->mmio_map_size); - if (!box->io_addr) + if (!box->io_addr) { + ret =3D -ENOMEM; pr_warn("perf uncore: Failed to ioremap for %s.\n", type->name); - + } +out: pci_dev_put(pdev); + return ret; } =20 -static void __uncore_imc_init_box(struct intel_uncore_box *box, +static int __uncore_imc_init_box(struct intel_uncore_box *box, unsigned int base_offset) { - uncore_get_box_mmio_addr(box, base_offset, + return uncore_get_box_mmio_addr(box, base_offset, SNB_UNCORE_PCI_IMC_BAR_OFFSET, TGL_UNCORE_MMIO_IMC_MEM_OFFSET); } =20 -static void tgl_uncore_imc_freerunning_init_box(struct intel_uncore_box *b= ox) +static int tgl_uncore_imc_freerunning_init_box(struct intel_uncore_box *bo= x) { - __uncore_imc_init_box(box, 0); + return __uncore_imc_init_box(box, 0); } =20 static struct intel_uncore_ops tgl_uncore_imc_freerunning_ops =3D { @@ -1648,13 +1664,15 @@ void tgl_uncore_mmio_init(void) #define ADL_UNCORE_IMC_CTL_INT (ADL_UNCORE_IMC_CTL_RST_CTRL | \ ADL_UNCORE_IMC_CTL_RST_CTRS) =20 -static void adl_uncore_imc_init_box(struct intel_uncore_box *box) +static int adl_uncore_imc_init_box(struct intel_uncore_box *box) { - __uncore_imc_init_box(box, ADL_UNCORE_IMC_BASE); + int ret =3D __uncore_imc_init_box(box, ADL_UNCORE_IMC_BASE); =20 /* The global control in MC1 can control both MCs. */ - if (box->io_addr && (box->pmu->pmu_idx =3D=3D 1)) + if (!ret && (box->pmu->pmu_idx =3D=3D 1)) writel(ADL_UNCORE_IMC_CTL_INT, box->io_addr + ADL_UNCORE_IMC_GLOBAL_CTL); + + return ret; } =20 static void adl_uncore_mmio_disable_box(struct intel_uncore_box *box) @@ -1731,9 +1749,9 @@ static struct freerunning_counters adl_uncore_imc_fre= erunning[] =3D { [ADL_MMIO_UNCORE_IMC_DATA_WRITE] =3D { 0xA0, 0x0, 0x0, 1, 64 }, }; =20 -static void adl_uncore_imc_freerunning_init_box(struct intel_uncore_box *b= ox) +static int adl_uncore_imc_freerunning_init_box(struct intel_uncore_box *bo= x) { - __uncore_imc_init_box(box, ADL_UNCORE_IMC_FREERUNNING_BASE); + return __uncore_imc_init_box(box, ADL_UNCORE_IMC_FREERUNNING_BASE); } =20 static struct intel_uncore_ops adl_uncore_imc_freerunning_ops =3D { @@ -1803,9 +1821,9 @@ static const struct attribute_group lnl_uncore_format= _group =3D { .attrs =3D lnl_uncore_formats_attr, }; =20 -static void lnl_uncore_hbo_init_box(struct intel_uncore_box *box) +static int lnl_uncore_hbo_init_box(struct intel_uncore_box *box) { - uncore_get_box_mmio_addr(box, LNL_UNCORE_HBO_BASE, + return uncore_get_box_mmio_addr(box, LNL_UNCORE_HBO_BASE, LNL_UNCORE_PCI_SAFBAR_OFFSET, LNL_UNCORE_HBO_OFFSET); } @@ -1829,14 +1847,16 @@ static struct intel_uncore_type lnl_uncore_hbo =3D { .format_group =3D &lnl_uncore_format_group, }; =20 -static void lnl_uncore_sncu_init_box(struct intel_uncore_box *box) +static int lnl_uncore_sncu_init_box(struct intel_uncore_box *box) { - uncore_get_box_mmio_addr(box, LNL_UNCORE_SNCU_BASE, + int ret =3D uncore_get_box_mmio_addr(box, LNL_UNCORE_SNCU_BASE, LNL_UNCORE_PCI_SAFBAR_OFFSET, 0); =20 - if (box->io_addr) + if (!ret) writel(ADL_UNCORE_IMC_CTL_INT, box->io_addr + LNL_UNCORE_GLOBAL_CTL); + + return ret; } =20 static struct intel_uncore_ops lnl_uncore_sncu_ops =3D { @@ -1887,13 +1907,15 @@ static struct intel_uncore_type ptl_uncore_imc =3D { .mmio_map_size =3D 0xf00, }; =20 -static void ptl_uncore_sncu_init_box(struct intel_uncore_box *box) +static int ptl_uncore_sncu_init_box(struct intel_uncore_box *box) { - intel_generic_uncore_mmio_init_box(box); + int ret =3D intel_generic_uncore_mmio_init_box(box); =20 /* Clear the global freeze bit */ if (box->io_addr) writel(0, box->io_addr + PTL_UNCORE_GLOBAL_CTL_OFFSET); + + return ret; } =20 static struct intel_uncore_ops ptl_uncore_sncu_ops =3D { diff --git a/arch/x86/events/intel/uncore_snbep.c b/arch/x86/events/intel/u= ncore_snbep.c index 334dc384b5b9..a97cd029db36 100644 --- a/arch/x86/events/intel/uncore_snbep.c +++ b/arch/x86/events/intel/uncore_snbep.c @@ -627,12 +627,12 @@ static u64 snbep_uncore_pci_read_counter(struct intel= _uncore_box *box, struct pe return count; } =20 -static void snbep_uncore_pci_init_box(struct intel_uncore_box *box) +static int snbep_uncore_pci_init_box(struct intel_uncore_box *box) { struct pci_dev *pdev =3D box->pci_dev; int box_ctl =3D uncore_pci_box_ctl(box); =20 - pci_write_config_dword(pdev, box_ctl, SNBEP_PMON_BOX_CTL_INT); + return pci_write_config_dword(pdev, box_ctl, SNBEP_PMON_BOX_CTL_INT); } =20 static void snbep_uncore_msr_disable_box(struct intel_uncore_box *box) @@ -680,12 +680,14 @@ static void snbep_uncore_msr_disable_event(struct int= el_uncore_box *box, wrmsrq(hwc->config_base, hwc->config); } =20 -static void snbep_uncore_msr_init_box(struct intel_uncore_box *box) +static int snbep_uncore_msr_init_box(struct intel_uncore_box *box) { unsigned msr =3D uncore_msr_box_ctl(box); =20 if (msr) wrmsrq(msr, SNBEP_PMON_BOX_CTL_INT); + + return 0; } =20 static struct attribute *snbep_uncore_formats_attr[] =3D { @@ -1507,18 +1509,21 @@ int snbep_uncore_pci_init(void) /* end of Sandy Bridge-EP uncore support */ =20 /* IvyTown uncore support */ -static void ivbep_uncore_msr_init_box(struct intel_uncore_box *box) +static int ivbep_uncore_msr_init_box(struct intel_uncore_box *box) { unsigned msr =3D uncore_msr_box_ctl(box); if (msr) wrmsrq(msr, IVBEP_PMON_BOX_CTL_INT); + + return 0; } =20 -static void ivbep_uncore_pci_init_box(struct intel_uncore_box *box) +static int ivbep_uncore_pci_init_box(struct intel_uncore_box *box) { struct pci_dev *pdev =3D box->pci_dev; =20 - pci_write_config_dword(pdev, SNBEP_PCI_PMON_BOX_CTL, IVBEP_PMON_BOX_CTL_I= NT); + return pci_write_config_dword(pdev, SNBEP_PCI_PMON_BOX_CTL, + IVBEP_PMON_BOX_CTL_INT); } =20 #define IVBEP_UNCORE_MSR_OPS_COMMON_INIT() \ @@ -2784,7 +2789,7 @@ static struct intel_uncore_type hswep_uncore_cbox =3D= { /* * Write SBOX Initialization register bit by bit to avoid spurious #GPs */ -static void hswep_uncore_sbox_msr_init_box(struct intel_uncore_box *box) +static int hswep_uncore_sbox_msr_init_box(struct intel_uncore_box *box) { unsigned msr =3D uncore_msr_box_ctl(box); =20 @@ -2798,6 +2803,8 @@ static void hswep_uncore_sbox_msr_init_box(struct int= el_uncore_box *box) wrmsrq(msr, flags); } } + + return 0; } =20 static struct intel_uncore_ops hswep_uncore_sbox_msr_ops =3D { @@ -4162,12 +4169,13 @@ static const struct attribute_group skx_upi_uncore_= format_group =3D { .attrs =3D skx_upi_uncore_formats_attr, }; =20 -static void skx_upi_uncore_pci_init_box(struct intel_uncore_box *box) +static int skx_upi_uncore_pci_init_box(struct intel_uncore_box *box) { struct pci_dev *pdev =3D box->pci_dev; =20 __set_bit(UNCORE_BOX_FLAG_CTL_OFFS8, &box->flags); - pci_write_config_dword(pdev, SKX_UPI_PCI_PMON_BOX_CTL, IVBEP_PMON_BOX_CTL= _INT); + return pci_write_config_dword(pdev, SKX_UPI_PCI_PMON_BOX_CTL, + IVBEP_PMON_BOX_CTL_INT); } =20 static struct intel_uncore_ops skx_upi_uncore_pci_ops =3D { @@ -4323,12 +4331,13 @@ static struct intel_uncore_type skx_uncore_upi =3D { .cleanup_mapping =3D skx_upi_cleanup_mapping, }; =20 -static void skx_m2m_uncore_pci_init_box(struct intel_uncore_box *box) +static int skx_m2m_uncore_pci_init_box(struct intel_uncore_box *box) { struct pci_dev *pdev =3D box->pci_dev; =20 __set_bit(UNCORE_BOX_FLAG_CTL_OFFS8, &box->flags); - pci_write_config_dword(pdev, SKX_M2M_PCI_PMON_BOX_CTL, IVBEP_PMON_BOX_CTL= _INT); + return pci_write_config_dword(pdev, SKX_M2M_PCI_PMON_BOX_CTL, + IVBEP_PMON_BOX_CTL_INT); } =20 static struct intel_uncore_ops skx_m2m_uncore_pci_ops =3D { @@ -4831,13 +4840,13 @@ void snr_uncore_cpu_init(void) uncore_msr_uncores =3D snr_msr_uncores; } =20 -static void snr_m2m_uncore_pci_init_box(struct intel_uncore_box *box) +static int snr_m2m_uncore_pci_init_box(struct intel_uncore_box *box) { struct pci_dev *pdev =3D box->pci_dev; int box_ctl =3D uncore_pci_box_ctl(box); =20 __set_bit(UNCORE_BOX_FLAG_CTL_OFFS8, &box->flags); - pci_write_config_dword(pdev, box_ctl, IVBEP_PMON_BOX_CTL_INT); + return pci_write_config_dword(pdev, box_ctl, IVBEP_PMON_BOX_CTL_INT); } =20 static struct intel_uncore_ops snr_m2m_uncore_pci_ops =3D { @@ -5010,17 +5019,22 @@ static int snr_uncore_mmio_map(struct intel_uncore_= box *box, return 0; } =20 -static void __snr_uncore_mmio_init_box(struct intel_uncore_box *box, +static int __snr_uncore_mmio_init_box(struct intel_uncore_box *box, unsigned int box_ctl, int mem_offset, unsigned int device) { - if (!snr_uncore_mmio_map(box, box_ctl, mem_offset, device)) + int ret; + + ret =3D snr_uncore_mmio_map(box, box_ctl, mem_offset, device); + if (!ret) writel(IVBEP_PMON_BOX_CTL_INT, box->io_addr); + + return ret; } =20 -static void snr_uncore_mmio_init_box(struct intel_uncore_box *box) +static int snr_uncore_mmio_init_box(struct intel_uncore_box *box) { - __snr_uncore_mmio_init_box(box, uncore_mmio_box_ctl(box), + return __snr_uncore_mmio_init_box(box, uncore_mmio_box_ctl(box), SNR_IMC_MMIO_MEM0_OFFSET, SNR_MC_DEVICE_ID); } @@ -5637,14 +5651,14 @@ int icx_uncore_pci_init(void) return 0; } =20 -static void icx_uncore_imc_init_box(struct intel_uncore_box *box) +static int icx_uncore_imc_init_box(struct intel_uncore_box *box) { unsigned int box_ctl =3D box->pmu->type->box_ctl + box->pmu->type->mmio_offset * (box->pmu->pmu_idx % ICX_NUMBER_IM= C_CHN); int mem_offset =3D (box->pmu->pmu_idx / ICX_NUMBER_IMC_CHN) * ICX_IMC_MEM= _STRIDE + SNR_IMC_MMIO_MEM0_OFFSET; =20 - __snr_uncore_mmio_init_box(box, box_ctl, mem_offset, + return __snr_uncore_mmio_init_box(box, box_ctl, mem_offset, SNR_MC_DEVICE_ID); } =20 @@ -5701,12 +5715,12 @@ static struct uncore_event_desc icx_uncore_imc_free= running_events[] =3D { { /* end: all zeroes */ }, }; =20 -static void icx_uncore_imc_freerunning_init_box(struct intel_uncore_box *b= ox) +static int icx_uncore_imc_freerunning_init_box(struct intel_uncore_box *bo= x) { int mem_offset =3D box->pmu->pmu_idx * ICX_IMC_MEM_STRIDE + SNR_IMC_MMIO_MEM0_OFFSET; =20 - snr_uncore_mmio_map(box, uncore_mmio_box_ctl(box), + return snr_uncore_mmio_map(box, uncore_mmio_box_ctl(box), mem_offset, SNR_MC_DEVICE_ID); } =20 @@ -6003,10 +6017,10 @@ static struct intel_uncore_type spr_uncore_mdf =3D { .name =3D "mdf", }; =20 -static void spr_uncore_mmio_offs8_init_box(struct intel_uncore_box *box) +static int spr_uncore_mmio_offs8_init_box(struct intel_uncore_box *box) { __set_bit(UNCORE_BOX_FLAG_CTL_OFFS8, &box->flags); - intel_generic_uncore_mmio_init_box(box); + return intel_generic_uncore_mmio_init_box(box); } =20 static struct intel_uncore_ops spr_uncore_mmio_offs8_ops =3D { @@ -6187,12 +6201,11 @@ static struct uncore_event_desc spr_uncore_imc_free= running_events[] =3D { =20 #define SPR_MC_DEVICE_ID 0x3251 =20 -static void spr_uncore_imc_freerunning_init_box(struct intel_uncore_box *b= ox) +static int spr_uncore_imc_freerunning_init_box(struct intel_uncore_box *bo= x) { int mem_offset =3D box->pmu->pmu_idx * ICX_IMC_MEM_STRIDE + SNR_IMC_MMIO_= MEM0_OFFSET; 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a="81994979" X-IronPort-AV: E=Sophos;i="6.24,199,1774335600"; d="scan'208";a="81994979" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Jun 2026 09:09:36 -0700 X-CSE-ConnectionGUID: FfNkKHtUQD6N6e82v7IN2A== X-CSE-MsgGUID: 8YsHfld9RxWStxUbN/298Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,199,1774335600"; d="scan'208";a="246403598" Received: from 9cc2c43eec6b.jf.intel.com ([10.54.77.29]) by orviesa008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Jun 2026 09:09:36 -0700 From: Zide Chen To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , Adrian Hunter , Alexander Shishkin , Andi Kleen , Eranian Stephane Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Dapeng Mi , Zide Chen Subject: [PATCH V3 4/8] perf/x86/intel/uncore: Keep PCI PMUs working when MMIO/MSR setup fails Date: Thu, 11 Jun 2026 09:00:29 -0700 Message-ID: <20260611160033.66760-5-zide.chen@intel.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260611160033.66760-1-zide.chen@intel.com> References: <20260611160033.66760-1-zide.chen@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" uncore_event_cpu_online() returns -ENOMEM early when both the MSR and MMIO box allocations fail. This also aborts PCI uncore setup, even though PCI PMUs are independent of the MSR/MMIO paths. Remove the early return so PCI uncore setup always runs regardless of whether MSR or MMIO box allocation succeeds. Fixes: 3da04b8a00dd ("perf/x86/intel/uncore: Support MMIO type uncore block= s") Reviewed-by: Ian Rogers Reviewed-by: Dapeng Mi Signed-off-by: Zide Chen --- v3: Add Reviewed-by tag. --- arch/x86/events/intel/uncore.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/x86/events/intel/uncore.c b/arch/x86/events/intel/uncore.c index 21c8ed1628cb..eae335df7634 100644 --- a/arch/x86/events/intel/uncore.c +++ b/arch/x86/events/intel/uncore.c @@ -1636,8 +1636,6 @@ static int uncore_event_cpu_online(unsigned int cpu) die =3D topology_logical_die_id(cpu); msr_ret =3D uncore_box_ref(uncore_msr_uncores, die, cpu); mmio_ret =3D uncore_box_ref(uncore_mmio_uncores, die, cpu); - if (msr_ret && mmio_ret) - return -ENOMEM; =20 /* * Check if there is an online cpu in the package --=20 2.54.0 From nobody Fri Jun 12 20:17:38 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CDEE441C31D; Thu, 11 Jun 2026 16:09:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.19 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781194181; cv=none; b=gvIT6bEcSDEe3AF20F/rMTNp75ri5UHrj1y6Ae1tkO6yW6EgWVHPJr+ateS3bVi8JLxYxCCfkz1IpUJLQM/0Gd9UHr3ojDU3HUA8plms7QfRZyhDlcu5PDzCZ87Mecqvoc6Mh5UuA8bBG5x4ncyLVIwBbOfiK+fQ1IF99HX12Yw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781194181; c=relaxed/simple; bh=on08egIOAIUyCSOrqKSgoOplMCXk0tbeTuaN1e++TjA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=uwEosx4qn/IS5pjC4fnqo6JkEyPcCOW7v2AP6TNvxHb7jq8x6DRnLZkWsB5AeobFfbamoQATEXz5SOVJlWMubTyIG47b4IHHM1Mn8sZuL9Cl70RspgQCpNCrx7kuzNxWCetfVnciUKntJjteV2KcyDNtsW6n6sUdI1gLPRRXAFU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Fe4lcpnS; arc=none smtp.client-ip=198.175.65.19 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Fe4lcpnS" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1781194180; x=1812730180; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=on08egIOAIUyCSOrqKSgoOplMCXk0tbeTuaN1e++TjA=; b=Fe4lcpnSlhwligsYmkjQjzpDHhpL0cksRppjbZbtfDrdWQMKhpEpZxC+ G6xUgI1UYsFpwCbdOk7PhSpaucBieAHX2bFtOEbuyvIepsdDsYBpEUYx6 F9SyeXoGD7Vm2e4vDrcuIIZ+yAywvj+ZVh9QheHbXYRdmW4oJSrTUYy4W wN6aJhZMVBqrd1F7Ncg3DwsicS5EevNS7D0KRAonrBt4GNHENfEgvxxhG +h90NsXY05u7pP7apF9TLkHlrJy75oZ3MFQGzd1sbf5Ka2Y87MV2rbCi/ BHc8ofc3Qnr9xbiGx3Acjkqs94j5DD9fraKWN9zntqiKBpDW7MfEFUHmW Q==; X-CSE-ConnectionGUID: eMGIE1obQGem0ryMkfMoXg== X-CSE-MsgGUID: 2JkGXLJGQy6xeYJ03pRyMA== X-IronPort-AV: E=McAfee;i="6800,10657,11813"; a="81994984" X-IronPort-AV: E=Sophos;i="6.24,199,1774335600"; d="scan'208";a="81994984" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Jun 2026 09:09:36 -0700 X-CSE-ConnectionGUID: NBWOECADRSy3h2yTKolROw== X-CSE-MsgGUID: 1A3tmy05SAiautpBduHF0w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,199,1774335600"; d="scan'208";a="246403601" Received: from 9cc2c43eec6b.jf.intel.com ([10.54.77.29]) by orviesa008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Jun 2026 09:09:36 -0700 From: Zide Chen To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , Adrian Hunter , Alexander Shishkin , Andi Kleen , Eranian Stephane Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Dapeng Mi , Zide Chen Subject: [PATCH V3 5/8] perf/x86/intel/uncore: Factor out box setup code Date: Thu, 11 Jun 2026 09:00:30 -0700 Message-ID: <20260611160033.66760-6-zide.chen@intel.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260611160033.66760-1-zide.chen@intel.com> References: <20260611160033.66760-1-zide.chen@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The PCI uncore PMU path already implements a lazy registration model: the PMU is registered when the first active box appears and unregistered when the last active box is removed. Factor this registration management into a shared helper, so the same code can be reused by the MSR and MMIO paths in later changes. No functional change intended. Reviewed-by: Ian Rogers Reviewed-by: Dapeng Mi Signed-off-by: Zide Chen --- v3: Add Reviewed-by tag. --- arch/x86/events/intel/uncore.c | 40 ++++++++++++++++++++++++---------- 1 file changed, 28 insertions(+), 12 deletions(-) diff --git a/arch/x86/events/intel/uncore.c b/arch/x86/events/intel/uncore.c index eae335df7634..06ef89f6ccc2 100644 --- a/arch/x86/events/intel/uncore.c +++ b/arch/x86/events/intel/uncore.c @@ -1148,6 +1148,29 @@ uncore_pci_find_dev_pmu(struct pci_dev *pdev, const = struct pci_device_id *ids) return pmu; } =20 +static int uncore_box_setup(struct intel_uncore_pmu *pmu, + struct intel_uncore_box *box) +{ + int ret; + + uncore_box_init(box); + + /* First active box registers the pmu. */ + if (atomic_inc_return(&pmu->activeboxes) > 1) + return 0; + + ret =3D uncore_pmu_register(pmu); + if (ret) { + atomic_dec(&pmu->activeboxes); + goto err; + } + + return 0; +err: + uncore_box_exit(box); + return ret; +} + /* * Register the PMU for a PCI device * @pdev: The PCI device. @@ -1174,20 +1197,13 @@ static int uncore_pci_pmu_register(struct pci_dev *= pdev, box->dieid =3D die; box->pci_dev =3D pdev; box->pmu =3D pmu; - uncore_box_init(box); =20 - pmu->boxes[die] =3D box; - if (atomic_inc_return(&pmu->activeboxes) > 1) - return 0; - - /* First active box registers the pmu */ - ret =3D uncore_pmu_register(pmu); - if (ret) { - atomic_dec(&pmu->activeboxes); - pmu->boxes[die] =3D NULL; - uncore_box_exit(box); + ret =3D uncore_box_setup(pmu, box); + if (!ret) + pmu->boxes[die] =3D box; + else kfree(box); - } + return ret; } =20 --=20 2.54.0 From nobody Fri Jun 12 20:17:38 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CDCAB41C31B; Thu, 11 Jun 2026 16:09:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.19 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781194181; cv=none; b=koaDFhukjZgouln+yXdmix+rtG9vjrXYq/cFXRdrHwK2+Lf56M0fqgjio2KfpGbF+XiLvevYCuN2J4k4UQN1rVTuZdGvjudNNJgpPmX1/1WsPUwd1kGv0XcA61mwudLy0vnLWM5Uj924Se5tslPRPM6pRLgq54R9c/Mp46+gWLo= ARC-Message-Signature: i=1; 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d="scan'208";a="246403604" Received: from 9cc2c43eec6b.jf.intel.com ([10.54.77.29]) by orviesa008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Jun 2026 09:09:36 -0700 From: Zide Chen To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , Adrian Hunter , Alexander Shishkin , Andi Kleen , Eranian Stephane Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Dapeng Mi , Zide Chen Subject: [PATCH V3 6/8] perf/x86/intel/uncore: Introduce PMU flags and broken state Date: Thu, 11 Jun 2026 09:00:31 -0700 Message-ID: <20260611160033.66760-7-zide.chen@intel.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260611160033.66760-1-zide.chen@intel.com> References: <20260611160033.66760-1-zide.chen@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Replace the boolean 'registered' field in intel_uncore_pmu with an unsigned long 'flags' field, and add a PMU_BROKEN flag to track box setup failures. The broken flag is sticky, meaning it is cleared only by a module reload or system reboot. Broken PMUs are skipped in the CPU hotplug and box allocation paths. When any box fails to initialize, the PMU is marked broken. Broken PMUs reject new event assignments and skip future box setup attempts. If the PMU was already registered, it remains so to avoid disrupting in-flight events on other boxes. Signed-off-by: Zide Chen --- v3: - Fix typo stick->sticky and other cosmetic fixes in code comment. v2: - Make the broken flag sticky by using clear_bit() in uncore_pmu_unregister() rather than zeroing out pmu->flags. - In uncore_change_type_ctx(), don't stop CPU migration on broken PMU for in-flight events. (Sashiko). - Use box->cpu =3D=3D -1 to identify inactive boxes that don't need migration, no need to check uncore_die_has_box(), which is incomplete. --- arch/x86/events/intel/uncore.c | 44 ++++++++++++++++++++++-------- arch/x86/events/intel/uncore.h | 13 ++++++++- arch/x86/events/intel/uncore_snb.c | 2 +- 3 files changed, 46 insertions(+), 13 deletions(-) diff --git a/arch/x86/events/intel/uncore.c b/arch/x86/events/intel/uncore.c index 06ef89f6ccc2..feb8c3b0076b 100644 --- a/arch/x86/events/intel/uncore.c +++ b/arch/x86/events/intel/uncore.c @@ -757,7 +757,7 @@ static int uncore_pmu_event_init(struct perf_event *eve= nt) =20 pmu =3D uncore_event_to_pmu(event); /* no device found for this pmu */ - if (!pmu->registered) + if (!uncore_pmu_available(pmu)) return -ENOENT; =20 /* Sampling not supported yet */ @@ -953,16 +953,18 @@ static int uncore_pmu_register(struct intel_uncore_pm= u *pmu) =20 ret =3D perf_pmu_register(&pmu->pmu, pmu->name, -1); if (!ret) - pmu->registered =3D true; + uncore_pmu_set_registered(pmu); return ret; } =20 static void uncore_pmu_unregister(struct intel_uncore_pmu *pmu) { - if (!pmu->registered) + if (!uncore_pmu_registered(pmu)) return; perf_pmu_unregister(&pmu->pmu); - pmu->registered =3D false; + + /* Keep PMU_BROKEN_BIT sticky. */ + uncore_pmu_clear_registered(pmu); } =20 static void uncore_free_boxes(struct intel_uncore_pmu *pmu) @@ -1153,7 +1155,12 @@ static int uncore_box_setup(struct intel_uncore_pmu = *pmu, { int ret; =20 - uncore_box_init(box); + if (uncore_pmu_broken(pmu)) + return -ENODEV; + + ret =3D uncore_box_init(box); + if (ret) + goto err; =20 /* First active box registers the pmu. */ if (atomic_inc_return(&pmu->activeboxes) > 1) @@ -1167,6 +1174,16 @@ static int uncore_box_setup(struct intel_uncore_pmu = *pmu, =20 return 0; err: + /* + * If any box fails, mark the per-package PMU as broken regardless of + * whether it was registered or not. + * + * Don't decrement refcnt to avoid other in-die CPUs from trying to set + * up the PMU box again. + * + * Don't kfree box; MSR and MMIO boxes are freed at module exit only. + */ + uncore_pmu_set_broken(pmu); uncore_box_exit(box); return ret; } @@ -1190,8 +1207,10 @@ static int uncore_pci_pmu_register(struct pci_dev *p= dev, return -EINVAL; =20 box =3D uncore_alloc_box(type, NUMA_NO_NODE); - if (!box) + if (!box) { + uncore_pmu_set_broken(pmu); return -ENOMEM; + } =20 atomic_inc(&box->refcnt); box->dieid =3D die; @@ -1507,7 +1526,8 @@ static void uncore_change_type_ctx(struct intel_uncor= e_type *type, int old_cpu, =20 if (old_cpu < 0) { WARN_ON_ONCE(box->cpu !=3D -1); - if (uncore_die_has_box(type, die, pmu->pmu_idx)) { + if (uncore_die_has_box(type, die, pmu->pmu_idx) && + !uncore_pmu_broken(pmu)) { box->cpu =3D new_cpu; cpumask_set_cpu(new_cpu, &pmu->cpu_mask); } @@ -1515,12 +1535,14 @@ static void uncore_change_type_ctx(struct intel_unc= ore_type *type, int old_cpu, } =20 WARN_ON_ONCE(box->cpu !=3D -1 && box->cpu !=3D old_cpu); - box->cpu =3D -1; cpumask_clear_cpu(old_cpu, &pmu->cpu_mask); - if (new_cpu < 0) + if (new_cpu < 0) { + box->cpu =3D -1; continue; + } =20 - if (!uncore_die_has_box(type, die, pmu->pmu_idx)) + /* An inactive box doesn't need migration. */ + if (box->cpu =3D=3D -1) continue; uncore_pmu_cancel_hrtimer(box); perf_pmu_migrate_context(&pmu->pmu, old_cpu, new_cpu); @@ -1596,7 +1618,7 @@ static int allocate_boxes(struct intel_uncore_type **= types, type =3D *types; pmu =3D type->pmus; for (i =3D 0; i < type->num_boxes; i++, pmu++) { - if (pmu->boxes[die]) + if (pmu->boxes[die] || uncore_pmu_broken(pmu)) continue; box =3D uncore_alloc_box(type, cpu_to_node(cpu)); if (!box) diff --git a/arch/x86/events/intel/uncore.h b/arch/x86/events/intel/uncore.h index d732b87be0a9..0adb477d9708 100644 --- a/arch/x86/events/intel/uncore.h +++ b/arch/x86/events/intel/uncore.h @@ -146,13 +146,24 @@ struct intel_uncore_pmu { struct pmu pmu; char name[UNCORE_PMU_NAME_LEN]; int pmu_idx; - bool registered; + unsigned long flags; atomic_t activeboxes; cpumask_t cpu_mask; struct intel_uncore_type *type; struct intel_uncore_box **boxes; }; =20 +#define PMU_REGISTERED_BIT 0 +#define PMU_BROKEN_BIT 1 + +#define uncore_pmu_registered(pmu) test_bit(PMU_REGISTERED_BIT, &(pmu)->fl= ags) +#define uncore_pmu_broken(pmu) test_bit(PMU_BROKEN_BIT, &(pmu)->flags) +#define uncore_pmu_available(pmu) (uncore_pmu_registered(pmu) && \ + !uncore_pmu_broken(pmu)) +#define uncore_pmu_set_registered(pmu) set_bit(PMU_REGISTERED_BIT, &(pmu)-= >flags) +#define uncore_pmu_set_broken(pmu) set_bit(PMU_BROKEN_BIT, &(pmu)->flags) +#define uncore_pmu_clear_registered(pmu) clear_bit(PMU_REGISTERED_BIT, &(p= mu)->flags) + struct intel_uncore_extra_reg { raw_spinlock_t lock; u64 config, config1, config2; diff --git a/arch/x86/events/intel/uncore_snb.c b/arch/x86/events/intel/unc= ore_snb.c index c5347920541c..055131c508ff 100644 --- a/arch/x86/events/intel/uncore_snb.c +++ b/arch/x86/events/intel/uncore_snb.c @@ -940,7 +940,7 @@ static int snb_uncore_imc_event_init(struct perf_event = *event) =20 pmu =3D uncore_event_to_pmu(event); /* no device found for this pmu */ - if (!pmu->registered) + if (!uncore_pmu_available(pmu)) return -ENOENT; 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X-CSE-ConnectionGUID: mTP+hF+UQmWjgZvmrMf1+Q== X-CSE-MsgGUID: TJfzZppmSUed+XoqdHdIaw== X-IronPort-AV: E=McAfee;i="6800,10657,11813"; a="81994995" X-IronPort-AV: E=Sophos;i="6.24,199,1774335600"; d="scan'208";a="81994995" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Jun 2026 09:09:37 -0700 X-CSE-ConnectionGUID: LjtzhPyEQ9mawAd/sI5Uhw== X-CSE-MsgGUID: q0ugtt6BQI6mVxWUsVyuIw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,199,1774335600"; d="scan'208";a="246403606" Received: from 9cc2c43eec6b.jf.intel.com ([10.54.77.29]) by orviesa008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Jun 2026 09:09:36 -0700 From: Zide Chen To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , Adrian Hunter , Alexander Shishkin , Andi Kleen , Eranian Stephane Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Dapeng Mi , Zide Chen Subject: [PATCH V3 7/8] perf/x86/intel/uncore: Fix uncore_box ref/unref ordering Date: Thu, 11 Jun 2026 09:00:32 -0700 Message-ID: <20260611160033.66760-8-zide.chen@intel.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260611160033.66760-1-zide.chen@intel.com> References: <20260611160033.66760-1-zide.chen@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In uncore_event_cpu_online(), uncore_box_ref() was called before uncore_change_context(). uncore_box_ref() gates on box->cpu >=3D 0, but box->cpu is still -1 at that point because uncore_change_context() has not run yet. As a result, the box is never initialized on the first CPU to come online in a die, leaving it permanently uninitialized in the single-CPU-per-die case. Thus, box->refcnt is one count below the true value, and in the CPU offline path, the box will be torn down on the second-to-last CPU. In uncore_event_cpu_offline(), uncore_box_unref() was called after uncore_change_context(), so box->cpu is already -1 when the collector CPU goes offline, which prevents it from tearing down the box. Fix by swapping the call order in both paths so that uncore_box_{ref,unref}() runs at the point where box->cpu reflects the correct context. Move allocate_boxes() out of uncore_box_ref() to enable this reordering. Fixes: c74443d92f68 ("perf/x86/uncore: Support per PMU cpumask") Reviewed-by: Ian Rogers Signed-off-by: Zide Chen --- v3: - Update changelog to mention moving allocate_boxes(). (Dapeng) - Update title; the bug is not limited to CPU hotplug. --- arch/x86/events/intel/uncore.c | 50 ++++++++++++++++------------------ 1 file changed, 23 insertions(+), 27 deletions(-) diff --git a/arch/x86/events/intel/uncore.c b/arch/x86/events/intel/uncore.c index feb8c3b0076b..b9ac2f7d31ca 100644 --- a/arch/x86/events/intel/uncore.c +++ b/arch/x86/events/intel/uncore.c @@ -1580,9 +1580,15 @@ static int uncore_event_cpu_offline(unsigned int cpu) { int die, target; =20 + /* Clear the references */ + die =3D topology_logical_die_id(cpu); + uncore_box_unref(uncore_msr_uncores, die); + uncore_box_unref(uncore_mmio_uncores, die); + /* Check if exiting cpu is used for collecting uncore events */ if (!cpumask_test_and_clear_cpu(cpu, &uncore_cpu_mask)) - goto unref; + return 0; + /* Find a new cpu to collect uncore events */ target =3D cpumask_any_but(topology_die_cpumask(cpu), cpu); =20 @@ -1595,16 +1601,10 @@ static int uncore_event_cpu_offline(unsigned int cp= u) uncore_change_context(uncore_msr_uncores, cpu, target); uncore_change_context(uncore_mmio_uncores, cpu, target); uncore_change_context(uncore_pci_uncores, cpu, target); - -unref: - /* Clear the references */ - die =3D topology_logical_die_id(cpu); - uncore_box_unref(uncore_msr_uncores, die); - uncore_box_unref(uncore_mmio_uncores, die); return 0; } =20 -static int allocate_boxes(struct intel_uncore_type **types, +static void allocate_boxes(struct intel_uncore_type **types, unsigned int die, unsigned int cpu) { struct intel_uncore_box *box, *tmp; @@ -1621,8 +1621,10 @@ static int allocate_boxes(struct intel_uncore_type *= *types, if (pmu->boxes[die] || uncore_pmu_broken(pmu)) continue; box =3D uncore_alloc_box(type, cpu_to_node(cpu)); - if (!box) + if (!box) { + uncore_pmu_set_broken(pmu); goto cleanup; + } box->pmu =3D pmu; box->dieid =3D die; list_add(&box->active_list, &allocated); @@ -1633,14 +1635,13 @@ static int allocate_boxes(struct intel_uncore_type = **types, list_del_init(&box->active_list); box->pmu->boxes[die] =3D box; } - return 0; + return; =20 cleanup: list_for_each_entry_safe(box, tmp, &allocated, active_list) { list_del_init(&box->active_list); kfree(box); } - return -ENOMEM; } =20 static int uncore_box_ref(struct intel_uncore_type **types, @@ -1649,11 +1650,7 @@ static int uncore_box_ref(struct intel_uncore_type *= *types, struct intel_uncore_type *type; struct intel_uncore_pmu *pmu; struct intel_uncore_box *box; - int i, ret; - - ret =3D allocate_boxes(types, die, cpu); - if (ret) - return ret; + int i; =20 for (; *types; types++) { type =3D *types; @@ -1669,27 +1666,26 @@ static int uncore_box_ref(struct intel_uncore_type = **types, =20 static int uncore_event_cpu_online(unsigned int cpu) { - int die, target, msr_ret, mmio_ret; + int die, target; =20 die =3D topology_logical_die_id(cpu); - msr_ret =3D uncore_box_ref(uncore_msr_uncores, die, cpu); - mmio_ret =3D uncore_box_ref(uncore_mmio_uncores, die, cpu); + allocate_boxes(uncore_msr_uncores, die, cpu); + allocate_boxes(uncore_mmio_uncores, die, cpu); =20 /* * Check if there is an online cpu in the package * which collects uncore events already. */ target =3D cpumask_any_and(&uncore_cpu_mask, topology_die_cpumask(cpu)); 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11 Jun 2026 09:09:37 -0700 X-CSE-ConnectionGUID: RxUZorLTT7aGjY0itp8Y9A== X-CSE-MsgGUID: gB+0euCKSo6mnNtlfOSaEQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,199,1774335600"; d="scan'208";a="246403609" Received: from 9cc2c43eec6b.jf.intel.com ([10.54.77.29]) by orviesa008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Jun 2026 09:09:36 -0700 From: Zide Chen To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , Adrian Hunter , Alexander Shishkin , Andi Kleen , Eranian Stephane Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Dapeng Mi , Zide Chen Subject: [PATCH V3 8/8] perf/x86/intel/uncore: Implement lazy setup for MSR/MMIO PMUs Date: Thu, 11 Jun 2026 09:00:33 -0700 Message-ID: <20260611160033.66760-9-zide.chen@intel.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260611160033.66760-1-zide.chen@intel.com> References: <20260611160033.66760-1-zide.chen@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" MSR and MMIO uncore PMUs are currently registered at module init time and appear in sysfs even when no PMU boxes are functional. Apply the same lazy registration model used by PCI uncore PMUs: the PMU is registered when the first box is successfully initialized, and unregistered when the last box exits. If a box fails to initialize on a subsequent die, the PMU is marked broken but remains registered to avoid disrupting any in-flight perf events. Box allocation and freeing remain at module init/exit time to avoid repeated kfree/alloc cycles across CPU offline/online events. Reviewed-by: Dapeng Mi Signed-off-by: Zide Chen --- v3: - Update title: PMU -> PMUs. - Add Reviewed-by tag. v2: - uncore_box_unref(): Only decrement pmu->activeboxes for active boxes (those without init_box callback or successfully initialized) to prevent underflow when initialization fails. - Set uncore_{msr,mmio}_uncores to empty_uncore when uncore_pmu_types_init() fails. - Rename uncore_cpu_mmio_init() to uncore_pmu_types_init() (Dapeng). --- arch/x86/events/intel/uncore.c | 78 +++++++--------------------------- arch/x86/events/intel/uncore.h | 6 +++ 2 files changed, 22 insertions(+), 62 deletions(-) diff --git a/arch/x86/events/intel/uncore.c b/arch/x86/events/intel/uncore.c index b9ac2f7d31ca..9f8a80c9dcb6 100644 --- a/arch/x86/events/intel/uncore.c +++ b/arch/x86/events/intel/uncore.c @@ -1570,8 +1570,13 @@ static void uncore_box_unref(struct intel_uncore_typ= e **types, int die) pmu =3D type->pmus; for (i =3D 0; i < type->num_boxes; i++, pmu++) { box =3D pmu->boxes[die]; - if (box && box->cpu >=3D 0 && atomic_dec_return(&box->refcnt) =3D=3D 0) + if (box && box->cpu >=3D 0 && + atomic_dec_return(&box->refcnt) =3D=3D 0) { + if (uncore_box_active(box) && + atomic_dec_return(&pmu->activeboxes) =3D=3D 0) + uncore_pmu_unregister(pmu); uncore_box_exit(box); + } } } } @@ -1658,7 +1663,7 @@ static int uncore_box_ref(struct intel_uncore_type **= types, for (i =3D 0; i < type->num_boxes; i++, pmu++) { box =3D pmu->boxes[die]; if (box && box->cpu >=3D 0 && atomic_inc_return(&box->refcnt) =3D=3D 1) - uncore_box_init(box); + uncore_box_setup(pmu, box); } } return 0; @@ -1689,67 +1694,12 @@ static int uncore_event_cpu_online(unsigned int cpu) return 0; } =20 -static int __init type_pmu_register(struct intel_uncore_type *type) +static int __init uncore_pmu_types_init(struct intel_uncore_type **types) { - int i, ret; - - for (i =3D 0; i < type->num_boxes; i++) { - ret =3D uncore_pmu_register(&type->pmus[i]); - if (ret) - return ret; - } - return 0; -} - -static int __init uncore_msr_pmus_register(void) -{ - struct intel_uncore_type **types =3D uncore_msr_uncores; - int ret; - - for (; *types; types++) { - ret =3D type_pmu_register(*types); - if (ret) - return ret; - } - return 0; -} - -static int __init uncore_cpu_init(void) -{ - int ret; - - ret =3D uncore_types_init(uncore_msr_uncores); - if (ret) - goto err; - - ret =3D uncore_msr_pmus_register(); - if (ret) - goto err; - return 0; -err: - uncore_types_exit(uncore_msr_uncores); - uncore_msr_uncores =3D empty_uncore; - return ret; -} - -static int __init uncore_mmio_init(void) -{ - struct intel_uncore_type **types =3D uncore_mmio_uncores; - int ret; - - ret =3D uncore_types_init(types); + int ret =3D uncore_types_init(types); if (ret) - goto err; + uncore_types_exit(types); =20 - for (; *types; types++) { - ret =3D type_pmu_register(*types); - if (ret) - goto err; - } - return 0; -err: - uncore_types_exit(uncore_mmio_uncores); - uncore_mmio_uncores =3D empty_uncore; return ret; } =20 @@ -2050,12 +2000,16 @@ static int __init intel_uncore_init(void) =20 if (uncore_init->cpu_init) { uncore_init->cpu_init(); - cret =3D uncore_cpu_init(); + cret =3D uncore_pmu_types_init(uncore_msr_uncores); + if (cret) + uncore_msr_uncores =3D empty_uncore; } =20 if (uncore_init->mmio_init) { uncore_init->mmio_init(); - mret =3D uncore_mmio_init(); + mret =3D uncore_pmu_types_init(uncore_mmio_uncores); + if (mret) + uncore_mmio_uncores =3D empty_uncore; } =20 if (cret && pret && mret) { diff --git a/arch/x86/events/intel/uncore.h b/arch/x86/events/intel/uncore.h index 0adb477d9708..c8dfa2d21bfd 100644 --- a/arch/x86/events/intel/uncore.h +++ b/arch/x86/events/intel/uncore.h @@ -568,6 +568,12 @@ static inline u64 uncore_read_counter(struct intel_unc= ore_box *box, return box->pmu->type->ops->read_counter(box, event); } =20 +static inline bool uncore_box_active(struct intel_uncore_box *box) +{ + return (!box->pmu->type->ops->init_box || + test_bit(UNCORE_BOX_FLAG_INITIALIZED, &box->flags)); +} + static inline int uncore_box_init(struct intel_uncore_box *box) { int ret =3D 0; --=20 2.54.0