From nobody Wed Jun 10 17:22:13 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B500C3F7885; Wed, 10 Jun 2026 10:41:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781088101; cv=none; b=VWvFC/LiM+IDr1x7srieVOD33pDqakci18ot8ewiH8Th7O1C6oH50XOAPpLFLDX0+eOu1gRba3bMbbSkq1kFDkFJ2lTL7ma9FRcsg8mVMxeVd+EnvIu8EkB52OHcY283SCcXCqBlDqlfNSn7vU4UMEVGiCh387A6aWBO7SJ4x8I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781088101; c=relaxed/simple; bh=K+dQPJWdfxFAzzSiB0uJ2SitxwdxXVHqZ1rahQEs52w=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=kRKGdkfRETHIiY7A7hBA5AfAWppkQFJCeWmtWSYFXOTuHDLU58hIBuFgMeJdxhVBZQqzd776P9561inFtQAE8+WjyCeX3WGmqE+0ss+cFE85bbqorzzLFEcLXBkZuaow0vDXgPTnPhygIcM+Ju0NcErId71Y4ATmT09kw5CIGak= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ttlrt3HM; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ttlrt3HM" Received: by smtp.kernel.org (Postfix) with ESMTPS id 2BD51C2BCB9; Wed, 10 Jun 2026 10:41:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1781088101; bh=K+dQPJWdfxFAzzSiB0uJ2SitxwdxXVHqZ1rahQEs52w=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=ttlrt3HMxrTCtwouY6Vl6i0DwnFn2R3e6Lgk94ZyZWyj6gwr+wyHYPc2mQCXUEX7s txDDQI8AHgEsVDvQPiPUGMGDpGh6GSXeuc4P+g/3EpOFpMLOfIqz0Z0Z09zDqGbs1Y 6k/d8/QS7a5Ea3RQL+zEumroSjRkM46PxsaN8HYAq/fwMND3qD07ybwxn2WgVOYKCj HsCSu9nj5LOxiYyqwJKNmugL64BEUe7HYf+QiuR3Bx/CD/8oMh5rK/zzdiOCRNnFMS 2lOWyOgHZzwLVx520IIzq8kY7q8+x/NrCpaKE8Tw5ZqkgxtVrwOSEinRB141o6vKFi qXoLwJCPt9TsA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 17D3ACD98C7; Wed, 10 Jun 2026 10:41:41 +0000 (UTC) From: Jack Wu via B4 Relay Date: Wed, 10 Jun 2026 18:41:04 +0800 Subject: [PATCH v2 1/7] net: wwan: t9xx: Add PCIe core Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260610-t9xx_driver_v1-v2-1-c65addf23b3f@compal.com> References: <20260610-t9xx_driver_v1-v2-0-c65addf23b3f@compal.com> In-Reply-To: <20260610-t9xx_driver_v1-v2-0-c65addf23b3f@compal.com> To: Loic Poulain , Sergey Ryazanov , Johannes Berg , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Jack Wu , Wen-Zhi Huang , Shi-Wei Yeh , Minano Tseng , Matthias Brugger , AngeloGioacchino Del Regno , Simon Horman , Jonathan Corbet , Shuah Khan Cc: linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-doc@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1781088081; l=49571; i=jackbb_wu@compal.com; s=20260526; h=from:subject:message-id; bh=Tf4yBWFsu7a5jlv/Rabf26T/WKd5hVCFK2uQfD50eFw=; b=48Qw08COCaDfrB6W5LydnMJcbZceKaNKGOCCjuwFZ6trgvJhrjI07erYqg91QnkJs/h/7tgIb H3RYJit+9mQBNeeQJqHrzsjT54kcegup+O9Lr7VuMKIdQt/y95yGEJ0 X-Developer-Key: i=jackbb_wu@compal.com; a=ed25519; pk=VH1prTWixNl8OEUPPSfII3p46MzJpQN8J3+ecE1tZXg= X-Endpoint-Received: by B4 Relay for jackbb_wu@compal.com/20260526 with auth_id=793 X-Original-From: Jack Wu Reply-To: jackbb_wu@compal.com From: Jack Wu Registers the T900 device driver with the kernel. Set up all the fundamental configurations for the device: PCIe layer, Modem Host Cross Core Interface (MHCCIF), Reset Generation Unit (RGU), modem common control operations and build infrastructure. * PCIe layer code implements driver probe and removal, MSI-X interrupt initialization and de-initialization, and the way of resetting the device. * MHCCIF provides interrupt channels to communicate events such as handshake, PM and port enumeration. * RGU provides interrupt channels to generate notifications from the device so that the T900 driver could get the device reset. * Modem common control operations provide the basic read/write functions of the device's hardware registers, mask/unmask/get/clear functions of the device's interrupt registers and inquiry functions of the device's status. Signed-off-by: Jack Wu --- drivers/net/wwan/Kconfig | 12 + drivers/net/wwan/Makefile | 1 + drivers/net/wwan/t9xx/Makefile | 10 + drivers/net/wwan/t9xx/mtk_dev.h | 108 +++ drivers/net/wwan/t9xx/pcie/mtk_pci.c | 1062 +++++++++++++++++++++= ++++ drivers/net/wwan/t9xx/pcie/mtk_pci.h | 232 ++++++ drivers/net/wwan/t9xx/pcie/mtk_pci_drv_m9xx.c | 69 ++ drivers/net/wwan/t9xx/pcie/mtk_pci_reg.h | 70 ++ 8 files changed, 1564 insertions(+) diff --git a/drivers/net/wwan/Kconfig b/drivers/net/wwan/Kconfig index 88df55d78d90..4cee537c739f 100644 --- a/drivers/net/wwan/Kconfig +++ b/drivers/net/wwan/Kconfig @@ -121,6 +121,18 @@ config MTK_T7XX =20 If unsure, say N. =20 +config MTK_T9XX + tristate "MediaTek PCIe 5G WWAN modem T9xx device" + depends on PCI + select NET_DEVLINK + help + Enables MediaTek PCIe based 5G WWAN modem (T9xx series) device. + + To compile this driver as a module, choose M here: the module will be + called mtk_t9xx. + + If unsure, say N. + endif # WWAN =20 endmenu diff --git a/drivers/net/wwan/Makefile b/drivers/net/wwan/Makefile index 3960c0ae2445..7361eef4c472 100644 --- a/drivers/net/wwan/Makefile +++ b/drivers/net/wwan/Makefile @@ -14,3 +14,4 @@ obj-$(CONFIG_QCOM_BAM_DMUX) +=3D qcom_bam_dmux.o obj-$(CONFIG_RPMSG_WWAN_CTRL) +=3D rpmsg_wwan_ctrl.o obj-$(CONFIG_IOSM) +=3D iosm/ obj-$(CONFIG_MTK_T7XX) +=3D t7xx/ +obj-$(CONFIG_MTK_T9XX) +=3D t9xx/ diff --git a/drivers/net/wwan/t9xx/Makefile b/drivers/net/wwan/t9xx/Makefile new file mode 100644 index 000000000000..6f2dd3f91454 --- /dev/null +++ b/drivers/net/wwan/t9xx/Makefile @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0-only + +ccflags-y +=3D -I$(src)/pcie +ccflags-y +=3D -I$(src) + +obj-$(CONFIG_MTK_T9XX) +=3D mtk_t9xx.o + +mtk_t9xx-y :=3D \ + pcie/mtk_pci.o \ + pcie/mtk_pci_drv_m9xx.o diff --git a/drivers/net/wwan/t9xx/mtk_dev.h b/drivers/net/wwan/t9xx/mtk_de= v.h new file mode 100644 index 000000000000..8278a0e2875e --- /dev/null +++ b/drivers/net/wwan/t9xx/mtk_dev.h @@ -0,0 +1,108 @@ +/* SPDX-License-Identifier: GPL-2.0-only + * + * Copyright (c) 2022, MediaTek Inc. + */ + +#ifndef __MTK_DEV_H__ +#define __MTK_DEV_H__ + +#include +#include +#include +#include +#include +#include +#include + +#define MTK_DEV_STR_LEN 16 + +enum mtk_user_id { + MTK_USER_MIN, + MTK_USER_CTRL, + MTK_USER_DATA, + MTK_USER_MAX +}; + +enum mtk_dev_evt_h2d { + DEV_EVT_H2D_DEVICE_RESET =3D BIT(2), + DEV_EVT_H2D_MAX =3D BIT(5) +}; + +enum mtk_dev_evt_d2h { + DEV_EVT_D2H_BOOT_FLOW_SYNC =3D BIT(4), + DEV_EVT_D2H_ASYNC_HS_NOTIFY_SAP =3D BIT(5), + DEV_EVT_D2H_ASYNC_HS_NOTIFY_MD =3D BIT(6), + DEV_EVT_D2H_MAX =3D BIT(11) +}; + +struct mtk_md_dev; + +struct mtk_dev_ops { + u32 (*get_dev_state)(struct mtk_md_dev *mdev); + void (*ack_dev_state)(struct mtk_md_dev *mdev, u32 state); + u32 (*get_dev_cfg)(struct mtk_md_dev *mdev); + int (*register_dev_evt)(struct mtk_md_dev *mdev, u32 dev_evt, + int (*evt_cb)(u32 status, void *data), void *data); + void (*unregister_dev_evt)(struct mtk_md_dev *mdev, u32 dev_evt); + void (*mask_dev_evt)(struct mtk_md_dev *mdev, u32 dev_evt); + void (*unmask_dev_evt)(struct mtk_md_dev *mdev, u32 dev_evt); + void (*clear_dev_evt)(struct mtk_md_dev *mdev, u32 dev_evt); + int (*send_dev_evt)(struct mtk_md_dev *mdev, u32 dev_evt); +}; + +/* mtk_md_dev defines the structure of MTK modem device */ +struct mtk_md_dev { + struct device *dev; + const struct mtk_dev_ops *dev_ops; + void *hw_priv; + u32 hw_ver; + char dev_str[MTK_DEV_STR_LEN]; +}; + +static inline u32 mtk_dev_get_dev_state(struct mtk_md_dev *mdev) +{ + return mdev->dev_ops->get_dev_state(mdev); +} + +static inline void mtk_dev_ack_dev_state(struct mtk_md_dev *mdev, u32 stat= e) +{ + return mdev->dev_ops->ack_dev_state(mdev, state); +} + +static inline u32 mtk_dev_get_dev_cfg(struct mtk_md_dev *mdev) +{ + return mdev->dev_ops->get_dev_cfg(mdev); +} + +static inline int mtk_dev_register_dev_evt(struct mtk_md_dev *mdev, u32 de= v_evt, + int (*evt_cb)(u32 status, void *data), void *data) +{ + return mdev->dev_ops->register_dev_evt(mdev, dev_evt, evt_cb, data); +} + +static inline void mtk_dev_unregister_dev_evt(struct mtk_md_dev *mdev, u32= dev_evt) +{ + mdev->dev_ops->unregister_dev_evt(mdev, dev_evt); +} + +static inline void mtk_dev_mask_dev_evt(struct mtk_md_dev *mdev, u32 dev_e= vt) +{ + mdev->dev_ops->mask_dev_evt(mdev, dev_evt); +} + +static inline void mtk_dev_unmask_dev_evt(struct mtk_md_dev *mdev, u32 dev= _evt) +{ + mdev->dev_ops->unmask_dev_evt(mdev, dev_evt); +} + +static inline void mtk_dev_clear_dev_evt(struct mtk_md_dev *mdev, u32 dev_= evt) +{ + mdev->dev_ops->clear_dev_evt(mdev, dev_evt); +} + +static inline int mtk_dev_send_dev_evt(struct mtk_md_dev *mdev, u32 dev_ev= t) +{ + return mdev->dev_ops->send_dev_evt(mdev, dev_evt); +} + +#endif /* __MTK_DEV_H__ */ diff --git a/drivers/net/wwan/t9xx/pcie/mtk_pci.c b/drivers/net/wwan/t9xx/p= cie/mtk_pci.c new file mode 100644 index 000000000000..616bf5f31b6c --- /dev/null +++ b/drivers/net/wwan/t9xx/pcie/mtk_pci.c @@ -0,0 +1,1062 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022, MediaTek Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "mtk_dev.h" +#include "mtk_pci.h" +#include "mtk_pci_reg.h" + +#define MTK_PCI_BAR_NUM 6 +#define MTK_PCI_TRANSPARENT_ATR_SIZE (0x3F) +#define MTK_PCI_MINIMUM_ATR_SIZE (0x1000) +#define ATR_SIZE_LO32_MASK GENMASK_ULL(31, 0) +#define ATR_SIZE_HI32_MASK GENMASK_ULL(63, 32) +#define ATR_SIZE_BIAS_FROM_LO32 2 +#define ATR_ADDR_ALIGN_MASK 0xFFFFF000 +#define ATR_EN BIT(0) +#define ATR_PARAM_OFFSET 16 +/* Delay between ACPI PXP._OFF and _ON for modem power cycle stabilization= */ +#define MTK_PLDR_POWER_OFF_DELAY_MS 500 +#define LE32_TO_U32(x) ((__force u32)(__le32)(x)) +#define SET_HW_BITS(dest, chs, mhccif, dev) \ + ({ \ + if ((chs) & (dev)) \ + (dest) |=3D FIELD_PREP(mhccif, 1); \ + }) + +extern const struct mtk_pci_dev_cfg mtk_dev_cfg_0900; + +struct mtk_mhccif_cb { + struct list_head entry; + int (*evt_cb)(u32 status, void *data); + void *data; + u32 chs; +}; + +/** + * mtk_pci_setup_atr() - Configure a PCIe address translation rule + * @mdev: MTK MD device + * @cfg: ATR configuration parameters + * + * Return: 0 on success, negative error code on failure. + */ +int mtk_pci_setup_atr(struct mtk_md_dev *mdev, struct mtk_atr_cfg *cfg) +{ + struct mtk_pci_priv *priv =3D mdev->hw_priv; + u32 addr, val, size_h, size_l; + int atr_size, pos, offset; + + if (cfg->transparent) { + /* No address conversion is performed */ + atr_size =3D MTK_PCI_TRANSPARENT_ATR_SIZE; + } else { + if (cfg->size < MTK_PCI_MINIMUM_ATR_SIZE) + cfg->size =3D MTK_PCI_MINIMUM_ATR_SIZE; + + if (cfg->src_addr & (cfg->size - 1)) { + dev_err((mdev)->dev, "Invalid atr src addr is not aligned to size\n"); + return -EFAULT; + } + + if (cfg->trsl_addr & (cfg->size - 1)) { + dev_err((mdev)->dev, + "Invalid atr trsl addr is not aligned to size, %llx, %llx\n", + cfg->trsl_addr, cfg->size - 1); + return -EFAULT; + } + + size_l =3D FIELD_GET(ATR_SIZE_LO32_MASK, cfg->size); + size_h =3D FIELD_GET(ATR_SIZE_HI32_MASK, cfg->size); + pos =3D ffs(size_l); + if (pos) { + atr_size =3D pos - ATR_SIZE_BIAS_FROM_LO32; + } else { + pos =3D ffs(size_h); + atr_size =3D pos + 32 - ATR_SIZE_BIAS_FROM_LO32; + } + } + + /* Calculate table offset */ + offset =3D ATR_PORT_OFFSET * cfg->port + ATR_TABLE_OFFSET * cfg->table; + addr =3D REG_ATR_PCIE_WIN0_T0_SRC_ADDR_MSB + offset; + val =3D (u32)(cfg->src_addr >> 32); + mtk_pci_mac_write32(priv, addr, val); + + addr =3D REG_ATR_PCIE_WIN0_T0_SRC_ADDR_LSB + offset; + val =3D (u32)(cfg->src_addr & ATR_ADDR_ALIGN_MASK) | (atr_size << 1) | AT= R_EN; + mtk_pci_mac_write32(priv, addr, val); + + addr =3D REG_ATR_PCIE_WIN0_T0_TRSL_ADDR_MSB + offset; + val =3D (u32)(cfg->trsl_addr >> 32); + mtk_pci_mac_write32(priv, addr, val); + + addr =3D REG_ATR_PCIE_WIN0_T0_TRSL_ADDR_LSB + offset; + val =3D (u32)(cfg->trsl_addr & ATR_ADDR_ALIGN_MASK); + mtk_pci_mac_write32(priv, addr, val); + + /* TRSL_PARAM */ + addr =3D REG_ATR_PCIE_WIN0_T0_TRSL_PARAM + offset; + val =3D (cfg->trsl_param << ATR_PARAM_OFFSET) | cfg->trsl_id; + mtk_pci_mac_write32(priv, addr, val); + + return 0; +} + +/** + * mtk_pci_atr_disable() - Disable all PCIe address translation rules + * @priv: MTK PCI private data + */ +void mtk_pci_atr_disable(struct mtk_pci_priv *priv) +{ + int port, tbl, offset; + u32 val; + + /* Disable all ATR table for all ports */ + for (port =3D ATR_SRC_PCI_WIN0; port <=3D ATR_SRC_AXIS_3; port++) + for (tbl =3D 0; tbl < ATR_TABLE_NUM_PER_ATR; tbl++) { + /* Calculate table offset */ + offset =3D ATR_PORT_OFFSET * port + ATR_TABLE_OFFSET * tbl; + val =3D mtk_pci_mac_read32(priv, REG_ATR_PCIE_WIN0_T0_SRC_ADDR_LSB + of= fset); + val =3D val & (~BIT(0)); + /* Disable table by SRC_ADDR_L */ + mtk_pci_mac_write32(priv, REG_ATR_PCIE_WIN0_T0_SRC_ADDR_LSB + offset, v= al); + } +} + +static void mtk_pci_set_msix_merged(struct mtk_pci_priv *priv, int irq_cnt) +{ + mtk_pci_mac_write32(priv, REG_PCIE_CFG_MSIX, ffs(irq_cnt) * 2 - 1); +} + +/** + * mtk_pci_get_dev_state() - Read the device state from the modem + * @mdev: MTK MD device + * + * Return: Device state value. + */ +u32 mtk_pci_get_dev_state(struct mtk_md_dev *mdev) +{ + return mtk_pci_mac_read32(mdev->hw_priv, REG_PCIE_DEBUG_DUMMY_7); +} + +/** + * mtk_pci_ack_dev_state() - Acknowledge the device state to the modem + * @mdev: MTK MD device + * @state: State value to acknowledge + */ +void mtk_pci_ack_dev_state(struct mtk_md_dev *mdev, u32 state) +{ + mtk_pci_mac_write32(mdev->hw_priv, REG_PCIE_DEBUG_DUMMY_7, state); +} + +/** + * mtk_pci_get_irq_id() - Map an IRQ source to its hardware IRQ ID + * @mdev: MTK MD device + * @irq_src: IRQ source enum + * + * Return: IRQ ID on success, -EINVAL on failure. + */ +int mtk_pci_get_irq_id(struct mtk_md_dev *mdev, enum mtk_irq_src irq_src) +{ + struct mtk_pci_priv *priv =3D mdev->hw_priv; + const int *irq_tbl =3D priv->cfg->irq_tbl; + int irq_id =3D -EINVAL; + + if (irq_src > MTK_IRQ_SRC_MIN && irq_src < MTK_IRQ_SRC_MAX) { + irq_id =3D irq_tbl[irq_src]; + if (irq_id < 0 || irq_id >=3D MTK_IRQ_CNT_MAX) + irq_id =3D -EINVAL; + } + + return irq_id; +} + +/** + * mtk_pci_get_virq_id() - Get the Linux virtual IRQ for a hardware IRQ ID + * @mdev: MTK MD device + * @irq_id: Hardware IRQ ID + * + * Return: Virtual IRQ number on success, negative error code on failure. + */ +int mtk_pci_get_virq_id(struct mtk_md_dev *mdev, int irq_id) +{ + struct pci_dev *pdev =3D to_pci_dev(mdev->dev); + struct mtk_pci_priv *priv =3D mdev->hw_priv; + + if (!priv->irq_cnt || irq_id < 0) + return -EINVAL; + + return pci_irq_vector(pdev, irq_id % priv->irq_cnt); +} + +/** + * mtk_pci_register_irq() - Register a callback for a hardware IRQ + * @mdev: MTK MD device + * @irq_id: Hardware IRQ ID + * @irq_cb: Callback function + * @data: Private data passed to callback + * + * Return: 0 on success, negative error code on failure. + */ +int mtk_pci_register_irq(struct mtk_md_dev *mdev, int irq_id, + int (*irq_cb)(int irq_id, void *data), void *data) +{ + struct mtk_pci_priv *priv =3D mdev->hw_priv; + + if ((irq_id < 0 || irq_id >=3D MTK_IRQ_CNT_MAX) || !irq_cb) + return -EINVAL; + + if (priv->irq_cb_list[irq_id]) { + dev_err((mdev)->dev, + "Unable to register irq, irq_id=3D%d, it's already been register by %ps= .\n", + irq_id, priv->irq_cb_list[irq_id]); + return -EFAULT; + } + priv->irq_cb_list[irq_id] =3D irq_cb; + priv->irq_cb_data[irq_id] =3D data; + + return 0; +} + +/** + * mtk_pci_unregister_irq() - Unregister a hardware IRQ callback + * @mdev: MTK MD device + * @irq_id: Hardware IRQ ID + * + * Return: 0 on success, negative error code on failure. + */ +int mtk_pci_unregister_irq(struct mtk_md_dev *mdev, int irq_id) +{ + struct mtk_pci_priv *priv =3D mdev->hw_priv; + + if (irq_id < 0 || irq_id >=3D MTK_IRQ_CNT_MAX) + return -EINVAL; + + if (!priv->irq_cb_list[irq_id]) { + dev_err((mdev)->dev, "irq_id=3D%d has not been registered\n", irq_id); + return -EFAULT; + } + priv->irq_cb_list[irq_id] =3D NULL; + priv->irq_cb_data[irq_id] =3D NULL; + + return 0; +} + +/** + * mtk_pci_mask_irq() - Mask (disable) a hardware IRQ + * @mdev: MTK MD device + * @irq_id: Hardware IRQ ID + * + * Return: 0 on success, negative error code on failure. + */ +int mtk_pci_mask_irq(struct mtk_md_dev *mdev, int irq_id) +{ + struct mtk_pci_priv *priv =3D mdev->hw_priv; + + if (irq_id < 0 || irq_id >=3D MTK_IRQ_CNT_MAX || + priv->irq_type !=3D PCI_IRQ_MSIX) { + dev_err(mdev->dev, "Failed to mask irq: input irq_id=3D%d\n", irq_id); + return -EINVAL; + } + + mtk_pci_mac_write32(priv, REG_IMASK_HOST_MSIX_CLR_GRP0_0, BIT(irq_id)); + + return 0; +} + +/** + * mtk_pci_unmask_irq() - Unmask (enable) a hardware IRQ + * @mdev: MTK MD device + * @irq_id: Hardware IRQ ID + * + * Return: 0 on success, negative error code on failure. + */ +int mtk_pci_unmask_irq(struct mtk_md_dev *mdev, int irq_id) +{ + struct mtk_pci_priv *priv =3D mdev->hw_priv; + + if (irq_id < 0 || irq_id >=3D MTK_IRQ_CNT_MAX || + priv->irq_type !=3D PCI_IRQ_MSIX) { + dev_err(mdev->dev, "Failed to unmask irq: input irq_id=3D%d\n", irq_id); + return -EINVAL; + } + + mtk_pci_mac_write32(priv, REG_IMASK_HOST_MSIX_SET_GRP0_0, BIT(irq_id)); + + return 0; +} + +/** + * mtk_pci_clear_irq() - Clear (acknowledge) a hardware IRQ + * @mdev: MTK MD device + * @irq_id: Hardware IRQ ID + * + * Return: 0 on success, negative error code on failure. + */ +int mtk_pci_clear_irq(struct mtk_md_dev *mdev, int irq_id) +{ + struct mtk_pci_priv *priv =3D mdev->hw_priv; + + if (irq_id < 0 || irq_id >=3D MTK_IRQ_CNT_MAX || + priv->irq_type !=3D PCI_IRQ_MSIX) { + dev_err(mdev->dev, "Failed to clear irq: input irq_id=3D%d\n", irq_id); + return -EINVAL; + } + + mtk_pci_mac_write32(priv, REG_MSIX_ISTATUS_HOST_GRP0_0, BIT(irq_id)); + + return 0; +} + +static u32 mtk_pci_ext_d2h_evt_hw_bits(u32 chs) +{ + u32 hw_bits =3D 0; + + SET_HW_BITS(hw_bits, chs, MHCCIF_EP2RC_EVT_BOOT_FLOW_SYNC, + DEV_EVT_D2H_BOOT_FLOW_SYNC); + SET_HW_BITS(hw_bits, chs, MHCCIF_EP2RC_EVT_ASYNC_HS_NOTIFY_SAP, + DEV_EVT_D2H_ASYNC_HS_NOTIFY_SAP); + SET_HW_BITS(hw_bits, chs, MHCCIF_EP2RC_EVT_ASYNC_HS_NOTIFY_MD, + DEV_EVT_D2H_ASYNC_HS_NOTIFY_MD); + + return LE32_TO_U32(cpu_to_le32(hw_bits)); +} + +static u32 mtk_pci_ext_d2h_evt_chs(u32 hw_bits) +{ + u32 chs =3D 0; + + if (!hw_bits) + return chs; + + chs =3D FIELD_PREP(DEV_EVT_D2H_BOOT_FLOW_SYNC, + FIELD_GET(MHCCIF_EP2RC_EVT_BOOT_FLOW_SYNC, hw_bits)) | + FIELD_PREP(DEV_EVT_D2H_ASYNC_HS_NOTIFY_SAP, + FIELD_GET(MHCCIF_EP2RC_EVT_ASYNC_HS_NOTIFY_SAP, hw_bits)) | + FIELD_PREP(DEV_EVT_D2H_ASYNC_HS_NOTIFY_MD, + FIELD_GET(MHCCIF_EP2RC_EVT_ASYNC_HS_NOTIFY_MD, hw_bits)); + + return chs; +} + +/** + * mtk_pci_register_ext_evt() - Register a callback for MHCCIF device even= ts + * @mdev: MTK MD device + * @chs: Bitmask of event channels to register + * @evt_cb: Callback function + * @data: Private data passed to callback + * + * Return: 0 on success, negative error code on failure. + */ +int mtk_pci_register_ext_evt(struct mtk_md_dev *mdev, u32 chs, + int (*evt_cb)(u32 status, void *data), void *data) +{ + struct mtk_pci_priv *priv =3D mdev->hw_priv; + struct mtk_mhccif_cb *cb; + int ret =3D 0; + + if (!chs || !evt_cb) + return -EINVAL; + + spin_lock_bh(&priv->mhccif_lock); + list_for_each_entry(cb, &priv->mhccif_cb_list, entry) { + if (cb->chs & chs) { + ret =3D -EFAULT; + dev_err((mdev)->dev, + "Unable to register evt, intersection: chs=3D0x%08x&0x%08x cb=3D%ps\n", + chs, cb->chs, cb->evt_cb); + goto err_spin_unlock; + } + } + cb =3D devm_kzalloc(mdev->dev, sizeof(*cb), GFP_ATOMIC); + if (!cb) { + ret =3D -ENOMEM; + goto err_spin_unlock; + } + cb->evt_cb =3D evt_cb; + cb->data =3D data; + cb->chs =3D chs; + list_add_tail(&cb->entry, &priv->mhccif_cb_list); +err_spin_unlock: + spin_unlock_bh(&priv->mhccif_lock); + + return ret; +} + +/** + * mtk_pci_unregister_ext_evt() - Unregister an MHCCIF device event callba= ck + * @mdev: MTK MD device + * @chs: Bitmask of event channels to unregister + */ +void mtk_pci_unregister_ext_evt(struct mtk_md_dev *mdev, u32 chs) +{ + struct mtk_pci_priv *priv =3D mdev->hw_priv; + struct mtk_mhccif_cb *cb, *next; + + if (!chs) + return; + + spin_lock_bh(&priv->mhccif_lock); + list_for_each_entry_safe(cb, next, &priv->mhccif_cb_list, entry) { + if (cb->chs =3D=3D chs) { + list_del(&cb->entry); + devm_kfree(mdev->dev, cb); + goto out; + } + } + dev_warn((mdev)->dev, + "Unable to unregister evt, no chs=3D0x%08x has been registered.\n", chs= ); +out: + spin_unlock_bh(&priv->mhccif_lock); +} + +/** + * mtk_pci_mask_ext_evt() - Mask (disable) MHCCIF device events + * @mdev: MTK MD device + * @chs: Bitmask of event channels to mask + */ +void mtk_pci_mask_ext_evt(struct mtk_md_dev *mdev, u32 chs) +{ + struct mtk_pci_priv *priv =3D mdev->hw_priv; + u32 hw_bits =3D mtk_pci_ext_d2h_evt_hw_bits(chs); + + mtk_pci_write32(mdev, priv->cfg->mhccif_rc_base_addr + + MHCCIF_EP2RC_SW_INT_EAP_MASK_SET, hw_bits); +} + +/** + * mtk_pci_unmask_ext_evt() - Unmask (enable) MHCCIF device events + * @mdev: MTK MD device + * @chs: Bitmask of event channels to unmask + */ +void mtk_pci_unmask_ext_evt(struct mtk_md_dev *mdev, u32 chs) +{ + struct mtk_pci_priv *priv =3D mdev->hw_priv; + u32 hw_bits =3D mtk_pci_ext_d2h_evt_hw_bits(chs); + + mtk_pci_write32(mdev, priv->cfg->mhccif_rc_base_addr + + MHCCIF_EP2RC_SW_INT_EAP_MASK_CLR, hw_bits); +} + +/** + * mtk_pci_clear_ext_evt() - Clear (acknowledge) MHCCIF device events + * @mdev: MTK MD device + * @chs: Bitmask of event channels to clear + */ +void mtk_pci_clear_ext_evt(struct mtk_md_dev *mdev, u32 chs) +{ + struct mtk_pci_priv *priv =3D mdev->hw_priv; + u32 hw_bits =3D mtk_pci_ext_d2h_evt_hw_bits(chs); + + mtk_pci_write32(mdev, priv->cfg->mhccif_rc_base_addr + + MHCCIF_EP2RC_SW_INT_ACK, hw_bits); +} + +static u32 mtk_pci_ext_h2d_evt_hw_bits(u32 chs) +{ + u32 hw_bits =3D 0; + + SET_HW_BITS(hw_bits, chs, MHCCIF_RC2EP_EVT_DEVICE_RESET, + DEV_EVT_H2D_DEVICE_RESET); + return LE32_TO_U32(cpu_to_le32(hw_bits)); +} + +/** + * mtk_pci_send_ext_evt() - Send an MHCCIF event to the modem + * @mdev: MTK MD device + * @ch: Event channel to trigger (must be a single bit) + * + * Return: 0 on success, negative error code on failure. + */ +int mtk_pci_send_ext_evt(struct mtk_md_dev *mdev, u32 ch) +{ + struct mtk_pci_priv *priv =3D mdev->hw_priv; + u32 rc_base, hw_bits; + + rc_base =3D priv->cfg->mhccif_rc_base_addr; + + /* Only allow one ch to be triggered at a time */ + if (!is_power_of_2(ch)) { + dev_err((mdev)->dev, "Unsupported ext evt ch=3D0x%08x\n", ch); + return -EINVAL; + } + + hw_bits =3D mtk_pci_ext_h2d_evt_hw_bits(ch); + mtk_pci_write32(mdev, rc_base + MHCCIF_RC2EP_SW_BSY, hw_bits); + mtk_pci_write32(mdev, rc_base + MHCCIF_RC2EP_SW_TCHNUM, ffs(hw_bits) - 1); + return 0; +} + +static u32 mtk_pci_get_ext_evt_hw_status(struct mtk_md_dev *mdev) +{ + struct mtk_pci_priv *priv =3D mdev->hw_priv; + + return mtk_pci_read32(mdev, priv->cfg->mhccif_rc_base_addr + + MHCCIF_EP2RC_SW_INT_STS); +} + +/** + * mtk_pci_fldr() - Perform a Function Level Device Reset via ACPI _RST + * @mdev: MTK MD device + * + * Return: 0 on success, negative error code on failure. + */ +int mtk_pci_fldr(struct mtk_md_dev *mdev) +{ +#ifdef CONFIG_ACPI + struct acpi_buffer buffer =3D { ACPI_ALLOCATE_BUFFER, NULL }; + acpi_status acpi_ret; + acpi_handle handle; + + if (acpi_disabled) { + dev_err((mdev)->dev, "Unsupported, acpi function isn't enable\n"); + return -ENODEV; + } + + handle =3D ACPI_HANDLE(mdev->dev); + + if (!handle) { + dev_err((mdev)->dev, "Unsupported, acpi handle isn't found\n"); + return -ENODEV; + } + + if (!acpi_has_method(handle, "_RST")) { + dev_err((mdev)->dev, "Unsupported, _RST method isn't found\n"); + return -ENODEV; + } + + acpi_ret =3D acpi_evaluate_object(handle, "_RST", NULL, &buffer); + if (ACPI_FAILURE(acpi_ret)) { + dev_err((mdev)->dev, "Failed to execute _RST method: %s\n", + acpi_format_exception(acpi_ret)); + return -EFAULT; + } + + acpi_os_free(buffer.pointer); + + return 0; +#else /* !CONFIG_ACPI */ + dev_err((mdev)->dev, "Unsupported, CONFIG ACPI hasn't been set to 'y'\n"); + + return -ENODEV; +#endif /* !CONFIG_ACPI */ +} + +/** + * mtk_pci_pldr() - Perform a PCIe Link Down Reset via ACPI PXP._OFF/_ON + * @mdev: MTK MD device + * + * Return: 0 on success, negative error code on failure. + */ +int mtk_pci_pldr(struct mtk_md_dev *mdev) +{ +#ifdef CONFIG_ACPI + struct acpi_buffer buffer =3D { ACPI_ALLOCATE_BUFFER, NULL }; + struct pci_dev *bridge; + acpi_status acpi_ret; + acpi_handle handle; + + if (acpi_disabled) { + dev_err((mdev)->dev, "Unsupported, acpi function isn't enable\n"); + return -ENODEV; + } + + bridge =3D pci_upstream_bridge(to_pci_dev(mdev->dev)); + if (!bridge) { + dev_err((mdev)->dev, "Unable to find bridge\n"); + return -ENODEV; + } + + handle =3D ACPI_HANDLE(&bridge->dev); + if (!handle) { + dev_err((mdev)->dev, "Unsupported, acpi handle isn't found\n"); + return -ENODEV; + } + if (!acpi_has_method(handle, "PXP._OFF") || + !acpi_has_method(handle, "PXP._ON")) { + dev_err((mdev)->dev, "Unsupported, pldr method isn't supported\n"); + return -ENODEV; + } + acpi_ret =3D acpi_evaluate_object(handle, "PXP._OFF", NULL, &buffer); + if (ACPI_FAILURE(acpi_ret)) { + dev_err((mdev)->dev, "Failed to execute _OFF method: %s\n", + acpi_format_exception(acpi_ret)); + return -EFAULT; + } + acpi_os_free(buffer.pointer); + + msleep(MTK_PLDR_POWER_OFF_DELAY_MS); + + buffer.length =3D ACPI_ALLOCATE_BUFFER; + buffer.pointer =3D NULL; + acpi_ret =3D acpi_evaluate_object(handle, "PXP._ON", NULL, &buffer); + if (ACPI_FAILURE(acpi_ret)) { + dev_err((mdev)->dev, "Failed to execute _ON method: %s\n", + acpi_format_exception(acpi_ret)); + return -EFAULT; + } + acpi_os_free(buffer.pointer); + + return 0; +#else + dev_err((mdev)->dev, "Unsupported, CONFIG ACPI hasn't been set to 'y'\n"); + + return -ENODEV; +#endif +} + +/** + * mtk_pci_get_dev_cfg() - Read the device configuration from the modem + * @mdev: MTK MD device + * + * Return: Device configuration value. + */ +u32 mtk_pci_get_dev_cfg(struct mtk_md_dev *mdev) +{ + u32 val; + + val =3D mtk_pci_mac_read32(mdev->hw_priv, REG_PCIE_DEBUG_DUMMY_4); + return (val >> MTK_CFG_INFO_BIT_SHIFT); +} + +static int mtk_pci_dev_reset(struct mtk_md_dev *mdev, enum mtk_reset_type = type) +{ + switch (type) { + case RESET_MHCCIF: + return mtk_pci_send_ext_evt(mdev, DEV_EVT_H2D_DEVICE_RESET); + case RESET_FLDR: + return mtk_pci_fldr(mdev); + case RESET_PLDR: + return mtk_pci_pldr(mdev); + default: + return -EINVAL; + } +} + +/** + * mtk_pci_reset() - Reset the modem device + * @mdev: MTK MD device + * @type: Reset type (MHCCIF, FLDR, or PLDR) + * + * Return: 0 on success, negative error code on failure. + */ +int mtk_pci_reset(struct mtk_md_dev *mdev, enum mtk_reset_type type) +{ + return mtk_pci_dev_reset(mdev, type); +} + +/** + * mtk_pci_link_check() - Check if the PCIe link to the modem is active + * @mdev: MTK MD device + * + * Return: true if the device is present, false otherwise. + */ +bool mtk_pci_link_check(struct mtk_md_dev *mdev) +{ + return pci_device_is_present(to_pci_dev(mdev->dev)); +} + +static void mtk_mhccif_isr_work(struct work_struct *work) +{ + struct mtk_pci_priv *priv =3D + container_of(work, struct mtk_pci_priv, mhccif_work); + struct mtk_md_dev *mdev =3D priv->irq_desc->mdev; + struct mtk_mhccif_cb *cb; + u32 stat, mask, chs; + + stat =3D mtk_pci_get_ext_evt_hw_status(mdev); + mask =3D mtk_pci_read32(mdev, priv->cfg->mhccif_rc_base_addr + + MHCCIF_EP2RC_SW_INT_EAP_MASK); + if (unlikely(stat =3D=3D U32_MAX && !(mtk_pci_link_check(mdev)))) { + /* When link failed, we don't need to unmask/clear. */ + dev_err((mdev)->dev, "Failed to check link in MHCCIF handler.\n"); + return; + } + + stat &=3D ~mask; + chs =3D mtk_pci_ext_d2h_evt_chs(stat); + spin_lock_bh(&priv->mhccif_lock); + list_for_each_entry(cb, &priv->mhccif_cb_list, entry) { + if (cb->chs & chs) + cb->evt_cb(cb->chs & chs, cb->data); + } + spin_unlock_bh(&priv->mhccif_lock); + + mtk_pci_clear_irq(mdev, priv->mhccif_irq_id); + mtk_pci_unmask_irq(mdev, priv->mhccif_irq_id); +} + +static const struct pci_device_id t9xx_pci_table[] =3D { + MTK_PCI_DEV_CFG(0x0900, mtk_dev_cfg_0900), + CEI_PCI_DEV_CFG(0x01CA, mtk_dev_cfg_0900), + {/* end: all zeroes */} +}; + +MODULE_DEVICE_TABLE(pci, t9xx_pci_table); + +static int mtk_pci_bar_init(struct mtk_md_dev *mdev) +{ + struct pci_dev *pdev =3D to_pci_dev(mdev->dev); + struct mtk_pci_priv *priv =3D mdev->hw_priv; + u32 bar[MTK_PCI_BAR_NUM]; + int i, ret; + + for (i =3D 0; i < MTK_PCI_BAR_NUM; i++) + pci_read_config_dword(to_pci_dev(mdev->dev), + PCI_BASE_ADDRESS_0 + (i << 2), bar + i); + + ret =3D pcim_iomap_regions(pdev, MTK_REQUESTED_BARS, mdev->dev_str); + if (ret) { + dev_err((mdev)->dev, "Failed to init MMIO. ret=3D%d\n", ret); + return ret; + } + + /* get ioremapped memory */ + priv->mac_reg_base =3D pcim_iomap_table(pdev)[MTK_BAR_0_1_IDX]; + priv->bar23_addr =3D pcim_iomap_table(pdev)[MTK_BAR_2_3_IDX]; + if (!priv->mac_reg_base || !priv->bar23_addr) { + dev_err((mdev)->dev, "Failed to init BAR.\n"); + return -EINVAL; + } + /* We use MD view base address "0" to observe registers */ + priv->ext_reg_base =3D priv->bar23_addr - ATR_PCIE_REG_TRSL_ADDR; + + return 0; +} + +static void mtk_pci_bar_exit(struct mtk_md_dev *mdev) +{ + pcim_iounmap_region(to_pci_dev(mdev->dev), MTK_REQUESTED_BARS); +} + +static int mtk_mhccif_irq_cb(int irq_id, void *data) +{ + struct mtk_md_dev *mdev =3D data; + struct mtk_pci_priv *priv; + + priv =3D mdev->hw_priv; + queue_work(system_highpri_wq, &priv->mhccif_work); + + return 0; +} + +static int mtk_mhccif_init(struct mtk_md_dev *mdev) +{ + struct mtk_pci_priv *priv =3D mdev->hw_priv; + int ret; + + INIT_LIST_HEAD(&priv->mhccif_cb_list); + spin_lock_init(&priv->mhccif_lock); + INIT_WORK(&priv->mhccif_work, mtk_mhccif_isr_work); + + ret =3D mtk_pci_get_irq_id(mdev, MTK_IRQ_SRC_MHCCIF); + if (ret < 0) { + dev_err((mdev)->dev, "Failed to get mhccif_irq_id. ret=3D%d\n", ret); + return ret; + } + priv->mhccif_irq_id =3D ret; + + ret =3D mtk_pci_register_irq(mdev, priv->mhccif_irq_id, mtk_mhccif_irq_cb= , mdev); + if (ret) { + dev_err((mdev)->dev, "Failed to register mhccif_irq callback\n"); + return ret; + } + + return 0; +} + +static void mtk_mhccif_exit(struct mtk_md_dev *mdev) +{ + struct mtk_pci_priv *priv =3D mdev->hw_priv; + + mtk_pci_unregister_irq(mdev, priv->mhccif_irq_id); + cancel_work_sync(&priv->mhccif_work); +} + +static irqreturn_t mtk_pci_irq_handler(struct mtk_md_dev *mdev, u32 irq_st= ate) +{ + struct mtk_pci_priv *priv =3D mdev->hw_priv; + int irq_id; + + /* Check whether each set bit has a callback, if has, call it */ + do { + irq_id =3D fls(irq_state) - 1; + irq_state &=3D ~BIT(irq_id); + if (likely(priv->irq_cb_list[irq_id])) + priv->irq_cb_list[irq_id](irq_id, priv->irq_cb_data[irq_id]); + else + dev_err((mdev)->dev, "Unhandled irq_id=3D%d, no callback for it.\n", ir= q_id); + } while (irq_state); + + return IRQ_HANDLED; +} + +static irqreturn_t mtk_pci_irq_msix(int irq, void *data) +{ + struct mtk_pci_irq_desc *irq_desc =3D data; + struct mtk_md_dev *mdev =3D irq_desc->mdev; + struct mtk_pci_priv *priv; + u32 irq_state, irq_enable; + + priv =3D mdev->hw_priv; + irq_state =3D mtk_pci_mac_read32(priv, REG_MSIX_ISTATUS_HOST_GRP0_0); + irq_enable =3D mtk_pci_mac_read32(priv, REG_IMASK_HOST_MSIX_GRP0_0); + irq_state &=3D irq_enable; + + if (unlikely(!irq_state) || + unlikely(!((irq_state & GENMASK(priv->irq_cnt - 1, 0)) & + irq_desc->msix_bits))) + return IRQ_NONE; + + /* Mask the bit and user needs to unmask by itself */ + mtk_pci_mac_write32(priv, REG_IMASK_HOST_MSIX_CLR_GRP0_0, + irq_state & ~BIT(30)); + + return mtk_pci_irq_handler(mdev, irq_state); +} + +static int mtk_pci_request_irq_msix(struct mtk_md_dev *mdev, + int irq_cnt_allocated) +{ + struct mtk_pci_priv *priv =3D mdev->hw_priv; + struct mtk_pci_irq_desc *irq_desc; + struct pci_dev *pdev; + int irq_cnt; + int ret, i; + + /* calculate the nearest 2's power number */ + irq_cnt =3D BIT(fls(irq_cnt_allocated) - 1); + pdev =3D to_pci_dev(mdev->dev); + irq_desc =3D priv->irq_desc; + for (i =3D 0; i < irq_cnt; i++) { + irq_desc[i].mdev =3D mdev; + irq_desc[i].msix_bits =3D BIT(i); + snprintf(irq_desc[i].name, MTK_IRQ_NAME_LEN, "msix%d-%s", i, mdev->dev_s= tr); + ret =3D pci_request_irq(pdev, i, mtk_pci_irq_msix, NULL, + &irq_desc[i], irq_desc[i].name); + if (ret) { + dev_err((mdev)->dev, "Failed to request %s: ret=3D%d\n", + irq_desc[i].name, ret); + for (i--; i >=3D 0; i--) + pci_free_irq(pdev, i, &irq_desc[i]); + return ret; + } + } + priv->irq_cnt =3D irq_cnt; + priv->irq_type =3D PCI_IRQ_MSIX; + + if (irq_cnt !=3D MTK_IRQ_CNT_MAX) + mtk_pci_set_msix_merged(priv, irq_cnt); + + return 0; +} + +static int mtk_pci_request_irq(struct mtk_md_dev *mdev) +{ + struct pci_dev *pdev =3D to_pci_dev(mdev->dev); + int irq_cnt, ret; + + irq_cnt =3D pci_alloc_irq_vectors(pdev, MTK_IRQ_CNT_MIN, + MTK_IRQ_CNT_MAX, PCI_IRQ_MSIX); + + if (irq_cnt < MTK_IRQ_CNT_MIN) { + dev_err(mdev->dev, + "Unable to alloc pci irq vectors. ret=3D%d maxirqcnt=3D%d irqtype=3D0x%= x\n", + irq_cnt, MTK_IRQ_CNT_MAX, PCI_IRQ_MSIX); + return -EFAULT; + } + + ret =3D mtk_pci_request_irq_msix(mdev, irq_cnt); + if (ret) + pci_free_irq_vectors(pdev); + + return ret; +} + +static void mtk_pci_free_irq(struct mtk_md_dev *mdev) +{ + struct pci_dev *pdev =3D to_pci_dev(mdev->dev); + struct mtk_pci_priv *priv =3D mdev->hw_priv; + int i; + + for (i =3D 0; i < priv->irq_cnt; i++) + pci_free_irq(pdev, i, &priv->irq_desc[i]); + + pci_free_irq_vectors(pdev); +} + +static const struct mtk_dev_ops pci_hw_ops =3D { + .get_dev_state =3D mtk_pci_get_dev_state, + .ack_dev_state =3D mtk_pci_ack_dev_state, + .get_dev_cfg =3D mtk_pci_get_dev_cfg, + .register_dev_evt =3D mtk_pci_register_ext_evt, + .unregister_dev_evt =3D mtk_pci_unregister_ext_evt, + .mask_dev_evt =3D mtk_pci_mask_ext_evt, + .unmask_dev_evt =3D mtk_pci_unmask_ext_evt, + .clear_dev_evt =3D mtk_pci_clear_ext_evt, + .send_dev_evt =3D mtk_pci_send_ext_evt, +}; + +static int mtk_pci_probe(struct pci_dev *pdev, const struct pci_device_id = *id) +{ + struct device *dev =3D &pdev->dev; + struct mtk_pci_priv *priv; + struct mtk_md_dev *mdev; + int ret; + + mdev =3D devm_kzalloc(dev, sizeof(*mdev), GFP_KERNEL); + if (!mdev) { + ret =3D -ENOMEM; + goto log_err; + } + mdev->dev_ops =3D &pci_hw_ops; + mdev->dev =3D dev; + + priv =3D devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) { + ret =3D -ENOMEM; + goto free_cntx_data; + } + + pci_set_drvdata(pdev, mdev); + priv->cfg =3D (void *)id->driver_data; + priv->mdev =3D mdev; + mdev->hw_ver =3D pdev->device; + mdev->hw_priv =3D priv; + mdev->dev =3D dev; + snprintf(mdev->dev_str, MTK_DEV_STR_LEN, "%02x%02x%d", + pdev->bus->number, PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn)); + if (pdev->state_saved) + pci_restore_state(pdev); + + ret =3D pcim_enable_device(pdev); + if (ret) { + dev_err((mdev)->dev, "Failed to enable pci device.\n"); + goto free_priv_data; + } + + ret =3D dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); + if (ret) { + dev_err((mdev)->dev, "Failed to set DMA Mask and Coherent. (ret=3D%d)\n"= , ret); + goto disable_device; + } + + ret =3D mtk_pci_bar_init(mdev); + if (ret) + goto disable_device; + + ret =3D priv->cfg->atr_init(mdev); + if (ret) + goto free_bar; + + ret =3D mtk_mhccif_init(mdev); + if (ret) + goto free_bar; + + /* mask all irqs */ + if (priv->cfg->flag & MTK_CFG_IRQ_DFLT_MASK) + mtk_pci_mac_write32(priv, REG_IMASK_HOST_MSIX_CLR_GRP0_0, U32_MAX); + + ret =3D mtk_pci_request_irq(mdev); + if (ret) + goto free_mhccif; + + pci_set_master(pdev); + mtk_pci_unmask_irq(mdev, priv->mhccif_irq_id); + + if (mtk_pci_link_check(mdev)) { + pci_save_state(pdev); + } else { + ret =3D -ENOLINK; + goto clear_master; + } + + priv->saved_state =3D pci_store_saved_state(pdev); + if (!priv->saved_state) { + ret =3D -EFAULT; + goto clear_master; + } + + return 0; + +clear_master: + pci_clear_master(pdev); + mtk_pci_free_irq(mdev); +free_mhccif: + mtk_mhccif_exit(mdev); +free_bar: + mtk_pci_bar_exit(mdev); +disable_device: + pci_disable_device(pdev); +free_priv_data: + devm_kfree(dev, priv); +free_cntx_data: + devm_kfree(dev, mdev); +log_err: + dev_err(dev, "Failed to probe device, ret=3D%d\n", ret); + + return ret; +} + +static void mtk_pci_remove(struct pci_dev *pdev) +{ + struct mtk_md_dev *mdev =3D pci_get_drvdata(pdev); + struct mtk_pci_priv *priv =3D mdev->hw_priv; + struct device *dev =3D &pdev->dev; + + mtk_pci_mask_irq(mdev, priv->mhccif_irq_id); + + if (mtk_pci_pldr(mdev)) { + dev_warn(dev, "Failed to execute PLDR, try external event\n"); + mtk_pci_reset(mdev, RESET_MHCCIF); + } + + pci_clear_master(pdev); + mtk_pci_free_irq(mdev); + mtk_mhccif_exit(mdev); + mtk_pci_bar_exit(mdev); + pci_disable_device(pdev); + pci_load_and_free_saved_state(pdev, &priv->saved_state); + + devm_kfree(dev, priv); + devm_kfree(dev, mdev); +} + +static pci_ers_result_t mtk_pci_error_detected(struct pci_dev *pdev, + pci_channel_state_t state) +{ + struct mtk_md_dev *mdev =3D pci_get_drvdata(pdev); + + dev_err((mdev)->dev, "AER detected: pci_channel_state_t=3D%d\n", state); + + /* Request a slot reset. */ + return PCI_ERS_RESULT_CAN_RECOVER; +} + +static const struct pci_error_handlers mtk_pci_err_handler =3D { + .error_detected =3D mtk_pci_error_detected, +}; + +static struct pci_driver mtk_pci_drv =3D { + .name =3D "mtk_pci_drv", + .id_table =3D t9xx_pci_table, + .probe =3D mtk_pci_probe, + .remove =3D mtk_pci_remove, + .err_handler =3D &mtk_pci_err_handler +}; + +module_pci_driver(mtk_pci_drv); + +MODULE_DESCRIPTION("MediaTek T9xx PCIe WWAN driver pcie layer"); +MODULE_LICENSE("GPL"); diff --git a/drivers/net/wwan/t9xx/pcie/mtk_pci.h b/drivers/net/wwan/t9xx/p= cie/mtk_pci.h new file mode 100644 index 000000000000..0c64636cb96b --- /dev/null +++ b/drivers/net/wwan/t9xx/pcie/mtk_pci.h @@ -0,0 +1,232 @@ +/* SPDX-License-Identifier: GPL-2.0-only + * + * Copyright (c) 2022, MediaTek Inc. + */ + +#ifndef __MTK_PCI_H__ +#define __MTK_PCI_H__ + +#include + +#include "../mtk_dev.h" + +enum mtk_irq_src { + MTK_IRQ_SRC_MIN, + MTK_IRQ_SRC_MHCCIF, + MTK_IRQ_SRC_DPMAIF, + MTK_IRQ_SRC_DPMAIF2, + MTK_IRQ_SRC_CLDMA0, + MTK_IRQ_SRC_CLDMA1, + MTK_IRQ_SRC_CLDMA2, + MTK_IRQ_SRC_CLDMA3, + MTK_IRQ_SRC_PM_LOCK, + MTK_IRQ_SRC_DPMAIF3, + MTK_IRQ_SRC_DPMAIF6, + MTK_IRQ_SRC_MAX +}; + +enum mtk_reset_type { + RESET_FLDR, + RESET_PLDR, + RESET_MHCCIF, +}; + +enum mtk_atr_type { + ATR_PCI2AXI =3D 0, + ATR_AXI2PCI, +}; + +enum mtk_atr_src_port { + ATR_SRC_PCI_WIN0 =3D 0, + ATR_SRC_PCI_WIN1, + ATR_SRC_AXIS_0, + ATR_SRC_AXIS_1, + ATR_SRC_AXIS_2, + ATR_SRC_AXIS_3, +}; + +enum mtk_atr_dst_port { + ATR_DST_PCI_TRX =3D 0, + ATR_DST_AXIM_0 =3D 4, + ATR_DST_AXIM_1, + ATR_DST_AXIM_2, + ATR_DST_AXIM_3, +}; + +enum mtk_pci_evt_h2d { + DEV_EVT_H2D_EXTEND_BASE =3D DEV_EVT_H2D_MAX, + EXT_EVT_H2D_RESERVED_FOR_CLDMA0 =3D DEV_EVT_H2D_EXTEND_BASE << 1, + EXT_EVT_H2D_RESERVED_FOR_CLDMA1 =3D DEV_EVT_H2D_EXTEND_BASE << 2, + EXT_EVT_H2D_RESERVED_FOR_CLDMA3 =3D DEV_EVT_H2D_EXTEND_BASE << 3, + EXT_EVT_H2D_RESERVED_FOR_CLDMA2 =3D DEV_EVT_H2D_EXTEND_BASE << 4, + EXT_EVT_H2D_RESERVED_FOR_DPMAIF =3D DEV_EVT_H2D_EXTEND_BASE << 5, + EXT_EVT_H2D_PCIE_PM_SUSPEND_REQ =3D DEV_EVT_H2D_EXTEND_BASE << 6, + EXT_EVT_H2D_PCIE_PM_RESUME_REQ =3D DEV_EVT_H2D_EXTEND_BASE << 7, + EXT_EVT_H2D_PCIE_PM_SUSPEND_REQ_AP =3D DEV_EVT_H2D_EXTEND_BASE << 8, + EXT_EVT_H2D_PCIE_PM_RESUME_REQ_AP =3D DEV_EVT_H2D_EXTEND_BASE << 9, + EXT_EVT_H2D_RESERVED_FOR_TEST =3D DEV_EVT_H2D_EXTEND_BASE << 11, +}; + +enum mtk_pci_evt_d2h { + DEV_EVT_D2H_EXTEND_BASE =3D DEV_EVT_D2H_MAX, + EXT_EVT_D2H_RESERVED_FOR_CLDMA0 =3D DEV_EVT_D2H_EXTEND_BASE << 1, + EXT_EVT_D2H_RESERVED_FOR_CLDMA1 =3D DEV_EVT_D2H_EXTEND_BASE << 2, + EXT_EVT_D2H_RESERVED_FOR_CLDMA3 =3D DEV_EVT_D2H_EXTEND_BASE << 3, + EXT_EVT_D2H_RESERVED_FOR_CLDMA2 =3D DEV_EVT_D2H_EXTEND_BASE << 4, + EXT_EVT_D2H_RESERVED_FOR_DPMAIF =3D DEV_EVT_D2H_EXTEND_BASE << 5, + EXT_EVT_D2H_PCIE_PM_SUSPEND_ACK =3D DEV_EVT_D2H_EXTEND_BASE << 6, + EXT_EVT_D2H_PCIE_PM_RESUME_ACK =3D DEV_EVT_D2H_EXTEND_BASE << 7, + EXT_EVT_D2H_PCIE_PM_SUSPEND_ACK_AP =3D DEV_EVT_D2H_EXTEND_BASE << 8, + EXT_EVT_D2H_PCIE_PM_RESUME_ACK_AP =3D DEV_EVT_D2H_EXTEND_BASE << 9, + EXT_EVT_D2H_SOFT_OFF_NOTIFY =3D DEV_EVT_D2H_EXTEND_BASE << 10, + EXT_EVT_D2H_FRC_DONE_NOTIFY =3D DEV_EVT_D2H_EXTEND_BASE << 11, + EXT_EVT_D2H_RESERVED_FOR_TEST1 =3D DEV_EVT_D2H_EXTEND_BASE << 12, + EXT_EVT_D2H_RESERVED_FOR_TEST2 =3D DEV_EVT_D2H_EXTEND_BASE << 13, +}; + +#define MTK_PCI_CLASS 0x0D4000 +#define MTK_PCI_VENDOR_ID 0x14C3 +#define CEI_PCI_VENDOR_ID 0x03F0 + +#define MTK_CFG_INFO_BIT_SHIFT 4 + +#define MTK_PCI_DEV_CFG(id, cfg) \ +{ \ + PCI_DEVICE(MTK_PCI_VENDOR_ID, id), \ + MTK_PCI_CLASS, PCI_ANY_ID, \ + .driver_data =3D (kernel_ulong_t)&(cfg), \ +} + +#define CEI_PCI_DEV_CFG(id, cfg) \ +{ \ + PCI_DEVICE(CEI_PCI_VENDOR_ID, id), \ + MTK_PCI_CLASS, PCI_ANY_ID, \ + .driver_data =3D (kernel_ulong_t)&(cfg), \ +} + +#define MTK_CFG_IRQ_DFLT_MASK BIT(0) +#define MTK_CFG_DISABLE_AP_DRM BIT(2) +#define MTK_CFG_PM_SW_IRQ BIT(6) + +#define MTK_BAR_0_1_IDX 0 +#define MTK_BAR_2_3_IDX 2 + +#define MTK_REQUESTED_BARS \ + ((1 << MTK_BAR_0_1_IDX) | \ + (1 << MTK_BAR_2_3_IDX)) + +#define MTK_IRQ_CNT_MIN 1 +#define MTK_IRQ_CNT_MAX 32 +#define MTK_IRQ_NAME_LEN 32 + +#define ATR_PORT_OFFSET 0x100 +#define ATR_TABLE_OFFSET 0x20 +#define ATR_TABLE_NUM_PER_ATR 8 +#define ATR_PCIE_REG_TRSL_ADDR 0x10000000 +#define ATR_PCIE_REG_SIZE 0x00400000 +#define ATR_PCIE_REG_PORT ATR_SRC_PCI_WIN0 +#define ATR_PCIE_REG_TABLE_NUM 1 +#define ATR_PCIE_REG_TRSL_PORT ATR_DST_AXIM_0 +#define ATR_PCIE_DEV_DMA_SRC_ADDR 0x00000000 +#define ATR_PCIE_DEV_DMA_TRANSPARENT 1 +#define ATR_PCIE_DEV_DMA_SIZE 0 +#define ATR_PCIE_DEV_DMA_TABLE_NUM 0 +#define ATR_PCIE_DEV_DMA_TRSL_ADDR 0x00000000 + +struct mtk_pci_irq_desc { + struct mtk_md_dev *mdev; + u32 msix_bits; + char name[MTK_IRQ_NAME_LEN]; +}; + +struct mtk_pci_dev_cfg { + u32 flag; + u32 mhccif_rc_base_addr; + u32 istatus_host_ctrl_addr; + int irq_tbl[MTK_IRQ_SRC_MAX]; + int (*atr_init)(struct mtk_md_dev *mdev); +}; + +struct mtk_pci_priv { + struct mtk_md_dev *mdev; + const struct mtk_pci_dev_cfg *cfg; + void __iomem *bar23_addr; + void __iomem *mac_reg_base; + void __iomem *ext_reg_base; + int irq_cnt; + int irq_type; + void *irq_cb_data[MTK_IRQ_CNT_MAX]; + + int (*irq_cb_list[MTK_IRQ_CNT_MAX])(int irq_id, void *data); + struct mtk_pci_irq_desc irq_desc[MTK_IRQ_CNT_MAX]; + struct list_head mhccif_cb_list; + /* mhccif_lock: lock to protect mhccif_cb_list */ + spinlock_t mhccif_lock; + struct work_struct mhccif_work; + int mhccif_irq_id; + struct pci_saved_state *saved_state; +}; + +struct mtk_atr_cfg { + u64 src_addr; + u64 trsl_addr; + u64 size; + u32 type; /* Port type */ + u32 port; /* Port number */ + u32 table; /* Table number (8 tables for each port) */ + u32 trsl_id; + u32 trsl_param; + u32 transparent; +}; + +/* BAR 0/1 MMIO access */ +static inline u32 mtk_pci_mac_read32(struct mtk_pci_priv *priv, u64 addr) +{ + return ioread32(priv->mac_reg_base + addr); +} + +static inline void mtk_pci_mac_write32(struct mtk_pci_priv *priv, u64 addr= , u32 val) +{ + iowrite32(val, priv->mac_reg_base + addr); +} + +/* BAR 2/3 MMIO access */ +static inline u32 mtk_pci_read32(struct mtk_md_dev *mdev, u64 addr) +{ + return ioread32(((struct mtk_pci_priv *)mdev->hw_priv)->ext_reg_base + ad= dr); +} + +static inline void mtk_pci_write32(struct mtk_md_dev *mdev, u64 addr, u32 = val) +{ + iowrite32(val, ((struct mtk_pci_priv *)mdev->hw_priv)->ext_reg_base + add= r); +} + +/* Device operations */ +u32 mtk_pci_get_dev_state(struct mtk_md_dev *mdev); +void mtk_pci_ack_dev_state(struct mtk_md_dev *mdev, u32 state); +u32 mtk_pci_get_dev_cfg(struct mtk_md_dev *mdev); +/* IRQ Related operations */ +int mtk_pci_get_irq_id(struct mtk_md_dev *mdev, enum mtk_irq_src irq_src); +int mtk_pci_get_virq_id(struct mtk_md_dev *mdev, int irq_id); +int mtk_pci_register_irq(struct mtk_md_dev *mdev, int irq_id, + int (*irq_cb)(int irq_id, void *data), void *data); +int mtk_pci_unregister_irq(struct mtk_md_dev *mdev, int irq_id); +int mtk_pci_mask_irq(struct mtk_md_dev *mdev, int irq_id); +int mtk_pci_unmask_irq(struct mtk_md_dev *mdev, int irq_id); +int mtk_pci_clear_irq(struct mtk_md_dev *mdev, int irq_id); +/* External event related */ +int mtk_pci_register_ext_evt(struct mtk_md_dev *mdev, u32 chs, + int (*evt_cb)(u32 status, void *data), void *data); +void mtk_pci_unregister_ext_evt(struct mtk_md_dev *mdev, u32 chs); +void mtk_pci_mask_ext_evt(struct mtk_md_dev *mdev, u32 chs); +void mtk_pci_unmask_ext_evt(struct mtk_md_dev *mdev, u32 chs); +void mtk_pci_clear_ext_evt(struct mtk_md_dev *mdev, u32 chs); +int mtk_pci_send_ext_evt(struct mtk_md_dev *mdev, u32 ch); +int mtk_pci_fldr(struct mtk_md_dev *mdev); +int mtk_pci_pldr(struct mtk_md_dev *mdev); +int mtk_pci_reset(struct mtk_md_dev *mdev, enum mtk_reset_type type); +bool mtk_pci_link_check(struct mtk_md_dev *mdev); +int mtk_pci_setup_atr(struct mtk_md_dev *mdev, struct mtk_atr_cfg *cfg); +void mtk_pci_atr_disable(struct mtk_pci_priv *priv); + +#endif /* __MTK_PCI_H__ */ diff --git a/drivers/net/wwan/t9xx/pcie/mtk_pci_drv_m9xx.c b/drivers/net/ww= an/t9xx/pcie/mtk_pci_drv_m9xx.c new file mode 100644 index 000000000000..88b44142afb7 --- /dev/null +++ b/drivers/net/wwan/t9xx/pcie/mtk_pci_drv_m9xx.c @@ -0,0 +1,69 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022, MediaTek Inc. + */ +#include +#include "mtk_pci.h" +#include "mtk_pci_reg.h" + +static int mtk_pci_atr_init_m9xx(struct mtk_md_dev *mdev) +{ + struct pci_dev *pdev =3D to_pci_dev(mdev->dev); + struct mtk_pci_priv *priv =3D mdev->hw_priv; + struct mtk_atr_cfg cfg; + int port, ret; + + mtk_pci_atr_disable(priv); + + /* Config ATR for RC to access device's register */ + cfg.src_addr =3D pci_resource_start(pdev, MTK_BAR_2_3_IDX); + cfg.size =3D ATR_PCIE_REG_SIZE; + cfg.trsl_addr =3D ATR_PCIE_REG_TRSL_ADDR; + cfg.type =3D ATR_PCI2AXI; + cfg.port =3D ATR_PCIE_REG_PORT; + cfg.table =3D ATR_PCIE_REG_TABLE_NUM; + cfg.trsl_id =3D ATR_PCIE_REG_TRSL_PORT; + cfg.trsl_param =3D 0x0; + cfg.transparent =3D 0x0; + ret =3D mtk_pci_setup_atr(mdev, &cfg); + if (ret) + return ret; + + /* Config ATR for EP to access RC's memory */ + for (port =3D ATR_SRC_AXIS_0; port <=3D ATR_SRC_AXIS_3; port++) { + cfg.src_addr =3D ATR_PCIE_DEV_DMA_SRC_ADDR; + cfg.size =3D ATR_PCIE_DEV_DMA_SIZE; + cfg.trsl_addr =3D ATR_PCIE_DEV_DMA_TRSL_ADDR; + cfg.type =3D ATR_AXI2PCI; + cfg.port =3D port; + cfg.table =3D ATR_PCIE_DEV_DMA_TABLE_NUM; + cfg.trsl_id =3D ATR_DST_PCI_TRX; + cfg.trsl_param =3D 0x0; + /* Enable transparent translation */ + cfg.transparent =3D ATR_PCIE_DEV_DMA_TRANSPARENT; + ret =3D mtk_pci_setup_atr(mdev, &cfg); + if (ret) + return ret; + } + + return 0; +} + +const struct mtk_pci_dev_cfg mtk_dev_cfg_0900 =3D { + .flag =3D MTK_CFG_PM_SW_IRQ, + .mhccif_rc_base_addr =3D 0x1000A000, + .istatus_host_ctrl_addr =3D REG_ISTATUS_HOST_CTRL_NEW, + .irq_tbl =3D { + [MTK_IRQ_SRC_DPMAIF] =3D 24, + [MTK_IRQ_SRC_CLDMA0] =3D 27, + [MTK_IRQ_SRC_CLDMA1] =3D 26, + [MTK_IRQ_SRC_CLDMA2] =3D 25, + [MTK_IRQ_SRC_MHCCIF] =3D 28, + [MTK_IRQ_SRC_DPMAIF2] =3D 29, + [MTK_IRQ_SRC_CLDMA3] =3D 31, + [MTK_IRQ_SRC_PM_LOCK] =3D 0, + [MTK_IRQ_SRC_DPMAIF3] =3D 7, + [MTK_IRQ_SRC_DPMAIF6] =3D 10, + }, + .atr_init =3D mtk_pci_atr_init_m9xx, +}; diff --git a/drivers/net/wwan/t9xx/pcie/mtk_pci_reg.h b/drivers/net/wwan/t9= xx/pcie/mtk_pci_reg.h new file mode 100644 index 000000000000..3f0667e8a846 --- /dev/null +++ b/drivers/net/wwan/t9xx/pcie/mtk_pci_reg.h @@ -0,0 +1,70 @@ +/* SPDX-License-Identifier: GPL-2.0-only + * + * Copyright (c) 2022, MediaTek Inc. + */ + +#ifndef __MTK_PCI_REG_H__ +#define __MTK_PCI_REG_H__ + +#define REG_ISTATUS_HOST_CTRL_NEW 0x031C +#define REG_PCIE_MISC_CTRL 0x0348 +#define REG_PCIE_CFG_MSIX 0x03EC +#define REG_ATR_PCIE_WIN0_T0_SRC_ADDR_LSB 0x0600 +#define REG_ATR_PCIE_WIN0_T0_SRC_ADDR_MSB 0x0604 +#define REG_ATR_PCIE_WIN0_T0_TRSL_ADDR_LSB 0x0608 +#define REG_ATR_PCIE_WIN0_T0_TRSL_ADDR_MSB 0x060C +#define REG_ATR_PCIE_WIN0_T0_TRSL_PARAM 0x0610 +#define REG_PCIE_DEBUG_DUMMY_3 0x0D0C +#define REG_PCIE_DEBUG_DUMMY_4 0x0D10 +#define REG_PCIE_DEBUG_DUMMY_7 0x0D1C +#define REG_MSIX_ISTATUS_HOST_GRP0_0 0x0F00 +#define REG_IMASK_HOST_MSIX_SET_GRP0_0 0x3000 +#define REG_IMASK_HOST_MSIX_CLR_GRP0_0 0x3080 +#define REG_IMASK_HOST_MSIX_GRP0_0 0x3100 + +/* mhccif registers */ +#define MHCCIF_RC2EP_SW_BSY 0x4 +#define MHCCIF_RC2EP_SW_TCHNUM 0xC +#define MHCCIF_RC2EP_EVT_RESERVED_FOR_CLDMA0 BIT(4) +#define MHCCIF_RC2EP_EVT_RESERVED_FOR_CLDMA1 BIT(5) +#define MHCCIF_RC2EP_EVT_RESERVED_FOR_CLDMA3 BIT(6) +#define MHCCIF_RC2EP_EVT_RESERVED_FOR_CLDMA2 BIT(7) +#define MHCCIF_RC2EP_EVT_RESERVED_FOR_DPMAIF BIT(8) +#define MHCCIF_RC2EP_EVT_PCIE_PM_SUSPEND_REQ BIT(9) +#define MHCCIF_RC2EP_EVT_PCIE_PM_RESUME_REQ BIT(10) +#define MHCCIF_RC2EP_EVT_PCIE_PM_SUSPEND_REQ_AP BIT(11) +#define MHCCIF_RC2EP_EVT_PCIE_PM_RESUME_REQ_AP BIT(12) +#define MHCCIF_RC2EP_EVT_DEVICE_RESET BIT(13) +#define MHCCIF_RC2EP_EVT_RESERVED_FOR_TEST BIT(31) + +#define MHCCIF_EP2RC_SW_INT_STS 0x10 +#define MHCCIF_EP2RC_SW_INT_ACK 0x14 +#define MHCCIF_EP2RC_SW_INT_EAP_MASK 0x20 +#define MHCCIF_EP2RC_SW_INT_EAP_MASK_SET 0x30 +#define MHCCIF_EP2RC_SW_INT_EAP_MASK_CLR 0x40 +#define MHCCIF_EP2RC_SPARE_REG_1 0x0104 +#define MHCCIF_EP2RC_SPARE_REG_5 0x0114 +#define MHCCIF_EP2RC_SPARE_REG_13 0x0134 +#define MHCCIF_EP2RC_SPARE_REG_14 0x0138 +#define MHCCIF_EP2RC_EVT_BOOT_FLOW_SYNC BIT(5) +#define MHCCIF_EP2RC_EVT_RESERVED_FOR_CLDMA0 BIT(6) +#define MHCCIF_EP2RC_EVT_RESERVED_FOR_CLDMA1 BIT(7) +#define MHCCIF_EP2RC_EVT_RESERVED_FOR_CLDMA3 BIT(8) +#define MHCCIF_EP2RC_EVT_RESERVED_FOR_CLDMA2 BIT(9) +#define MHCCIF_EP2RC_EVT_RESERVED_FOR_DPMAIF BIT(10) +#define MHCCIF_EP2RC_EVT_PCIE_PM_SUSPEND_ACK BIT(11) +#define MHCCIF_EP2RC_EVT_PCIE_PM_RESUME_ACK BIT(12) +#define MHCCIF_EP2RC_EVT_PCIE_PM_SUSPEND_ACK_AP BIT(13) +#define MHCCIF_EP2RC_EVT_PCIE_PM_RESUME_ACK_AP BIT(14) +#define MHCCIF_EP2RC_EVT_ASYNC_HS_NOTIFY_SAP BIT(15) +#define MHCCIF_EP2RC_EVT_ASYNC_HS_NOTIFY_MD BIT(16) +#define MHCCIF_EP2RC_EVT_SOFT_OFF_NOTIFY BIT(17) +#define MHCCIF_EP2RC_EVT_MD_REBOOT BIT(19) +#define MHCCIF_EP2RC_EVT_MD_POWEROFF BIT(20) +#define MHCCIF_EP2RC_EVT_GNSS_ENABLE BIT(21) +#define MHCCIF_EP2RC_EVT_GNSS_DISABLE BIT(22) +#define MHCCIF_EP2RC_EVT_FRC_DONE_NOTIFY BIT(24) +#define MHCCIF_EP2RC_EVT_RESERVED_FOR_TEST1 BIT(30) +#define MHCCIF_EP2RC_EVT_RESERVED_FOR_TEST2 BIT(31) + +#endif /* __MTK_PCI_REG_H__ */ --=20 2.34.1 From nobody Wed Jun 10 17:22:13 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B24BD3F7884; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Msfzxnst" Received: by smtp.kernel.org (Postfix) with ESMTPS id 3B2E1C4AF0E; Wed, 10 Jun 2026 10:41:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1781088101; bh=VT6qgK4mn/du9ZXrGgtdvRyh3fKqhB/ygg9sLwK3SHk=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=MsfzxnstLb5fMqYF6nN/cOS2WzF4LKVMgz1iNYMrr1p79ezNNyjKxka9/ZZnF86Ib RGFHVP0toc3Ov8i+yjb9zcMQ8XpqP8z5hYQGJsOBmAfzMockSDwTZ0WxGB0Nvh4JXj 0LQmKBsKY+Xhvu/Hf8IUaA1S392YTF30Nu1GAfKfHhC6E9BwwnWqR5QayenMA953G0 z/6kHIzw+Owb3OmqFRPQ4x+OA2qeTMrYsOcQFsjY7q8c7rXZeJAL50AHT6dMjAscj7 75mWSSJLsbVyQe1aw/PTQrIHFWIjVJs/dFtnFZBAIv5FHVEYkDs0c0sxtTg55QD06q iBY4RN2Ksr4og== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 27326CD8CB9; Wed, 10 Jun 2026 10:41:41 +0000 (UTC) From: Jack Wu via B4 Relay Date: Wed, 10 Jun 2026 18:41:05 +0800 Subject: [PATCH v2 2/7] net: wwan: t9xx: Add control plane transaction layer Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260610-t9xx_driver_v1-v2-2-c65addf23b3f@compal.com> References: <20260610-t9xx_driver_v1-v2-0-c65addf23b3f@compal.com> In-Reply-To: <20260610-t9xx_driver_v1-v2-0-c65addf23b3f@compal.com> To: Loic Poulain , Sergey Ryazanov , Johannes Berg , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Jack Wu , Wen-Zhi Huang , Shi-Wei Yeh , Minano Tseng , Matthias Brugger , AngeloGioacchino Del Regno , Simon Horman , Jonathan Corbet , Shuah Khan Cc: linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-doc@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1781088082; l=9013; i=jackbb_wu@compal.com; s=20260526; h=from:subject:message-id; bh=/8JlCnQOCD1zznDNQhn1Ckv3gur6ScI6WuxfW1gOeII=; b=+nPy0oU37leFylf41M7G6lD16JO7lubCLp46x56h1DVlw/xs5bVTqHTNxPtcKbO19G5PriJXB WBT2BjaW97MDc0HnvHO+JiR3kJOJQkM+9rjuLOeNxn0wDaZrevCm2iO X-Developer-Key: i=jackbb_wu@compal.com; a=ed25519; pk=VH1prTWixNl8OEUPPSfII3p46MzJpQN8J3+ecE1tZXg= X-Endpoint-Received: by B4 Relay for jackbb_wu@compal.com/20260526 with auth_id=793 X-Original-From: Jack Wu Reply-To: jackbb_wu@compal.com From: Jack Wu The control plane implements TX services that reside in the transaction layer. The services receive the packets from the port layer and call the corresponding DMA components to transmit data to the device. Meanwhile, TX services receive and manage the port control commands from the port layer. The control plane implements RX services that reside in the transaction layer. The services receive the downlink packets from the modem and transfer the packets to the corresponding port layer interfaces. Signed-off-by: Jack Wu --- drivers/net/wwan/Kconfig | 5 +++ drivers/net/wwan/t9xx/Makefile | 5 +-- drivers/net/wwan/t9xx/mtk_ctrl_plane.c | 48 +++++++++++++++++++++++++= ++++ drivers/net/wwan/t9xx/mtk_ctrl_plane.h | 22 +++++++++++++ drivers/net/wwan/t9xx/mtk_dev.c | 44 ++++++++++++++++++++++++++ drivers/net/wwan/t9xx/mtk_dev.h | 5 +++ drivers/net/wwan/t9xx/pcie/Makefile | 10 ++++++ drivers/net/wwan/t9xx/pcie/mtk_pci.c | 10 +++--- drivers/net/wwan/t9xx/pcie/mtk_trans_ctrl.h | 21 +++++++++++++ 9 files changed, 163 insertions(+), 7 deletions(-) diff --git a/drivers/net/wwan/Kconfig b/drivers/net/wwan/Kconfig index 4cee537c739f..7019b44494f8 100644 --- a/drivers/net/wwan/Kconfig +++ b/drivers/net/wwan/Kconfig @@ -124,6 +124,7 @@ config MTK_T7XX config MTK_T9XX tristate "MediaTek PCIe 5G WWAN modem T9xx device" depends on PCI + select MTK_T9XX_PCI select NET_DEVLINK help Enables MediaTek PCIe based 5G WWAN modem (T9xx series) device. @@ -133,6 +134,10 @@ config MTK_T9XX =20 If unsure, say N. =20 +config MTK_T9XX_PCI + tristate + depends on PCI + endif # WWAN =20 endmenu diff --git a/drivers/net/wwan/t9xx/Makefile b/drivers/net/wwan/t9xx/Makefile index 6f2dd3f91454..ae9d6f2344ab 100644 --- a/drivers/net/wwan/t9xx/Makefile +++ b/drivers/net/wwan/t9xx/Makefile @@ -4,7 +4,8 @@ ccflags-y +=3D -I$(src)/pcie ccflags-y +=3D -I$(src) =20 obj-$(CONFIG_MTK_T9XX) +=3D mtk_t9xx.o +obj-$(CONFIG_MTK_T9XX_PCI) +=3D pcie/ =20 mtk_t9xx-y :=3D \ - pcie/mtk_pci.o \ - pcie/mtk_pci_drv_m9xx.o + mtk_dev.o \ + mtk_ctrl_plane.o diff --git a/drivers/net/wwan/t9xx/mtk_ctrl_plane.c b/drivers/net/wwan/t9xx= /mtk_ctrl_plane.c new file mode 100644 index 000000000000..07938f3e6fe2 --- /dev/null +++ b/drivers/net/wwan/t9xx/mtk_ctrl_plane.c @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022, MediaTek Inc. + * Copyright (c) 2022-2023, Intel Corporation. + */ + +#include + +#include "mtk_ctrl_plane.h" + +/** + * mtk_ctrl_init() - Initialize the control plane block. + * @mdev: Pointer to the MTK modem device. + * + * Allocates and initializes the control plane block + * associated with @mdev. + * + * Return: 0 on success, -ENOMEM on allocation failure. + */ +int mtk_ctrl_init(struct mtk_md_dev *mdev) +{ + struct mtk_ctrl_blk *ctrl_blk; + + ctrl_blk =3D devm_kzalloc(mdev->dev, sizeof(*ctrl_blk), GFP_KERNEL); + if (!ctrl_blk) + return -ENOMEM; + + ctrl_blk->mdev =3D mdev; + mdev->ctrl_blk =3D ctrl_blk; + + return 0; +} +EXPORT_SYMBOL(mtk_ctrl_init); + +/** + * mtk_ctrl_exit() - Clean up the control plane block. + * @mdev: Pointer to the MTK modem device. + * + * Frees the control plane block associated with @mdev. + */ +void mtk_ctrl_exit(struct mtk_md_dev *mdev) +{ + struct mtk_ctrl_blk *ctrl_blk =3D mdev->ctrl_blk; + + devm_kfree(mdev->dev, ctrl_blk); + mdev->ctrl_blk =3D NULL; +} +EXPORT_SYMBOL(mtk_ctrl_exit); diff --git a/drivers/net/wwan/t9xx/mtk_ctrl_plane.h b/drivers/net/wwan/t9xx= /mtk_ctrl_plane.h new file mode 100644 index 000000000000..c141876ef95d --- /dev/null +++ b/drivers/net/wwan/t9xx/mtk_ctrl_plane.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only + * + * Copyright (c) 2022, MediaTek Inc. + */ + +#ifndef __MTK_CTRL_PLANE_H__ +#define __MTK_CTRL_PLANE_H__ + +#include +#include + +#include "mtk_dev.h" + +struct mtk_ctrl_blk { + struct mtk_md_dev *mdev; + struct mtk_ctrl_trans *trans; +}; + +int mtk_ctrl_init(struct mtk_md_dev *mdev); +void mtk_ctrl_exit(struct mtk_md_dev *mdev); + +#endif /* __MTK_CTRL_PLANE_H__ */ diff --git a/drivers/net/wwan/t9xx/mtk_dev.c b/drivers/net/wwan/t9xx/mtk_de= v.c new file mode 100644 index 000000000000..f254ca7ed877 --- /dev/null +++ b/drivers/net/wwan/t9xx/mtk_dev.c @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022, MediaTek Inc. + */ + +#include + +#include "mtk_dev.h" + +struct mtk_md_dev *mtk_dev_alloc(struct device *pdev, const struct mtk_dev= _ops *dev_ops) +{ + struct mtk_md_dev *mdev; + + mdev =3D devm_kzalloc(pdev, sizeof(*mdev), GFP_KERNEL); + if (!mdev) + return NULL; + + mdev->dev_ops =3D dev_ops; + mdev->dev =3D pdev; + return mdev; +} +EXPORT_SYMBOL(mtk_dev_alloc); + +void mtk_dev_free(struct mtk_md_dev *mdev) +{ + struct device *dev =3D mdev->dev; + + devm_kfree(dev, mdev); +} +EXPORT_SYMBOL(mtk_dev_free); + +static int __init mtk_common_drv_init(void) +{ + return 0; +} +module_init(mtk_common_drv_init); + +static void __exit mtk_common_drv_exit(void) +{ +} +module_exit(mtk_common_drv_exit); + +MODULE_DESCRIPTION("MediaTek T9xx PCIe WWAN driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/net/wwan/t9xx/mtk_dev.h b/drivers/net/wwan/t9xx/mtk_de= v.h index 8278a0e2875e..bb3ea68890ea 100644 --- a/drivers/net/wwan/t9xx/mtk_dev.h +++ b/drivers/net/wwan/t9xx/mtk_dev.h @@ -36,6 +36,7 @@ enum mtk_dev_evt_d2h { }; =20 struct mtk_md_dev; +struct mtk_ctrl_blk; =20 struct mtk_dev_ops { u32 (*get_dev_state)(struct mtk_md_dev *mdev); @@ -57,6 +58,7 @@ struct mtk_md_dev { void *hw_priv; u32 hw_ver; char dev_str[MTK_DEV_STR_LEN]; + struct mtk_ctrl_blk *ctrl_blk; }; =20 static inline u32 mtk_dev_get_dev_state(struct mtk_md_dev *mdev) @@ -105,4 +107,7 @@ static inline int mtk_dev_send_dev_evt(struct mtk_md_de= v *mdev, u32 dev_evt) return mdev->dev_ops->send_dev_evt(mdev, dev_evt); } =20 +struct mtk_md_dev *mtk_dev_alloc(struct device *pdev, const struct mtk_dev= _ops *dev_ops); +void mtk_dev_free(struct mtk_md_dev *mdev); + #endif /* __MTK_DEV_H__ */ diff --git a/drivers/net/wwan/t9xx/pcie/Makefile b/drivers/net/wwan/t9xx/pc= ie/Makefile new file mode 100644 index 000000000000..7410d1796d27 --- /dev/null +++ b/drivers/net/wwan/t9xx/pcie/Makefile @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0-only + +ccflags-y +=3D -I$(src) +ccflags-y +=3D -I$(src)/.. + +obj-$(CONFIG_MTK_T9XX_PCI) +=3D mtk_t9xx_pcie.o + +mtk_t9xx_pcie-y :=3D \ + mtk_pci_drv_m9xx.o \ + mtk_pci.o diff --git a/drivers/net/wwan/t9xx/pcie/mtk_pci.c b/drivers/net/wwan/t9xx/p= cie/mtk_pci.c index 616bf5f31b6c..9f71685ea96c 100644 --- a/drivers/net/wwan/t9xx/pcie/mtk_pci.c +++ b/drivers/net/wwan/t9xx/pcie/mtk_pci.c @@ -14,6 +14,7 @@ #include =20 #include "mtk_dev.h" +#include "mtk_trans_ctrl.h" #include "mtk_pci.h" #include "mtk_pci_reg.h" =20 @@ -469,6 +470,7 @@ static u32 mtk_pci_ext_h2d_evt_hw_bits(u32 chs) =20 SET_HW_BITS(hw_bits, chs, MHCCIF_RC2EP_EVT_DEVICE_RESET, DEV_EVT_H2D_DEVICE_RESET); + return LE32_TO_U32(cpu_to_le32(hw_bits)); } =20 @@ -915,13 +917,11 @@ static int mtk_pci_probe(struct pci_dev *pdev, const = struct pci_device_id *id) struct mtk_md_dev *mdev; int ret; =20 - mdev =3D devm_kzalloc(dev, sizeof(*mdev), GFP_KERNEL); + mdev =3D mtk_dev_alloc(dev, &pci_hw_ops); if (!mdev) { ret =3D -ENOMEM; goto log_err; } - mdev->dev_ops =3D &pci_hw_ops; - mdev->dev =3D dev; =20 priv =3D devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); if (!priv) { @@ -1002,7 +1002,7 @@ static int mtk_pci_probe(struct pci_dev *pdev, const = struct pci_device_id *id) free_priv_data: devm_kfree(dev, priv); free_cntx_data: - devm_kfree(dev, mdev); + mtk_dev_free(mdev); log_err: dev_err(dev, "Failed to probe device, ret=3D%d\n", ret); =20 @@ -1030,7 +1030,7 @@ static void mtk_pci_remove(struct pci_dev *pdev) pci_load_and_free_saved_state(pdev, &priv->saved_state); =20 devm_kfree(dev, priv); - devm_kfree(dev, mdev); + mtk_dev_free(mdev); } =20 static pci_ers_result_t mtk_pci_error_detected(struct pci_dev *pdev, diff --git a/drivers/net/wwan/t9xx/pcie/mtk_trans_ctrl.h b/drivers/net/wwan= /t9xx/pcie/mtk_trans_ctrl.h new file mode 100644 index 000000000000..d6de4c43b529 --- /dev/null +++ b/drivers/net/wwan/t9xx/pcie/mtk_trans_ctrl.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only + * + * Copyright (c) 2022, MediaTek Inc. + */ + +#ifndef __MTK_TRANS_CTRL_H__ +#define __MTK_TRANS_CTRL_H__ + +#include +#include +#include +#include + +#include "mtk_dev.h" + +struct mtk_ctrl_trans { + struct mtk_ctrl_blk *ctrl_blk; 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Wed, 10 Jun 2026 10:41:41 +0000 (UTC) From: Jack Wu via B4 Relay Date: Wed, 10 Jun 2026 18:41:06 +0800 Subject: [PATCH v2 3/7] net: wwan: t9xx: Add control DMA interface Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260610-t9xx_driver_v1-v2-3-c65addf23b3f@compal.com> References: <20260610-t9xx_driver_v1-v2-0-c65addf23b3f@compal.com> In-Reply-To: <20260610-t9xx_driver_v1-v2-0-c65addf23b3f@compal.com> To: Loic Poulain , Sergey Ryazanov , Johannes Berg , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Jack Wu , Wen-Zhi Huang , Shi-Wei Yeh , Minano Tseng , Matthias Brugger , AngeloGioacchino Del Regno , Simon Horman , Jonathan Corbet , Shuah Khan Cc: linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-doc@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1781088082; l=94513; i=jackbb_wu@compal.com; s=20260526; h=from:subject:message-id; bh=sZaOjNWJMG+uX7YybI4Giv0Uaj+pza5CRtiGoCCAT+Q=; b=ILvUqn37PPFxejVYdQ8dfZHfCOfDBlJM/jv3Htpu8mK00DKtd8RhG65xdlof7tg4cEGLn/qxN datc6dKs3nGBTtNd+HkyhZrz9cLYqrPq6/tfeK4n9wp+kt30W6O8UOX X-Developer-Key: i=jackbb_wu@compal.com; a=ed25519; pk=VH1prTWixNl8OEUPPSfII3p46MzJpQN8J3+ecE1tZXg= X-Endpoint-Received: by B4 Relay for jackbb_wu@compal.com/20260526 with auth_id=793 X-Original-From: Jack Wu Reply-To: jackbb_wu@compal.com From: Jack Wu Cross Layer Direct Memory Access(CLDMA) is the hardware interface used by the control plane and designated to translate data between the host and the device. It supports 8 hardware queues for the device AP and modem respectively. CLDMA driver uses General Purpose Descriptor (GPD) to describe transaction information that can be recognized by CLDMA hardware. Once CLDMA hardware transaction is started, it would fetch and parse GPD to transfer data correctly. To facilitate the CLDMA transaction, a GPD ring for each queue is used. Once the transaction is started, CLDMA hardware will traverse the GPD ring to transfer data between the host and the device until no GPD is available. CLDMA TX flow: Once a TX service receives the TX data from the port layer, it uses APIs exported by the CLDMA driver to configure GPD with the DMA address of TX data. After that, the service triggers CLDMA to fetch the first available GPD to transfer data. CLDMA RX flow: When there is RX data from the MD, CLDMA hardware asserts an interrupt to notify the host to fetch data and dispatch it to FSM (for handshake messages) or the port layer. After CLDMA opening is finished, All RX GPDs are fulfilled and ready to receive data from the device. Signed-off-by: Jack Wu --- drivers/net/wwan/t9xx/mtk_ctrl_plane.c | 4 +- drivers/net/wwan/t9xx/mtk_ctrl_plane.h | 52 +- drivers/net/wwan/t9xx/pcie/Makefile | 7 +- drivers/net/wwan/t9xx/pcie/mtk_cldma.c | 1200 +++++++++++++++++++= ++++ drivers/net/wwan/t9xx/pcie/mtk_cldma.h | 170 ++++ drivers/net/wwan/t9xx/pcie/mtk_cldma_drv.c | 371 +++++++ drivers/net/wwan/t9xx/pcie/mtk_cldma_drv.h | 177 ++++ drivers/net/wwan/t9xx/pcie/mtk_cldma_drv_m9xx.c | 182 ++++ drivers/net/wwan/t9xx/pcie/mtk_cldma_drv_m9xx.h | 103 ++ drivers/net/wwan/t9xx/pcie/mtk_ctrl_cfg_m9xx.c | 24 + drivers/net/wwan/t9xx/pcie/mtk_pci.c | 38 + drivers/net/wwan/t9xx/pcie/mtk_pci_reg.h | 1 + drivers/net/wwan/t9xx/pcie/mtk_trans_ctrl.c | 583 +++++++++++ drivers/net/wwan/t9xx/pcie/mtk_trans_ctrl.h | 84 ++ 14 files changed, 2992 insertions(+), 4 deletions(-) diff --git a/drivers/net/wwan/t9xx/mtk_ctrl_plane.c b/drivers/net/wwan/t9xx= /mtk_ctrl_plane.c index 07938f3e6fe2..70348696ac44 100644 --- a/drivers/net/wwan/t9xx/mtk_ctrl_plane.c +++ b/drivers/net/wwan/t9xx/mtk_ctrl_plane.c @@ -11,13 +11,14 @@ /** * mtk_ctrl_init() - Initialize the control plane block. * @mdev: Pointer to the MTK modem device. + * @ops: HIF operations for the control plane. * * Allocates and initializes the control plane block * associated with @mdev. * * Return: 0 on success, -ENOMEM on allocation failure. */ -int mtk_ctrl_init(struct mtk_md_dev *mdev) +int mtk_ctrl_init(struct mtk_md_dev *mdev, struct mtk_ctrl_hif_ops *ops) { struct mtk_ctrl_blk *ctrl_blk; =20 @@ -27,6 +28,7 @@ int mtk_ctrl_init(struct mtk_md_dev *mdev) =20 ctrl_blk->mdev =3D mdev; mdev->ctrl_blk =3D ctrl_blk; + ctrl_blk->ops =3D ops; =20 return 0; } diff --git a/drivers/net/wwan/t9xx/mtk_ctrl_plane.h b/drivers/net/wwan/t9xx= /mtk_ctrl_plane.h index c141876ef95d..88d71ac92084 100644 --- a/drivers/net/wwan/t9xx/mtk_ctrl_plane.h +++ b/drivers/net/wwan/t9xx/mtk_ctrl_plane.h @@ -11,12 +11,60 @@ =20 #include "mtk_dev.h" =20 +enum mtk_trb_cmd_type { + TRB_CMD_MIN, + TRB_CMD_ENABLE, + TRB_CMD_TX, + TRB_CMD_DISABLE, + TRB_CMD_STOP, + TRB_CMD_RECOVER, + TRB_CMD_MAX, +}; + +enum mtk_hif_dev_ctrl_cmd { + HIF_CTRL_CMD_CHECK_TX_FULL, +}; + +struct trb_open_priv { + u8 log_rg_offset; + u32 tx_mtu; + u32 rx_mtu; + u32 tx_frag_size; + u32 rx_frag_size; + int (*rx_done)(struct sk_buff *skb, void *priv, bool force_recv); +}; + +struct trb { + u32 channel_id; + enum mtk_trb_cmd_type cmd; + int status; + struct kref kref; + void *priv; + int (*trb_complete)(struct sk_buff *skb); +}; + +union ctrl_hif_cmd_data { + u32 rx_ch; +}; + +struct mtk_ctrl_hif_ops { + int (*init)(struct mtk_md_dev *mdev); + int (*exit)(struct mtk_md_dev *mdev); + int (*submit_skb)(struct mtk_md_dev *mdev, struct sk_buff *skb, bool forc= e_send); + int (*send_cmd)(struct mtk_md_dev *mdev, int cmd, void *data); +}; + +struct mtk_ctrl_cfg; +struct mtk_ctrl_trans; + struct mtk_ctrl_blk { struct mtk_md_dev *mdev; - struct mtk_ctrl_trans *trans; + struct mtk_ctrl_hif_ops *ops; + void *ctrl_hw_priv; + struct mtk_ctrl_cfg *cfg; }; =20 -int mtk_ctrl_init(struct mtk_md_dev *mdev); +int mtk_ctrl_init(struct mtk_md_dev *mdev, struct mtk_ctrl_hif_ops *ops); void mtk_ctrl_exit(struct mtk_md_dev *mdev); =20 #endif /* __MTK_CTRL_PLANE_H__ */ diff --git a/drivers/net/wwan/t9xx/pcie/Makefile b/drivers/net/wwan/t9xx/pc= ie/Makefile index 7410d1796d27..5252f158b058 100644 --- a/drivers/net/wwan/t9xx/pcie/Makefile +++ b/drivers/net/wwan/t9xx/pcie/Makefile @@ -7,4 +7,9 @@ obj-$(CONFIG_MTK_T9XX_PCI) +=3D mtk_t9xx_pcie.o =20 mtk_t9xx_pcie-y :=3D \ mtk_pci_drv_m9xx.o \ - mtk_pci.o + mtk_cldma_drv_m9xx.o \ + mtk_ctrl_cfg_m9xx.o \ + mtk_pci.o \ + mtk_trans_ctrl.o \ + mtk_cldma.o \ + mtk_cldma_drv.o diff --git a/drivers/net/wwan/t9xx/pcie/mtk_cldma.c b/drivers/net/wwan/t9xx= /pcie/mtk_cldma.c new file mode 100644 index 000000000000..7a0815aa2fc8 --- /dev/null +++ b/drivers/net/wwan/t9xx/pcie/mtk_cldma.c @@ -0,0 +1,1200 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022, MediaTek Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "mtk_pci.h" +#include "mtk_cldma.h" +#include "mtk_cldma_drv.h" +#include "mtk_dev.h" + +#define cldma_drv_ops_null NULL +#define DMA_POOL_NAME_LEN (64) +#define WAIT_HWO_ROUND (10) +#define WAIT_HWO_TIME (5) +#define CLDMA_RETRY_DELAY_MS (100) +#define NO_BUDGET (0) + +static const int mtk_cldma_hw_id_tbl[NR_CLDMA] =3D { + [CLDMA0] =3D CLDMA0_HW_ID, + [CLDMA1] =3D CLDMA1_HW_ID, + [CLDMA4] =3D CLDMA4_HW_ID, +}; + +static inline void mtk_cldma_clr_bd_dsc(struct cldma_drv_info *drv_info, + struct bd_dsc *bd_dsc_pool, int nr_bds) +{ + struct bd_dsc *bd_dsc; + int i; + + for (i =3D 0; i < nr_bds; i++) { + bd_dsc =3D bd_dsc_pool + i; + dma_unmap_single(drv_info->mdev->dev, bd_dsc->data_dma_addr, + bd_dsc->data_len, DMA_TO_DEVICE); + bd_dsc->data_dma_addr =3D 0; + bd_dsc->data_len =3D 0; + if (bd_dsc->bd->tx_bd.bd_flags & CLDMA_BD_FLAG_EOL) { + bd_dsc->bd->tx_bd.bd_flags &=3D ~CLDMA_BD_FLAG_EOL; + break; + } + } +} + +static void mtk_cldma_tx_done_work(struct work_struct *work) +{ + struct txq *txq =3D container_of(work, struct txq, tx_done_work); + struct cldma_drv_info *drv_info; + struct cldma_drv_ops *drv_ops; + struct mtk_ctrl_trans *trans; + struct mtk_md_dev *mdev; + struct tx_req *req; + unsigned int state; + struct trb *trb; + int i, hif_id; + u32 txqno; + + drv_info =3D txq->drv_info; + hif_id =3D drv_info->hif_id; + txqno =3D txq->txqno; + mdev =3D drv_info->mdev; + drv_ops =3D drv_info->drv_ops; + trans =3D drv_info->cd->trans; + +again: + for (i =3D 0; i < txq->nr_gpds; i++) { + req =3D txq->req_pool + txq->free_idx; + + rmb(); /* ensure HWO setup done before HWO read */ + + if (!req->data_vm_addr || (req->gpd->tx_gpd.gpd_flags & CLDMA_GPD_FLAG_H= WO)) + break; + + if (txq->nr_bds) + mtk_cldma_clr_bd_dsc(drv_info, req->bd_dsc_pool, txq->nr_bds); + else + dma_unmap_single(mdev->dev, req->data_dma_addr, + req->data_len, DMA_TO_DEVICE); + + trb =3D (struct trb *)req->skb->cb; + trb->status =3D 0; + trb->trb_complete(req->skb); + + req->data_vm_addr =3D NULL; + req->data_dma_addr =3D 0; + req->data_len =3D 0; + req->skb =3D NULL; + + txq->free_idx =3D (txq->free_idx + 1) % txq->nr_gpds; + if (atomic_fetch_inc(&txq->req_budget) =3D=3D NO_BUDGET) + wake_up(&trans->trb_srv[trans->srv_cfg[hif_id][txqno]]->trb_waitq); + } + + state =3D drv_ops->cldma_check_intr_status(drv_info, DIR_TX, txqno, QUEUE= _XFER_DONE); + if (state) { + if (unlikely(state =3D=3D LINK_ERROR_VAL)) + goto out; + + drv_ops->cldma_clr_intr_status(drv_info, DIR_TX, txqno, QUEUE_XFER_DONE); + + cond_resched(); + + goto again; + } + +out: + drv_ops->cldma_unmask_intr(drv_info, DIR_TX, txqno, QUEUE_XFER_DONE); +} + +static void mtk_cldma_rx_skb_adjust(struct mtk_md_dev *mdev, struct rxq *r= xq, + struct rx_req *req) +{ + struct bd_dsc *bd_dsc; + int i; + + for (i =3D 0; i < rxq->nr_bds; i++) { + bd_dsc =3D req->bd_dsc_pool + i; + if (bd_dsc->data_dma_addr) { + dma_unmap_single(mdev->dev, bd_dsc->data_dma_addr, + req->frag_size, DMA_FROM_DEVICE); + bd_dsc->data_dma_addr =3D 0; + } + bd_dsc->skb->len =3D 0; + skb_reset_tail_pointer(bd_dsc->skb); + skb_put(bd_dsc->skb, + min_t(u16, le16_to_cpu(bd_dsc->bd->rx_bd.data_recv_len), + req->frag_size)); + if (req->skb !=3D bd_dsc->skb) { + req->skb->len +=3D bd_dsc->skb->len; + req->skb->data_len +=3D bd_dsc->skb->len; + } + bd_dsc->bd->rx_bd.data_recv_len =3D 0; + bd_dsc->skb =3D NULL; + } + if (!rxq->nr_bds) { + if (req->data_dma_addr) { + dma_unmap_single(mdev->dev, req->data_dma_addr, + req->mtu, DMA_FROM_DEVICE); + req->data_dma_addr =3D 0; + } + req->skb->len =3D 0; + skb_reset_tail_pointer(req->skb); + skb_put(req->skb, + min_t(u16, le16_to_cpu(req->gpd->rx_gpd.data_recv_len), + req->mtu)); + } + + req->gpd->rx_gpd.data_recv_len =3D 0; +} + +static int mtk_cldma_reload_rx_skb(struct mtk_md_dev *mdev, struct rxq *rx= q, + struct rx_req *req) +{ + struct sk_buff *tail =3D NULL; + struct bd_dsc *bd_dsc; + int nr_bds; + int i, ret; + + nr_bds =3D rxq->nr_bds; + + for (i =3D 0; i < nr_bds; i++) { + bd_dsc =3D req->bd_dsc_pool + i; + bd_dsc->skb =3D __dev_alloc_skb(req->frag_size, GFP_KERNEL); + if (!bd_dsc->skb) { + dev_warn((mdev)->dev, "Failed to alloc SKB\n"); + ret =3D -ENOMEM; + goto err_free_skb; + } + bd_dsc->skb->next =3D NULL; + bd_dsc->data_dma_addr =3D dma_map_single(mdev->dev, bd_dsc->skb->data, + req->frag_size, DMA_FROM_DEVICE); + ret =3D dma_mapping_error(mdev->dev, bd_dsc->data_dma_addr); + if (unlikely(ret)) { + dev_warn((mdev)->dev, "Failed to map SKB data\n"); + ret =3D -EFAULT; + goto err_free_skb; + } + bd_dsc->bd->rx_bd.data_buff_ptr_h =3D + cpu_to_le32((u64)(bd_dsc->data_dma_addr) >> 32); + bd_dsc->bd->rx_bd.data_buff_ptr_l =3D + cpu_to_le32(bd_dsc->data_dma_addr); + if (tail) { + tail->next =3D bd_dsc->skb; + tail =3D bd_dsc->skb; + continue; + } + if (!req->skb) { + req->skb =3D bd_dsc->skb; + } else { + skb_shinfo(req->skb)->frag_list =3D bd_dsc->skb; + tail =3D bd_dsc->skb; + } + } + if (!nr_bds) { + req->skb =3D __dev_alloc_skb(req->mtu, GFP_KERNEL); + if (!req->skb) { + ret =3D -ENOMEM; + goto err_free_skb; + } + + req->data_dma_addr =3D dma_map_single(mdev->dev, req->skb->data, + req->mtu, DMA_FROM_DEVICE); + ret =3D dma_mapping_error(mdev->dev, req->data_dma_addr); + if (unlikely(ret)) { + dev_warn((mdev)->dev, "Failed to map SKB data\n"); + ret =3D -EFAULT; + goto err_free_skb; + } + req->gpd->rx_gpd.data_buff_ptr_h =3D cpu_to_le32((u64)req->data_dma_addr= >> 32); + req->gpd->rx_gpd.data_buff_ptr_l =3D cpu_to_le32(req->data_dma_addr); + } + return 0; + +err_free_skb: + if (nr_bds) { + if (req->skb) + skb_shinfo(req->skb)->frag_list =3D NULL; + for (i =3D 0; i < nr_bds; i++) { + bd_dsc =3D req->bd_dsc_pool + i; + if (!bd_dsc->skb) + break; + if (!dma_mapping_error(mdev->dev, bd_dsc->data_dma_addr)) + dma_unmap_single(mdev->dev, bd_dsc->data_dma_addr, + req->frag_size, DMA_FROM_DEVICE); + bd_dsc->data_dma_addr =3D 0; + bd_dsc->skb->next =3D NULL; + dev_kfree_skb_any(bd_dsc->skb); + } + } else { + req->data_dma_addr =3D 0; + if (req->skb) + dev_kfree_skb_any(req->skb); + } + req->skb =3D NULL; + + return ret; +} + +static int mtk_cldma_check_rx_req(struct cldma_drv_info *drv_info, struct = rxq *rxq) +{ + struct rx_req *req =3D rxq->req_pool + rxq->free_idx; + u64 curr_addr; + int i; + + curr_addr =3D drv_info->drv_ops->cldma_get_rx_curr_addr(drv_info, rxq->rx= qno); + if (unlikely(!curr_addr)) + return -ENXIO; + + if (req->gpd_dma_addr =3D=3D curr_addr) + return -EAGAIN; + for (i =3D 0; i < WAIT_HWO_ROUND; i++) { + udelay(WAIT_HWO_TIME); + if (!(READ_ONCE(req->gpd->rx_gpd.gpd_flags) & CLDMA_GPD_FLAG_HWO)) + break; + } + if (i =3D=3D WAIT_HWO_ROUND) { + dev_err((drv_info->mdev)->dev, "Failed to check HWO=3D0\n"); + return -EAGAIN; + } + + return 0; +} + +static bool mtk_cldma_rx_check_again(struct rxq *rxq) +{ + struct cldma_drv_info *drv_info; + struct cldma_drv_ops *drv_ops; + bool need_check_again =3D false; + u32 state; + int rxqno; + + drv_info =3D rxq->drv_info; + drv_ops =3D drv_info->drv_ops; + rxqno =3D rxq->rxqno; + + do { + state =3D drv_ops->cldma_check_intr_status(drv_info, DIR_RX, + rxqno, QUEUE_XFER_DONE); + if (state) { + if (unlikely(state =3D=3D LINK_ERROR_VAL)) + break; + + drv_ops->cldma_clr_intr_status(drv_info, DIR_RX, + rxqno, QUEUE_XFER_DONE); + cond_resched(); + return true; + } + } while (need_check_again); + + return false; +} + +static void mtk_cldma_rx_done_work(struct work_struct *work) +{ + struct rx_req *req =3D NULL, *pre_req =3D NULL; + struct rxq *rxq =3D container_of(work, struct rxq, rx_done_work); + struct cldma_drv_info *drv_info; + struct cldma_drv_ops *drv_ops; + struct mtk_md_dev *mdev; + int i, ret, idx; + + drv_info =3D rxq->drv_info; + mdev =3D drv_info->mdev; + drv_ops =3D drv_info->drv_ops; + +again: + for (i =3D 0; i < rxq->nr_gpds; i++) { + req =3D rxq->req_pool + rxq->free_idx; + if (!req->skb) { + dev_err((mdev)->dev, + "Failed to get valid req cldma%d rxq%d req%d\n", + drv_info->hw_id, rxq->rxqno, rxq->free_idx); + goto out; + } + + if (req->gpd->rx_gpd.gpd_flags & CLDMA_GPD_FLAG_HWO) + break; + + mtk_cldma_rx_skb_adjust(mdev, rxq, req); + do { + ret =3D rxq->rx_done(req->skb, rxq->arg, + atomic_read(&rxq->need_exit) ? true : false); + if (ret =3D=3D -EAGAIN) + usleep_range(1000, 2000); + else + req->skb =3D NULL; + } while (ret =3D=3D -EAGAIN); + + ret =3D mtk_cldma_reload_rx_skb(mdev, rxq, req); + if (ret) + goto out; + + wmb(); /* ensure addr set done before HWO setup done */ + + idx =3D rxq->free_idx =3D=3D 0 ? rxq->nr_gpds - 1 : rxq->free_idx - 1; + pre_req =3D rxq->req_pool + idx; + pre_req->gpd->rx_gpd.gpd_flags |=3D CLDMA_GPD_FLAG_HWO; + rxq->free_idx =3D (rxq->free_idx + 1) % rxq->nr_gpds; + } + + ret =3D mtk_cldma_check_rx_req(drv_info, rxq); + if (!ret) + goto again; + else if (ret =3D=3D -ENXIO) + goto out; + + if (!atomic_read(&rxq->need_exit)) + drv_ops->cldma_resume_queue(drv_info, DIR_RX, rxq->rxqno); + + if (mtk_cldma_rx_check_again(rxq)) + goto again; + +out: + drv_ops->cldma_unmask_intr(drv_info, DIR_RX, rxq->rxqno, QUEUE_XFER_DONE); + drv_ops->cldma_clear_ip_busy(drv_info); +} + +static int mtk_cldma_alloc_tx_bd(struct cldma_drv_info *drv_info, struct t= xq *txq, + struct tx_req *req) +{ + struct bd_dsc *bd_dsc, *last_bd_dsc =3D NULL; + int i; + + req->bd_dsc_pool =3D devm_kcalloc(drv_info->mdev->dev, txq->nr_bds, + sizeof(*bd_dsc), GFP_KERNEL); + if (!req->bd_dsc_pool) + return -ENOMEM; + + for (i =3D 0; i < txq->nr_bds; i++) { + bd_dsc =3D req->bd_dsc_pool + i; + bd_dsc->bd =3D dma_pool_zalloc(drv_info->bd_dma_pool, GFP_KERNEL, + &bd_dsc->bd_dma_addr); + if (!bd_dsc->bd) + return -ENOMEM; + if (!last_bd_dsc) { + req->gpd->tx_gpd.data_buff_ptr_h =3D + cpu_to_le32((u64)(bd_dsc->bd_dma_addr) >> 32); + req->gpd->tx_gpd.data_buff_ptr_l =3D + cpu_to_le32(bd_dsc->bd_dma_addr); + } else { + last_bd_dsc->bd->tx_bd.next_bd_ptr_h =3D + cpu_to_le32((u64)(bd_dsc->bd_dma_addr) >> 32); + last_bd_dsc->bd->tx_bd.next_bd_ptr_l =3D + cpu_to_le32(bd_dsc->bd_dma_addr); + } + last_bd_dsc =3D bd_dsc; + } + return 0; +} + +static struct txq *mtk_cldma_txq_alloc(struct cldma_drv_info *drv_info, st= ruct sk_buff *skb) +{ + struct trb *trb =3D (struct trb *)skb->cb; + struct cldma_drv_ops *drv_ops; + struct mtk_ctrl_trans *trans; + struct mtk_ctrl_blk *ctrl_blk; + struct mtk_md_dev *mdev; + struct bd_dsc *bd_dsc; + struct tx_req *next; + struct tx_req *req; + u16 tx_frag_size; + struct txq *txq; + int i, j, ret; + + mdev =3D drv_info->mdev; + ctrl_blk =3D mdev->ctrl_blk; + trans =3D ctrl_blk->ctrl_hw_priv; + drv_ops =3D drv_info->drv_ops; + + txq =3D devm_kzalloc(mdev->dev, sizeof(*txq), GFP_KERNEL); + if (!txq) + return NULL; + + txq->que =3D radix_tree_lookup(&trans->queue_tbl, trb->channel_id & 0xFFF= F); + txq->drv_info =3D drv_info; + txq->txqno =3D txq->que->txqno; + txq->nr_gpds =3D txq->que->tx_nr_gpds; + atomic_set(&txq->req_budget, txq->que->tx_nr_gpds); + txq->is_stopping =3D false; + tx_frag_size =3D txq->que->tx_frag_size; + if (txq->que->tx_mtu > tx_frag_size && tx_frag_size) + txq->nr_bds =3D (txq->que->tx_mtu + tx_frag_size - 1) / tx_frag_size; + + txq->req_pool =3D devm_kcalloc(mdev->dev, txq->nr_gpds, sizeof(*req), GFP= _KERNEL); + if (!txq->req_pool) + goto err_free_txq; + + for (i =3D 0; i < txq->nr_gpds; i++) { + req =3D txq->req_pool + i; + req->mtu =3D txq->que->tx_mtu; + req->frag_size =3D tx_frag_size; + req->gpd =3D dma_pool_zalloc(drv_info->gpd_dma_pool, GFP_KERNEL, &req->g= pd_dma_addr); + if (!req->gpd) + goto err_free_req; + if (txq->nr_bds) { + ret =3D mtk_cldma_alloc_tx_bd(drv_info, txq, req); + if (ret) + goto err_free_req; + req->gpd->tx_gpd.gpd_flags |=3D CLDMA_GPD_FLAG_BDP; + } + } + + for (i =3D 0; i < txq->nr_gpds; i++) { + req =3D txq->req_pool + i; + next =3D txq->req_pool + ((i + 1) % txq->nr_gpds); + req->gpd->tx_gpd.gpd_flags |=3D CLDMA_GPD_FLAG_IOC; + req->gpd->tx_gpd.next_gpd_ptr_h =3D cpu_to_le32((u64)(next->gpd_dma_addr= ) >> 32); + req->gpd->tx_gpd.next_gpd_ptr_l =3D cpu_to_le32(next->gpd_dma_addr); + } + + INIT_WORK(&txq->tx_done_work, mtk_cldma_tx_done_work); + + drv_ops->cldma_stop_queue(drv_info, DIR_TX, txq->txqno); + txq->tx_started =3D false; + drv_ops->cldma_setup_start_addr(drv_info, DIR_TX, txq->txqno, + txq->req_pool[0].gpd_dma_addr); + drv_ops->cldma_unmask_intr(drv_info, DIR_TX, txq->txqno, QUEUE_ERROR); + drv_ops->cldma_unmask_intr(drv_info, DIR_TX, txq->txqno, QUEUE_XFER_DONE); + + drv_info->txq[txq->txqno] =3D txq; + return txq; + +err_free_req: + for (i =3D 0; i < txq->nr_gpds; i++) { + req =3D txq->req_pool + i; + if (!req->gpd) + break; + if (req->bd_dsc_pool) { + for (j =3D 0; j < txq->nr_bds; j++) { + bd_dsc =3D req->bd_dsc_pool + j; + if (!bd_dsc->bd) + break; + dma_pool_free(drv_info->bd_dma_pool, bd_dsc->bd, + bd_dsc->bd_dma_addr); + } + devm_kfree(mdev->dev, req->bd_dsc_pool); + } + dma_pool_free(drv_info->gpd_dma_pool, req->gpd, req->gpd_dma_addr); + } + devm_kfree(mdev->dev, txq->req_pool); +err_free_txq: + devm_kfree(mdev->dev, txq); + return NULL; +} + +static void mtk_cldma_txq_free(struct cldma_drv_info *drv_info, u32 txqno) +{ + struct cldma_drv_ops *drv_ops; + struct mtk_md_dev *mdev; + struct bd_dsc *bd_dsc; + struct tx_req *req; + struct txq *txq; + struct trb *trb; + int irq_id; + int i, j; + + mdev =3D drv_info->mdev; + drv_ops =3D drv_info->drv_ops; + + txq =3D drv_info->txq[txqno]; + drv_info->txq[txqno] =3D NULL; + /* stop HW tx transaction */ + drv_ops->cldma_stop_queue(drv_info, DIR_TX, txqno); + txq->tx_started =3D false; + + irq_id =3D mtk_pci_get_virq_id(mdev, drv_info->pci_ext_irq_id); + synchronize_irq(irq_id); + /* flush on-going work */ + flush_work(&txq->tx_done_work); + drv_ops->cldma_mask_intr(drv_info, DIR_TX, txqno, QUEUE_XFER_DONE); + drv_ops->cldma_mask_intr(drv_info, DIR_TX, txqno, QUEUE_ERROR); + + /* free tx req resource */ + for (i =3D 0; i < txq->nr_gpds; i++) { + req =3D txq->req_pool + txq->free_idx; + if (req->skb && req->data_len) { + if (!txq->nr_bds) + dma_unmap_single(mdev->dev, req->data_dma_addr, + req->data_len, DMA_TO_DEVICE); + for (j =3D 0; j < txq->nr_bds; j++) { + bd_dsc =3D req->bd_dsc_pool + j; + if (!bd_dsc->data_dma_addr) + continue; + dma_unmap_single(mdev->dev, bd_dsc->data_dma_addr, + bd_dsc->data_len, DMA_TO_DEVICE); + } + trb =3D (struct trb *)req->skb->cb; + trb->status =3D -EPIPE; + trb->trb_complete(req->skb); + } + for (j =3D 0; j < txq->nr_bds; j++) { + bd_dsc =3D req->bd_dsc_pool + j; + dma_pool_free(drv_info->bd_dma_pool, bd_dsc->bd, + bd_dsc->bd_dma_addr); + } + if (req->bd_dsc_pool) + devm_kfree(mdev->dev, req->bd_dsc_pool); + dma_pool_free(drv_info->gpd_dma_pool, req->gpd, req->gpd_dma_addr); + txq->free_idx =3D (txq->free_idx + 1) % txq->nr_gpds; + } + + devm_kfree(mdev->dev, txq->req_pool); + devm_kfree(mdev->dev, txq); +} + +static int mtk_cldma_alloc_rx_bd(struct cldma_drv_info *drv_info, struct r= x_req *req, + int nr_bds) +{ + struct bd_dsc *bd_dsc, *last_bd_dsc =3D NULL; + struct sk_buff *tail =3D NULL; + struct mtk_md_dev *mdev; + u32 left_size; + int ret; + int i; + + mdev =3D drv_info->mdev; + left_size =3D req->mtu; + + req->bd_dsc_pool =3D devm_kcalloc(mdev->dev, nr_bds, + sizeof(*bd_dsc), GFP_KERNEL); + if (!req->bd_dsc_pool) + return -ENOMEM; + for (i =3D 0; i < nr_bds; i++) { + bd_dsc =3D req->bd_dsc_pool + i; + bd_dsc->bd =3D dma_pool_zalloc(drv_info->bd_dma_pool, GFP_KERNEL, + &bd_dsc->bd_dma_addr); + if (!bd_dsc->bd) + return -ENOMEM; + + bd_dsc->skb =3D __dev_alloc_skb(req->frag_size, GFP_KERNEL); + if (!bd_dsc->skb) + return -ENOMEM; + bd_dsc->skb->next =3D NULL; + bd_dsc->data_dma_addr =3D + dma_map_single(mdev->dev, bd_dsc->skb->data, + req->frag_size, DMA_FROM_DEVICE); + ret =3D dma_mapping_error(mdev->dev, bd_dsc->data_dma_addr); + if (unlikely(ret)) + return -ENOMEM; + + bd_dsc->bd->rx_bd.data_buff_ptr_h =3D + cpu_to_le32((u64)(bd_dsc->data_dma_addr) >> 32); + bd_dsc->bd->rx_bd.data_buff_ptr_l =3D + cpu_to_le32(bd_dsc->data_dma_addr); + bd_dsc->bd->rx_bd.data_allow_len =3D + cpu_to_le16(min(req->frag_size, left_size)); + left_size -=3D min(req->frag_size, left_size); + if (!last_bd_dsc) { + req->gpd->rx_gpd.data_buff_ptr_h =3D + cpu_to_le32((u64)(bd_dsc->bd_dma_addr) >> 32); + req->gpd->rx_gpd.data_buff_ptr_l =3D + cpu_to_le32(bd_dsc->bd_dma_addr); + } else { + last_bd_dsc->bd->rx_bd.next_bd_ptr_h =3D + cpu_to_le32((u64)(bd_dsc->bd_dma_addr) >> 32); + last_bd_dsc->bd->rx_bd.next_bd_ptr_l =3D + cpu_to_le32(bd_dsc->bd_dma_addr); + } + last_bd_dsc =3D bd_dsc; + if (tail) { + tail->next =3D bd_dsc->skb; + tail =3D bd_dsc->skb; + continue; + } + if (!req->skb) { + req->skb =3D bd_dsc->skb; + } else { + skb_shinfo(req->skb)->frag_list =3D bd_dsc->skb; + tail =3D bd_dsc->skb; + } + } + last_bd_dsc->bd->rx_bd.bd_flags |=3D CLDMA_BD_FLAG_EOL; + return 0; +} + +static void mtk_cldma_rxq_alloc_cancel(struct cldma_drv_info *drv_info, st= ruct rx_req *req, + int nr_bds) +{ + struct mtk_md_dev *mdev; + struct bd_dsc *bd_dsc; + int i; + + mdev =3D drv_info->mdev; + + if (nr_bds) { + if (req->skb) + skb_shinfo(req->skb)->frag_list =3D NULL; + if (req->bd_dsc_pool) { + for (i =3D 0; i < nr_bds; i++) { + bd_dsc =3D req->bd_dsc_pool + i; + if (!bd_dsc->bd) + break; + if (bd_dsc->skb) { + if (!dma_mapping_error(mdev->dev, bd_dsc->data_dma_addr)) + dma_unmap_single(mdev->dev, bd_dsc->data_dma_addr, + req->frag_size, DMA_FROM_DEVICE); + bd_dsc->data_dma_addr =3D 0; + bd_dsc->skb->next =3D NULL; + dev_kfree_skb_any(bd_dsc->skb); + } + dma_pool_free(drv_info->bd_dma_pool, bd_dsc->bd, + bd_dsc->bd_dma_addr); + } + devm_kfree(mdev->dev, req->bd_dsc_pool); + } + } else { + if (req->skb) { + if (!dma_mapping_error(mdev->dev, req->data_dma_addr)) + dma_unmap_single(mdev->dev, req->data_dma_addr, + req->mtu, DMA_FROM_DEVICE); + req->data_dma_addr =3D 0; + dev_kfree_skb_any(req->skb); + } + } + dma_pool_free(drv_info->gpd_dma_pool, req->gpd, req->gpd_dma_addr); +} + +static struct rxq *mtk_cldma_rxq_alloc(struct cldma_drv_info *drv_info, st= ruct sk_buff *skb) +{ + struct trb_open_priv *trb_open_priv =3D (struct trb_open_priv *)skb->data; + struct trb *trb =3D (struct trb *)skb->cb; + struct cldma_drv_ops *drv_ops; + struct mtk_ctrl_trans *trans; + struct mtk_ctrl_blk *ctrl_blk; + struct mtk_md_dev *mdev; + struct rx_req *next; + struct rx_req *req; + u16 rx_frag_size; + struct rxq *rxq; + int ret; + int i; + + mdev =3D drv_info->mdev; + ctrl_blk =3D mdev->ctrl_blk; + trans =3D ctrl_blk->ctrl_hw_priv; + drv_ops =3D drv_info->drv_ops; + + rxq =3D devm_kzalloc(mdev->dev, sizeof(*rxq), GFP_KERNEL); + if (!rxq) + return NULL; + + rxq->que =3D radix_tree_lookup(&trans->queue_tbl, trb->channel_id & 0xFFF= F); + if (rxq->que->rx_nr_gpds < MIN_GPD_NUM) { + dev_err((mdev)->dev, + "Failed to alloc cldma%d rxq%d due to gpd number < 2\n", + drv_info->hw_id, rxq->rxqno); + goto err_free_rxq; + } + rxq->drv_info =3D drv_info; + rxq->rxqno =3D rxq->que->rxqno; + rxq->nr_gpds =3D rxq->que->rx_nr_gpds; + rxq->arg =3D trb->priv; + rxq->rx_done =3D trb_open_priv->rx_done; + atomic_set(&rxq->need_exit, 0); + rx_frag_size =3D rxq->que->rx_frag_size; + if (rxq->que->rx_mtu > rx_frag_size && rx_frag_size) + rxq->nr_bds =3D (rxq->que->rx_mtu + rx_frag_size - 1) / rx_frag_size; + + rxq->req_pool =3D devm_kcalloc(mdev->dev, rxq->nr_gpds, sizeof(*req), GFP= _KERNEL); + if (!rxq->req_pool) + goto err_free_rxq; + + /* setup rx request */ + for (i =3D 0; i < rxq->nr_gpds; i++) { + req =3D rxq->req_pool + i; + req->mtu =3D rxq->que->rx_mtu; + req->frag_size =3D rx_frag_size; + req->gpd =3D dma_pool_zalloc(drv_info->gpd_dma_pool, GFP_KERNEL, &req->g= pd_dma_addr); + if (!req->gpd) + goto err_free_req; + if (rxq->nr_bds) { + ret =3D mtk_cldma_alloc_rx_bd(drv_info, req, rxq->nr_bds); + if (ret) + goto err_free_req; + req->gpd->rx_gpd.gpd_flags |=3D CLDMA_GPD_FLAG_BDP; + } else { + req->skb =3D __dev_alloc_skb(req->mtu, GFP_KERNEL); + if (!req->skb) + goto err_free_req; + req->data_dma_addr =3D dma_map_single(mdev->dev, req->skb->data, + req->mtu, DMA_FROM_DEVICE); + ret =3D dma_mapping_error(mdev->dev, req->data_dma_addr); + if (unlikely(ret)) + goto err_free_req; + } + } + + for (i =3D 0; i < rxq->nr_gpds; i++) { + req =3D rxq->req_pool + i; + next =3D rxq->req_pool + ((i + 1) % rxq->nr_gpds); + req->gpd->rx_gpd.gpd_flags |=3D CLDMA_GPD_FLAG_IOC; + req->gpd->rx_gpd.data_allow_len =3D cpu_to_le16(req->mtu); + req->gpd->rx_gpd.next_gpd_ptr_h =3D cpu_to_le32((u64)(next->gpd_dma_addr= ) >> 32); + req->gpd->rx_gpd.next_gpd_ptr_l =3D cpu_to_le32(next->gpd_dma_addr); + if (!rxq->nr_bds) { + req->gpd->rx_gpd.data_buff_ptr_h =3D + cpu_to_le32((u64)(req->data_dma_addr) >> 32); + req->gpd->rx_gpd.data_buff_ptr_l =3D cpu_to_le32(req->data_dma_addr); + } + if (i !=3D rxq->nr_gpds - 1) + req->gpd->rx_gpd.gpd_flags |=3D CLDMA_GPD_FLAG_HWO; + } + + INIT_WORK(&rxq->rx_done_work, mtk_cldma_rx_done_work); + + drv_info->rxq[rxq->rxqno] =3D rxq; + drv_ops->cldma_stop_queue(drv_info, DIR_RX, rxq->rxqno); + drv_ops->cldma_setup_start_addr(drv_info, DIR_RX, + rxq->rxqno, rxq->req_pool[0].gpd_dma_addr); + drv_ops->cldma_start_queue(drv_info, DIR_RX, rxq->rxqno); + drv_ops->cldma_unmask_intr(drv_info, DIR_RX, rxq->rxqno, QUEUE_ERROR); + drv_ops->cldma_unmask_intr(drv_info, DIR_RX, rxq->rxqno, QUEUE_XFER_DONE); + + return rxq; + +err_free_req: + for (i =3D 0; i < rxq->nr_gpds; i++) { + req =3D rxq->req_pool + i; + if (!req->gpd) + break; + mtk_cldma_rxq_alloc_cancel(drv_info, req, rxq->nr_bds); + } + + devm_kfree(mdev->dev, rxq->req_pool); +err_free_rxq: + devm_kfree(mdev->dev, rxq); + return NULL; +} + +static void mtk_cldma_rxq_free(struct cldma_drv_info *drv_info, u32 rxqno) +{ + struct cldma_drv_ops *drv_ops; + struct mtk_md_dev *mdev; + struct bd_dsc *bd_dsc; + struct rx_req *req; + struct rxq *rxq; + int irq_id; + int i, j; + + mdev =3D drv_info->mdev; + drv_ops =3D drv_info->drv_ops; + + rxq =3D drv_info->rxq[rxqno]; + drv_info->rxq[rxqno] =3D NULL; + + /* stop HW rx transaction */ + atomic_set(&rxq->need_exit, 1); + drv_ops->cldma_stop_queue(drv_info, DIR_RX, rxqno); + + irq_id =3D mtk_pci_get_virq_id(mdev, drv_info->pci_ext_irq_id); + synchronize_irq(irq_id); + /* flush on-going work */ + flush_work(&rxq->rx_done_work); + /* mask L2 RX interrupt again to avoid race condition causing use-after-f= ree issue */ + drv_ops->cldma_mask_intr(drv_info, DIR_RX, rxqno, QUEUE_XFER_DONE); + drv_ops->cldma_mask_intr(drv_info, DIR_RX, rxqno, QUEUE_ERROR); + + /* free rx req resource */ + for (i =3D 0; i < rxq->nr_gpds; i++) { + req =3D rxq->req_pool + rxq->free_idx; + if (!(req->gpd->rx_gpd.gpd_flags & CLDMA_GPD_FLAG_HWO) && + le16_to_cpu(req->gpd->rx_gpd.data_recv_len)) { + mtk_cldma_rx_skb_adjust(mdev, rxq, req); + rxq->rx_done(req->skb, rxq->arg, true); + req->skb =3D NULL; + } + if (req->skb) { + if (rxq->nr_bds) { + skb_shinfo(req->skb)->frag_list =3D NULL; + } else { + if (req->data_dma_addr) + dma_unmap_single(mdev->dev, req->data_dma_addr, + req->mtu, DMA_FROM_DEVICE); + dev_kfree_skb_any(req->skb); + } + } + for (j =3D 0; j < rxq->nr_bds; j++) { + bd_dsc =3D req->bd_dsc_pool + j; + if (bd_dsc->skb) { + if (bd_dsc->data_dma_addr) + dma_unmap_single(mdev->dev, bd_dsc->data_dma_addr, + req->frag_size, DMA_FROM_DEVICE); + bd_dsc->skb->next =3D NULL; + dev_kfree_skb_any(bd_dsc->skb); + } + dma_pool_free(drv_info->bd_dma_pool, + bd_dsc->bd, bd_dsc->bd_dma_addr); + } + if (req->bd_dsc_pool) + devm_kfree(mdev->dev, req->bd_dsc_pool); + dma_pool_free(drv_info->gpd_dma_pool, req->gpd, req->gpd_dma_addr); + rxq->free_idx =3D (rxq->free_idx + 1) % rxq->nr_gpds; + } + + devm_kfree(mdev->dev, rxq->req_pool); + devm_kfree(mdev->dev, rxq); +} + +static int mtk_cldma_start_xfer(struct cldma_drv_info *drv_info, u32 qno) +{ + struct cldma_drv_ops *drv_ops; + struct txq *txq; + u32 val; + + txq =3D drv_info->txq[qno]; + drv_ops =3D drv_info->drv_ops; + + val =3D drv_ops->cldma_get_tx_start_addr(drv_info, qno); + if (unlikely(val =3D=3D LINK_ERROR_VAL)) + return -EIO; + + if (unlikely(!val)) { + drv_ops->cldma_drv_init(drv_info); + txq =3D drv_info->txq[qno]; + drv_ops->cldma_setup_start_addr(drv_info, DIR_TX, qno, + txq->req_pool[txq->free_idx].gpd_dma_addr); + drv_ops->cldma_start_queue(drv_info, DIR_TX, qno); + txq->tx_started =3D true; + } else if (unlikely(!txq->tx_started)) { + drv_ops->cldma_start_queue(drv_info, DIR_TX, qno); + txq->tx_started =3D true; + } else { + drv_ops->cldma_resume_queue(drv_info, DIR_TX, qno); + } + + return 0; +} + +int mtk_cldma_init(struct mtk_ctrl_trans *trans) +{ + struct cldma_dev *cd; + + cd =3D devm_kzalloc(trans->mdev->dev, sizeof(*cd), GFP_KERNEL); + if (!cd) + return -ENOMEM; + + cd->trans =3D trans; + trans->dev =3D cd; + + return 0; +} + +void mtk_cldma_exit(struct mtk_ctrl_trans *trans) +{ + if (!trans->dev) + return; + + devm_kfree(trans->mdev->dev, trans->dev); + trans->dev =3D NULL; +} + +static int mtk_cldma_open(struct cldma_dev *cd, struct sk_buff *skb) +{ + struct trb_open_priv *trb_open_priv =3D (struct trb_open_priv *)skb->data; + struct trb *trb =3D (struct trb *)skb->cb; + struct cldma_drv_info *drv_info; + struct queue_info *que; + struct txq *txq; + struct rxq *rxq; + int ret =3D 0; + + que =3D radix_tree_lookup(&cd->trans->queue_tbl, trb->channel_id & 0xFFFF= ); + drv_info =3D cd->cldma_drv_info[que->hif_id]; + if (!drv_info) { + ret =3D -EIO; + goto out; + } + + if (que->tx_mtu =3D=3D 0 || que->rx_mtu =3D=3D 0) { + dev_err((cd->trans->mdev)->dev, + "Failed to enable cldma%d txq%d rxq%d due to wrong mtu\n", + drv_info->hw_id, que->txqno, que->rxqno); + ret =3D -EINVAL; + goto out; + } + + trb_open_priv->tx_mtu =3D que->tx_mtu; + trb_open_priv->rx_mtu =3D que->rx_mtu; + trb_open_priv->tx_frag_size =3D que->tx_frag_size; + trb_open_priv->rx_frag_size =3D que->rx_frag_size; + + if (drv_info->txq[que->txqno] || drv_info->rxq[que->rxqno]) { + ret =3D -EBUSY; + goto out; + } + + txq =3D mtk_cldma_txq_alloc(drv_info, skb); + if (!txq) { + ret =3D -ENOMEM; + goto out; + } + + rxq =3D mtk_cldma_rxq_alloc(drv_info, skb); + if (!rxq) { + ret =3D -ENOMEM; + mtk_cldma_txq_free(drv_info, txq->txqno); + goto out; + } + +out: + trb->status =3D ret; + trb->trb_complete(skb); + + return ret; +} + +static int mtk_cldma_tx(struct cldma_dev *cd, struct sk_buff *skb) +{ + struct trb *trb =3D (struct trb *)skb->cb; + struct cldma_drv_info *drv_info; + struct mtk_md_dev *mdev; + struct queue_info *que; + struct txq *txq; + int ret; + + que =3D radix_tree_lookup(&cd->trans->queue_tbl, trb->channel_id & 0xFFFF= ); + drv_info =3D cd->cldma_drv_info[que->hif_id]; + if (unlikely(!drv_info)) + return -EPIPE; + txq =3D drv_info->txq[que->txqno]; + if (unlikely(!txq) || txq->is_stopping) + return -EPIPE; + + mdev =3D drv_info->mdev; + + ret =3D mtk_cldma_start_xfer(drv_info, que->txqno); + if (unlikely(ret)) + dev_err((mdev)->dev, "Failed to trigger cldma tx\n"); + + return ret; +} + +static int mtk_cldma_close(struct cldma_dev *cd, struct sk_buff *skb) +{ + struct trb *trb =3D (struct trb *)skb->cb; + struct cldma_drv_info *drv_info; + struct queue_info *que; + + que =3D radix_tree_lookup(&cd->trans->queue_tbl, trb->channel_id & 0xFFFF= ); + drv_info =3D cd->cldma_drv_info[que->hif_id]; + if (unlikely(!drv_info)) + return -EPIPE; + + if (drv_info->txq[que->txqno]) + mtk_cldma_txq_free(drv_info, que->txqno); + if (drv_info->rxq[que->rxqno]) + mtk_cldma_rxq_free(drv_info, que->rxqno); + + trb->status =3D 0; + trb->trb_complete(skb); + + return 0; +} + +static int mtk_cldma_txbuf_set(struct cldma_drv_info *drv_info, struct sk_= buff *skb, + struct tx_req *req, int nr_bds) +{ + struct sk_buff *curr_skb, *next_skb; + struct mtk_md_dev *mdev; + struct bd_dsc *bd_dsc; + int ret; + int i; + + mdev =3D drv_info->mdev; + + if (nr_bds) { + bd_dsc =3D req->bd_dsc_pool; + curr_skb =3D skb; + for (i =3D 0; i < nr_bds && curr_skb; i++) { + bd_dsc =3D req->bd_dsc_pool + i; + if (req->bd_dsc_pool =3D=3D bd_dsc) { + bd_dsc->data_len =3D skb->len - skb->data_len; + next_skb =3D skb_shinfo(skb)->frag_list; + } else { + bd_dsc->data_len =3D curr_skb->len; + next_skb =3D curr_skb->next; + } + bd_dsc->data_dma_addr =3D dma_map_single(mdev->dev, curr_skb->data, + bd_dsc->data_len, DMA_TO_DEVICE); + ret =3D dma_mapping_error(mdev->dev, bd_dsc->data_dma_addr); + if (unlikely(ret)) + goto err_unmap_buffer; + + bd_dsc->bd->tx_bd.data_buff_ptr_h =3D + cpu_to_le32((u64)(bd_dsc->data_dma_addr) >> 32); + bd_dsc->bd->tx_bd.data_buff_ptr_l =3D cpu_to_le32(bd_dsc->data_dma_addr= ); + bd_dsc->bd->tx_bd.data_buffer_len =3D cpu_to_le16(bd_dsc->data_len); + curr_skb =3D next_skb; + } + bd_dsc->bd->tx_bd.bd_flags =3D CLDMA_BD_FLAG_EOL; + } else { + req->data_dma_addr =3D dma_map_single(mdev->dev, skb->data, + skb->len, DMA_TO_DEVICE); + ret =3D dma_mapping_error(mdev->dev, req->data_dma_addr); + if (unlikely(ret)) { + req->data_dma_addr =3D 0; + goto err_exit; + } + + req->gpd->tx_gpd.data_buff_ptr_h =3D cpu_to_le32((u64)(req->data_dma_add= r) >> 32); + req->gpd->tx_gpd.data_buff_ptr_l =3D cpu_to_le32(req->data_dma_addr); + } + + return 0; + +err_unmap_buffer: + for (i =3D 0; i < nr_bds; i++) { + bd_dsc =3D req->bd_dsc_pool + i; + if (dma_mapping_error(mdev->dev, bd_dsc->data_dma_addr)) { + bd_dsc->data_dma_addr =3D 0; + break; + } + dma_unmap_single(mdev->dev, bd_dsc->data_dma_addr, + bd_dsc->data_len, DMA_TO_DEVICE); + bd_dsc->data_dma_addr =3D 0; + } +err_exit: + dev_err((mdev)->dev, "Failed to map dma! error:%d\n", ret); + return -EAGAIN; +} + +int mtk_cldma_submit_tx(void *dev, struct sk_buff *skb) +{ + struct trb *trb =3D (struct trb *)skb->cb; + struct cldma_drv_info *drv_info; + struct cldma_dev *cd =3D dev; + struct queue_info *que; + struct tx_req *req; + struct txq *txq; + int ret; + + que =3D radix_tree_lookup(&cd->trans->queue_tbl, trb->channel_id & 0xFFFF= ); + drv_info =3D cd->cldma_drv_info[que->hif_id]; + if (unlikely(!drv_info)) + return -EINVAL; + + txq =3D drv_info->txq[que->txqno]; + if (unlikely(!txq)) + return -EINVAL; + + if (!atomic_read(&txq->req_budget)) + return -EAGAIN; + + req =3D txq->req_pool + txq->wr_idx; + req->gpd->tx_gpd.debug_id =3D 0x01; + ret =3D mtk_cldma_txbuf_set(drv_info, skb, req, txq->nr_bds); + if (ret) + return ret; + + req->gpd->tx_gpd.data_buff_len =3D cpu_to_le16(skb->len); + + req->data_len =3D skb->len; + req->skb =3D skb; + req->data_vm_addr =3D skb->data; + + wmb(); /* ensure req and data msg set done before HWO setup */ + + req->gpd->tx_gpd.gpd_flags |=3D CLDMA_GPD_FLAG_HWO; + + wmb(); /* ensure HWO setup done before index update */ + + txq->wr_idx =3D (txq->wr_idx + 1) % txq->nr_gpds; + atomic_dec(&txq->req_budget); + + return 0; +} + +int mtk_cldma_get_tx_budget(void *dev, enum mtk_hif_id hif_id, u32 qno) +{ + struct cldma_drv_info *drv_info; + struct cldma_dev *cd =3D dev; + struct txq *txq; + + if (unlikely(hif_id >=3D NR_CLDMA || qno >=3D HW_QUE_NUM || !cd)) + return -EINVAL; + + drv_info =3D cd->cldma_drv_info[hif_id]; + if (!drv_info) + return -EINVAL; + txq =3D drv_info->txq[qno]; + if (!txq) + return -EINVAL; + return atomic_read(&txq->req_budget); +} + +static int (*trb_act_tbl[TRB_CMD_MAX])(struct cldma_dev *cd, struct sk_buf= f *skb) =3D { + [TRB_CMD_ENABLE] =3D mtk_cldma_open, + [TRB_CMD_TX] =3D mtk_cldma_tx, + [TRB_CMD_DISABLE] =3D mtk_cldma_close, +}; + +int mtk_cldma_trb_process(void *dev, struct sk_buff *skb) +{ + struct cldma_dev *cd; + struct trb *trb; + + if (!dev || !skb) + return -EINVAL; + + cd =3D (struct cldma_dev *)dev; + trb =3D (struct trb *)skb->cb; + + if (!(trb->cmd > TRB_CMD_MIN && trb->cmd < TRB_CMD_STOP)) + return -EINVAL; + + return trb_act_tbl[trb->cmd](cd, skb); +} + +int mtk_cldma_check_ch_cfg(void *dev, struct queue_info *que) +{ + struct cldma_drv_info *drv_info; + struct cldma_dev *cd =3D dev; + struct mtk_md_dev *mdev; + struct txq *txq; + struct rxq *rxq; + + mdev =3D cd->trans->mdev; + drv_info =3D cd->cldma_drv_info[que->hif_id]; + + if (!drv_info) { + dev_err((mdev)->dev, "CLDMA%d has not been initialized\n", + mtk_cldma_hw_id_tbl[que->hif_id]); + return -EINVAL; + } + + txq =3D drv_info->txq[que->txqno]; + rxq =3D drv_info->rxq[que->rxqno]; + if (!txq || !rxq) { + dev_err((mdev)->dev, + "CLDMA%d txq%d rxq%d has not been enabled\n", + mtk_cldma_hw_id_tbl[que->hif_id], que->txqno, que->rxqno); + return -EINVAL; + } + + if (que->tx_mtu !=3D txq->que->tx_mtu || que->rx_mtu !=3D rxq->que->rx_mt= u) { + dev_err((mdev)->dev, + "Channel:%08x tx_mtu:%08x rx_mtu:%08x do not match ch cfg\n", + que->tx_chl, que->tx_mtu, que->rx_mtu); + return -EINVAL; + } + + return 0; +} diff --git a/drivers/net/wwan/t9xx/pcie/mtk_cldma.h b/drivers/net/wwan/t9xx= /pcie/mtk_cldma.h new file mode 100644 index 000000000000..74ce4f2f0b30 --- /dev/null +++ b/drivers/net/wwan/t9xx/pcie/mtk_cldma.h @@ -0,0 +1,170 @@ +/* SPDX-License-Identifier: GPL-2.0-only + * + * Copyright (c) 2022, MediaTek Inc. + */ + +#ifndef __MTK_CLDMA_H__ +#define __MTK_CLDMA_H__ + +#include +#include +#include +#include +#include +#include + +#include "mtk_ctrl_plane.h" +#include "mtk_trans_ctrl.h" + +struct mtk_fsm_param; + +#define TXQ(N) (N) +#define RXQ(N) (N) + +#define CLDMA_GPD_FLAG_HWO BIT(0) +#define CLDMA_GPD_FLAG_BDP BIT(1) +#define CLDMA_GPD_FLAG_BPS BIT(2) +#define CLDMA_GPD_FLAG_IOC BIT(7) +#define CLDMA_BD_FLAG_EOL BIT(0) + +union gpd { + struct { + u8 gpd_flags; + u8 non_used1; + __le16 data_allow_len; + __le32 next_gpd_ptr_h; + __le32 next_gpd_ptr_l; + __le32 data_buff_ptr_h; + __le32 data_buff_ptr_l; + __le16 data_recv_len; + u8 non_used2; + u8 debug_id; + } rx_gpd; + + struct { + u8 gpd_flags; + u8 non_used1; + u8 non_used2; + u8 debug_id; + __le32 next_gpd_ptr_h; + __le32 next_gpd_ptr_l; + __le32 data_buff_ptr_h; + __le32 data_buff_ptr_l; + __le16 data_buff_len; + __le16 non_used3; + } tx_gpd; +} __packed; + +union bd { + struct { + u8 bd_flags; + u8 non_used1; + __le16 data_allow_len; + __le32 next_bd_ptr_h; + __le32 next_bd_ptr_l; + __le32 data_buff_ptr_h; + __le32 data_buff_ptr_l; + __le16 data_recv_len; + __le16 non_used2; + } rx_bd; + + struct { + u8 bd_flags; + u8 non_used1; + __le16 non_used2; + __le32 next_bd_ptr_h; + __le32 next_bd_ptr_l; + __le32 data_buff_ptr_h; + __le32 data_buff_ptr_l; + __le16 data_buffer_len; + u8 extension_len; + u8 non_used3; + } tx_bd; +} __packed; + +struct bd_dsc { + union bd *bd; + struct sk_buff *skb; + dma_addr_t bd_dma_addr; + dma_addr_t data_dma_addr; + size_t data_len; +}; + +struct rx_req { + union gpd *gpd; + u32 mtu; + struct sk_buff *skb; + size_t data_len; + dma_addr_t gpd_dma_addr; + dma_addr_t data_dma_addr; + u32 frag_size; + struct bd_dsc *bd_dsc_pool; +}; + +struct rxq { + struct cldma_drv_info *drv_info; + u32 rxqno; + struct queue_info *que; + struct work_struct rx_done_work; + struct rx_req *req_pool; + u32 nr_gpds; + u32 free_idx; + unsigned short rx_done_cnt; + void *arg; + int (*rx_done)(struct sk_buff *skb, void *priv, bool force_recv); + u32 nr_bds; + atomic_t need_exit; +}; + +struct tx_req { + union gpd *gpd; + u32 mtu; + void *data_vm_addr; + size_t data_len; + dma_addr_t data_dma_addr; + dma_addr_t gpd_dma_addr; + struct sk_buff *skb; + int (*trb_complete)(struct sk_buff *skb); + u32 frag_size; + struct bd_dsc *bd_dsc_pool; +}; + +struct txq { + struct cldma_drv_info *drv_info; + u32 txqno; + struct queue_info *que; + struct work_struct tx_done_work; + struct tx_req *req_pool; + u32 nr_gpds; + atomic_t req_budget; + u32 wr_idx; + u32 free_idx; + bool tx_started; + bool is_stopping; + unsigned short tx_done_cnt; + u32 nr_bds; +}; + +struct cldma_dev { + struct cldma_drv_info *cldma_drv_info[NR_CLDMA]; + struct mtk_ctrl_trans *trans; +}; + +struct cldma_drv_info_desc { + u32 hw_ver; + struct cldma_drv_ops *drv_ops; + struct cldma_hw_regs *hw_regs; +}; + +int mtk_cldma_init(struct mtk_ctrl_trans *trans); +void mtk_cldma_exit(struct mtk_ctrl_trans *trans); +int mtk_cldma_submit_tx(void *dev, struct sk_buff *skb); +int mtk_cldma_get_tx_budget(void *dev, enum mtk_hif_id hif_id, u32 qno); +int mtk_cldma_trb_process(void *dev, struct sk_buff *skb); +void mtk_cldma_fsm_state_listener(struct mtk_fsm_param *param, struct mtk_= ctrl_trans *trans); +int mtk_cldma_check_ch_cfg(void *dev, struct queue_info *que); + +#define drv_ops_name(NAME) cldma_drv_ops_##NAME +#define cldma_regs_name(NAME) mtk_cldma_regs_##NAME + +#endif diff --git a/drivers/net/wwan/t9xx/pcie/mtk_cldma_drv.c b/drivers/net/wwan/= t9xx/pcie/mtk_cldma_drv.c new file mode 100644 index 000000000000..b5d3894dd62c --- /dev/null +++ b/drivers/net/wwan/t9xx/pcie/mtk_cldma_drv.c @@ -0,0 +1,371 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2023, MediaTek Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "mtk_cldma_drv.h" +#include "mtk_dev.h" +#include "mtk_pci.h" +#include "mtk_pci_reg.h" + +#define WAIT_QUEUE_STOP (70) + +void mtk_cldma_drv_init(struct cldma_drv_info *drv_info) +{ + struct cldma_hw_regs *hw_regs; + struct mtk_md_dev *mdev; + int base; + u32 val; + + mdev =3D drv_info->mdev; + base =3D drv_info->base_addr; + hw_regs =3D drv_info->hw_regs; + + /* set CLDMA to 64 bit mode GPD */ + val =3D mtk_pci_read32(mdev, base + hw_regs->reg_cldma_ul_cfg); + val =3D (val & (~(0x7 << 5))) | ((0x4) << 5); + mtk_pci_write32(mdev, base + hw_regs->reg_cldma_ul_cfg, val); + + val =3D mtk_pci_read32(mdev, base + hw_regs->reg_cldma_so_cfg); + val =3D (val & (~(0x7 << 10))) | ((0x4) << 10) | (1 << 2); + mtk_pci_write32(mdev, base + hw_regs->reg_cldma_so_cfg, val); + + mtk_pci_write32(mdev, base + hw_regs->reg_cldma_rx_work_to_reg_mask_set, = ALLQ); + mtk_pci_write32(mdev, base + hw_regs->reg_cldma_ip_busy_to_pcie_mask_set, + ALLQ << 16); + mtk_pci_write32(mdev, base + hw_regs->reg_cldma_ip_busy_to_pcie_mask_clr, + ALLQ << 24); + + /* enable interrupt to PCIe */ + mtk_pci_write32(mdev, base + hw_regs->reg_cldma_int_mask, 0); + + /* disable illegal memory check */ + mtk_pci_write32(mdev, base + hw_regs->reg_cldma_ul_dummy_0, 1); + mtk_pci_write32(mdev, base + hw_regs->reg_cldma_so_dummy_0, 1); +} + +void mtk_cldma_setup_start_addr(struct cldma_drv_info *drv_info, enum mtk_= tx_rx dir, + u32 qno, dma_addr_t addr) +{ + struct cldma_hw_regs *hw_regs; + unsigned int addr_l; + unsigned int addr_h; + int base; + + hw_regs =3D drv_info->hw_regs; + base =3D drv_info->base_addr; + + if (dir =3D=3D DIR_TX) { + addr_l =3D base + hw_regs->reg_cldma_ul_start_addrl_0 + qno * HW_QUEUE_N= UM; + addr_h =3D base + hw_regs->reg_cldma_ul_start_addrh_0 + qno * HW_QUEUE_N= UM; + } else { + addr_l =3D base + hw_regs->reg_cldma_so_start_addrl_0 + qno * HW_QUEUE_N= UM; + addr_h =3D base + hw_regs->reg_cldma_so_start_addrh_0 + qno * HW_QUEUE_N= UM; + } + + mtk_pci_write32(drv_info->mdev, addr_l, (u32)addr); + mtk_pci_write32(drv_info->mdev, addr_h, (u32)((u64)addr >> 32)); +} + +void mtk_cldma_mask_intr(struct cldma_drv_info *drv_info, enum mtk_tx_rx d= ir, + u32 qno, enum mtk_intr_type type) +{ + struct cldma_hw_regs *hw_regs; + int base; + u32 addr; + u32 val; + + hw_regs =3D drv_info->hw_regs; + base =3D drv_info->base_addr; + + if (dir =3D=3D DIR_TX) + addr =3D base + hw_regs->reg_cldma_l2timsr0; + else + addr =3D base + hw_regs->reg_cldma_l2rimsr0; + + if (qno =3D=3D ALLQ) + val =3D qno << type; + else + val =3D BIT(qno) << type; + + mtk_pci_write32(drv_info->mdev, addr, val); +} + +void mtk_cldma_unmask_intr(struct cldma_drv_info *drv_info, enum mtk_tx_rx= dir, + u32 qno, enum mtk_intr_type type) +{ + struct cldma_hw_regs *hw_regs; + int base; + u32 addr; + u32 val; + + hw_regs =3D drv_info->hw_regs; + base =3D drv_info->base_addr; + + if (dir =3D=3D DIR_TX) + addr =3D base + hw_regs->reg_cldma_l2timcr0; + else + addr =3D base + hw_regs->reg_cldma_l2rimcr0; + + if (qno =3D=3D ALLQ) + val =3D qno << type; + else + val =3D BIT(qno) << type; + + mtk_pci_write32(drv_info->mdev, addr, val); +} + +void mtk_cldma_clr_intr_status(struct cldma_drv_info *drv_info, enum mtk_t= x_rx dir, + u32 qno, enum mtk_intr_type type) +{ + struct cldma_hw_regs *hw_regs; + struct mtk_md_dev *mdev; + int base; + u32 addr; + u32 val; + + hw_regs =3D drv_info->hw_regs; + base =3D drv_info->base_addr; + mdev =3D drv_info->mdev; + + if (type =3D=3D QUEUE_ERROR) { + if (dir =3D=3D DIR_TX) { + val =3D mtk_pci_read32(mdev, base + hw_regs->reg_cldma_l3tisar0); + mtk_pci_write32(mdev, base + hw_regs->reg_cldma_l3tisar0, val); + val =3D mtk_pci_read32(mdev, base + hw_regs->reg_cldma_l3tisar1); + mtk_pci_write32(mdev, base + hw_regs->reg_cldma_l3tisar1, val); + val =3D mtk_pci_read32(mdev, base + hw_regs->reg_cldma_l3tisar2); + mtk_pci_write32(mdev, base + hw_regs->reg_cldma_l3tisar2, val); + } else { + val =3D mtk_pci_read32(mdev, base + hw_regs->reg_cldma_l3risar0); + mtk_pci_write32(mdev, base + hw_regs->reg_cldma_l3risar0, val); + val =3D mtk_pci_read32(mdev, base + hw_regs->reg_cldma_l3risar1); + mtk_pci_write32(mdev, base + hw_regs->reg_cldma_l3risar1, val); + } + } + + if (dir =3D=3D DIR_TX) + addr =3D base + hw_regs->reg_cldma_l2tisar0; + else + addr =3D base + hw_regs->reg_cldma_l2risar0; + + if (qno =3D=3D ALLQ) + val =3D qno << type; + else + val =3D BIT(qno) << type; + + mtk_pci_write32(mdev, addr, val); + val =3D mtk_pci_read32(mdev, addr); +} + +u32 mtk_cldma_check_intr_status(struct cldma_drv_info *drv_info, enum mtk_= tx_rx dir, + u32 qno, enum mtk_intr_type type) +{ + struct cldma_hw_regs *hw_regs; + u32 addr, val, sta; + int base; + + hw_regs =3D drv_info->hw_regs; + base =3D drv_info->base_addr; + + if (dir =3D=3D DIR_TX) + addr =3D base + hw_regs->reg_cldma_l2tisar0; + else + addr =3D base + hw_regs->reg_cldma_l2risar0; + + val =3D mtk_pci_read32(drv_info->mdev, addr); + if (val =3D=3D LINK_ERROR_VAL) + sta =3D val; + else if (qno =3D=3D ALLQ) + sta =3D (val >> type) & 0xFF; + else + sta =3D (val >> type) & BIT(qno); + + return sta; +} + +void mtk_cldma_start_queue(struct cldma_drv_info *drv_info, enum mtk_tx_rx= dir, u32 qno) +{ + struct cldma_hw_regs *hw_regs; + u32 val =3D BIT(qno); + int base; + u32 addr; + + hw_regs =3D drv_info->hw_regs; + base =3D drv_info->base_addr; + + if (dir =3D=3D DIR_TX) + addr =3D base + hw_regs->reg_cldma_ul_start_cmd; + else + addr =3D base + hw_regs->reg_cldma_so_start_cmd; + + mtk_pci_write32(drv_info->mdev, addr, val); +} + +void mtk_cldma_resume_queue(struct cldma_drv_info *drv_info, enum mtk_tx_r= x dir, u32 qno) +{ + struct cldma_hw_regs *hw_regs; + u32 val =3D BIT(qno); + int base; + u32 addr; + + hw_regs =3D drv_info->hw_regs; + base =3D drv_info->base_addr; + + if (dir =3D=3D DIR_TX) + addr =3D base + hw_regs->reg_cldma_ul_resume_cmd; + else + addr =3D base + hw_regs->reg_cldma_so_resume_cmd; + + mtk_pci_write32(drv_info->mdev, addr, val); +} + +u32 mtk_cldma_queue_status(struct cldma_drv_info *drv_info, enum mtk_tx_rx= dir, u32 qno) +{ + struct cldma_hw_regs *hw_regs; + int base; + u32 addr; + u32 val; + + hw_regs =3D drv_info->hw_regs; + base =3D drv_info->base_addr; + + if (dir =3D=3D DIR_TX) + addr =3D base + hw_regs->reg_cldma_ul_status; + else + addr =3D base + hw_regs->reg_cldma_so_status; + + val =3D mtk_pci_read32(drv_info->mdev, addr); + + if (qno =3D=3D ALLQ || val =3D=3D LINK_ERROR_VAL) + return val; + + return val & BIT(qno); +} + +u32 mtk_cldma_stop_queue(struct cldma_drv_info *drv_info, enum mtk_tx_rx d= ir, u32 qno) +{ + u32 val =3D (qno =3D=3D ALLQ) ? qno : BIT(qno); + struct cldma_hw_regs *hw_regs; + unsigned int active; + int cnt =3D 0; + int base; + u32 addr; + + hw_regs =3D drv_info->hw_regs; + base =3D drv_info->base_addr; + + if (dir =3D=3D DIR_TX) + addr =3D base + hw_regs->reg_cldma_ul_stop_cmd; + else + addr =3D base + hw_regs->reg_cldma_so_stop_cmd; + + mtk_pci_write32(drv_info->mdev, addr, val); + + do { + active =3D drv_info->drv_ops->cldma_queue_status(drv_info, dir, qno); + if (active =3D=3D LINK_ERROR_VAL || !active) + break; + usleep_range(WAIT_QUEUE_STOP, 2 * WAIT_QUEUE_STOP); + } while (++cnt < 10); + + return active; +} + +void mtk_cldma_clear_ip_busy(struct cldma_drv_info *drv_info) +{ + mtk_pci_write32(drv_info->mdev, drv_info->base_addr + + drv_info->hw_regs->reg_cldma_ip_busy, 0x01); +} + +void mtk_cldma_get_intr_status(struct cldma_drv_info *drv_info, u32 *tx_st= a, u32 *rx_sta) +{ + struct cldma_hw_regs *hw_regs; + struct mtk_md_dev *mdev; + u32 tx_mask, rx_mask; + int base; + + mdev =3D drv_info->mdev; + base =3D drv_info->base_addr; + hw_regs =3D drv_info->hw_regs; + + *tx_sta =3D mtk_pci_read32(mdev, base + hw_regs->reg_cldma_l2tisar0); + tx_mask =3D mtk_pci_read32(mdev, base + hw_regs->reg_cldma_l2timr0); + *rx_sta =3D mtk_pci_read32(mdev, base + hw_regs->reg_cldma_l2risar0); + rx_mask =3D mtk_pci_read32(mdev, base + hw_regs->reg_cldma_l2rimr0); + + *tx_sta =3D (*tx_sta) & (~tx_mask); + *rx_sta =3D (*rx_sta) & (~rx_mask); + + if (*tx_sta) { + /* TX XFER_DONE and QUEUE_ERROR mask */ + mtk_pci_write32(mdev, base + hw_regs->reg_cldma_l2timsr0, *tx_sta); + /* TX XFER_DONE clear */ + mtk_pci_write32(mdev, base + hw_regs->reg_cldma_l2tisar0, + (*tx_sta) & (0xFF << QUEUE_XFER_DONE)); + } + + if (*rx_sta) { + /* RX XFER_DONE and QUEUE_ERROR mask */ + mtk_pci_write32(mdev, base + hw_regs->reg_cldma_l2rimsr0, *rx_sta); + /* RX XFER_DONE clear */ + mtk_pci_write32(mdev, base + hw_regs->reg_cldma_l2risar0, + (*rx_sta) & (0xFF << QUEUE_XFER_DONE)); + } +} + +u32 mtk_cldma_get_tx_start_addr(struct cldma_drv_info *drv_info, u32 qno) +{ + u32 addr, val; + + addr =3D drv_info->base_addr + drv_info->hw_regs->reg_cldma_ul_start_addr= l_0 + + qno * HW_QUEUE_NUM; + val =3D mtk_pci_read32(drv_info->mdev, addr); + + return val; +} + +u64 mtk_cldma_get_rx_curr_addr(struct cldma_drv_info *drv_info, u32 qno) +{ + struct cldma_hw_regs *hw_regs; + u32 curr_addr_h, curr_addr_l; + struct mtk_md_dev *mdev; + u64 curr_addr; + int base; + u64 addr; + + hw_regs =3D drv_info->hw_regs; + base =3D drv_info->base_addr; + mdev =3D drv_info->mdev; + + addr =3D base + hw_regs->reg_cldma_so_current_addrh_0 + + (u64)qno * HW_QUEUE_NUM; + curr_addr_h =3D mtk_pci_read32(mdev, addr); + addr =3D base + hw_regs->reg_cldma_so_current_addrl_0 + + (u64)qno * HW_QUEUE_NUM; + curr_addr_l =3D mtk_pci_read32(mdev, addr); + curr_addr =3D ((u64)curr_addr_h << 32) | curr_addr_l; + if (curr_addr_h =3D=3D LINK_ERROR_VAL && curr_addr_l =3D=3D LINK_ERROR_VA= L) + curr_addr =3D 0; + return curr_addr; +} diff --git a/drivers/net/wwan/t9xx/pcie/mtk_cldma_drv.h b/drivers/net/wwan/= t9xx/pcie/mtk_cldma_drv.h new file mode 100644 index 000000000000..8763c23abf54 --- /dev/null +++ b/drivers/net/wwan/t9xx/pcie/mtk_cldma_drv.h @@ -0,0 +1,177 @@ +/* SPDX-License-Identifier: GPL-2.0-only + * + * Copyright (c) 2023, MediaTek Inc. + */ + +#ifndef __MTK_CLDMA_DRV_H__ +#define __MTK_CLDMA_DRV_H__ + +#define HW_QUEUE_NUM (8) +#define ALLQ (0xFF) +#define LINK_ERROR_VAL (0xFFFFFFFF) +#define CLDMA0_HW_ID (0) +#define CLDMA1_HW_ID (1) +#define CLDMA4_HW_ID (4) + +struct cldma_hw_regs { + u8 cldma_rx_skb_pool_max_size; + u8 cldma_rx_skb_reload_threshold; + u8 tq_err_int_offset; + u8 tq_active_start_err_int_offset; + u8 rq_err_int_offset; + u8 rq_active_start_err_int_offset; + u16 reg_cldma_so_cfg; + u16 reg_cldma_so_start_addrl_0; + u16 reg_cldma_so_start_addrh_0; + u16 reg_cldma_so_current_addrl_0; + u16 reg_cldma_so_current_addrh_0; + u16 reg_cldma_so_status; + u16 reg_cldma_debug_id_en; + u16 reg_cldma_so_last_update_addrl_0; + u16 reg_cldma_so_last_update_addrh_0; + u16 reg_cldma_l2rimr0; + u16 reg_cldma_l2rimr1; + u16 reg_cldma_l2rimcr0; + u16 reg_cldma_l2rimcr1; + u16 reg_cldma_l2rimsr0; + u16 reg_cldma_l2rimsr1; + u16 reg_cldma_int_mask; + u16 reg_cldma4_int_mask; + u16 reg_cldma_slp_mem_ctl; + u16 reg_cldma_busy_mask; + u16 reg_cldma_ip_busy_to_pcie_mask; + u16 reg_cldma_ip_busy_to_pcie_mask_set; + u16 reg_cldma_ip_busy_to_pcie_mask_clr; + u16 reg_cldma_ip_busy_to_ap_mask; + u16 reg_cldma_ip_busy_to_ap_mask_set; + u16 reg_cldma_ip_busy_to_ap_mask_clr; + u16 reg_cldma_ip_busy_to_md_mask_set; + u16 reg_cldma_rx_work_to_reg_mask_set; + u16 reg_infra_rst4_set; + u16 reg_infra_rst4_clr; + u16 reg_infra_rst2_set; + u16 reg_infra_rst2_clr; + u16 reg_infra_rst0_set; + u16 reg_infra_rst0_clr; + u32 tq_err_int_bitmask; + u32 tq_active_start_err_int_bitmask; + u32 rq_err_int_bitmask; + u32 cldma0_base_addr; + u32 cldma1_base_addr; + u32 cldma4_base_addr; + u32 rq_active_start_err_int_bitmask; + u32 reg_cldma_ul_start_addrl_0; + u32 reg_cldma_ul_start_addrh_0; + u32 reg_cldma_ul_current_addrl_0; + u32 reg_cldma_ul_current_addrh_0; + u32 reg_cldma_ul_status; + u32 reg_cldma_ul_start_cmd; + u32 reg_cldma_ul_resume_cmd; + u32 reg_cldma_ul_stop_cmd; + u32 reg_cldma_ul_error; + u32 reg_cldma_ul_cfg; + u32 reg_cldma_ul_dummy_0; + u32 reg_cldma_so_error; + u32 reg_cldma_so_start_cmd; + u32 reg_cldma_so_resume_cmd; + u32 reg_cldma_so_stop_cmd; + u32 reg_cldma_so_dummy_0; + u32 reg_cldma_l2tisar0; + u32 reg_cldma_l2tisar1; + u32 reg_cldma_l2timr0; + u32 reg_cldma_l2timr1; + u32 reg_cldma_l2timcr0; + u32 reg_cldma_l2timcr1; + u32 reg_cldma_l2timsr0; + u32 reg_cldma_l2timsr1; + u32 reg_cldma_l2risar0; + u32 reg_cldma_l2risar1; + u32 reg_cldma_l3tisar0; + u32 reg_cldma_l3tisar1; + u32 reg_cldma_l3tisar2; + u32 reg_cldma_l3risar0; + u32 reg_cldma_l3risar1; + u32 reg_cldma_ip_busy; +}; + +enum mtk_ip_busy_src { + IP_BUSY_TXDONE =3D 0, + IP_BUSY_TXEMPTY =3D 8, + IP_BUSY_TXACTIVE =3D 16, + IP_BUSY_RXDONE =3D 24 +}; + +enum mtk_intr_type { + QUEUE_XFER_DONE =3D 0, + QUEUE_EMPTY =3D 8, + QUEUE_ERROR =3D 16, + QUEUE_ACTIVE_START =3D 24, + INVALID_TYPE +}; + +enum mtk_tx_rx { + DIR_TX, + DIR_RX, + DIR_MAX +}; + +struct cldma_drv_info { + int hif_id; + int hw_id; + int base_addr; + int pci_ext_irq_id; + struct mtk_md_dev *mdev; + struct cldma_dev *cd; + struct txq *txq[HW_QUEUE_NUM]; + struct rxq *rxq[HW_QUEUE_NUM]; + struct dma_pool *gpd_dma_pool; + struct dma_pool *bd_dma_pool; + struct workqueue_struct *wq; + struct cldma_hw_regs *hw_regs; + struct cldma_drv_ops *drv_ops; +}; + +struct cldma_drv_ops { + void (*cldma_drv_init)(struct cldma_drv_info *drv_info); + void (*cldma_drv_reset)(struct cldma_drv_info *drv_info); + void (*cldma_setup_start_addr)(struct cldma_drv_info *drv_info, enum mtk_= tx_rx dir, + u32 qno, dma_addr_t addr); + void (*cldma_mask_intr)(struct cldma_drv_info *drv_info, enum mtk_tx_rx d= ir, + u32 qno, enum mtk_intr_type type); + void (*cldma_unmask_intr)(struct cldma_drv_info *drv_info, enum mtk_tx_rx= dir, + u32 qno, enum mtk_intr_type type); + void (*cldma_clr_intr_status)(struct cldma_drv_info *drv_info, enum mtk_t= x_rx dir, + u32 qno, enum mtk_intr_type type); + u32 (*cldma_check_intr_status)(struct cldma_drv_info *drv_info, enum mtk_= tx_rx dir, + u32 qno, enum mtk_intr_type type); + void (*cldma_start_queue)(struct cldma_drv_info *drv_info, enum mtk_tx_rx= dir, u32 qno); + void (*cldma_resume_queue)(struct cldma_drv_info *drv_info, enum mtk_tx_r= x dir, u32 qno); + u32 (*cldma_queue_status)(struct cldma_drv_info *drv_info, enum mtk_tx_rx= dir, u32 qno); + u32 (*cldma_stop_queue)(struct cldma_drv_info *drv_info, enum mtk_tx_rx d= ir, u32 qno); + void (*cldma_clear_ip_busy)(struct cldma_drv_info *drv_info); + void (*cldma_get_intr_status)(struct cldma_drv_info *drv_info, u32 *tx_st= a, u32 *rx_sta); + u32 (*cldma_get_tx_start_addr)(struct cldma_drv_info *drv_info, u32 qno); + u64 (*cldma_get_rx_curr_addr)(struct cldma_drv_info *drv_info, u32 qno); +}; + +void mtk_cldma_drv_init(struct cldma_drv_info *drv_info); +void mtk_cldma_setup_start_addr(struct cldma_drv_info *drv_info, enum mtk_= tx_rx dir, + u32 qno, dma_addr_t addr); +void mtk_cldma_mask_intr(struct cldma_drv_info *drv_info, enum mtk_tx_rx d= ir, + u32 qno, enum mtk_intr_type type); +void mtk_cldma_unmask_intr(struct cldma_drv_info *drv_info, enum mtk_tx_rx= dir, + u32 qno, enum mtk_intr_type type); +void mtk_cldma_clr_intr_status(struct cldma_drv_info *drv_info, enum mtk_t= x_rx dir, + u32 qno, enum mtk_intr_type type); +u32 mtk_cldma_check_intr_status(struct cldma_drv_info *drv_info, enum mtk_= tx_rx dir, + u32 qno, enum mtk_intr_type type); +void mtk_cldma_start_queue(struct cldma_drv_info *drv_info, enum mtk_tx_rx= dir, u32 qno); +void mtk_cldma_resume_queue(struct cldma_drv_info *drv_info, enum mtk_tx_r= x dir, u32 qno); +u32 mtk_cldma_queue_status(struct cldma_drv_info *drv_info, enum mtk_tx_rx= dir, u32 qno); +u32 mtk_cldma_stop_queue(struct cldma_drv_info *drv_info, enum mtk_tx_rx d= ir, u32 qno); +void mtk_cldma_clear_ip_busy(struct cldma_drv_info *drv_info); +void mtk_cldma_get_intr_status(struct cldma_drv_info *drv_info, u32 *tx_st= a, u32 *rx_sta); +u32 mtk_cldma_get_tx_start_addr(struct cldma_drv_info *drv_info, u32 qno); +u64 mtk_cldma_get_rx_curr_addr(struct cldma_drv_info *drv_info, u32 qno); + +#endif diff --git a/drivers/net/wwan/t9xx/pcie/mtk_cldma_drv_m9xx.c b/drivers/net/= wwan/t9xx/pcie/mtk_cldma_drv_m9xx.c new file mode 100644 index 000000000000..240a9f58f658 --- /dev/null +++ b/drivers/net/wwan/t9xx/pcie/mtk_cldma_drv_m9xx.c @@ -0,0 +1,182 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2023, MediaTek Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "mtk_cldma_drv.h" +#include "mtk_cldma_drv_m9xx.h" +#include "mtk_dev.h" +#include "mtk_pci.h" +#include "mtk_pci_reg.h" +#include "mtk_trans_ctrl.h" + +struct cldma_hw_regs mtk_cldma_regs_m9xx =3D { + .cldma0_base_addr =3D CLDMA0_BASE_ADDR, + .cldma1_base_addr =3D CLDMA1_BASE_ADDR, + .cldma4_base_addr =3D CLDMA4_BASE_ADDR, + .cldma_rx_skb_pool_max_size =3D CLDMA_RX_SKB_POOL_MAX_SIZE, + .cldma_rx_skb_reload_threshold =3D CLDMA_RX_SKB_RELOAD_THRESHOLD, + .tq_err_int_offset =3D TQ_ERR_INT_OFFSET, + .tq_err_int_bitmask =3D TQ_ERR_INT_BITMASK, + .tq_active_start_err_int_offset =3D TQ_ACTIVE_START_ERR_INT_OFFSET, + .tq_active_start_err_int_bitmask =3D TQ_ACTIVE_START_ERR_INT_BITMASK, + .rq_err_int_offset =3D RQ_ERR_INT_OFFSET, + .rq_err_int_bitmask =3D RQ_ERR_INT_BITMASK, + .rq_active_start_err_int_offset =3D RQ_ACTIVE_START_ERR_INT_OFFSET, + .rq_active_start_err_int_bitmask =3D RQ_ACTIVE_START_ERR_INT_BITMASK, + .reg_cldma_ul_start_addrl_0 =3D REG_CLDMA_UL_START_ADDRL_0, + .reg_cldma_ul_start_addrh_0 =3D REG_CLDMA_UL_START_ADDRH_0, + .reg_cldma_ul_current_addrl_0 =3D REG_CLDMA_UL_CURRENT_ADDRL_0, + .reg_cldma_ul_current_addrh_0 =3D REG_CLDMA_UL_CURRENT_ADDRH_0, + .reg_cldma_ul_status =3D REG_CLDMA_UL_STATUS, + .reg_cldma_ul_start_cmd =3D REG_CLDMA_UL_START_CMD, + .reg_cldma_ul_resume_cmd =3D REG_CLDMA_UL_RESUME_CMD, + .reg_cldma_ul_stop_cmd =3D REG_CLDMA_UL_STOP_CMD, + .reg_cldma_ul_error =3D REG_CLDMA_UL_ERROR, + .reg_cldma_ul_cfg =3D REG_CLDMA_UL_CFG, + .reg_cldma_ul_dummy_0 =3D REG_CLDMA_UL_DUMMY_0, + .reg_cldma_so_error =3D REG_CLDMA_SO_ERROR, + .reg_cldma_so_start_cmd =3D REG_CLDMA_SO_START_CMD, + .reg_cldma_so_resume_cmd =3D REG_CLDMA_SO_RESUME_CMD, + .reg_cldma_so_stop_cmd =3D REG_CLDMA_SO_STOP_CMD, + .reg_cldma_so_dummy_0 =3D REG_CLDMA_SO_DUMMY_0, + .reg_cldma_so_cfg =3D REG_CLDMA_SO_CFG, + .reg_cldma_so_start_addrl_0 =3D REG_CLDMA_SO_START_ADDRL_0, + .reg_cldma_so_start_addrh_0 =3D REG_CLDMA_SO_START_ADDRH_0, + .reg_cldma_so_current_addrl_0 =3D REG_CLDMA_SO_CUR_ADDRL_0, + .reg_cldma_so_current_addrh_0 =3D REG_CLDMA_SO_CUR_ADDRH_0, + .reg_cldma_so_status =3D REG_CLDMA_SO_STATUS, + .reg_cldma_debug_id_en =3D REG_CLDMA_DEBUG_ID_EN, + .reg_cldma_so_last_update_addrl_0 =3D REG_CLDMA_SO_LAST_UPDATE_ADDRL_0, + .reg_cldma_so_last_update_addrh_0 =3D REG_CLDMA_SO_LAST_UPDATE_ADDRH_0, + .reg_cldma_l2tisar0 =3D REG_CLDMA_L2TISAR0, + .reg_cldma_l2tisar1 =3D REG_CLDMA_L2TISAR1, + .reg_cldma_l2timr0 =3D REG_CLDMA_L2TIMR0, + .reg_cldma_l2timr1 =3D REG_CLDMA_L2TIMR1, + .reg_cldma_l2timcr0 =3D REG_CLDMA_L2TIMCR0, + .reg_cldma_l2timcr1 =3D REG_CLDMA_L2TIMCR1, + .reg_cldma_l2timsr0 =3D REG_CLDMA_L2TIMSR0, + .reg_cldma_l2timsr1 =3D REG_CLDMA_L2TIMSR1, + .reg_cldma_l3tisar0 =3D REG_CLDMA_L3TISAR0, + .reg_cldma_l3tisar1 =3D REG_CLDMA_L3TISAR1, + .reg_cldma_l3tisar2 =3D REG_CLDMA_L3TISAR2, + .reg_cldma_l2risar0 =3D REG_CLDMA_L2RISAR0, + .reg_cldma_l2risar1 =3D REG_CLDMA_L2RISAR1, + .reg_cldma_l2rimr0 =3D REG_CLDMA_L2RIMR0, + .reg_cldma_l2rimr1 =3D REG_CLDMA_L2RIMR1, + .reg_cldma_l2rimcr0 =3D REG_CLDMA_L2RIMCR0, + .reg_cldma_l2rimcr1 =3D REG_CLDMA_L2RIMCR1, + .reg_cldma_l2rimsr0 =3D REG_CLDMA_L2RIMSR0, + .reg_cldma_l2rimsr1 =3D REG_CLDMA_L2RIMSR1, + .reg_cldma_l3risar0 =3D REG_CLDMA_L3RISAR0, + .reg_cldma_l3risar1 =3D REG_CLDMA_L3RISAR1, + .reg_cldma_ip_busy =3D REG_CLDMA_IP_BUSY, + .reg_cldma_int_mask =3D REG_CLDMA_INT_EAP_USIP_MASK, + .reg_cldma4_int_mask =3D REG_CLDMA_INT_WF_MASK, + .reg_cldma_ip_busy_to_pcie_mask =3D REG_CLDMA_IP_BUSY_TO_PCIE_MASK, + .reg_cldma_ip_busy_to_pcie_mask_set =3D REG_CLDMA_IP_BUSY_TO_PCIE_MASK_SE= T, + .reg_cldma_ip_busy_to_pcie_mask_clr =3D REG_CLDMA_IP_BUSY_TO_PCIE_MASK_CL= R, + .reg_cldma_ip_busy_to_ap_mask =3D REG_CLDMA_IP_BUSY_TO_AP_MASK, + .reg_cldma_ip_busy_to_ap_mask_set =3D REG_CLDMA_IP_BUSY_TO_AP_MASK_SET, + .reg_cldma_ip_busy_to_ap_mask_clr =3D REG_CLDMA_IP_BUSY_TO_AP_MASK_CLR, + .reg_cldma_ip_busy_to_md_mask_set =3D REG_CLDMA_IP_BUSY_TO_MD_MASK_SET, + .reg_cldma_rx_work_to_reg_mask_set =3D REG_CLDMA_RX_WORK_TO_REG_MASK_SET, + .reg_infra_rst0_set =3D REG_INFRA_RST0_SET, + .reg_infra_rst0_clr =3D REG_INFRA_RST0_CLR, +}; + +static void mtk_cldma_drv_init_m9xx(struct cldma_drv_info *drv_info) +{ + struct cldma_hw_regs *hw_regs; + struct mtk_md_dev *mdev; + int base; + u32 val; + + mdev =3D drv_info->mdev; + base =3D drv_info->base_addr; + hw_regs =3D drv_info->hw_regs; + + /* set CLDMA to 64 bit mode GPD */ + val =3D mtk_pci_read32(mdev, base + hw_regs->reg_cldma_ul_cfg); + + val =3D (val & (~(0x7 << 5))) | ((0x4) << 5); + mtk_pci_write32(mdev, base + hw_regs->reg_cldma_ul_cfg, val); + + val =3D mtk_pci_read32(mdev, base + hw_regs->reg_cldma_so_cfg); + val =3D (val & (~(0x7 << 10))) | ((0x4) << 10) | (1 << 2); + mtk_pci_write32(mdev, base + hw_regs->reg_cldma_so_cfg, val); + + mtk_pci_write32(mdev, base + hw_regs->reg_cldma_rx_work_to_reg_mask_set, = ALLQ); + + mtk_pci_write32(mdev, base + hw_regs->reg_cldma_ip_busy_to_pcie_mask_set, + ALLQ << 16); + mtk_pci_write32(mdev, base + hw_regs->reg_cldma_ip_busy_to_pcie_mask_clr, + ALLQ << 24); + + /* enable interrupt to PCIe */ + if (drv_info->hw_id =3D=3D CLDMA4_HW_ID) + mtk_pci_write32(mdev, base + hw_regs->reg_cldma4_int_mask, 0); + else + mtk_pci_write32(mdev, base + hw_regs->reg_cldma_int_mask, 0); + + /* disable illegal memory check */ + mtk_pci_write32(mdev, base + hw_regs->reg_cldma_ul_dummy_0, 1); + mtk_pci_write32(mdev, base + hw_regs->reg_cldma_so_dummy_0, 1); +} + +static void mtk_cldma_drv_reset_m9xx(struct cldma_drv_info *drv_info) +{ + struct cldma_hw_regs *hw_regs; + struct mtk_md_dev *mdev; + u32 val; + + mdev =3D drv_info->mdev; + hw_regs =3D drv_info->hw_regs; + + val =3D mtk_pci_read32(mdev, REG_DEV_INFRA_BASE + hw_regs->reg_infra_rst0= _set); + + val |=3D 1 << (REG_CLDMA0_RST_SET_BIT + drv_info->hw_id); + mtk_pci_write32(mdev, REG_DEV_INFRA_BASE + hw_regs->reg_infra_rst0_set, v= al); + udelay(1); + val =3D mtk_pci_read32(mdev, REG_DEV_INFRA_BASE + hw_regs->reg_infra_rst0= _clr); + val |=3D 1 << (REG_CLDMA0_RST_CLR_BIT + drv_info->hw_id); + mtk_pci_write32(mdev, REG_DEV_INFRA_BASE + hw_regs->reg_infra_rst0_clr, v= al); +} + +struct cldma_drv_ops cldma_drv_ops_m9xx =3D { + .cldma_drv_init =3D mtk_cldma_drv_init_m9xx, + .cldma_drv_reset =3D mtk_cldma_drv_reset_m9xx, + .cldma_setup_start_addr =3D mtk_cldma_setup_start_addr, + .cldma_mask_intr =3D mtk_cldma_mask_intr, + .cldma_unmask_intr =3D mtk_cldma_unmask_intr, + .cldma_clr_intr_status =3D mtk_cldma_clr_intr_status, + .cldma_check_intr_status =3D mtk_cldma_check_intr_status, + .cldma_start_queue =3D mtk_cldma_start_queue, + .cldma_resume_queue =3D mtk_cldma_resume_queue, + .cldma_queue_status =3D mtk_cldma_queue_status, + .cldma_stop_queue =3D mtk_cldma_stop_queue, + .cldma_clear_ip_busy =3D mtk_cldma_clear_ip_busy, + .cldma_get_intr_status =3D mtk_cldma_get_intr_status, + .cldma_get_tx_start_addr =3D mtk_cldma_get_tx_start_addr, + .cldma_get_rx_curr_addr =3D mtk_cldma_get_rx_curr_addr, +}; diff --git a/drivers/net/wwan/t9xx/pcie/mtk_cldma_drv_m9xx.h b/drivers/net/= wwan/t9xx/pcie/mtk_cldma_drv_m9xx.h new file mode 100644 index 000000000000..2c63c43ff065 --- /dev/null +++ b/drivers/net/wwan/t9xx/pcie/mtk_cldma_drv_m9xx.h @@ -0,0 +1,103 @@ +/* SPDX-License-Identifier: GPL-2.0-only + * + * Copyright (c) 2023, MediaTek Inc. + */ + +#ifndef __MTK_CLDMA_DRV_M9XX_H__ +#define __MTK_CLDMA_DRV_M9XX_H__ + +#define CLDMA0_BASE_ADDR (0x1021C000) +#define CLDMA1_BASE_ADDR (0x1021E000) +#define CLDMA4_BASE_ADDR (0x10224000) + +#define CLDMA_RX_SKB_POOL_MAX_SIZE (64) +#define CLDMA_RX_SKB_RELOAD_THRESHOLD (16) + +/* L2TISAR0 */ +#define TQ_ERR_INT_OFFSET (16) +#define TQ_ERR_INT_BITMASK (0x00FF0000) +#define TQ_ACTIVE_START_ERR_INT_OFFSET (24) +#define TQ_ACTIVE_START_ERR_INT_BITMASK (0xFF000000) + +/* L2RISAR0 */ +#define RQ_ERR_INT_OFFSET (16) +#define RQ_ERR_INT_BITMASK (0x00FF0000) +#define RQ_ACTIVE_START_ERR_INT_OFFSET (24) +#define RQ_ACTIVE_START_ERR_INT_BITMASK (0xFF000000) + +/* CLDMA IN(Tx) */ +#define REG_CLDMA_UL_START_ADDRL_0 (0x0004) +#define REG_CLDMA_UL_START_ADDRH_0 (0x0008) +#define REG_CLDMA_UL_CURRENT_ADDRL_0 (0x0044) +#define REG_CLDMA_UL_CURRENT_ADDRH_0 (0x0048) +#define REG_CLDMA_UL_STATUS (0x0084) +#define REG_CLDMA_UL_START_CMD (0x0088) +#define REG_CLDMA_UL_RESUME_CMD (0x008C) +#define REG_CLDMA_UL_STOP_CMD (0x0090) +#define REG_CLDMA_UL_ERROR (0x0094) +#define REG_CLDMA_UL_CFG (0x0098) +#define REG_CLDMA_UL_DUMMY_0 (0x009C) + +/* CLDMA OUT(Rx) */ +#define REG_CLDMA_SO_ERROR (0x0400 + 0x0100) +#define REG_CLDMA_SO_START_CMD (0x0400 + 0x01BC) +#define REG_CLDMA_SO_RESUME_CMD (0x0400 + 0x01C0) +#define REG_CLDMA_SO_STOP_CMD (0x0400 + 0x01C4) +#define REG_CLDMA_SO_DUMMY_0 (0x0400 + 0x0108) +#define REG_CLDMA_SO_CFG (0x0400 + 0x0004) +#define REG_CLDMA_SO_START_ADDRL_0 (0x0400 + 0x0078) +#define REG_CLDMA_SO_START_ADDRH_0 (0x0400 + 0x007C) +#define REG_CLDMA_SO_CUR_ADDRL_0 (0x0400 + 0x00B8) +#define REG_CLDMA_SO_CUR_ADDRH_0 (0x0400 + 0x00BC) +#define REG_CLDMA_SO_STATUS (0x0400 + 0x00F8) +#define REG_CLDMA_DEBUG_ID_EN (0x0400 + 0x00FC) +#define REG_CLDMA_SO_LAST_UPDATE_ADDRL_0 (0x0400 + 0x01C8) +#define REG_CLDMA_SO_LAST_UPDATE_ADDRH_0 (0x0400 + 0x01CC) + +/* CLDMA MISC */ +#define REG_CLDMA_L2TISAR0 (0x0800 + 0x0010) +#define REG_CLDMA_L2TISAR1 (0x0800 + 0x0014) +#define REG_CLDMA_L2TIMR0 (0x0800 + 0x0018) +#define REG_CLDMA_L2TIMR1 (0x0800 + 0x001C) +#define REG_CLDMA_L2TIMCR0 (0x0800 + 0x0020) +#define REG_CLDMA_L2TIMCR1 (0x0800 + 0x0024) +#define REG_CLDMA_L2TIMSR0 (0x0800 + 0x0028) +#define REG_CLDMA_L2TIMSR1 (0x0800 + 0x002C) +#define REG_CLDMA_L3TISAR0 (0x0800 + 0x0030) +#define REG_CLDMA_L3TISAR1 (0x0800 + 0x0034) +#define REG_CLDMA_L2RISAR0 (0x0800 + 0x0050) +#define REG_CLDMA_L2RISAR1 (0x0800 + 0x0054) +#define REG_CLDMA_L3RISAR0 (0x0800 + 0x0070) +#define REG_CLDMA_L3RISAR1 (0x0800 + 0x0074) +#define REG_CLDMA_IP_BUSY (0x0800 + 0x00B4) +#define REG_CLDMA_L3TISAR2 (0x0800 + 0x00C0) + +#define REG_CLDMA_L2RIMR0 (0x0800 + 0x00E8) +#define REG_CLDMA_L2RIMR1 (0x0800 + 0x00EC) +#define REG_CLDMA_L2RIMCR0 (0x0800 + 0x00F0) +#define REG_CLDMA_L2RIMCR1 (0x0800 + 0x00F4) +#define REG_CLDMA_L2RIMSR0 (0x0800 + 0x00F8) +#define REG_CLDMA_L2RIMSR1 (0x0800 + 0x00FC) + +#define REG_CLDMA_INT_EAP_USIP_MASK (0x0800 + 0x011C) +#define REG_CLDMA_INT_WF_MASK (0x0800 + 0x0120) +#define REG_CLDMA_RQ1_GPD_DONE_CNT (0x0800 + 0x0174) +#define REG_CLDMA_TQ1_GPD_DONE_CNT (0x0800 + 0x0184) + +#define REG_CLDMA_IP_BUSY_TO_PCIE_MASK (0x0800 + 0x0194) +#define REG_CLDMA_IP_BUSY_TO_PCIE_MASK_SET (0x0800 + 0x0198) +#define REG_CLDMA_IP_BUSY_TO_PCIE_MASK_CLR (0x0800 + 0x019C) + +#define REG_CLDMA_IP_BUSY_TO_AP_MASK (0x0800 + 0x0200) +#define REG_CLDMA_IP_BUSY_TO_AP_MASK_SET (0x0800 + 0x0204) +#define REG_CLDMA_IP_BUSY_TO_AP_MASK_CLR (0x0800 + 0x0208) +#define REG_CLDMA_IP_BUSY_TO_MD_MASK_SET (0x0800 + 0x0210) +#define REG_CLDMA_RX_WORK_TO_REG_MASK_SET (0x0800 + 0x021C) + +/* CLDMA RESET */ +#define REG_INFRA_RST0_SET (0x120) +#define REG_INFRA_RST0_CLR (0x124) +#define REG_CLDMA0_RST_SET_BIT (8) +#define REG_CLDMA0_RST_CLR_BIT (8) + +#endif diff --git a/drivers/net/wwan/t9xx/pcie/mtk_ctrl_cfg_m9xx.c b/drivers/net/w= wan/t9xx/pcie/mtk_ctrl_cfg_m9xx.c new file mode 100644 index 000000000000..c1bb787ee981 --- /dev/null +++ b/drivers/net/wwan/t9xx/pcie/mtk_ctrl_cfg_m9xx.c @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022, MediaTek Inc. + */ + +#include "mtk_cldma.h" +#include "mtk_trans_ctrl.h" + +#define TRB_SRV_NUM (1) + +static const int mtk_srv_cfg_m9xx[NR_CLDMA][HW_QUE_NUM] =3D { + {0}, + {0}, +}; + +static const struct queue_info mtk_queue_info_m9xx[] =3D { +}; + +struct mtk_ctrl_info mtk_ctrl_info_m9xx =3D { + .queue_info =3D (struct queue_info *)mtk_queue_info_m9xx, + .queue_info_num =3D ARRAY_SIZE(mtk_queue_info_m9xx), + .srv_cfg =3D (int **)mtk_srv_cfg_m9xx, + .trb_srv_num =3D TRB_SRV_NUM, +}; diff --git a/drivers/net/wwan/t9xx/pcie/mtk_pci.c b/drivers/net/wwan/t9xx/p= cie/mtk_pci.c index 9f71685ea96c..9bcfc6e26f5f 100644 --- a/drivers/net/wwan/t9xx/pcie/mtk_pci.c +++ b/drivers/net/wwan/t9xx/pcie/mtk_pci.c @@ -898,6 +898,28 @@ static void mtk_pci_free_irq(struct mtk_md_dev *mdev) pci_free_irq_vectors(pdev); } =20 +static int mtk_pci_dev_init(struct mtk_md_dev *mdev) +{ + int ret; + + ret =3D mtk_trans_ctrl_init(mdev); + if (ret) { + dev_err(mdev->dev, "Failed to initialize control plane: %d\n", ret); + return ret; + } + + return 0; +} + +static void mtk_pci_dev_exit(struct mtk_md_dev *mdev) +{ + mtk_trans_ctrl_exit(mdev); +} + +static int mtk_pci_dev_start(struct mtk_md_dev *mdev) +{ + return 0; +} static const struct mtk_dev_ops pci_hw_ops =3D { .get_dev_state =3D mtk_pci_get_dev_state, .ack_dev_state =3D mtk_pci_ack_dev_state, @@ -972,6 +994,12 @@ static int mtk_pci_probe(struct pci_dev *pdev, const s= truct pci_device_id *id) if (ret) goto free_mhccif; =20 + ret =3D mtk_pci_dev_init(mdev); + if (ret) { + dev_err((mdev)->dev, "Failed to init dev.\n"); + goto free_irq; + } + pci_set_master(pdev); mtk_pci_unmask_irq(mdev, priv->mhccif_irq_id); =20 @@ -988,10 +1016,20 @@ static int mtk_pci_probe(struct pci_dev *pdev, const= struct pci_device_id *id) goto clear_master; } =20 + ret =3D mtk_pci_dev_start(mdev); + if (ret) { + dev_err((mdev)->dev, "Failed to start dev.\n"); + goto free_saved_state; + } + return 0; =20 +free_saved_state: + pci_load_and_free_saved_state(pdev, &priv->saved_state); clear_master: pci_clear_master(pdev); + mtk_pci_dev_exit(mdev); +free_irq: mtk_pci_free_irq(mdev); free_mhccif: mtk_mhccif_exit(mdev); diff --git a/drivers/net/wwan/t9xx/pcie/mtk_pci_reg.h b/drivers/net/wwan/t9= xx/pcie/mtk_pci_reg.h index 3f0667e8a846..73299ae03f89 100644 --- a/drivers/net/wwan/t9xx/pcie/mtk_pci_reg.h +++ b/drivers/net/wwan/t9xx/pcie/mtk_pci_reg.h @@ -21,6 +21,7 @@ #define REG_IMASK_HOST_MSIX_SET_GRP0_0 0x3000 #define REG_IMASK_HOST_MSIX_CLR_GRP0_0 0x3080 #define REG_IMASK_HOST_MSIX_GRP0_0 0x3100 +#define REG_DEV_INFRA_BASE 0x10001000 =20 /* mhccif registers */ #define MHCCIF_RC2EP_SW_BSY 0x4 diff --git a/drivers/net/wwan/t9xx/pcie/mtk_trans_ctrl.c b/drivers/net/wwan= /t9xx/pcie/mtk_trans_ctrl.c new file mode 100644 index 000000000000..0588200ace76 --- /dev/null +++ b/drivers/net/wwan/t9xx/pcie/mtk_trans_ctrl.c @@ -0,0 +1,583 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022, MediaTek Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "mtk_cldma.h" +#include "mtk_ctrl_plane.h" +#include "mtk_dev.h" +#include "mtk_pci.h" +#include "mtk_trans_ctrl.h" + +#define MTK_DFLT_PORT_NAME_LEN (20) +extern struct mtk_ctrl_info ctrl_info_name(m9xx); + +static struct mtk_ctrl_info_desc mtk_ctrl_info_tbl[] =3D { + {2304, &ctrl_info_name(m9xx)}, + {0, NULL}, +}; + +#define RX_CH_ID_SHIFT 16 +#define PORT_MTU_MASK 0xFFFF +#define QUEUE_CHL_MASK 0xFFFF + +static bool mtk_queue_list_is_full(struct mtk_ctrl_trans *trans, struct qu= eue_info *que) +{ + return trans->trans_list[que->hif_id].skb_list[que->txqno].qlen >=3D SKB_= LIST_MAX_LEN; +} + +static bool mtk_ctrl_chs_is_busy_or_empty(struct trb_srv *srv) +{ + struct srv_que *srv_que; + int i; + + for (i =3D 0; i < NR_CLDMA; i++) + list_for_each_entry(srv_que, &srv->srv_q_list[i], list) + if (!skb_queue_empty(&srv->trans->trans_list[i].skb_list[srv_que->qno])= && + mtk_cldma_get_tx_budget(srv->trans->dev, i, srv_que->qno)) + return false; + + return true; +} + +static void mtk_ctrl_ch_flush(struct sk_buff_head *skb_list) +{ + struct sk_buff *skb; + struct trb *trb; + + while (!skb_queue_empty(skb_list)) { + skb =3D skb_dequeue(skb_list); + trb =3D (struct trb *)skb->cb; + trb->status =3D -EIO; + trb->trb_complete(skb); + } +} + +static void mtk_ctrl_chs_flush(struct trb_srv *srv) +{ + struct srv_que *srv_que; + int i; + + for (i =3D 0; i < NR_CLDMA; i++) + list_for_each_entry(srv_que, &srv->srv_q_list[i], list) + mtk_ctrl_ch_flush(&srv->trans->trans_list[i].skb_list[srv_que->qno]); +} + +static int mtk_ch_status_check(struct mtk_ctrl_trans *trans, struct sk_buf= f *skb) +{ + struct trb *trb =3D (struct trb *)skb->cb; + struct trb_open_priv *trb_open_priv; + struct queue_info *que; + int ret =3D 0; + + que =3D radix_tree_lookup(&trans->queue_tbl, trb->channel_id & QUEUE_CHL_= MASK); + + switch (trb->cmd) { + case TRB_CMD_ENABLE: + trb_open_priv =3D (struct trb_open_priv *)skb->data; + trb_open_priv->log_rg_offset =3D que->log_rg_offset; + trans->usr_cnt[que->hif_id][que->txqno]++; + if (trans->usr_cnt[que->hif_id][que->txqno] =3D=3D 1) + break; + trb_open_priv->tx_mtu =3D que->tx_mtu; + trb_open_priv->rx_mtu =3D que->rx_mtu; + trb_open_priv->tx_frag_size =3D que->tx_frag_size; + trb_open_priv->rx_frag_size =3D que->rx_frag_size; + if (mtk_cldma_check_ch_cfg(trans->dev, que)) { + trb->status =3D -EINVAL; + ret =3D -EINVAL; + } else { + trb->status =3D -EBUSY; + ret =3D -EBUSY; + } + trb->trb_complete(skb); + break; + case TRB_CMD_DISABLE: + if (trans->usr_cnt[que->hif_id][que->txqno] > 0) { + trans->usr_cnt[que->hif_id][que->txqno]--; + if (!trans->usr_cnt[que->hif_id][que->txqno]) + break; + } + trb->status =3D -EBUSY; + trb->trb_complete(skb); + ret =3D -EBUSY; + break; + default: + dev_err((trans->mdev)->dev, "Invalid trb command(%d)\n", trb->cmd); + ret =3D -EINVAL; + break; + } + return ret; +} + +static void mtk_ctrl_trb_handler(struct trb_srv *srv, struct trans_list *t= rans_list, u32 qno) +{ + struct sk_buff_head *skb_list =3D &trans_list->skb_list[qno]; + struct mtk_ctrl_trans *trans =3D srv->trans; + struct sk_buff *skb, *skb_next; + struct trb *trb, *trb_next; + bool kick =3D false; + int loop =3D 0; + int err; + + do { + skb =3D skb_peek(skb_list); + if (!skb) + break; + trb =3D (struct trb *)skb->cb; + + switch (trb->cmd) { + case TRB_CMD_ENABLE: + case TRB_CMD_DISABLE: + skb_unlink(skb, skb_list); + err =3D mtk_ch_status_check(trans, skb); + if (!err) { + kick =3D true; + if (trb->cmd =3D=3D TRB_CMD_DISABLE) + mtk_ctrl_ch_flush(skb_list); + } + break; + case TRB_CMD_TX: + err =3D mtk_cldma_submit_tx(trans->dev, skb); + if (err) { + if (trans_list->tx_burst_cnt[qno]) { + kick =3D true; + break; + } + if (err =3D=3D -EAGAIN) + return; + + skb_unlink(skb, skb_list); + trb->status =3D err; + trb->trb_complete(skb); + break; + } + + trans_list->tx_burst_cnt[qno]++; + if (trans_list->tx_burst_cnt[qno] >=3D TX_BURST_MAX_CNT || + skb_queue_is_last(skb_list, skb)) { + kick =3D true; + } else { + skb_next =3D skb_peek_next(skb, skb_list); + trb_next =3D (struct trb *)skb_next->cb; + if (trb_next->cmd !=3D TRB_CMD_TX) + kick =3D true; + } + + skb_unlink(skb, skb_list); + break; + default: + skb_unlink(skb, skb_list); + } + + if (kick) { + mtk_cldma_trb_process(trans->dev, skb); + trans_list->tx_burst_cnt[qno] =3D 0; + kick =3D false; + } + + loop++; + } while (loop < TRB_NUM_PER_ROUND); +} + +static void mtk_ctrl_trb_process(struct trb_srv *srv) +{ + struct mtk_ctrl_trans *trans =3D srv->trans; + struct srv_que *srv_que; + int i; + + for (i =3D 0; i < NR_CLDMA; i++) + list_for_each_entry(srv_que, &srv->srv_q_list[i], list) + mtk_ctrl_trb_handler(srv, &trans->trans_list[i], srv_que->qno); +} + +static int mtk_ctrl_trb_thread(void *args) +{ + struct trb_srv *srv =3D args; + + for (;;) { + wait_event_interruptible(srv->trb_waitq, + !mtk_ctrl_chs_is_busy_or_empty(srv) || + kthread_should_stop() || kthread_should_park()); + if (kthread_should_stop()) + break; + + if (kthread_should_park()) + kthread_parkme(); + + do { + mtk_ctrl_trb_process(srv); + cond_resched(); + } while (!mtk_ctrl_chs_is_busy_or_empty(srv) && !kthread_should_stop() && + !kthread_should_park()); + } + mtk_ctrl_chs_flush(srv); + return 0; +} + +static int mtk_ctrl_trb_srv_init(struct mtk_ctrl_trans *trans) +{ + struct srv_que *srv_que; + struct trb_srv *srv; + int i, j; + int ret; + + for (i =3D 0; i < trans->trb_srv_num; i++) { + srv =3D devm_kzalloc(trans->mdev->dev, sizeof(*srv), GFP_KERNEL); + if (!srv) { + ret =3D -ENOMEM; + goto err_free_srv; + } + + srv->trans =3D trans; + srv->srv_id =3D i; + trans->trb_srv[i] =3D srv; + + init_waitqueue_head(&srv->trb_waitq); + for (j =3D 0; j < NR_CLDMA; j++) + INIT_LIST_HEAD(&srv->srv_q_list[j]); + } + + for (i =3D 0; i < NR_CLDMA; i++) + for (j =3D 0; j < HW_QUE_NUM; j++) { + if (trans->srv_cfg[i][j] < 0 || + trans->srv_cfg[i][j] >=3D trans->trb_srv_num) + trans->srv_cfg[i][j] =3D 0; + srv_que =3D devm_kzalloc(trans->mdev->dev, sizeof(*srv_que), GFP_KERNEL= ); + if (!srv_que) { + ret =3D -ENOMEM; + goto err_free_srv_que; + } + srv_que->hif_id =3D i; + srv_que->qno =3D j; + list_add_tail(&srv_que->list, + &trans->trb_srv[trans->srv_cfg[i][j]]->srv_q_list[i]); + } + + for (i =3D 0; i < trans->trb_srv_num; i++) { + trans->trb_srv[i]->trb_thread =3D kthread_run(mtk_ctrl_trb_thread, trans= ->trb_srv[i], + "mtk_trb_srv%d_%s", i, + trans->mdev->dev_str); + if (IS_ERR(trans->trb_srv[i]->trb_thread)) { + ret =3D PTR_ERR(trans->trb_srv[i]->trb_thread); + trans->trb_srv[i]->trb_thread =3D NULL; + goto err_stop_kthread; + } + } + + return 0; +err_stop_kthread: + while (--i >=3D 0) + kthread_stop(trans->trb_srv[i]->trb_thread); +err_free_srv_que: + for (i =3D 0; i < trans->trb_srv_num; i++) { + for (j =3D 0; j < NR_CLDMA; j++) { + struct srv_que *next_srv_que; + + list_for_each_entry_safe(srv_que, next_srv_que, + &trans->trb_srv[i]->srv_q_list[j], list) { + list_del(&srv_que->list); + devm_kfree(trans->mdev->dev, srv_que); + } + } + } +err_free_srv: + for (i =3D 0; i < trans->trb_srv_num; i++) { + if (!trans->trb_srv[i]) + break; + devm_kfree(trans->mdev->dev, trans->trb_srv[i]); + trans->trb_srv[i] =3D NULL; + } + + return ret; +} + +static void mtk_ctrl_trb_srv_exit(struct mtk_ctrl_trans *trans) +{ + struct srv_que *srv_que, *next_srv_que; + struct trb_srv *srv; + int i, j; + + for (i =3D 0; i < trans->trb_srv_num; i++) { + srv =3D trans->trb_srv[i]; + kthread_stop(srv->trb_thread); + for (j =3D 0; j < NR_CLDMA; j++) { + list_for_each_entry_safe(srv_que, next_srv_que, + &trans->trb_srv[i]->srv_q_list[j], list) { + list_del(&srv_que->list); + devm_kfree(trans->mdev->dev, srv_que); + } + } + devm_kfree(trans->mdev->dev, srv); + trans->trb_srv[i] =3D NULL; + } +} + +static void mtk_ctrl_remove_radix_tree(struct mtk_ctrl_trans *trans) +{ + struct queue_info **queues; + int ret, idx; + + queues =3D kcalloc(trans->queues_cnt, sizeof(struct queue_info *), GFP_KE= RNEL); + if (!queues) + return; + + ret =3D radix_tree_gang_lookup(&trans->queue_tbl, (void **)queues, + 0, trans->queues_cnt); + for (idx =3D 0; idx < ret; idx++) { + radix_tree_delete(&trans->queue_tbl, queues[idx]->rx_chl & QUEUE_CHL_MAS= K); + kfree(queues[idx]); + } + kfree(queues); +} + +static void mtk_ctrl_queue_info_update(struct radix_tree_root *queue_tbl, = u32 port_chl_mtu) +{ + struct queue_info *queue; + u32 rx_chl, mtu; + + if (!port_chl_mtu) + return; + + rx_chl =3D port_chl_mtu >> RX_CH_ID_SHIFT; + mtu =3D port_chl_mtu & PORT_MTU_MASK; + queue =3D radix_tree_lookup(queue_tbl, rx_chl); + if (!queue) + return; + + queue->tx_mtu =3D mtu; + queue->rx_mtu =3D mtu; + queue->tx_frag_size =3D mtu; + queue->rx_frag_size =3D mtu; +} + +static unsigned int ctrl_port_chl_mtu; + +static int mtk_pcie_hif_init(struct mtk_md_dev *mdev) +{ + struct mtk_ctrl_blk *ctrl_blk =3D mdev->ctrl_blk; + struct queue_info *queue, *queue_info; + struct mtk_ctrl_trans *trans; + int i, j; + int ret; + + trans =3D ctrl_blk->ctrl_hw_priv; + trans->ctrl_blk =3D ctrl_blk; + queue_info =3D trans->queue_info; + + INIT_RADIX_TREE(&trans->queue_tbl, GFP_KERNEL); + for (i =3D 0; i < trans->queue_info_num; i++) { + queue =3D kmemdup(queue_info + i, sizeof(*queue), GFP_KERNEL); + if (!queue) { + ret =3D -ENOMEM; + goto err_free_radix_tree; + } + if (queue->txqno >=3D HW_QUE_NUM || queue->rxqno >=3D HW_QUE_NUM || + queue->hif_id >=3D NR_CLDMA) { + dev_err((mdev)->dev, "Failed to get correct queue info %x\n", + queue->rx_chl); + kfree(queue); + ret =3D -EINVAL; + goto err_free_radix_tree; + } + ret =3D radix_tree_insert(&trans->queue_tbl, queue->rx_chl & QUEUE_CHL_M= ASK, queue); + if (ret) { + dev_err((mdev)->dev, "Insert %x fail, ret: %d", queue->rx_chl, ret); + kfree(queue); + goto err_free_radix_tree; + } + trans->queues_cnt++; + } + + mtk_ctrl_queue_info_update(&trans->queue_tbl, ctrl_port_chl_mtu); + + for (i =3D 0; i < NR_CLDMA; i++) { + for (j =3D 0; j < HW_QUE_NUM; j++) { + skb_queue_head_init(&trans->trans_list[i].skb_list[j]); + trans->trans_list[i].tx_burst_cnt[j] =3D 0; + } + } + ret =3D mtk_cldma_init(trans); + if (ret) + goto err_free_radix_tree; + + ret =3D mtk_ctrl_trb_srv_init(trans); + if (ret) + goto err_cldma_exit; + + atomic_set(&trans->available, 1); + + return 0; + +err_cldma_exit: + mtk_cldma_exit(trans); +err_free_radix_tree: + mtk_ctrl_remove_radix_tree(trans); + + return ret; +} + +static int mtk_pcie_hif_exit(struct mtk_md_dev *mdev) +{ + struct mtk_ctrl_blk *ctrl_blk =3D mdev->ctrl_blk; + struct mtk_ctrl_trans *trans; + + trans =3D ctrl_blk->ctrl_hw_priv; + + atomic_set(&trans->available, 0); + mtk_ctrl_trb_srv_exit(trans); + mtk_ctrl_remove_radix_tree(trans); + mtk_cldma_exit(trans); + + return 0; +} + +static int mtk_pcie_hif_submit_skb(struct mtk_md_dev *mdev, struct sk_buff= *skb, bool force_send) +{ + struct mtk_ctrl_blk *ctrl_blk =3D mdev->ctrl_blk; + struct mtk_ctrl_trans *trans; + struct queue_info *que; + struct trb *trb; + + trans =3D ctrl_blk->ctrl_hw_priv; + trb =3D (struct trb *)skb->cb; + + if (trb->cmd =3D=3D TRB_CMD_STOP || trb->cmd =3D=3D TRB_CMD_RECOVER) { + trb->trb_complete(skb); + return 0; + } + + que =3D radix_tree_lookup(&trans->queue_tbl, trb->channel_id & QUEUE_CHL_= MASK); + if (!que) { + dev_warn((mdev)->dev, "lookup que fail, ch_id: %x, que: 0x%p\n", + trb->channel_id, que); + return -EINVAL; + } + + if (!atomic_read(&trans->available)) + return -EIO; + + if (mtk_queue_list_is_full(trans, que) && !force_send) + return -EAGAIN; + + if (trb->cmd =3D=3D TRB_CMD_DISABLE) + skb_queue_head(&trans->trans_list[que->hif_id].skb_list[que->txqno], skb= ); + else + skb_queue_tail(&trans->trans_list[que->hif_id].skb_list[que->txqno], skb= ); + + wake_up(&trans->trb_srv[trans->srv_cfg[que->hif_id][que->txqno]]->trb_wai= tq); + + return 0; +} + +static int mtk_pcie_hif_cmd_func(struct mtk_md_dev *mdev, int cmd, void *d= ata) +{ + struct mtk_ctrl_blk *ctrl_blk =3D mdev->ctrl_blk; + struct mtk_ctrl_trans *trans; + struct queue_info *que; + + switch (cmd) { + case HIF_CTRL_CMD_CHECK_TX_FULL: + trans =3D ctrl_blk->ctrl_hw_priv; + que =3D radix_tree_lookup(&trans->queue_tbl, + ((union ctrl_hif_cmd_data *)data)->rx_ch & QUEUE_CHL_MASK); + if (!que) { + dev_warn((mdev)->dev, "Failed to find que to check tx full\n"); + return -EINVAL; + } + return mtk_queue_list_is_full(trans, que); + default: + return -EINVAL; + } + + return 0; +} + +static struct mtk_ctrl_hif_ops pcie_ctrl_ops =3D { + .init =3D mtk_pcie_hif_init, + .exit =3D mtk_pcie_hif_exit, + .submit_skb =3D mtk_pcie_hif_submit_skb, + .send_cmd =3D mtk_pcie_hif_cmd_func, +}; + +static void mtk_trans_get_ctrl_info(struct mtk_ctrl_cfg *cfg, + struct mtk_ctrl_trans *trans, u32 hw_ver) +{ + struct mtk_ctrl_info_desc *ctrl_info_desc; + struct mtk_ctrl_info *ctrl_info; + u8 i; + + for (i =3D 0; (ctrl_info_desc =3D &mtk_ctrl_info_tbl[i]) && ctrl_info_des= c && + ctrl_info_desc->ctrl_info; i++) { + if (ctrl_info_desc->hw_ver !=3D hw_ver) + continue; + + ctrl_info =3D ctrl_info_desc->ctrl_info; + memcpy(trans->srv_cfg, ctrl_info->srv_cfg, + sizeof(int) * NR_CLDMA * HW_QUE_NUM); + trans->queue_info =3D ctrl_info->queue_info; + trans->queue_info_num =3D ctrl_info->queue_info_num; + trans->trb_srv_num =3D ctrl_info->trb_srv_num; + } +} + +int mtk_trans_ctrl_init(struct mtk_md_dev *mdev) +{ + struct mtk_ctrl_trans *trans; + struct mtk_ctrl_blk *ctrl_blk; + int err; + + trans =3D devm_kzalloc(mdev->dev, sizeof(*trans), GFP_KERNEL); + if (!trans) + return -ENOMEM; + trans->mdev =3D mdev; + trans->queues_cnt =3D 0; + + mtk_trans_get_ctrl_info(NULL, trans, mdev->hw_ver); + if (!trans->queue_info || + trans->trb_srv_num <=3D 0 || trans->trb_srv_num > TRB_SRV_MAX_NUM || + trans->queue_info_num <=3D 0) { + dev_err((mdev)->dev, "Failed to get ctrl info!\n"); + goto err_free_cfg; + } + + err =3D mtk_ctrl_init(mdev, &pcie_ctrl_ops); + if (err) + goto err_free_cfg; + + ctrl_blk =3D mdev->ctrl_blk; + ctrl_blk->ctrl_hw_priv =3D trans; + + return 0; + +err_free_cfg: + devm_kfree(mdev->dev, trans); + return -ENOMEM; +} + +int mtk_trans_ctrl_exit(struct mtk_md_dev *mdev) +{ + struct mtk_ctrl_trans *trans; + struct mtk_ctrl_blk *ctrl_blk; + + ctrl_blk =3D mdev->ctrl_blk; + trans =3D ctrl_blk->ctrl_hw_priv; + + devm_kfree(mdev->dev, ctrl_blk->cfg); + mtk_ctrl_exit(mdev); + devm_kfree(mdev->dev, trans); + + return 0; +} + +module_param(ctrl_port_chl_mtu, uint, 0644); +MODULE_PARM_DESC(ctrl_port_chl_mtu, "This is used to config the ctrl port = mtu!\n"); diff --git a/drivers/net/wwan/t9xx/pcie/mtk_trans_ctrl.h b/drivers/net/wwan= /t9xx/pcie/mtk_trans_ctrl.h index d6de4c43b529..c2df0bf6ed65 100644 --- a/drivers/net/wwan/t9xx/pcie/mtk_trans_ctrl.h +++ b/drivers/net/wwan/t9xx/pcie/mtk_trans_ctrl.h @@ -13,9 +13,93 @@ =20 #include "mtk_dev.h" =20 +#define TRB_SRV_MAX_NUM (1) +#define HW_QUE_NUM (8) +#define TX_GPD_NUM (16) +#define RX_GPD_NUM (TX_GPD_NUM) +#define MIN_GPD_NUM (2) +#define SKB_LIST_MAX_LEN (16) +#define MTU_RSV_ROOM (0x100) +#define TRB_NUM_PER_ROUND (TX_GPD_NUM) +#define TX_BURST_MAX_CNT (TX_GPD_NUM / 4 + 1) + +#define HIF_ID(peer_id) ((peer_id) - 1) + +enum mtk_hif_id { + CLDMA0, + CLDMA1, + CLDMA4, + NR_CLDMA +}; + +struct queue_info { + u32 tx_chl; + u32 rx_chl; + enum mtk_hif_id hif_id; + u32 txqno; + u32 rxqno; + u32 tx_mtu; + u32 rx_mtu; + u32 tx_nr_gpds; + u32 rx_nr_gpds; + u32 tx_frag_size; + u32 rx_frag_size; + u8 log_rg_offset; +}; + +struct trans_list { + struct sk_buff_head skb_list[HW_QUE_NUM]; + u8 tx_burst_cnt[HW_QUE_NUM]; +}; + struct mtk_ctrl_trans { struct mtk_ctrl_blk *ctrl_blk; + struct trb_srv *trb_srv[TRB_SRV_MAX_NUM]; + struct trans_list trans_list[NR_CLDMA]; + void *dev; + struct radix_tree_root queue_tbl; struct mtk_md_dev *mdev; + int usr_cnt[NR_CLDMA][HW_QUE_NUM]; + u32 tx_mtu_cfg[NR_CLDMA][HW_QUE_NUM]; + u32 rx_mtu_cfg[NR_CLDMA][HW_QUE_NUM]; + atomic_t available; + int queues_cnt; + int srv_cfg[NR_CLDMA][HW_QUE_NUM]; + struct queue_info *queue_info; + int queue_info_num; + int trb_srv_num; +}; + +struct srv_que { + u32 hif_id; + u32 qno; + struct list_head list; +}; + +struct trb_srv { + u32 srv_id; + struct list_head srv_q_list[NR_CLDMA]; + struct mtk_ctrl_trans *trans; + wait_queue_head_t trb_waitq; + struct task_struct *trb_thread; +}; + +struct mtk_ctrl_info { + struct mtk_ctrl_cfg *ctrl_cfg; + int **srv_cfg; + struct queue_info *queue_info; + u32 queue_info_num; + u32 trb_srv_num; }; =20 +struct mtk_ctrl_info_desc { + u32 hw_ver; + struct mtk_ctrl_info *ctrl_info; +}; + +#define ctrl_info_name(NAME) mtk_ctrl_info_##NAME + +int mtk_trans_ctrl_init(struct mtk_md_dev *mdev); +int mtk_trans_ctrl_exit(struct mtk_md_dev *mdev); + #endif --=20 2.34.1 From nobody Wed Jun 10 17:22:13 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B7E763F823B; Wed, 10 Jun 2026 10:41:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781088101; cv=none; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260610-t9xx_driver_v1-v2-4-c65addf23b3f@compal.com> References: <20260610-t9xx_driver_v1-v2-0-c65addf23b3f@compal.com> In-Reply-To: <20260610-t9xx_driver_v1-v2-0-c65addf23b3f@compal.com> To: Loic Poulain , Sergey Ryazanov , Johannes Berg , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Jack Wu , Wen-Zhi Huang , Shi-Wei Yeh , Minano Tseng , Matthias Brugger , AngeloGioacchino Del Regno , Simon Horman , Jonathan Corbet , Shuah Khan Cc: linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-doc@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1781088082; l=47020; i=jackbb_wu@compal.com; s=20260526; h=from:subject:message-id; bh=22WOIng3xvCVlbOwdL3pEfL09ZcW946bAp8L1GMEpHE=; b=362t1jSCukHPJts0msYBElYESYyoUiK3/xHRCBAtn/ijdPA/UN/3JWA65GpJEQFI6WvjI6QfL SkOHfCD1brQBs9LdCCU6IpS8tAIcYBoLZUj7njJ2IMuW1VdQZyEy0QT X-Developer-Key: i=jackbb_wu@compal.com; a=ed25519; pk=VH1prTWixNl8OEUPPSfII3p46MzJpQN8J3+ecE1tZXg= X-Endpoint-Received: by B4 Relay for jackbb_wu@compal.com/20260526 with auth_id=793 X-Original-From: Jack Wu Reply-To: jackbb_wu@compal.com From: Jack Wu The control port consists of port I/O and port manager. Port I/O provides a common operation as defined by "struct port_ops", and the operation is managed by the "port manager". It provides interfaces to internal users, the implemented internal interfaces are open, close, write and recv_register. The port manager defines and implements port management interfaces and structures. It is responsible for port creation, destroying, and managing port states. It sends data from port I/O to CLDMA via TRB ( Transaction Request Block ), and dispatches received data from CLDMA to port I/O. The using port will be held in the "stale list" when the driver destroys it, and after creating it again, the user can continue to use it. Signed-off-by: Jack Wu --- drivers/net/wwan/t9xx/Makefile | 4 +- drivers/net/wwan/t9xx/mtk_ctrl_plane.c | 19 +- drivers/net/wwan/t9xx/mtk_ctrl_plane.h | 20 +- drivers/net/wwan/t9xx/mtk_dev.c | 13 +- drivers/net/wwan/t9xx/mtk_port.c | 877 +++++++++++++++++++++= ++++ drivers/net/wwan/t9xx/mtk_port.h | 159 +++++ drivers/net/wwan/t9xx/mtk_port_io.c | 238 +++++++ drivers/net/wwan/t9xx/mtk_port_io.h | 36 + drivers/net/wwan/t9xx/pcie/mtk_ctrl_cfg_m9xx.c | 25 +- drivers/net/wwan/t9xx/pcie/mtk_pci.c | 2 + drivers/net/wwan/t9xx/pcie/mtk_trans_ctrl.c | 28 +- drivers/net/wwan/t9xx/pcie/mtk_trans_ctrl.h | 1 + 12 files changed, 1406 insertions(+), 16 deletions(-) diff --git a/drivers/net/wwan/t9xx/Makefile b/drivers/net/wwan/t9xx/Makefile index ae9d6f2344ab..db3b1aa1928b 100644 --- a/drivers/net/wwan/t9xx/Makefile +++ b/drivers/net/wwan/t9xx/Makefile @@ -8,4 +8,6 @@ obj-$(CONFIG_MTK_T9XX_PCI) +=3D pcie/ =20 mtk_t9xx-y :=3D \ mtk_dev.o \ - mtk_ctrl_plane.o + mtk_ctrl_plane.o \ + mtk_port.o \ + mtk_port_io.o diff --git a/drivers/net/wwan/t9xx/mtk_ctrl_plane.c b/drivers/net/wwan/t9xx= /mtk_ctrl_plane.c index 70348696ac44..b9a0443ce8ec 100644 --- a/drivers/net/wwan/t9xx/mtk_ctrl_plane.c +++ b/drivers/net/wwan/t9xx/mtk_ctrl_plane.c @@ -7,20 +7,23 @@ #include =20 #include "mtk_ctrl_plane.h" +#include "mtk_port.h" =20 /** * mtk_ctrl_init() - Initialize the control plane block. * @mdev: Pointer to the MTK modem device. * @ops: HIF operations for the control plane. + * @cfg: Control plane configuration. * * Allocates and initializes the control plane block * associated with @mdev. * - * Return: 0 on success, -ENOMEM on allocation failure. + * Return: 0 on success, negative error code on failure. */ -int mtk_ctrl_init(struct mtk_md_dev *mdev, struct mtk_ctrl_hif_ops *ops) +int mtk_ctrl_init(struct mtk_md_dev *mdev, struct mtk_ctrl_hif_ops *ops, s= truct mtk_ctrl_cfg *cfg) { struct mtk_ctrl_blk *ctrl_blk; + int err; =20 ctrl_blk =3D devm_kzalloc(mdev->dev, sizeof(*ctrl_blk), GFP_KERNEL); if (!ctrl_blk) @@ -29,8 +32,19 @@ int mtk_ctrl_init(struct mtk_md_dev *mdev, struct mtk_ct= rl_hif_ops *ops) ctrl_blk->mdev =3D mdev; mdev->ctrl_blk =3D ctrl_blk; ctrl_blk->ops =3D ops; + ctrl_blk->cfg =3D cfg; + + err =3D mtk_port_mngr_init(ctrl_blk, cfg->port_layer_cfg->port_cfg, + cfg->port_layer_cfg->port_cnt); + if (err) + goto err_free_mem; =20 return 0; + +err_free_mem: + devm_kfree(mdev->dev, ctrl_blk); + + return err; } EXPORT_SYMBOL(mtk_ctrl_init); =20 @@ -44,6 +58,7 @@ void mtk_ctrl_exit(struct mtk_md_dev *mdev) { struct mtk_ctrl_blk *ctrl_blk =3D mdev->ctrl_blk; =20 + mtk_port_mngr_exit(ctrl_blk); devm_kfree(mdev->dev, ctrl_blk); mdev->ctrl_blk =3D NULL; } diff --git a/drivers/net/wwan/t9xx/mtk_ctrl_plane.h b/drivers/net/wwan/t9xx= /mtk_ctrl_plane.h index 88d71ac92084..d7fcccde8a1b 100644 --- a/drivers/net/wwan/t9xx/mtk_ctrl_plane.h +++ b/drivers/net/wwan/t9xx/mtk_ctrl_plane.h @@ -11,6 +11,17 @@ =20 #include "mtk_dev.h" =20 +#define Q_MTU_2K (0x800) +#define Q_MTU_3_5K (0xE00) +#define Q_MTU_7K (0x1C00) +#define Q_MTU_32K (0x8000) +#define Q_MTU_63K (0xFC00) +#define Q_FRAG_2K (0x800) +#define Q_FRAG_3_5K (0xE00) +#define Q_FRAG_7K (0x1C00) +#define Q_FRAG_32K (0x8000) +#define Q_FRAG_63K (0xFC00) + enum mtk_trb_cmd_type { TRB_CMD_MIN, TRB_CMD_ENABLE, @@ -54,17 +65,22 @@ struct mtk_ctrl_hif_ops { int (*send_cmd)(struct mtk_md_dev *mdev, int cmd, void *data); }; =20 -struct mtk_ctrl_cfg; +struct mtk_ctrl_cfg { + struct mtk_port_layer_cfg *port_layer_cfg; +}; + struct mtk_ctrl_trans; =20 struct mtk_ctrl_blk { struct mtk_md_dev *mdev; + struct mtk_port_mngr *port_mngr; struct mtk_ctrl_hif_ops *ops; void *ctrl_hw_priv; struct mtk_ctrl_cfg *cfg; }; =20 -int mtk_ctrl_init(struct mtk_md_dev *mdev, struct mtk_ctrl_hif_ops *ops); +int mtk_ctrl_init(struct mtk_md_dev *mdev, struct mtk_ctrl_hif_ops *ops, + struct mtk_ctrl_cfg *cfg); void mtk_ctrl_exit(struct mtk_md_dev *mdev); =20 #endif /* __MTK_CTRL_PLANE_H__ */ diff --git a/drivers/net/wwan/t9xx/mtk_dev.c b/drivers/net/wwan/t9xx/mtk_de= v.c index f254ca7ed877..8ba70d432e6f 100644 --- a/drivers/net/wwan/t9xx/mtk_dev.c +++ b/drivers/net/wwan/t9xx/mtk_dev.c @@ -6,6 +6,8 @@ #include =20 #include "mtk_dev.h" +#include "mtk_port.h" +#include "mtk_port_io.h" =20 struct mtk_md_dev *mtk_dev_alloc(struct device *pdev, const struct mtk_dev= _ops *dev_ops) { @@ -31,12 +33,21 @@ EXPORT_SYMBOL(mtk_dev_free); =20 static int __init mtk_common_drv_init(void) { - return 0; + int ret; + + ret =3D mtk_port_io_init(); + if (ret) + goto err_init_devid; + +err_init_devid: + return ret; } module_init(mtk_common_drv_init); =20 static void __exit mtk_common_drv_exit(void) { + mtk_port_io_exit(); + mtk_port_stale_list_grp_cleanup(); } module_exit(mtk_common_drv_exit); =20 diff --git a/drivers/net/wwan/t9xx/mtk_port.c b/drivers/net/wwan/t9xx/mtk_p= ort.c new file mode 100644 index 000000000000..c70a73a8d9de --- /dev/null +++ b/drivers/net/wwan/t9xx/mtk_port.c @@ -0,0 +1,877 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022, MediaTek Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "mtk_port.h" +#include "mtk_port_io.h" + +#define MTK_DFLT_TRB_TIMEOUT (5 * HZ) +#define MTK_DFLT_TRB_STATUS (0x1) +#define MTK_TRB_HEADER_ADDED (0xADDED) +#define MTK_CHECK_RX_SEQ_MASK (0x7fff) + +#define MTK_PORT_ENUM_VER (0) +#define MTK_PORT_ENUM_HEAD_PATTERN (0x5a5a5a5a) +#define MTK_PORT_ENUM_TAIL_PATTERN (0xa5a5a5a5) + +#define MTK_PORT_SEARCH_FROM_RADIX_TREE(p, s) ({\ + struct mtk_port *_p; \ + _p =3D rcu_dereference_raw(*(s)); \ + if (!_p) \ + continue; \ + p =3D _p; \ +}) + +#define MTK_PORT_INTERNAL_NODE_CHECK(p, s, i) ({\ + if (radix_tree_is_internal_node(p)) { \ + s =3D radix_tree_iter_retry(&(i));\ + continue; \ + } \ +}) + +struct mtk_port_info { + __le16 channel; + __le16 reserved; +} __packed; + +struct mtk_port_enum_msg { + __le32 head_pattern; + __le16 port_cnt; + __le16 version; + __le32 tail_pattern; + u8 data[]; +} __packed; + +/* global group for stale ports */ +static LIST_HEAD(stale_list_grp); +/* mutex lock for stale_list_group */ +DEFINE_MUTEX(port_mngr_grp_mtx); + +static DEFINE_IDA(ccci_dev_ids); + +/* This function working always under mutex lock port_mngr_grp_mtx */ +void mtk_port_release(struct kref *port_kref) +{ + struct mtk_stale_list *s_list; + struct mtk_port *port; + + port =3D container_of(port_kref, struct mtk_port, kref); + if (!test_bit(PORT_S_ON_STALE_LIST, &port->status)) + goto port_exit; + + list_del(&port->stale_entry); + list_for_each_entry(s_list, &stale_list_grp, entry) { + if (!strncmp(s_list->dev_str, port->dev_str, MTK_DEV_STR_LEN) && + list_empty(&s_list->ports) && s_list->dev_id >=3D 0) { + ida_free(&ccci_dev_ids, s_list->dev_id); + s_list->dev_id =3D -1; + break; + } + } +port_exit: + ports_ops[port->info.type]->exit(port); + kfree(port); +} + +static int mtk_port_tbl_add(struct mtk_port_mngr *port_mngr, struct mtk_po= rt *port) +{ + int ret; + + ret =3D radix_tree_insert(&port_mngr->port_tbl[MTK_PORT_TBL_TYPE(port->in= fo.rx_ch)], + port->info.rx_ch & 0xFFF, port); + if (ret) + dev_err(port_mngr->ctrl_blk->mdev->dev, + "port(%s) add to port_tbl failed, return %d\n", + port->info.name, ret); + else + port_mngr->port_cnt++; + + return ret; +} + +static void mtk_port_tbl_del(struct mtk_port_mngr *port_mngr, struct mtk_p= ort *port) +{ + radix_tree_delete(&port_mngr->port_tbl[MTK_PORT_TBL_TYPE(port->info.rx_ch= )], + port->info.rx_ch & 0xFFF); + port_mngr->port_cnt--; +} + +static struct mtk_port *mtk_port_restore_from_stale_list(struct mtk_port_m= ngr *port_mngr, + struct mtk_stale_list *s_list) +{ + struct mtk_port *port, *next_port; + int ret; + + mutex_lock(&port_mngr_grp_mtx); + list_for_each_entry_safe(port, next_port, &s_list->ports, stale_entry) { + kref_get(&port->kref); + list_del(&port->stale_entry); + ret =3D mtk_port_tbl_add(port_mngr, port); + if (ret) { + list_add_tail(&port->stale_entry, &s_list->ports); + kref_put(&port->kref, mtk_port_release); + mutex_unlock(&port_mngr_grp_mtx); + dev_err(port_mngr->ctrl_blk->mdev->dev, + "Failed when adding (%s) to port mngr\n", + port->info.name); + return ERR_PTR(ret); + } + + port->port_mngr =3D port_mngr; + clear_bit(PORT_S_ON_STALE_LIST, &port->status); + ports_ops[port->info.type]->reset(port); + } + mutex_unlock(&port_mngr_grp_mtx); + + return NULL; +} + +static struct mtk_port *mtk_port_alloc_and_add(struct mtk_port_mngr *port_= mngr, + struct mtk_port_cfg *dflt_info) +{ + struct mtk_port *port; + int ret; + + port =3D kzalloc_obj(*port, GFP_KERNEL); + if (!port) { + ret =3D -ENOMEM; + goto err_alloc_port; + } + memcpy(&port->info, dflt_info, sizeof(*dflt_info)); + + ret =3D mtk_port_tbl_add(port_mngr, port); + if (ret < 0) { + dev_err(port_mngr->ctrl_blk->mdev->dev, + "Failed to add port(%s) to port tbl\n", dflt_info->name); + goto err_free_port; + } + + port->port_mngr =3D port_mngr; + ret =3D ports_ops[port->info.type]->init(port); + if (ret < 0) { + mtk_port_tbl_del(port_mngr, port); + goto err_free_port; + } + + memcpy(port->dev_str, port_mngr->ctrl_blk->mdev->dev_str, MTK_DEV_STR_LEN= ); + return port; + +err_free_port: + kfree(port); +err_alloc_port: + return ERR_PTR(ret); +} + +static void mtk_port_free_or_backup(struct mtk_port_mngr *port_mngr, + struct mtk_port *port, struct mtk_stale_list *s_list) +{ + mutex_lock(&port_mngr_grp_mtx); + mtk_port_tbl_del(port_mngr, port); + if (port->info.type !=3D PORT_TYPE_INTERNAL) { + if (test_bit(PORT_S_OPEN, &port->status)) { + list_add_tail(&port->stale_entry, &s_list->ports); + set_bit(PORT_S_ON_STALE_LIST, &port->status); + memcpy(port->dev_str, port_mngr->ctrl_blk->mdev->dev_str, + MTK_DEV_STR_LEN); + port->port_mngr =3D NULL; + } + kref_put(&port->kref, mtk_port_release); + } else { + mtk_port_release(&port->kref); + } + mutex_unlock(&port_mngr_grp_mtx); +} + +static struct mtk_port *mtk_port_search_by_id(struct mtk_port_mngr *port_m= ngr, int rx_ch) +{ + int tbl_type =3D MTK_PORT_TBL_TYPE(rx_ch); + + if (tbl_type < PORT_TBL_SAP || tbl_type >=3D PORT_TBL_MAX) + return NULL; + + return radix_tree_lookup(&port_mngr->port_tbl[tbl_type], MTK_CH_ID(rx_ch)= ); +} + +struct mtk_port *mtk_port_search_by_name(struct mtk_port_mngr *port_mngr, = char *name) +{ + int tbl_type =3D PORT_TBL_SAP; + struct radix_tree_iter iter; + struct mtk_port *port; + void __rcu **slot; + + do { + radix_tree_for_each_slot(slot, &port_mngr->port_tbl[tbl_type], &iter, 0)= { + MTK_PORT_SEARCH_FROM_RADIX_TREE(port, slot); + MTK_PORT_INTERNAL_NODE_CHECK(port, slot, iter); + if (!strncmp(port->info.name, name, MTK_DFLT_PORT_NAME_LEN)) + return port; + } + tbl_type++; + } while (tbl_type < PORT_TBL_MAX); + + return NULL; +} + +static int mtk_port_tbl_create(struct mtk_port_mngr *port_mngr, struct mtk= _port_cfg *cfg, + const int port_cnt, struct mtk_stale_list *s_list) +{ + struct mtk_port_cfg *dflt_port; + struct mtk_port *port; + int i; + + INIT_RADIX_TREE(&port_mngr->port_tbl[PORT_TBL_SAP], GFP_KERNEL); + INIT_RADIX_TREE(&port_mngr->port_tbl[PORT_TBL_MD], GFP_KERNEL); + + mtk_port_restore_from_stale_list(port_mngr, s_list); + + /* copy ports from static port cfg table */ + for (i =3D 0; i < port_cnt; i++) { + dflt_port =3D cfg + i; + if (!mtk_port_search_by_id(port_mngr, dflt_port->rx_ch)) { + port =3D mtk_port_alloc_and_add(port_mngr, dflt_port); + if (IS_ERR(port)) + return PTR_ERR(port); + } + } + + return 0; +} + +static void mtk_port_tbl_destroy(struct mtk_port_mngr *port_mngr, struct m= tk_stale_list *s_list) +{ + struct mtk_port **ports; + int tbl_type; + int ret, idx; + + ports =3D kcalloc(port_mngr->port_cnt, sizeof(struct mtk_port *), GFP_KER= NEL); + if (!ports) + return; + + tbl_type =3D PORT_TBL_SAP; + do { + ret =3D radix_tree_gang_lookup(&port_mngr->port_tbl[tbl_type], + (void **)ports, 0, port_mngr->port_cnt); + for (idx =3D 0; idx < ret; idx++) + ports_ops[ports[idx]->info.type]->disable(ports[idx]); + for (idx =3D 0; idx < ret; idx++) + mtk_port_free_or_backup(port_mngr, ports[idx], s_list); + } while (++tbl_type < PORT_TBL_MAX); + kfree(ports); +} + +static struct mtk_stale_list *mtk_port_stale_list_create(struct mtk_ctrl_b= lk *ctrl_blk) +{ + struct mtk_stale_list *s_list; + + s_list =3D kzalloc_obj(*s_list, GFP_KERNEL); + if (!s_list) + return NULL; + + memcpy(s_list->dev_str, ctrl_blk->mdev->dev_str, MTK_DEV_STR_LEN); + s_list->dev_id =3D -1; + INIT_LIST_HEAD(&s_list->ports); + rwlock_init(&s_list->port_mngr_lock); + + mutex_lock(&port_mngr_grp_mtx); + list_add_tail(&s_list->entry, &stale_list_grp); + mutex_unlock(&port_mngr_grp_mtx); + + return s_list; +} + +static void mtk_port_stale_list_destroy(struct mtk_stale_list *s_list) +{ + mutex_lock(&port_mngr_grp_mtx); + list_del(&s_list->entry); + mutex_unlock(&port_mngr_grp_mtx); + kfree(s_list); +} + +static struct mtk_stale_list *mtk_port_stale_list_search(const char *dev_s= tr) +{ + struct mtk_stale_list *tmp, *s_list =3D NULL; + + mutex_lock(&port_mngr_grp_mtx); + list_for_each_entry(tmp, &stale_list_grp, entry) { + if (!strncmp(tmp->dev_str, dev_str, MTK_DEV_STR_LEN)) { + s_list =3D tmp; + break; + } + } + mutex_unlock(&port_mngr_grp_mtx); + + return s_list; +} + +void mtk_port_stale_list_grp_cleanup(void) +{ + struct mtk_stale_list *s_list, *next_s_list; + struct mtk_port *port, *next_port; + + mutex_lock(&port_mngr_grp_mtx); + list_for_each_entry_safe(s_list, next_s_list, &stale_list_grp, entry) { + list_del(&s_list->entry); + + list_for_each_entry_safe(port, next_port, &s_list->ports, stale_entry) { + clear_bit(PORT_S_ON_STALE_LIST, &port->status); + mtk_port_release(&port->kref); + } + + kfree(s_list); + } + mutex_unlock(&port_mngr_grp_mtx); +} + +static struct mtk_stale_list *mtk_port_stale_list_init(struct mtk_ctrl_blk= *ctrl_blk, int *dev_id) +{ + struct mtk_stale_list *s_list; + + s_list =3D mtk_port_stale_list_search(ctrl_blk->mdev->dev_str); + if (!s_list) { + s_list =3D mtk_port_stale_list_create(ctrl_blk); + if (unlikely(!s_list)) + return NULL; + } + + mutex_lock(&port_mngr_grp_mtx); + if (s_list->dev_id < 0) { + *dev_id =3D ida_alloc_range(&ccci_dev_ids, 0, MTK_DFLT_MAX_DEV_CNT - 1, = GFP_KERNEL); + } else { + *dev_id =3D s_list->dev_id; + s_list->dev_id =3D -1; + } + mutex_unlock(&port_mngr_grp_mtx); + + return s_list; +} + +static void mtk_port_stale_list_exit(struct mtk_ctrl_blk *ctrl_blk, + struct mtk_stale_list *s_list, int dev_id) +{ + if (!s_list) + return; + mutex_lock(&port_mngr_grp_mtx); + if (list_empty(&s_list->ports)) { + ida_free(&ccci_dev_ids, dev_id); + mutex_unlock(&port_mngr_grp_mtx); + mtk_port_stale_list_destroy(s_list); + } else { + s_list->dev_id =3D dev_id; + mutex_unlock(&port_mngr_grp_mtx); + } +} + +void mtk_port_trb_init(struct mtk_port *port, struct trb *trb, enum mtk_tr= b_cmd_type cmd, + int (*trb_complete)(struct sk_buff *skb)) +{ + kref_init(&trb->kref); + trb->channel_id =3D port->info.rx_ch; + trb->status =3D MTK_DFLT_TRB_STATUS; + trb->priv =3D port; + trb->cmd =3D cmd; + trb->trb_complete =3D trb_complete; +} + +void mtk_port_trb_free(struct kref *trb_kref) +{ + struct trb *trb =3D container_of(trb_kref, struct trb, kref); + struct sk_buff *skb, *frag_skb, *next_skb; + + skb =3D container_of((char *)trb, struct sk_buff, cb[0]); + /* Free frag_list for scatter gather TX */ + if (trb->cmd =3D=3D TRB_CMD_TX && skb_has_frag_list(skb)) { + frag_skb =3D skb_shinfo(skb)->frag_list; + while (frag_skb) { + next_skb =3D frag_skb->next; + frag_skb->next =3D NULL; + dev_kfree_skb_any(frag_skb); + frag_skb =3D next_skb; + } + skb_shinfo(skb)->frag_list =3D NULL; + skb->data_len =3D 0; + } + dev_kfree_skb_any(skb); +} +EXPORT_SYMBOL(mtk_port_trb_free); + +static int mtk_port_open_trb_complete(struct sk_buff *skb) +{ + struct trb_open_priv *trb_open_priv =3D (struct trb_open_priv *)skb->data; + struct trb *trb =3D (struct trb *)skb->cb; + struct mtk_port *port =3D trb->priv; + + if (!trb->status) { + port->tx_mtu =3D trb_open_priv->tx_mtu; + port->rx_mtu =3D trb_open_priv->rx_mtu; + port->tx_frag_size =3D trb_open_priv->tx_frag_size; + port->rx_frag_size =3D trb_open_priv->rx_frag_size; + port->tx_mtu -=3D MTK_CCCI_H_ELEN; + port->rx_mtu -=3D MTK_CCCI_H_ELEN; + } + + wake_up_interruptible_all(&port->trb_wq); + + kref_put(&trb->kref, mtk_port_trb_free); + return 0; +} + +static int mtk_port_close_trb_complete(struct sk_buff *skb) +{ + struct trb *trb =3D (struct trb *)skb->cb; + struct mtk_port *port =3D trb->priv; + + wake_up_interruptible_all(&port->trb_wq); + wake_up_interruptible_all(&port->rx_wq); + kref_put(&trb->kref, mtk_port_trb_free); + + return 0; +} + +static int mtk_port_tx_complete(struct sk_buff *skb) +{ + struct trb *trb =3D (struct trb *)skb->cb; + struct mtk_port *port =3D trb->priv; + + if (trb->status < 0) + dev_warn(port->port_mngr->ctrl_blk->mdev->dev, + "Failed to send data: status:%d, port:%s\n", + trb->status, port->info.name); + + wake_up_interruptible_all(&port->trb_wq); + kref_put(&trb->kref, mtk_port_trb_free); + + return 0; +} + +int mtk_port_status_check(struct mtk_port *port) +{ + if (!test_bit(PORT_S_ENABLE, &port->status)) + return -ENODEV; + + if (!test_bit(PORT_S_OPEN, &port->status) || test_bit(PORT_S_FLUSH, &port= ->status) || + !test_bit(PORT_S_WR, &port->status)) + return -EBADF; + + return 0; +} + +int mtk_port_send_data(struct mtk_port *port, void *data) +{ + struct mtk_port_mngr *port_mngr; + struct sk_buff *skb =3D data; + bool force_send; + struct trb *trb; + int ret, len; + + port_mngr =3D port->port_mngr; + + force_send =3D !!(port->info.flags & (PORT_F_BLOCKING | PORT_F_FORCE_SEND= )); + trb =3D (struct trb *)skb->cb; + mtk_port_trb_init(port, trb, TRB_CMD_TX, mtk_port_tx_complete); + len =3D skb->len; + kref_get(&trb->kref); /* kref count 1->2 */ + + /* add ccci header */ + mtk_port_add_header(skb); + ret =3D mtk_port_status_check(port); + if (!ret) + ret =3D port_mngr->ctrl_blk->ops->submit_skb(port_mngr->ctrl_blk->mdev, + skb, force_send); + + if (ret < 0) { + kref_put(&trb->kref, mtk_port_trb_free); /* kref count 2->1 */ + kref_put(&trb->kref, mtk_port_trb_free); /* kref count 1->0 */ + port->tx_seq--; + goto out; + } + + if (!(port->info.flags & PORT_F_BLOCKING)) { + kref_put(&trb->kref, mtk_port_trb_free); + ret =3D len; + goto out; + } +start_wait: + + /* wait trb done, and no timeout in tx blocking mode */ + ret =3D wait_event_interruptible_timeout(port->trb_wq, + trb->status <=3D 0 || + test_bit(PORT_S_FLUSH, &port->status) || + !test_bit(PORT_S_WR, &port->status), + MTK_DFLT_TRB_TIMEOUT); + if (!ret) { + goto start_wait; + } else if (ret =3D=3D -ERESTARTSYS) { + ret =3D -EINTR; + } else if (ret > 0) { + if (test_bit(PORT_S_FLUSH, &port->status)) + ret =3D len; + else + ret =3D (!trb->status) ? len : trb->status; + } + kref_put(&trb->kref, mtk_port_trb_free); + +out: + return ret; +} + +static int mtk_port_check_rx_seq(struct mtk_port *port, struct mtk_ccci_he= ader *ccci_h) +{ + u16 seq_num, assert_bit, channel; + struct mtk_md_dev *mdev; + + seq_num =3D FIELD_GET(MTK_HDR_FLD_SEQ, le32_to_cpu(ccci_h->status)); + assert_bit =3D FIELD_GET(MTK_HDR_FLD_AST, le32_to_cpu(ccci_h->status)); + if (assert_bit && port->rx_seq && + ((seq_num - port->rx_seq) & MTK_CHECK_RX_SEQ_MASK) !=3D 1) { + mdev =3D port->port_mngr->ctrl_blk->mdev; + channel =3D FIELD_GET(MTK_HDR_FLD_CHN, le32_to_cpu(ccci_h->status)); + dev_warn((mdev)->dev, + " seq num out-of-order %d->%d, len(%u)\n", + channel, seq_num, port->rx_seq, + le32_to_cpu(ccci_h->packet_len)); + + port->rx_seq =3D seq_num; + return -EPROTO; + } + + return 0; +} + +static int mtk_port_rx_dispatch_frag_skb(struct mtk_port *port, struct sk_= buff *skb) +{ + struct sk_buff *frag_skb, *frag_next; + int ret; + + frag_skb =3D skb_shinfo(skb)->frag_list; + skb->len -=3D skb->data_len; + skb->data_len =3D 0; + skb_shinfo(skb)->frag_list =3D NULL; + + ret =3D ports_ops[port->info.type]->recv(port, skb); + if (ret < 0) { + skb_shinfo(skb)->frag_list =3D frag_skb; + return ret; + } + + while (frag_skb) { + frag_next =3D frag_skb->next; + if (!frag_skb->len) { + frag_skb->next =3D NULL; + dev_kfree_skb_any(frag_skb); + frag_skb =3D frag_next; + continue; + } + frag_skb->next =3D NULL; + ret =3D ports_ops[port->info.type]->recv(port, frag_skb); + if (ret < 0) { + frag_skb->next =3D frag_next; + while (frag_skb) { + frag_next =3D frag_skb->next; + frag_skb->next =3D NULL; + dev_kfree_skb_any(frag_skb); + frag_skb =3D frag_next; + } + return -EIO; + } + frag_skb =3D frag_next; + } + + return 0; +} + +static int mtk_port_rx_dispatch(struct sk_buff *skb, void *priv, bool forc= e_recv) +{ + struct mtk_port_mngr *port_mngr; + struct mtk_ccci_header *ccci_h; + struct mtk_port *port =3D priv; + int ret =3D -EPROTO; + u16 channel; + + if (!skb || !priv) { + pr_err("Invalid input value in rx dispatch\n"); + return -EINVAL; + } + + port_mngr =3D port->port_mngr; + + ccci_h =3D mtk_port_strip_header(skb); + if (unlikely(!ccci_h)) { + dev_warn(port_mngr->ctrl_blk->mdev->dev, + "Unsupported: skb length(%d) is less than ccci header\n", + skb->len); + goto drop_data; + } + + channel =3D FIELD_GET(MTK_HDR_FLD_CHN, le32_to_cpu(ccci_h->status)); + port =3D mtk_port_search_by_id(port_mngr, channel); + if (unlikely(!port)) { + dev_warn(port_mngr->ctrl_blk->mdev->dev, + "Failed to find port by channel:%d\n", channel); + goto drop_data; + } + + ret =3D mtk_port_check_rx_seq(port, ccci_h); + if (unlikely(ret)) + goto drop_data; + + port->rx_seq =3D FIELD_GET(MTK_HDR_FLD_SEQ, le32_to_cpu(ccci_h->status)); + skb_pull(skb, sizeof(*ccci_h)); + + /* Support scatter gather transmission */ + if (port->rx_mtu > port->rx_frag_size) { + ret =3D mtk_port_rx_dispatch_frag_skb(port, skb); + /* -EIO means partial data dispatch complete, does not goto drop flow */ + if (ret < 0 && ret !=3D -EIO) + goto drop_frag_skb; + } else { + ret =3D ports_ops[port->info.type]->recv(port, skb); + if (ret < 0) + goto drop_data; + } + + return ret; + +drop_frag_skb: + { + struct sk_buff *frag_skb, *tmp; + + frag_skb =3D skb_shinfo(skb)->frag_list; + while (frag_skb) { + tmp =3D frag_skb->next; + frag_skb->next =3D NULL; + dev_kfree_skb_any(frag_skb); + frag_skb =3D tmp; + } + skb_shinfo(skb)->frag_list =3D NULL; + } +drop_data: + dev_kfree_skb_any(skb); + return ret; +} + +int mtk_port_add_header(struct sk_buff *skb) +{ + struct mtk_ccci_header *ccci_h; + struct mtk_port *port; + struct trb *trb; + + trb =3D (struct trb *)skb->cb; + if (trb->status =3D=3D MTK_TRB_HEADER_ADDED) + return 0; + + port =3D trb->priv; + if (!port) + return -EINVAL; + + ccci_h =3D skb_push(skb, sizeof(*ccci_h)); + + ccci_h->packet_header =3D cpu_to_le32(0); + ccci_h->packet_len =3D cpu_to_le32(skb->len); + ccci_h->ex_msg =3D cpu_to_le32(0); + ccci_h->status =3D cpu_to_le32(FIELD_PREP(MTK_HDR_FLD_CHN, port->info.tx_= ch) | + FIELD_PREP(MTK_HDR_FLD_SEQ, port->tx_seq++) | + FIELD_PREP(MTK_HDR_FLD_AST, 1)); + + trb->status =3D MTK_TRB_HEADER_ADDED; + + return 0; +} + +struct mtk_ccci_header *mtk_port_strip_header(struct sk_buff *skb) +{ + struct mtk_ccci_header *ccci_h; + + if (skb->len < sizeof(*ccci_h)) { + pr_err("Invalid input value\n"); + return NULL; + } + + ccci_h =3D (struct mtk_ccci_header *)skb->data; + + return ccci_h; +} + +int mtk_port_status_update(struct mtk_md_dev *mdev, void *data) +{ + struct mtk_port_enum_msg *msg =3D data; + struct mtk_port_info *port_info; + struct mtk_port_mngr *port_mngr; + struct mtk_ctrl_blk *ctrl_blk; + struct mtk_port *port; + int port_id; + u16 ch_id; + + if (unlikely(!mdev || !msg)) + return -EINVAL; + + ctrl_blk =3D mdev->ctrl_blk; + port_mngr =3D ctrl_blk->port_mngr; + if (le16_to_cpu(msg->version) !=3D MTK_PORT_ENUM_VER || + le32_to_cpu(msg->head_pattern) !=3D MTK_PORT_ENUM_HEAD_PATTERN || + le32_to_cpu(msg->tail_pattern) !=3D MTK_PORT_ENUM_TAIL_PATTERN) + return -EPROTO; + + for (port_id =3D 0; port_id < le16_to_cpu(msg->port_cnt); port_id++) { + port_info =3D (struct mtk_port_info *)(msg->data + + (sizeof(*port_info) * port_id)); + ch_id =3D FIELD_GET(MTK_INFO_FLD_CHID, le16_to_cpu(port_info->channel)); + port =3D mtk_port_search_by_id(port_mngr, ch_id); + if (!port) + continue; + port->enable =3D FIELD_GET(MTK_INFO_FLD_EN, le16_to_cpu(port_info->chann= el)); + } + + return 0; +} + +int mtk_port_ch_enable(struct mtk_port *port) +{ + struct mtk_port_mngr *port_mngr =3D port->port_mngr; + struct trb_open_priv *trb_open_priv; + struct sk_buff *skb; + struct trb *trb; + int ret; + + skb =3D __dev_alloc_skb(Q_MTU_3_5K, GFP_KERNEL); + if (!skb) + return -ENOMEM; + + trb_open_priv =3D (struct trb_open_priv *)skb->data; + trb_open_priv->rx_done =3D mtk_port_rx_dispatch; + + skb_put(skb, sizeof(struct trb_open_priv)); + trb =3D (struct trb *)skb->cb; + mtk_port_trb_init(port, trb, TRB_CMD_ENABLE, mtk_port_open_trb_complete); + kref_get(&trb->kref); + + ret =3D port_mngr->ctrl_blk->ops->submit_skb(port_mngr->ctrl_blk->mdev, s= kb, true); + if (ret) { + dev_err(port_mngr->ctrl_blk->mdev->dev, + "Failed to submit trb for port(%s), ret=3D%d\n", + port->info.name, ret); + kref_put(&trb->kref, mtk_port_trb_free); + kref_put(&trb->kref, mtk_port_trb_free); + return ret; + } + +start_wait: + ret =3D wait_event_interruptible_timeout(port->trb_wq, trb->status <=3D 0, + MTK_DFLT_TRB_TIMEOUT); + if (ret =3D=3D -ERESTARTSYS) + goto start_wait; + else if (!ret) + ret =3D -ETIMEDOUT; + else + ret =3D trb->status; + + kref_put(&trb->kref, mtk_port_trb_free); + + return ret; +} + +int mtk_port_ch_disable(struct mtk_port *port) +{ + struct mtk_port_mngr *port_mngr =3D port->port_mngr; + struct sk_buff *skb; + struct trb *trb; + int ret; + + skb =3D __dev_alloc_skb(Q_MTU_3_5K, GFP_KERNEL); + if (!skb) + return -ENOMEM; + + trb =3D (struct trb *)skb->cb; + mtk_port_trb_init(port, trb, TRB_CMD_DISABLE, mtk_port_close_trb_complete= ); + kref_get(&trb->kref); + + ret =3D port_mngr->ctrl_blk->ops->submit_skb(port_mngr->ctrl_blk->mdev, s= kb, true); + if (ret) { + dev_warn(port_mngr->ctrl_blk->mdev->dev, + "Failed to submit trb for port(%s), ret=3D%d\n", + port->info.name, ret); + kref_put(&trb->kref, mtk_port_trb_free); + kref_put(&trb->kref, mtk_port_trb_free); + return ret; + } + +start_wait: + ret =3D wait_event_interruptible_timeout(port->trb_wq, trb->status <=3D 0, + MTK_DFLT_TRB_TIMEOUT); + if (ret =3D=3D -ERESTARTSYS) + goto start_wait; + else if (!ret) + ret =3D -ETIMEDOUT; + else + ret =3D trb->status; + + kref_put(&trb->kref, mtk_port_trb_free); + + return ret; +} + +int mtk_port_mngr_init(struct mtk_ctrl_blk *ctrl_blk, struct mtk_port_cfg = *port_cfg, int port_cnt) +{ + struct mtk_port_mngr *port_mngr; + struct mtk_stale_list *s_list; + int ret =3D -ENOMEM; + int dev_id; + + s_list =3D mtk_port_stale_list_init(ctrl_blk, &dev_id); + if (!s_list) { + dev_err((ctrl_blk->mdev)->dev, "Failed to init mtk_stale_list\n"); + goto err_out; + } + + port_mngr =3D devm_kzalloc(ctrl_blk->mdev->dev, sizeof(*port_mngr), GFP_K= ERNEL); + if (unlikely(!port_mngr)) { + dev_err((ctrl_blk->mdev)->dev, "Failed to alloc memory for port_mngr\n"); + goto err_exit_stale_list; + } + + port_mngr->ctrl_blk =3D ctrl_blk; + port_mngr->dev_id =3D dev_id; + + ret =3D mtk_port_tbl_create(port_mngr, port_cfg, port_cnt, s_list); + if (unlikely(ret)) { + dev_err((ctrl_blk->mdev)->dev, "Failed to create port_tbl\n"); + goto err_free_port_mngr; + } + + ctrl_blk->port_mngr =3D port_mngr; + + return ret; + +err_free_port_mngr: + mtk_port_tbl_destroy(port_mngr, s_list); + devm_kfree(ctrl_blk->mdev->dev, port_mngr); +err_exit_stale_list: + mtk_port_stale_list_exit(ctrl_blk, s_list, dev_id); +err_out: + return ret; +} + +void mtk_port_mngr_exit(struct mtk_ctrl_blk *ctrl_blk) +{ + struct mtk_port_mngr *port_mngr =3D ctrl_blk->port_mngr; + struct mtk_stale_list *s_list; + int dev_id; + + s_list =3D mtk_port_stale_list_search(port_mngr->ctrl_blk->mdev->dev_str); + dev_id =3D port_mngr->dev_id; + + mtk_port_tbl_destroy(port_mngr, s_list); + + devm_kfree(ctrl_blk->mdev->dev, port_mngr); + ctrl_blk->port_mngr =3D NULL; + mtk_port_stale_list_exit(ctrl_blk, s_list, dev_id); +} diff --git a/drivers/net/wwan/t9xx/mtk_port.h b/drivers/net/wwan/t9xx/mtk_p= ort.h new file mode 100644 index 000000000000..bd4291408bc2 --- /dev/null +++ b/drivers/net/wwan/t9xx/mtk_port.h @@ -0,0 +1,159 @@ +/* SPDX-License-Identifier: GPL-2.0-only + * + * Copyright (c) 2022, MediaTek Inc. + */ + +#ifndef __MTK_PORT_H__ +#define __MTK_PORT_H__ + +#include +#include +#include +#include +#include + +#include "mtk_ctrl_plane.h" +#include "mtk_dev.h" + +#define MTK_PEER_ID_MASK (0xF000) +#define MTK_PEER_ID_SHIFT (12) +#define MTK_PEER_ID(ch) (((ch) & MTK_PEER_ID_MASK) >> MTK_PEER_ID_SHIFT) +#define MTK_PEER_ID_SAP (0x1) +#define MTK_PEER_ID_MD (0x2) +#define MTK_CH_ID_MASK (0x0FFF) +#define MTK_CH_ID(ch) ((ch) & MTK_CH_ID_MASK) +#define MTK_DFLT_MAX_DEV_CNT (10) +#define MTK_DFLT_PORT_NAME_LEN (20) + +/* Mapping MTK_PEER_ID and mtk_port_tbl index */ +#define MTK_PORT_TBL_TYPE(ch) (MTK_PEER_ID(ch) - 1) + +/* ccci header length + reserved space that is used in exception flow */ +#define MTK_CCCI_H_ELEN (128) + +#define MTK_HDR_FLD_AST ((u32)BIT(31)) +#define MTK_HDR_FLD_SEQ GENMASK(30, 16) +#define MTK_HDR_FLD_CHN GENMASK(15, 0) + +#define MTK_INFO_FLD_EN ((u16)BIT(15)) +#define MTK_INFO_FLD_CHID GENMASK(14, 0) + +enum mtk_port_status { + PORT_S_DFLT =3D 0, + PORT_S_ENABLE, + PORT_S_OPEN, + PORT_S_RD, + PORT_S_WR, + PORT_S_FLUSH, + PORT_S_ON_STALE_LIST, + PORT_S_STOP, +}; + +enum mtk_ccci_ch { + /* to sAP */ + CCCI_SAP_CONTROL_RX =3D 0x1000, + CCCI_SAP_CONTROL_TX =3D 0x1001, + /* to MD */ + CCCI_CONTROL_RX =3D 0x2000, + CCCI_CONTROL_TX =3D 0x2001, +}; + +enum mtk_port_flag { + PORT_F_DFLT =3D 0, + PORT_F_BLOCKING =3D BIT(1), + PORT_F_ALLOW_DROP =3D BIT(2), + PORT_F_FORCE_SEND =3D BIT(6), +}; + +enum mtk_port_tbl { + PORT_TBL_SAP, + PORT_TBL_MD, + PORT_TBL_MAX +}; + +enum mtk_port_type { + PORT_TYPE_INTERNAL, + PORT_TYPE_MAX +}; + +struct mtk_internal_port { + void *arg; + int (*recv_cb)(void *arg, struct sk_buff *skb); +}; + +struct mtk_port_cfg { + enum mtk_ccci_ch tx_ch; + enum mtk_ccci_ch rx_ch; + enum mtk_port_type type; + char name[MTK_DFLT_PORT_NAME_LEN]; + unsigned char flags; +}; + +struct mtk_port { + struct mtk_port_cfg info; + struct kref kref; + bool enable; + unsigned long status; + unsigned int minor; + unsigned short tx_seq; + unsigned short rx_seq; + unsigned int tx_mtu; + unsigned int rx_mtu; + u32 tx_frag_size; + u32 rx_frag_size; + struct sk_buff_head rx_skb_list; + unsigned int rx_data_len; + unsigned int rx_buf_size; + wait_queue_head_t trb_wq; + wait_queue_head_t rx_wq; + struct list_head stale_entry; + char dev_str[MTK_DEV_STR_LEN]; + struct mtk_port_mngr *port_mngr; + struct mtk_internal_port i_priv; +}; + +struct mtk_port_mngr { + struct mtk_ctrl_blk *ctrl_blk; + struct radix_tree_root port_tbl[PORT_TBL_MAX]; + unsigned int port_cnt; + int dev_id; +}; + +struct mtk_stale_list { + struct list_head entry; + struct list_head ports; + char dev_str[MTK_DEV_STR_LEN]; + int dev_id; + rwlock_t port_mngr_lock; +}; + +struct mtk_ccci_header { + __le32 packet_header; + __le32 packet_len; + __le32 status; + __le32 ex_msg; +}; + +struct mtk_port_layer_cfg { + struct mtk_port_cfg *port_cfg; + int port_cnt; +}; + +extern const struct port_ops *ports_ops[PORT_TYPE_MAX]; + +void mtk_port_release(struct kref *port_kref); +void mtk_port_trb_free(struct kref *trb_kref); +struct mtk_port *mtk_port_search_by_name(struct mtk_port_mngr *port_mngr, = char *name); +void mtk_port_stale_list_grp_cleanup(void); +int mtk_port_add_header(struct sk_buff *skb); +struct mtk_ccci_header *mtk_port_strip_header(struct sk_buff *skb); +int mtk_port_status_check(struct mtk_port *port); +int mtk_port_send_data(struct mtk_port *port, void *data); +int mtk_port_status_update(struct mtk_md_dev *mdev, void *data); +int mtk_port_ch_enable(struct mtk_port *port); +int mtk_port_ch_disable(struct mtk_port *port); +int mtk_port_mngr_init(struct mtk_ctrl_blk *ctrl_blk, struct mtk_port_cfg = *port_cfg, int port_cnt); +void mtk_port_mngr_exit(struct mtk_ctrl_blk *ctrl_blk); +void mtk_port_trb_init(struct mtk_port *port, struct trb *trb, enum mtk_tr= b_cmd_type cmd, + int (*trb_complete)(struct sk_buff *skb)); +#endif /* __MTK_PORT_H__ */ diff --git a/drivers/net/wwan/t9xx/mtk_port_io.c b/drivers/net/wwan/t9xx/mt= k_port_io.c new file mode 100644 index 000000000000..bbde0d950226 --- /dev/null +++ b/drivers/net/wwan/t9xx/mtk_port_io.c @@ -0,0 +1,238 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022, MediaTek Inc. + */ +#include + +#include "mtk_port_io.h" + +static int mtk_port_get_locked(struct mtk_port *port) +{ + int ret =3D 0; + + mutex_lock(&port_mngr_grp_mtx); + if (!port) { + mutex_unlock(&port_mngr_grp_mtx); + pr_err("Port does not exist\n"); + return -ENODEV; + } + kref_get(&port->kref); + mutex_unlock(&port_mngr_grp_mtx); + + return ret; +} + +static void mtk_port_put_locked(struct mtk_port *port) +{ + mutex_lock(&port_mngr_grp_mtx); + kref_put(&port->kref, mtk_port_release); + mutex_unlock(&port_mngr_grp_mtx); +} + +static void mtk_port_struct_init(struct mtk_port *port) +{ + port->tx_seq =3D 0; + port->rx_seq =3D -1; + clear_bit(PORT_S_ENABLE, &port->status); + kref_init(&port->kref); + skb_queue_head_init(&port->rx_skb_list); + port->rx_buf_size =3D MTK_RX_BUF_SIZE; + init_waitqueue_head(&port->trb_wq); + init_waitqueue_head(&port->rx_wq); +} + +static int mtk_port_internal_init(struct mtk_port *port) +{ + mtk_port_struct_init(port); + port->enable =3D false; + + return 0; +} + +static void mtk_port_internal_exit(struct mtk_port *port) +{ + if (test_bit(PORT_S_ENABLE, &port->status)) + ports_ops[port->info.type]->disable(port); +} + +static void mtk_port_reset(struct mtk_port *port) +{ + port->tx_seq =3D 0; + port->rx_seq =3D -1; +} + +static void mtk_port_internal_enable(struct mtk_port *port) +{ + int ret; + + if (test_bit(PORT_S_ENABLE, &port->status)) + return; + + ret =3D mtk_port_ch_enable(port); + if (ret && ret !=3D -EBUSY) + return; + + set_bit(PORT_S_WR, &port->status); + set_bit(PORT_S_ENABLE, &port->status); +} + +static void mtk_port_internal_disable(struct mtk_port *port) +{ + if (!test_and_clear_bit(PORT_S_ENABLE, &port->status)) + return; + + clear_bit(PORT_S_WR, &port->status); + mtk_port_ch_disable(port); +} + +static int mtk_port_internal_recv(struct mtk_port *port, struct sk_buff *s= kb) +{ + struct mtk_internal_port *priv; + int ret =3D -ENXIO; + + if (!test_bit(PORT_S_OPEN, &port->status)) + goto drop_data; + + priv =3D &port->i_priv; + if (!priv->recv_cb || !priv->arg) + goto drop_data; + + ret =3D priv->recv_cb(priv->arg, skb); + return ret; + +drop_data: + dev_kfree_skb_any(skb); + return ret; +} + +static int mtk_port_common_open(struct mtk_port *port) +{ + int ret =3D 0; + + if (!test_bit(PORT_S_ENABLE, &port->status)) + return -ENODEV; + + if (test_bit(PORT_S_OPEN, &port->status)) + return -EBUSY; + + skb_queue_purge(&port->rx_skb_list); + set_bit(PORT_S_OPEN, &port->status); + clear_bit(PORT_S_FLUSH, &port->status); + + return ret; +} + +static void mtk_port_common_close(struct mtk_port *port) +{ + clear_bit(PORT_S_OPEN, &port->status); + + skb_queue_purge(&port->rx_skb_list); + port->rx_data_len =3D 0; + + set_bit(PORT_S_FLUSH, &port->status); + wake_up_interruptible_all(&port->trb_wq); + wake_up_interruptible_all(&port->rx_wq); +} + +void *mtk_port_internal_open(struct mtk_md_dev *mdev, char *name, int flag) +{ + struct mtk_port_mngr *port_mngr; + struct mtk_ctrl_blk *ctrl_blk; + struct mtk_port *port; + int ret; + + ctrl_blk =3D mdev->ctrl_blk; + port_mngr =3D ctrl_blk->port_mngr; + + port =3D mtk_port_search_by_name(port_mngr, name); + if (port && port->info.type !=3D PORT_TYPE_INTERNAL) { + port =3D NULL; + goto out; + } + + ret =3D mtk_port_get_locked(port); + if (ret) + goto out; + + ret =3D mtk_port_common_open(port); + if (ret) { + mtk_port_put_locked(port); + goto out; + } + + if (flag & O_NONBLOCK) + port->info.flags &=3D ~PORT_F_BLOCKING; + else + port->info.flags |=3D PORT_F_BLOCKING; +out: + return port; +} + +int mtk_port_internal_close(void *i_port) +{ + struct mtk_port *port =3D i_port; + int ret =3D 0; + + if (!port) { + ret =3D -EINVAL; + goto end; + } + + if (!test_bit(PORT_S_OPEN, &port->status)) { + pr_err("Port(%s) has been closed\n", port->info.name); + ret =3D -EBADF; + goto end; + } + + mtk_port_common_close(port); + mtk_port_put_locked(port); +end: + return ret; +} + +int mtk_port_internal_write(void *i_port, struct sk_buff *skb) +{ + struct mtk_port *port =3D i_port; + + if (!port || !skb) { + if (skb) + dev_kfree_skb_any(skb); + pr_err_ratelimited("Internal write: invalid input\n"); + return -EINVAL; + } + return mtk_port_send_data(port, skb); +} + +void mtk_port_internal_recv_register(void *i_port, + int (*cb)(void *priv, struct sk_buff *skb), + void *arg) +{ + struct mtk_port *port =3D i_port; + struct mtk_internal_port *priv; + + priv =3D &port->i_priv; + priv->arg =3D arg; + priv->recv_cb =3D cb; +} + +int mtk_port_io_init(void) +{ + return 0; +} + +void mtk_port_io_exit(void) +{ +} + +static const struct port_ops port_internal_ops =3D { + .init =3D mtk_port_internal_init, + .exit =3D mtk_port_internal_exit, + .reset =3D mtk_port_reset, + .enable =3D mtk_port_internal_enable, + .disable =3D mtk_port_internal_disable, + .recv =3D mtk_port_internal_recv, +}; + +const struct port_ops *ports_ops[PORT_TYPE_MAX] =3D { + &port_internal_ops, +}; diff --git a/drivers/net/wwan/t9xx/mtk_port_io.h b/drivers/net/wwan/t9xx/mt= k_port_io.h new file mode 100644 index 000000000000..0c10e893b7e0 --- /dev/null +++ b/drivers/net/wwan/t9xx/mtk_port_io.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-only + * + * Copyright (c) 2022, MediaTek Inc. + */ + +#ifndef __MTK_PORT_IO_H__ +#define __MTK_PORT_IO_H__ + +#include + +#include "mtk_port.h" + +#define MTK_RX_BUF_SIZE (1024 * 1024) + +extern struct mutex port_mngr_grp_mtx; + +struct port_ops { + int (*init)(struct mtk_port *port); + void (*exit)(struct mtk_port *port); + void (*reset)(struct mtk_port *port); + void (*enable)(struct mtk_port *port); + void (*disable)(struct mtk_port *port); + int (*recv)(struct mtk_port *port, struct sk_buff *skb); +}; + +void *mtk_port_internal_open(struct mtk_md_dev *mdev, char *name, int flag= ); +int mtk_port_internal_close(void *i_port); +int mtk_port_internal_write(void *i_port, struct sk_buff *skb); +void mtk_port_internal_recv_register(void *i_port, + int (*cb)(void *priv, struct sk_buff *skb), + void *arg); + +int mtk_port_io_init(void); +void mtk_port_io_exit(void); + +#endif /* __MTK_PORT_IO_H__ */ diff --git a/drivers/net/wwan/t9xx/pcie/mtk_ctrl_cfg_m9xx.c b/drivers/net/w= wan/t9xx/pcie/mtk_ctrl_cfg_m9xx.c index c1bb787ee981..8611561dd67c 100644 --- a/drivers/net/wwan/t9xx/pcie/mtk_ctrl_cfg_m9xx.c +++ b/drivers/net/wwan/t9xx/pcie/mtk_ctrl_cfg_m9xx.c @@ -4,6 +4,7 @@ */ =20 #include "mtk_cldma.h" +#include "mtk_port.h" #include "mtk_trans_ctrl.h" =20 #define TRB_SRV_NUM (1) @@ -13,12 +14,34 @@ static const int mtk_srv_cfg_m9xx[NR_CLDMA][HW_QUE_NUM]= =3D { {0}, }; =20 +/* the number of RX GPDs should be at last two */ static const struct queue_info mtk_queue_info_m9xx[] =3D { + {CCCI_CONTROL_TX, CCCI_CONTROL_RX, CLDMA1, TXQ(0), RXQ(0), + Q_MTU_3_5K, Q_MTU_3_5K, TX_GPD_NUM, RX_GPD_NUM, Q_FRAG_3_5K, Q_FRAG_3_5K= , 0}, + {CCCI_SAP_CONTROL_TX, CCCI_SAP_CONTROL_RX, CLDMA0, TXQ(0), RXQ(0), + Q_MTU_3_5K, Q_MTU_3_5K, TX_GPD_NUM, RX_GPD_NUM, Q_FRAG_3_5K, Q_FRAG_3_5K= , 0}, +}; + +static const struct mtk_port_cfg port_cfg_m9xx[] =3D { + {CCCI_CONTROL_TX, CCCI_CONTROL_RX, PORT_TYPE_INTERNAL, "MDCTRL", + PORT_F_ALLOW_DROP}, + {CCCI_SAP_CONTROL_TX, CCCI_SAP_CONTROL_RX, PORT_TYPE_INTERNAL, "SAPCTRL", + PORT_F_ALLOW_DROP}, +}; + +static struct mtk_port_layer_cfg port_layer_cfg_m9xx =3D { + .port_cfg =3D (struct mtk_port_cfg *)port_cfg_m9xx, + .port_cnt =3D ARRAY_SIZE(port_cfg_m9xx), +}; + +static struct mtk_ctrl_cfg mtk_ctrl_cfg_m9xx =3D { + .port_layer_cfg =3D &port_layer_cfg_m9xx, }; =20 struct mtk_ctrl_info mtk_ctrl_info_m9xx =3D { + .ctrl_cfg =3D &mtk_ctrl_cfg_m9xx, + .srv_cfg =3D (int **)mtk_srv_cfg_m9xx, .queue_info =3D (struct queue_info *)mtk_queue_info_m9xx, .queue_info_num =3D ARRAY_SIZE(mtk_queue_info_m9xx), - .srv_cfg =3D (int **)mtk_srv_cfg_m9xx, .trb_srv_num =3D TRB_SRV_NUM, }; diff --git a/drivers/net/wwan/t9xx/pcie/mtk_pci.c b/drivers/net/wwan/t9xx/p= cie/mtk_pci.c index 9bcfc6e26f5f..0a0ebfede45c 100644 --- a/drivers/net/wwan/t9xx/pcie/mtk_pci.c +++ b/drivers/net/wwan/t9xx/pcie/mtk_pci.c @@ -17,6 +17,8 @@ #include "mtk_trans_ctrl.h" #include "mtk_pci.h" #include "mtk_pci_reg.h" +#include "mtk_port.h" +#include "mtk_port_io.h" =20 #define MTK_PCI_BAR_NUM 6 #define MTK_PCI_TRANSPARENT_ATR_SIZE (0x3F) diff --git a/drivers/net/wwan/t9xx/pcie/mtk_trans_ctrl.c b/drivers/net/wwan= /t9xx/pcie/mtk_trans_ctrl.c index 0588200ace76..899b04403b18 100644 --- a/drivers/net/wwan/t9xx/pcie/mtk_trans_ctrl.c +++ b/drivers/net/wwan/t9xx/pcie/mtk_trans_ctrl.c @@ -16,13 +16,14 @@ #include "mtk_ctrl_plane.h" #include "mtk_dev.h" #include "mtk_pci.h" +#include "mtk_port.h" #include "mtk_trans_ctrl.h" =20 #define MTK_DFLT_PORT_NAME_LEN (20) extern struct mtk_ctrl_info ctrl_info_name(m9xx); =20 static struct mtk_ctrl_info_desc mtk_ctrl_info_tbl[] =3D { - {2304, &ctrl_info_name(m9xx)}, + {0x01CA, &ctrl_info_name(m9xx)}, {0, NULL}, }; =20 @@ -134,6 +135,7 @@ static void mtk_ctrl_trb_handler(struct trb_srv *srv, s= truct trans_list *trans_l if (!skb) break; trb =3D (struct trb *)skb->cb; + kref_get(&trb->kref); =20 switch (trb->cmd) { case TRB_CMD_ENABLE: @@ -153,12 +155,10 @@ static void mtk_ctrl_trb_handler(struct trb_srv *srv,= struct trans_list *trans_l kick =3D true; break; } - if (err =3D=3D -EAGAIN) + if (err =3D=3D -EAGAIN) { + kref_put(&trb->kref, mtk_port_trb_free); return; - - skb_unlink(skb, skb_list); - trb->status =3D err; - trb->trb_complete(skb); + } break; } =20 @@ -185,6 +185,8 @@ static void mtk_ctrl_trb_handler(struct trb_srv *srv, s= truct trans_list *trans_l kick =3D false; } =20 + kref_put(&trb->kref, mtk_port_trb_free); + loop++; } while (loop < TRB_NUM_PER_ROUND); } @@ -522,6 +524,7 @@ static void mtk_trans_get_ctrl_info(struct mtk_ctrl_cfg= *cfg, continue; =20 ctrl_info =3D ctrl_info_desc->ctrl_info; + cfg->port_layer_cfg =3D ctrl_info->ctrl_cfg->port_layer_cfg; memcpy(trans->srv_cfg, ctrl_info->srv_cfg, sizeof(int) * NR_CLDMA * HW_QUE_NUM); trans->queue_info =3D ctrl_info->queue_info; @@ -534,6 +537,7 @@ int mtk_trans_ctrl_init(struct mtk_md_dev *mdev) { struct mtk_ctrl_trans *trans; struct mtk_ctrl_blk *ctrl_blk; + struct mtk_ctrl_cfg *cfg; int err; =20 trans =3D devm_kzalloc(mdev->dev, sizeof(*trans), GFP_KERNEL); @@ -542,15 +546,19 @@ int mtk_trans_ctrl_init(struct mtk_md_dev *mdev) trans->mdev =3D mdev; trans->queues_cnt =3D 0; =20 - mtk_trans_get_ctrl_info(NULL, trans, mdev->hw_ver); - if (!trans->queue_info || + cfg =3D devm_kzalloc(mdev->dev, sizeof(*cfg), GFP_KERNEL); + if (!cfg) + goto err_free_trans; + + mtk_trans_get_ctrl_info(cfg, trans, mdev->hw_ver); + if (!cfg->port_layer_cfg || !trans->queue_info || trans->trb_srv_num <=3D 0 || trans->trb_srv_num > TRB_SRV_MAX_NUM || trans->queue_info_num <=3D 0) { dev_err((mdev)->dev, "Failed to get ctrl info!\n"); goto err_free_cfg; } =20 - err =3D mtk_ctrl_init(mdev, &pcie_ctrl_ops); + err =3D mtk_ctrl_init(mdev, &pcie_ctrl_ops, cfg); if (err) goto err_free_cfg; =20 @@ -560,6 +568,8 @@ int mtk_trans_ctrl_init(struct mtk_md_dev *mdev) return 0; =20 err_free_cfg: + devm_kfree(mdev->dev, cfg); +err_free_trans: devm_kfree(mdev->dev, trans); return -ENOMEM; } diff --git a/drivers/net/wwan/t9xx/pcie/mtk_trans_ctrl.h b/drivers/net/wwan= /t9xx/pcie/mtk_trans_ctrl.h index c2df0bf6ed65..cca8e6f1532e 100644 --- a/drivers/net/wwan/t9xx/pcie/mtk_trans_ctrl.h +++ b/drivers/net/wwan/t9xx/pcie/mtk_trans_ctrl.h @@ -12,6 +12,7 @@ #include =20 #include "mtk_dev.h" +#include "mtk_port.h" =20 #define TRB_SRV_MAX_NUM (1) #define HW_QUE_NUM (8) --=20 2.34.1 From nobody Wed Jun 10 17:22:13 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 312E03FAE15; Wed, 10 Jun 2026 10:41:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781088102; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260610-t9xx_driver_v1-v2-5-c65addf23b3f@compal.com> References: <20260610-t9xx_driver_v1-v2-0-c65addf23b3f@compal.com> In-Reply-To: <20260610-t9xx_driver_v1-v2-0-c65addf23b3f@compal.com> To: Loic Poulain , Sergey Ryazanov , Johannes Berg , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Jack Wu , Wen-Zhi Huang , Shi-Wei Yeh , Minano Tseng , Matthias Brugger , AngeloGioacchino Del Regno , Simon Horman , Jonathan Corbet , Shuah Khan Cc: linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-doc@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1781088082; l=53496; i=jackbb_wu@compal.com; s=20260526; h=from:subject:message-id; bh=0jYHOYoY0RSVqD63eQnqKOUh7n9YlDx4TWu6ENS3BFw=; b=PyrBsTRfXsh5ldjqnT4NeFXpXF5OEaqPa6NmkJN+thlls8wdwdddwqASX1xO5LiPiLfSpLkUx EPhZeKA0bBlAwd0LRoPPL04JUvDQblwMXvqscFdeRpSssAug62zbMVK X-Developer-Key: i=jackbb_wu@compal.com; a=ed25519; pk=VH1prTWixNl8OEUPPSfII3p46MzJpQN8J3+ecE1tZXg= X-Endpoint-Received: by B4 Relay for jackbb_wu@compal.com/20260526 with auth_id=793 X-Original-From: Jack Wu Reply-To: jackbb_wu@compal.com From: Jack Wu The FSM (Finite-state Machine) thread is responsible for synchronizing the actions of different modules. The asynchronous events from the device or the OS will trigger a state transition. The FSM thread will append it to the event queue when an event arrives. It handles the events sequentially. After processing the event, the FSM thread notifies other modules before and after the state transition. Seven FSM states are defined. They can transition from one state to another, self-transition in some states, and transition in some sub-states. Signed-off-by: Jack Wu --- drivers/net/wwan/t9xx/Makefile | 3 +- drivers/net/wwan/t9xx/mtk_ctrl_plane.c | 46 ++ drivers/net/wwan/t9xx/mtk_ctrl_plane.h | 2 + drivers/net/wwan/t9xx/mtk_dev.h | 1 + drivers/net/wwan/t9xx/mtk_fsm.c | 948 ++++++++++++++++++++= ++++ drivers/net/wwan/t9xx/mtk_fsm.h | 140 ++++ drivers/net/wwan/t9xx/mtk_port.c | 65 ++ drivers/net/wwan/t9xx/mtk_port.h | 2 + drivers/net/wwan/t9xx/mtk_utility.h | 33 + drivers/net/wwan/t9xx/pcie/mtk_cldma.c | 213 +++++- drivers/net/wwan/t9xx/pcie/mtk_cldma.h | 3 + drivers/net/wwan/t9xx/pcie/mtk_cldma_drv.h | 3 - drivers/net/wwan/t9xx/pcie/mtk_cldma_drv_m9xx.c | 7 +- drivers/net/wwan/t9xx/pcie/mtk_cldma_drv_m9xx.h | 2 - drivers/net/wwan/t9xx/pcie/mtk_pci.c | 16 +- drivers/net/wwan/t9xx/pcie/mtk_trans_ctrl.c | 10 + drivers/net/wwan/t9xx/pcie/mtk_trans_ctrl.h | 1 - 17 files changed, 1479 insertions(+), 16 deletions(-) diff --git a/drivers/net/wwan/t9xx/Makefile b/drivers/net/wwan/t9xx/Makefile index db3b1aa1928b..75760b2039dc 100644 --- a/drivers/net/wwan/t9xx/Makefile +++ b/drivers/net/wwan/t9xx/Makefile @@ -10,4 +10,5 @@ mtk_t9xx-y :=3D \ mtk_dev.o \ mtk_ctrl_plane.o \ mtk_port.o \ - mtk_port_io.o + mtk_port_io.o \ + mtk_fsm.o diff --git a/drivers/net/wwan/t9xx/mtk_ctrl_plane.c b/drivers/net/wwan/t9xx= /mtk_ctrl_plane.c index b9a0443ce8ec..dc6a0670fe2b 100644 --- a/drivers/net/wwan/t9xx/mtk_ctrl_plane.c +++ b/drivers/net/wwan/t9xx/mtk_ctrl_plane.c @@ -5,10 +5,46 @@ */ =20 #include +#include +#include +#include +#include +#include +#include =20 #include "mtk_ctrl_plane.h" #include "mtk_port.h" =20 +#define TAG "CTRL" + +static void mtk_ctrl_trans_fsm_state_handler(struct mtk_fsm_param *param, + struct mtk_ctrl_blk *ctrl_blk) +{ + struct mtk_md_dev *mdev =3D ctrl_blk->mdev; + + switch (param->to) { + case FSM_STATE_OFF: + ctrl_blk->ops->fsm_indication(mdev, param); + ctrl_blk->ops->exit(mdev); + break; + case FSM_STATE_ON: + ctrl_blk->ops->init(mdev); + fallthrough; + default: + ctrl_blk->ops->fsm_indication(mdev, param); + break; + } +} + +static void mtk_ctrl_fsm_state_listener(struct mtk_fsm_param *param, void = *data) +{ + struct mtk_ctrl_blk *ctrl_blk =3D data; + + mtk_port_mngr_fsm_state_handler(param, ctrl_blk->port_mngr); + mtk_ctrl_trans_fsm_state_handler(param, ctrl_blk); + mtk_port_mngr_fsm_state_handler_late(param, ctrl_blk->port_mngr); +} + /** * mtk_ctrl_init() - Initialize the control plane block. * @mdev: Pointer to the MTK modem device. @@ -39,8 +75,17 @@ int mtk_ctrl_init(struct mtk_md_dev *mdev, struct mtk_ct= rl_hif_ops *ops, struct if (err) goto err_free_mem; =20 + err =3D mtk_fsm_notifier_register(mdev, MTK_USER_CTRL, mtk_ctrl_fsm_state= _listener, + ctrl_blk, FSM_PRIO_1, false); + if (err) { + dev_err((mdev)->dev, "Fail to register fsm notification(ret =3D %d)\n", = err); + goto err_port_exit; + } + return 0; =20 +err_port_exit: + mtk_port_mngr_exit(ctrl_blk); err_free_mem: devm_kfree(mdev->dev, ctrl_blk); =20 @@ -58,6 +103,7 @@ void mtk_ctrl_exit(struct mtk_md_dev *mdev) { struct mtk_ctrl_blk *ctrl_blk =3D mdev->ctrl_blk; =20 + mtk_fsm_notifier_unregister(mdev, MTK_USER_CTRL); mtk_port_mngr_exit(ctrl_blk); devm_kfree(mdev->dev, ctrl_blk); mdev->ctrl_blk =3D NULL; diff --git a/drivers/net/wwan/t9xx/mtk_ctrl_plane.h b/drivers/net/wwan/t9xx= /mtk_ctrl_plane.h index d7fcccde8a1b..92817e92a2e4 100644 --- a/drivers/net/wwan/t9xx/mtk_ctrl_plane.h +++ b/drivers/net/wwan/t9xx/mtk_ctrl_plane.h @@ -10,6 +10,7 @@ #include =20 #include "mtk_dev.h" +#include "mtk_fsm.h" =20 #define Q_MTU_2K (0x800) #define Q_MTU_3_5K (0xE00) @@ -62,6 +63,7 @@ struct mtk_ctrl_hif_ops { int (*init)(struct mtk_md_dev *mdev); int (*exit)(struct mtk_md_dev *mdev); int (*submit_skb)(struct mtk_md_dev *mdev, struct sk_buff *skb, bool forc= e_send); + void (*fsm_indication)(struct mtk_md_dev *mdev, struct mtk_fsm_param *par= am); int (*send_cmd)(struct mtk_md_dev *mdev, int cmd, void *data); }; =20 diff --git a/drivers/net/wwan/t9xx/mtk_dev.h b/drivers/net/wwan/t9xx/mtk_de= v.h index bb3ea68890ea..2388ada2c6a6 100644 --- a/drivers/net/wwan/t9xx/mtk_dev.h +++ b/drivers/net/wwan/t9xx/mtk_dev.h @@ -59,6 +59,7 @@ struct mtk_md_dev { u32 hw_ver; char dev_str[MTK_DEV_STR_LEN]; struct mtk_ctrl_blk *ctrl_blk; + struct mtk_md_fsm *fsm; }; =20 static inline u32 mtk_dev_get_dev_state(struct mtk_md_dev *mdev) diff --git a/drivers/net/wwan/t9xx/mtk_fsm.c b/drivers/net/wwan/t9xx/mtk_fs= m.c new file mode 100644 index 000000000000..a9943c63986c --- /dev/null +++ b/drivers/net/wwan/t9xx/mtk_fsm.c @@ -0,0 +1,948 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022, MediaTek Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "mtk_fsm.h" +#include "mtk_port.h" +#include "mtk_port_io.h" +#include "mtk_utility.h" + +#define EVT_TF_GATECLOSED (1) +#define MTK_FSM_INFO_LEN (64) + +#define FSM_HS_START_MASK (FSM_F_SAP_HS_START | FSM_F_MD_HS_START) +#define FSM_HS2_DONE_MASK (FSM_F_SAP_HS2_DONE | FSM_F_MD_HS2_DONE) + +#define RTFT_DATA_SIZE (3 * 1024) +#define EVT_HANDLER_TIMEOUT (HZ * 30) +#define BLOCKING_EVT_TIMEOUT (2 * EVT_HANDLER_TIMEOUT) + +#define REGION_BITMASK 0xF +#define DEVICE_CFG_SHIFT 24 +#define DEVICE_CFG_REGION_MASK 0x3 + +enum device_stage { + DEV_STAGE_IDLE =3D 4, + DEV_STAGE_MAX +}; + +enum device_cfg { + DEV_CFG_NORMAL =3D 0, + DEV_CFG_MD_ONLY, +}; + +enum runtime_feature_support_type { + RTFT_TYPE_NOT_EXIST =3D 0, + RTFT_TYPE_NOT_SUPPORT =3D 1, + RTFT_TYPE_MUST_SUPPORT =3D 2, + RTFT_TYPE_OPTIONAL_SUPPORT =3D 3, + RTFT_TYPE_SUPPORT_BACKWARD_COMPAT =3D 4, +}; + +enum query_runtime_feature_id { + QUERY_RTFT_ID_MD_PORT_ENUM =3D 0, + QUERY_RTFT_ID_SAP_PORT_ENUM =3D 1, + QUERY_RTFT_ID_MD_PORT_CFG =3D 2, + QUERY_RTFT_ID_MAX +}; + +enum ctrl_msg_id { + CTRL_MSG_HS1 =3D 0, + CTRL_MSG_HS2 =3D 1, + CTRL_MSG_HS3 =3D 2, +}; + +struct ctrl_msg_header { + __le32 id; + __le32 ex_msg; + __le32 data_len; + u8 reserved[]; +} __packed; + +struct runtime_feature_entry { + u8 feature_id; + struct runtime_feature_info support_info; + u8 reserved[2]; + __le32 data_len; + u8 data[]; +}; + +struct feature_query { + __le32 head_pattern; + struct runtime_feature_info ft_set[FEATURE_CNT]; + __le32 tail_pattern; +}; + +static int mtk_fsm_send_hs1_msg(struct fsm_hs_info *hs_info) +{ + struct ctrl_msg_header *ctrl_msg_h; + struct feature_query *ft_query; + struct sk_buff *skb; + int ret, msg_size; + + msg_size =3D sizeof(*ctrl_msg_h) + sizeof(*ft_query); + skb =3D __dev_alloc_skb(msg_size, GFP_KERNEL); + if (!skb) + return -ENOMEM; + + skb_put(skb, msg_size); + ctrl_msg_h =3D (struct ctrl_msg_header *)skb->data; + ctrl_msg_h->id =3D cpu_to_le32(CTRL_MSG_HS1); + ctrl_msg_h->ex_msg =3D 0; + ctrl_msg_h->data_len =3D cpu_to_le32(sizeof(*ft_query)); + + ft_query =3D (struct feature_query *)(skb->data + sizeof(*ctrl_msg_h)); + ft_query->head_pattern =3D cpu_to_le32(FEATURE_QUERY_PATTERN); + memcpy(ft_query->ft_set, hs_info->query_ft_set, sizeof(hs_info->query_ft_= set)); + ft_query->tail_pattern =3D cpu_to_le32(FEATURE_QUERY_PATTERN); + + /* send handshake1 message to device */ + ret =3D mtk_port_internal_write(hs_info->ctrl_port, skb); + if (ret <=3D 0) + return ret; + + return 0; +} + +static int mtk_fsm_feature_set_match(enum runtime_feature_support_type *cu= r_ft_spt, + struct runtime_feature_info rtft_info_st, + struct runtime_feature_info rtft_info_cfg) +{ + int ret =3D 0; + + switch (FIELD_GET(FEATURE_TYPE, rtft_info_st.feature)) { + case RTFT_TYPE_NOT_EXIST: + fallthrough; + case RTFT_TYPE_NOT_SUPPORT: + *cur_ft_spt =3D RTFT_TYPE_NOT_EXIST; + break; + case RTFT_TYPE_MUST_SUPPORT: + if (FIELD_GET(FEATURE_TYPE, rtft_info_cfg.feature) =3D=3D RTFT_TYPE_NOT_= EXIST || + FIELD_GET(FEATURE_TYPE, rtft_info_cfg.feature) =3D=3D RTFT_TYPE_NOT_= SUPPORT) + ret =3D -EPROTO; + else + *cur_ft_spt =3D RTFT_TYPE_MUST_SUPPORT; + break; + case RTFT_TYPE_OPTIONAL_SUPPORT: + if (FIELD_GET(FEATURE_TYPE, rtft_info_cfg.feature) =3D=3D RTFT_TYPE_NOT_= EXIST || + FIELD_GET(FEATURE_TYPE, rtft_info_cfg.feature) =3D=3D RTFT_TYPE_NOT_= SUPPORT) { + *cur_ft_spt =3D RTFT_TYPE_NOT_SUPPORT; + } else { + if (FIELD_GET(FEATURE_VER, rtft_info_st.feature) =3D=3D + FIELD_GET(FEATURE_VER, rtft_info_cfg.feature)) + *cur_ft_spt =3D RTFT_TYPE_MUST_SUPPORT; + else + *cur_ft_spt =3D RTFT_TYPE_NOT_SUPPORT; + } + break; + case RTFT_TYPE_SUPPORT_BACKWARD_COMPAT: + if (FIELD_GET(FEATURE_VER, rtft_info_st.feature) >=3D + FIELD_GET(FEATURE_VER, rtft_info_cfg.feature)) + *cur_ft_spt =3D RTFT_TYPE_MUST_SUPPORT; + else + *cur_ft_spt =3D RTFT_TYPE_NOT_EXIST; + break; + default: + ret =3D -EPROTO; + } + + return ret; +} + +static int (*query_rtft_action[FEATURE_CNT])(struct mtk_md_dev *mdev, void= *rt_data) =3D { + [QUERY_RTFT_ID_MD_PORT_ENUM] =3D mtk_port_status_update, + [QUERY_RTFT_ID_SAP_PORT_ENUM] =3D mtk_port_status_update, +}; + +static int mtk_fsm_parse_hs2_msg(struct fsm_hs_info *hs_info) +{ + struct mtk_md_fsm *fsm =3D container_of(hs_info, struct mtk_md_fsm, hs_in= fo[hs_info->id]); + char *rt_data =3D ((struct sk_buff *)hs_info->rt_data)->data; + enum runtime_feature_support_type cur_ft_spt; + struct runtime_feature_entry *rtft_entry; + unsigned int ft_id, offset, data_len; + int ret =3D 0; + + offset =3D sizeof(struct feature_query); + for (ft_id =3D 0; ft_id < FEATURE_CNT; ft_id++) { + if (offset + sizeof(*rtft_entry) > hs_info->rt_data_len) + break; + + rtft_entry =3D (struct runtime_feature_entry *)(rt_data + offset); + ret =3D mtk_fsm_feature_set_match(&cur_ft_spt, + rtft_entry->support_info, + hs_info->query_ft_set[ft_id]); + if (ret < 0) + break; + + if (cur_ft_spt =3D=3D RTFT_TYPE_MUST_SUPPORT) + if (query_rtft_action[ft_id]) + ret =3D query_rtft_action[ft_id](fsm->mdev, rtft_entry->data); + if (ret < 0) + break; + + data_len =3D le32_to_cpu(rtft_entry->data_len); + if (data_len > hs_info->rt_data_len - offset - sizeof(*rtft_entry)) + break; + + offset +=3D sizeof(*rtft_entry) + data_len; + } + + if (ft_id !=3D FEATURE_CNT) { + dev_err((fsm->mdev)->dev, "Unable to handle mistake hs2 msg, ft_id=3D%d\= n", ft_id); + ret =3D -EPROTO; + } + + return ret; +} + +static int mtk_fsm_append_rtft_entries(struct mtk_md_dev *mdev, void *feat= ure_data, + unsigned int *len, struct fsm_hs_info *hs_info) +{ + char *rt_data =3D ((struct sk_buff *)hs_info->rt_data)->data; + struct runtime_feature_entry *rtft_entry; + int ft_id, ret =3D 0, rtdata_len =3D 0; + struct feature_query *ft_query; + + ft_query =3D (struct feature_query *)rt_data; + if (le32_to_cpu(ft_query->head_pattern) !=3D FEATURE_QUERY_PATTERN || + le32_to_cpu(ft_query->tail_pattern) !=3D FEATURE_QUERY_PATTERN) { + ret =3D -EPROTO; + goto hs_err; + } + + /* parse runtime feature query and fill runtime feature entry */ + rtft_entry =3D feature_data; + for (ft_id =3D 0; ft_id < FEATURE_CNT && rtdata_len < RTFT_DATA_SIZE; ft_= id++) { + rtft_entry->feature_id =3D ft_id; + rtft_entry->data_len =3D 0; + + switch (FIELD_GET(FEATURE_TYPE, ft_query->ft_set[ft_id].feature)) { + case RTFT_TYPE_NOT_EXIST: + fallthrough; + case RTFT_TYPE_NOT_SUPPORT: + fallthrough; + case RTFT_TYPE_MUST_SUPPORT: + rtft_entry->support_info =3D ft_query->ft_set[ft_id]; + break; + case RTFT_TYPE_OPTIONAL_SUPPORT: + fallthrough; + case RTFT_TYPE_SUPPORT_BACKWARD_COMPAT: + rtft_entry->support_info.feature =3D FEATURE_TYPE_NOT; + rtft_entry->support_info.feature |=3D FEATURE_VER_0; + break; + } + + rtdata_len +=3D sizeof(*rtft_entry) + le32_to_cpu(rtft_entry->data_len); + rtft_entry =3D (struct runtime_feature_entry *)(feature_data + rtdata_le= n); + } + *len =3D rtdata_len; + return 0; + +hs_err: + *len =3D 0; + return ret; +} + +static int mtk_fsm_send_hs3_msg(struct fsm_hs_info *hs_info) +{ + struct mtk_md_fsm *fsm =3D container_of(hs_info, struct mtk_md_fsm, hs_in= fo[hs_info->id]); + unsigned int data_len, msg_size =3D 0; + struct ctrl_msg_header *ctrl_msg_h; + struct sk_buff *skb; + int ret; + + skb =3D __dev_alloc_skb(RTFT_DATA_SIZE, GFP_KERNEL); + if (!skb) + return -ENOMEM; + + msg_size +=3D sizeof(*ctrl_msg_h); + ctrl_msg_h =3D (struct ctrl_msg_header *)skb->data; + ctrl_msg_h->id =3D cpu_to_le32(CTRL_MSG_HS3); + ctrl_msg_h->ex_msg =3D 0; + ret =3D mtk_fsm_append_rtft_entries(fsm->mdev, + skb->data + sizeof(*ctrl_msg_h), + &data_len, hs_info); + if (ret) { + dev_kfree_skb(skb); + return ret; + } + + ctrl_msg_h->data_len =3D cpu_to_le32(data_len); + msg_size +=3D data_len; + skb_put(skb, msg_size); + ret =3D mtk_port_internal_write(hs_info->ctrl_port, skb); + if (ret <=3D 0) + return ret; + + return 0; +} + +static int mtk_fsm_sap_ctrl_msg_handler(void *__fsm, struct sk_buff *skb) +{ + struct ctrl_msg_header *ctrl_msg_h; + struct mtk_md_fsm *fsm =3D __fsm; + struct fsm_hs_info *hs_info; + int ret; + + if (skb->len < sizeof(*ctrl_msg_h)) { + dev_kfree_skb(skb); + return -EINVAL; + } + + ctrl_msg_h =3D (struct ctrl_msg_header *)skb->data; + skb_pull(skb, sizeof(*ctrl_msg_h)); + + hs_info =3D &fsm->hs_info[HS_ID_SAP]; + if (le32_to_cpu(ctrl_msg_h->id) !=3D CTRL_MSG_HS2) { + dev_kfree_skb(skb); + return -EPROTO; + } + + hs_info->rt_data =3D skb; + hs_info->rt_data_len =3D skb->len; + ret =3D mtk_fsm_evt_submit(fsm->mdev, FSM_EVT_STARTUP, + hs_info->fsm_flag_hs2, hs_info, sizeof(*hs_info), 0); + if (ret =3D=3D FSM_EVT_RET_FAIL) + dev_kfree_skb(skb); + + return 0; +} + +static int mtk_fsm_md_ctrl_msg_handler(void *__fsm, struct sk_buff *skb) +{ + struct ctrl_msg_header *ctrl_msg_h; + struct mtk_md_fsm *fsm =3D __fsm; + struct fsm_hs_info *hs_info; + bool consumed_skb =3D false; + int ret; + + if (skb->len < sizeof(*ctrl_msg_h)) { + dev_kfree_skb(skb); + return -EINVAL; + } + + ctrl_msg_h =3D (struct ctrl_msg_header *)skb->data; + hs_info =3D &fsm->hs_info[HS_ID_MD]; + switch (le32_to_cpu(ctrl_msg_h->id)) { + case CTRL_MSG_HS2: + skb_pull(skb, sizeof(*ctrl_msg_h)); + hs_info->rt_data =3D skb; + hs_info->rt_data_len =3D skb->len; + ret =3D mtk_fsm_evt_submit(fsm->mdev, FSM_EVT_STARTUP, + hs_info->fsm_flag_hs2, hs_info, sizeof(*hs_info), 0); + if (ret !=3D FSM_EVT_RET_FAIL) + consumed_skb =3D true; + break; + default: + dev_err(fsm->mdev->dev, "Invalid ctrl msg id\n"); + } + + if (!consumed_skb) + dev_kfree_skb(skb); + + return 0; +} + +static int (*ctrl_msg_handler[HS_ID_MAX])(void *__fsm, struct sk_buff *skb= ) =3D { + [HS_ID_MD] =3D mtk_fsm_md_ctrl_msg_handler, + [HS_ID_SAP] =3D mtk_fsm_sap_ctrl_msg_handler, +}; + +static void mtk_fsm_idle_evt_handler(struct mtk_md_dev *mdev, + u32 dev_state, struct mtk_md_fsm *fsm) +{ + u32 dev_cfg =3D dev_state >> DEVICE_CFG_SHIFT & DEVICE_CFG_REGION_MASK; + int hs_id; + + if (dev_cfg =3D=3D DEV_CFG_MD_ONLY) + fsm->hs_done_flag =3D FSM_F_MD_HS_START | FSM_F_MD_HS2_DONE; + else + fsm->hs_done_flag =3D FSM_HS_START_MASK | FSM_HS2_DONE_MASK; + + mtk_fsm_evt_submit(mdev, FSM_EVT_STARTUP, FSM_F_DFLT, NULL, 0, 0); + + for (hs_id =3D 0; hs_id < HS_ID_MAX; hs_id++) + mtk_dev_unmask_dev_evt(mdev, fsm->hs_info[hs_id].mhccif_ch); +} + +static int mtk_fsm_early_bootup_handler(u32 status, void *__fsm) +{ + struct mtk_md_fsm *fsm =3D __fsm; + struct mtk_md_dev *mdev; + u32 dev_state, dev_stage; + + mdev =3D fsm->mdev; + mtk_dev_mask_dev_evt(mdev, status); + mtk_dev_clear_dev_evt(mdev, status); + + dev_state =3D mtk_dev_get_dev_state(mdev); + dev_stage =3D dev_state & REGION_BITMASK; + if (dev_stage >=3D DEV_STAGE_MAX) { + dev_err(mdev->dev, "Invalid dev state 0x%x\n", dev_state); + return -ENXIO; + } + + if (dev_state =3D=3D fsm->last_dev_state) + goto exit; + fsm->last_dev_state =3D dev_state; + + if (dev_stage =3D=3D DEV_STAGE_IDLE) + mtk_fsm_idle_evt_handler(mdev, dev_state, fsm); + +exit: + return 0; +} + +static int mtk_fsm_ctrl_ch_start(struct mtk_md_fsm *fsm, struct fsm_hs_inf= o *hs_info, int flag) +{ + if (!hs_info->ctrl_port) { + hs_info->ctrl_port =3D mtk_port_internal_open(fsm->mdev, hs_info->port_n= ame, flag); + if (!hs_info->ctrl_port) { + dev_err(fsm->mdev->dev, "Failed to open ctrl port(%s)\n", + hs_info->port_name); + return -ENODEV; + } + + mtk_port_internal_recv_register(hs_info->ctrl_port, + ctrl_msg_handler[hs_info->id], fsm); + } + + return 0; +} + +static void mtk_fsm_ctrl_ch_stop(struct mtk_md_fsm *fsm) +{ + struct fsm_hs_info *hs_info; + int hs_id; + + for (hs_id =3D 0; hs_id < HS_ID_MAX; hs_id++) { + hs_info =3D &fsm->hs_info[hs_id]; + if (hs_info->ctrl_port) { + mtk_port_internal_close(hs_info->ctrl_port); + hs_info->ctrl_port =3D NULL; + } + } +} + +static void mtk_fsm_switch_state(struct mtk_md_fsm *fsm, + enum mtk_fsm_state to_state, struct mtk_fsm_evt *event) +{ + char fsm_info[MTK_FSM_INFO_LEN]; + struct mtk_fsm_notifier *nt; + struct mtk_fsm_param param; + + param.from =3D fsm->state; + param.to =3D to_state; + param.evt_id =3D event ? event->id : FSM_EVT_MAX; + param.fsm_flag =3D event ? event->fsm_flag : FSM_F_DFLT; + + list_for_each_entry(nt, &fsm->pre_notifiers, entry) + nt->cb(¶m, nt->data); + + fsm->state =3D to_state; + fsm->fsm_flag |=3D event ? event->fsm_flag : FSM_F_DFLT; + + snprintf(fsm_info, MTK_FSM_INFO_LEN, + "state=3D%d, fsm_flag=3D0x%x", to_state, fsm->fsm_flag); + mtk_uevent_notify(fsm->mdev->dev, MTK_UEVENT_FSM, fsm_info); + + list_for_each_entry(nt, &fsm->post_notifiers, entry) + nt->cb(¶m, nt->data); +} + +static int mtk_fsm_startup_act(struct mtk_md_fsm *fsm, struct mtk_fsm_evt = *event) +{ + enum mtk_fsm_state to_state =3D FSM_STATE_BOOTUP; + struct fsm_hs_info *hs_info =3D event->data; + struct mtk_md_dev *mdev =3D fsm->mdev; + int ret =3D 0; + + if (fsm->state !=3D FSM_STATE_ON && fsm->state !=3D FSM_STATE_BOOTUP) { + ret =3D -EPROTO; + goto free_rt_data; + } + + if (fsm->state !=3D FSM_STATE_BOOTUP) { + mtk_fsm_switch_state(fsm, to_state, event); + return 0; + } + + if (event->fsm_flag & FSM_HS_START_MASK) { + mtk_fsm_switch_state(fsm, to_state, event); + + ret =3D mtk_fsm_ctrl_ch_start(fsm, hs_info, O_NONBLOCK); + if (!ret) + ret =3D mtk_fsm_send_hs1_msg(hs_info); + if (ret) + goto hs_err; + } else if (event->fsm_flag & FSM_HS2_DONE_MASK) { + ret =3D mtk_fsm_parse_hs2_msg(hs_info); + if (!ret) { + mtk_fsm_switch_state(fsm, to_state, event); + ret =3D mtk_fsm_send_hs3_msg(hs_info); + } + dev_kfree_skb(hs_info->rt_data); + hs_info->rt_data =3D NULL; + if (ret) + goto hs_err; + } + + if (((fsm->fsm_flag | event->fsm_flag) & fsm->hs_done_flag) =3D=3D fsm->h= s_done_flag) { + to_state =3D FSM_STATE_READY; + mtk_fsm_switch_state(fsm, to_state, NULL); + } + + return 0; + +free_rt_data: + if (hs_info && hs_info->rt_data) { + dev_kfree_skb(hs_info->rt_data); + hs_info->rt_data =3D NULL; + } +hs_err: + dev_err((mdev)->dev, "Failed to hs with device %d:0x%x, ret=3D%d", + fsm->state, fsm->fsm_flag, ret); + return ret; +} + +static void mtk_fsm_evt_release(struct kref *kref) +{ + struct mtk_fsm_evt *event =3D container_of(kref, struct mtk_fsm_evt, kref= ); + + kfree(event); +} + +static void mtk_fsm_evt_put(struct mtk_fsm_evt *event) +{ + kref_put(&event->kref, mtk_fsm_evt_release); +} + +static void mtk_fsm_evt_finish(struct mtk_md_fsm *fsm, + struct mtk_fsm_evt *event, int retval) +{ + if (event->mode & EVT_MODE_BLOCKING) { + event->status =3D retval; + wake_up(&fsm->evt_waitq); + } + mtk_fsm_evt_put(event); +} + +static void mtk_fsm_evt_cleanup(struct mtk_md_fsm *fsm, struct list_head *= evtq) +{ + struct mtk_fsm_evt *event, *tmp; + + list_for_each_entry_safe(event, tmp, evtq, entry) { + list_del(&event->entry); + mtk_fsm_evt_finish(fsm, event, FSM_EVT_RET_FAIL); + } +} + +static int mtk_fsm_enter_off_state(struct mtk_md_fsm *fsm, struct mtk_fsm_= evt *event) +{ + struct mtk_md_dev *mdev =3D fsm->mdev; + int hs_id; + + if (fsm->state =3D=3D FSM_STATE_OFF || fsm->state =3D=3D FSM_STATE_INVALI= D) + return -EPROTO; + + mtk_dev_mask_dev_evt(mdev, DEV_EVT_D2H_BOOT_FLOW_SYNC); + for (hs_id =3D 0; hs_id < HS_ID_MAX; hs_id++) + mtk_dev_mask_dev_evt(mdev, fsm->hs_info[hs_id].mhccif_ch); + + mtk_fsm_ctrl_ch_stop(fsm); + mtk_fsm_switch_state(fsm, FSM_STATE_OFF, event); + + return 0; +} + +static int mtk_fsm_dev_rm_act(struct mtk_md_fsm *fsm, struct mtk_fsm_evt *= event) +{ + unsigned long flags; + + spin_lock_irqsave(&fsm->evtq_lock, flags); + set_bit(EVT_TF_GATECLOSED, &fsm->t_flag); + mtk_fsm_evt_cleanup(fsm, &fsm->evtq); + spin_unlock_irqrestore(&fsm->evtq_lock, flags); + + return mtk_fsm_enter_off_state(fsm, event); +} + +static int mtk_fsm_hs1_handler(u32 status, void *__hs_info) +{ + struct fsm_hs_info *hs_info =3D __hs_info; + struct mtk_md_dev *mdev; + struct mtk_md_fsm *fsm; + + fsm =3D container_of(hs_info, struct mtk_md_fsm, hs_info[hs_info->id]); + mdev =3D fsm->mdev; + mtk_fsm_evt_submit(mdev, FSM_EVT_STARTUP, + hs_info->fsm_flag_hs1, hs_info, sizeof(*hs_info), 0); + mtk_dev_mask_dev_evt(mdev, hs_info->mhccif_ch); + mtk_dev_clear_dev_evt(mdev, hs_info->mhccif_ch); + + return 0; +} + +static void mtk_fsm_hs_info_init_by_hsid(struct mtk_md_fsm *fsm, int hs_id) +{ + struct fsm_hs_info *hs_info; + + if (hs_id < 0 || hs_id >=3D HS_ID_MAX) { + dev_warn((fsm->mdev)->dev, "hs_id =3D %d, invalid.\n", hs_id); + return; + } + + hs_info =3D &fsm->hs_info[hs_id]; + hs_info->id =3D hs_id; + hs_info->ctrl_port =3D NULL; + hs_info->rt_data =3D NULL; + switch (hs_id) { + case HS_ID_MD: + snprintf(hs_info->port_name, PORT_NAME_LEN, "MDCTRL"); + hs_info->mhccif_ch =3D DEV_EVT_D2H_ASYNC_HS_NOTIFY_MD; + hs_info->fsm_flag_hs1 =3D FSM_F_MD_HS_START; + hs_info->fsm_flag_hs2 =3D FSM_F_MD_HS2_DONE; + hs_info->query_ft_set[QUERY_RTFT_ID_MD_PORT_ENUM].feature =3D + FIELD_PREP(FEATURE_TYPE, RTFT_TYPE_MUST_SUPPORT); + hs_info->query_ft_set[QUERY_RTFT_ID_MD_PORT_ENUM].feature |=3D + FIELD_PREP(FEATURE_VER, 0); + hs_info->query_ft_set[QUERY_RTFT_ID_MD_PORT_CFG].feature =3D + FIELD_PREP(FEATURE_TYPE, RTFT_TYPE_NOT_SUPPORT); + break; + case HS_ID_SAP: + snprintf(hs_info->port_name, PORT_NAME_LEN, "SAPCTRL"); + hs_info->mhccif_ch =3D DEV_EVT_D2H_ASYNC_HS_NOTIFY_SAP; + hs_info->fsm_flag_hs1 =3D FSM_F_SAP_HS_START; + hs_info->fsm_flag_hs2 =3D FSM_F_SAP_HS2_DONE; + hs_info->query_ft_set[QUERY_RTFT_ID_SAP_PORT_ENUM].feature =3D + FIELD_PREP(FEATURE_TYPE, RTFT_TYPE_MUST_SUPPORT); + hs_info->query_ft_set[QUERY_RTFT_ID_SAP_PORT_ENUM].feature |=3D + FIELD_PREP(FEATURE_VER, 0); + break; + } +} + +static void mtk_fsm_hs_info_init(struct mtk_md_fsm *fsm) +{ + struct mtk_md_dev *mdev =3D fsm->mdev; + struct fsm_hs_info *hs_info; + int hs_id; + + for (hs_id =3D 0; hs_id < HS_ID_MAX; hs_id++) { + mtk_fsm_hs_info_init_by_hsid(fsm, hs_id); + hs_info =3D &fsm->hs_info[hs_id]; + mtk_dev_register_dev_evt(mdev, hs_info->mhccif_ch, + mtk_fsm_hs1_handler, hs_info); + } +} + +static void mtk_fsm_hs_info_exit(struct mtk_md_fsm *fsm) +{ + struct mtk_md_dev *mdev =3D fsm->mdev; + struct fsm_hs_info *hs_info; + int hs_id; + + for (hs_id =3D 0; hs_id < HS_ID_MAX; hs_id++) { + hs_info =3D &fsm->hs_info[hs_id]; + mtk_dev_unregister_dev_evt(mdev, hs_info->mhccif_ch); + } +} + +static int mtk_fsm_dev_add_act(struct mtk_md_fsm *fsm, struct mtk_fsm_evt = *event) +{ + if (fsm->state !=3D FSM_STATE_OFF && fsm->state !=3D FSM_STATE_INVALID) + return -EPROTO; + + mtk_fsm_switch_state(fsm, FSM_STATE_ON, event); + mtk_dev_unmask_dev_evt(fsm->mdev, DEV_EVT_D2H_BOOT_FLOW_SYNC); + + return 0; +} + +static int (*evts_act_tbl[FSM_EVT_MAX])(struct mtk_md_fsm *__fsm, struct m= tk_fsm_evt *event) =3D { + [FSM_EVT_STARTUP] =3D mtk_fsm_startup_act, + [FSM_EVT_DEV_RM] =3D mtk_fsm_dev_rm_act, + [FSM_EVT_DEV_ADD] =3D mtk_fsm_dev_add_act, +}; + +int mtk_fsm_start(struct mtk_md_dev *mdev) +{ + struct mtk_md_fsm *fsm =3D mdev->fsm; + + if (!fsm) + return -EINVAL; + + if (!fsm->fsm_handler) + return -EFAULT; + + wake_up_process(fsm->fsm_handler); + return 0; +} +EXPORT_SYMBOL(mtk_fsm_start); + +static void mkt_fsm_notifier_cleanup(struct mtk_md_dev *mdev, struct list_= head *ntq) +{ + struct mtk_fsm_notifier *nt, *tmp; + + list_for_each_entry_safe(nt, tmp, ntq, entry) { + list_del(&nt->entry); + dev_warn((mdev)->dev, "Having to free notifier(%d) by FSM!\n", nt->id); + devm_kfree(mdev->dev, nt); + } +} + +static void mtk_fsm_notifier_insert(struct mtk_fsm_notifier *notifier, str= uct list_head *head) +{ + struct mtk_fsm_notifier *nt; + + list_for_each_entry(nt, head, entry) { + if (notifier->prio > nt->prio) { + list_add(¬ifier->entry, nt->entry.prev); + return; + } + } + list_add_tail(¬ifier->entry, head); +} + +int mtk_fsm_notifier_register(struct mtk_md_dev *mdev, enum mtk_user_id id, + void (*cb)(struct mtk_fsm_param *, void *data), + void *data, enum mtk_fsm_prio prio, bool is_pre) +{ + struct mtk_md_fsm *fsm =3D mdev->fsm; + struct mtk_fsm_notifier *notifier; + + if (!fsm) + return -EINVAL; + + if (id >=3D MTK_USER_MAX || !cb || prio >=3D FSM_PRIO_MAX) + return -EINVAL; + + notifier =3D devm_kzalloc(mdev->dev, sizeof(*notifier), GFP_KERNEL); + if (!notifier) + return -ENOMEM; + + INIT_LIST_HEAD(¬ifier->entry); + notifier->id =3D id; + notifier->cb =3D cb; + notifier->data =3D data; + notifier->prio =3D prio; + + if (is_pre) + mtk_fsm_notifier_insert(notifier, &fsm->pre_notifiers); + else + mtk_fsm_notifier_insert(notifier, &fsm->post_notifiers); + + return 0; +} +EXPORT_SYMBOL(mtk_fsm_notifier_register); + +int mtk_fsm_notifier_unregister(struct mtk_md_dev *mdev, enum mtk_user_id = id) +{ + struct mtk_md_fsm *fsm =3D mdev->fsm; + struct mtk_fsm_notifier *nt, *tmp; + + if (!fsm) + return -EINVAL; + + list_for_each_entry_safe(nt, tmp, &fsm->pre_notifiers, entry) { + if (nt->id =3D=3D id) { + list_del(&nt->entry); + devm_kfree(mdev->dev, nt); + break; + } + } + list_for_each_entry_safe(nt, tmp, &fsm->post_notifiers, entry) { + if (nt->id =3D=3D id) { + list_del(&nt->entry); + devm_kfree(mdev->dev, nt); + break; + } + } + return 0; +} +EXPORT_SYMBOL(mtk_fsm_notifier_unregister); + +int mtk_fsm_evt_submit(struct mtk_md_dev *mdev, + enum mtk_fsm_evt_id id, enum mtk_fsm_flag flag, + void *data, unsigned int len, unsigned char mode) +{ + struct mtk_md_fsm *fsm =3D mdev->fsm; + struct mtk_fsm_evt *event; + unsigned long flags; + int ret =3D 0; + + if (!fsm || id >=3D FSM_EVT_MAX) { + dev_err((mdev)->dev, "Invalid param!\n"); + return FSM_EVT_RET_FAIL; + } + + if (test_bit(EVT_TF_GATECLOSED, &fsm->t_flag)) { + dev_err((mdev)->dev, "Failed to submit evt, fsm has been removed!\n"); + return FSM_EVT_RET_FAIL; + } + + event =3D kzalloc(sizeof(*event), + (in_hardirq() || in_softirq() || irqs_disabled()) ? + GFP_ATOMIC : GFP_KERNEL); + if (!event) + return FSM_EVT_RET_FAIL; + + kref_init(&event->kref); + event->mdev =3D mdev; + event->id =3D id; + event->fsm_flag =3D flag; + event->status =3D FSM_EVT_RET_ONGOING; + event->data =3D data; + event->len =3D len; + event->mode =3D mode; + + spin_lock_irqsave(&fsm->evtq_lock, flags); + if (test_bit(EVT_TF_GATECLOSED, &fsm->t_flag)) { + spin_unlock_irqrestore(&fsm->evtq_lock, flags); + mtk_fsm_evt_put(event); + dev_err(mdev->dev, "Failed to add event, fsm dev has been removed!\n"); + return FSM_EVT_RET_FAIL; + } + + kref_get(&event->kref); + if (mode & EVT_MODE_TOHEAD) + list_add(&event->entry, &fsm->evtq); + else + list_add_tail(&event->entry, &fsm->evtq); + spin_unlock_irqrestore(&fsm->evtq_lock, flags); + + wake_up_process(fsm->fsm_handler); + if (mode & EVT_MODE_BLOCKING) { + ret =3D wait_event_timeout(fsm->evt_waitq, + (event->status !=3D 0), BLOCKING_EVT_TIMEOUT); + if (!ret && event->status !=3D FSM_EVT_RET_DONE) { + dev_err((mdev)->dev, "Handling fsm blocking event timeout!\n"); + ret =3D -ETIMEDOUT; + } else { + ret =3D event->status; + } + } + mtk_fsm_evt_put(event); + + return ret; +} +EXPORT_SYMBOL(mtk_fsm_evt_submit); + +static int mtk_fsm_evt_handler(void *__fsm) +{ + struct mtk_md_fsm *fsm =3D __fsm; + struct mtk_fsm_evt *event; + unsigned long flags; + int ret; + +wake_up: + set_current_state(TASK_UNINTERRUPTIBLE); + while (!kthread_should_stop() && !list_empty(&fsm->evtq)) { + set_current_state(TASK_RUNNING); + spin_lock_irqsave(&fsm->evtq_lock, flags); + event =3D list_first_entry(&fsm->evtq, struct mtk_fsm_evt, entry); + list_del(&event->entry); + spin_unlock_irqrestore(&fsm->evtq_lock, flags); + + if (event->id < FSM_EVT_MAX) { + ret =3D evts_act_tbl[event->id](fsm, event); + if (ret) { + dev_err((fsm->mdev)->dev, + "Failed to handle evt, fsm state =3D %d, ret =3D %d\n", + fsm->state, ret); + mtk_fsm_evt_finish(fsm, event, FSM_EVT_RET_FAIL); + } else { + mtk_fsm_evt_finish(fsm, event, FSM_EVT_RET_DONE); + } + } else { + mtk_fsm_evt_finish(fsm, event, FSM_EVT_RET_DONE); + } + } + + if (kthread_should_stop()) { + set_current_state(TASK_RUNNING); + return 0; + } + + schedule(); + goto wake_up; +} + +int mtk_fsm_init(struct mtk_md_dev *mdev) +{ + struct mtk_md_fsm *fsm; + int ret; + + fsm =3D devm_kzalloc(mdev->dev, sizeof(*fsm), GFP_KERNEL); + if (!fsm) + return -ENOMEM; + + fsm->fsm_handler =3D kthread_create(mtk_fsm_evt_handler, fsm, "fsm_evt_th= read%d_%s", + mdev->hw_ver, mdev->dev_str); + if (IS_ERR(fsm->fsm_handler)) { + ret =3D PTR_ERR(fsm->fsm_handler); + goto exit; + } + + fsm->mdev =3D mdev; + fsm->state =3D FSM_STATE_INVALID; + fsm->fsm_flag =3D FSM_F_DFLT; + + INIT_LIST_HEAD(&fsm->evtq); + spin_lock_init(&fsm->evtq_lock); + init_waitqueue_head(&fsm->evt_waitq); + + INIT_LIST_HEAD(&fsm->pre_notifiers); + INIT_LIST_HEAD(&fsm->post_notifiers); + + mtk_fsm_hs_info_init(fsm); + mtk_dev_register_dev_evt(mdev, DEV_EVT_D2H_BOOT_FLOW_SYNC, + mtk_fsm_early_bootup_handler, fsm); + mdev->fsm =3D fsm; + return 0; +exit: + devm_kfree(mdev->dev, fsm); + return ret; +} +EXPORT_SYMBOL(mtk_fsm_init); + +int mtk_fsm_exit(struct mtk_md_dev *mdev) +{ + struct mtk_md_fsm *fsm =3D mdev->fsm; + unsigned long flags; + + if (!fsm) + return -EINVAL; + + if (fsm->fsm_handler) { + kthread_stop(fsm->fsm_handler); + fsm->fsm_handler =3D NULL; + } + + spin_lock_irqsave(&fsm->evtq_lock, flags); + if (WARN_ON(!list_empty(&fsm->evtq))) + mtk_fsm_evt_cleanup(fsm, &fsm->evtq); + spin_unlock_irqrestore(&fsm->evtq_lock, flags); + + mkt_fsm_notifier_cleanup(mdev, &fsm->pre_notifiers); + mkt_fsm_notifier_cleanup(mdev, &fsm->post_notifiers); + + mtk_dev_unregister_dev_evt(mdev, DEV_EVT_D2H_BOOT_FLOW_SYNC); + mtk_fsm_hs_info_exit(fsm); + + devm_kfree(mdev->dev, fsm); + return 0; +} +EXPORT_SYMBOL(mtk_fsm_exit); diff --git a/drivers/net/wwan/t9xx/mtk_fsm.h b/drivers/net/wwan/t9xx/mtk_fs= m.h new file mode 100644 index 000000000000..f2fc66bcef61 --- /dev/null +++ b/drivers/net/wwan/t9xx/mtk_fsm.h @@ -0,0 +1,140 @@ +/* SPDX-License-Identifier: GPL-2.0-only + * + * Copyright (c) 2022, MediaTek Inc. + */ + +#ifndef __MTK_FSM_H__ +#define __MTK_FSM_H__ + +#include "mtk_dev.h" + +#define FEATURE_CNT (64) +#define FEATURE_QUERY_PATTERN (0x49434343) + +#define FEATURE_TYPE GENMASK(3, 0) +#define FEATURE_VER GENMASK(7, 4) + +#define FEATURE_TYPE_NOT FIELD_PREP(FEATURE_TYPE, RTFT_TYPE_NOT_SUPPORT) +#define FEATURE_TYPE_MUST FIELD_PREP(FEATURE_TYPE, RTFT_TYPE_MUST_SUPPORT) +#define FEATURE_TYPE_OPTIONAL FIELD_PREP(FEATURE_TYPE, RTFT_TYPE_OPTIONAL_= SUPPORT) +#define FEATURE_VER_0 FIELD_PREP(FEATURE_VER, 0) + +#define EVT_MODE_BLOCKING (0x01) +#define EVT_MODE_TOHEAD (0x02) + +#define FSM_EVT_RET_FAIL (-1) +#define FSM_EVT_RET_ONGOING (0) +#define FSM_EVT_RET_DONE (1) + +enum mtk_fsm_flag { + FSM_F_DFLT =3D 0, + FSM_F_SAP_HS_START =3D BIT(0), + FSM_F_SAP_HS2_DONE =3D BIT(1), + FSM_F_MD_HS_START =3D BIT(2), + FSM_F_MD_HS2_DONE =3D BIT(3), +}; + +enum mtk_fsm_state { + FSM_STATE_INVALID =3D 0, + FSM_STATE_OFF, + FSM_STATE_ON, + FSM_STATE_BOOTUP, + FSM_STATE_READY, +}; + +enum mtk_fsm_evt_id { + FSM_EVT_STARTUP =3D 0, + FSM_EVT_DEV_RM, + FSM_EVT_DEV_ADD, + FSM_EVT_MAX +}; + +enum mtk_fsm_prio { + FSM_PRIO_0 =3D 0, + FSM_PRIO_1 =3D 1, + FSM_PRIO_MAX +}; + +struct mtk_fsm_param { + enum mtk_fsm_state from; + enum mtk_fsm_state to; + enum mtk_fsm_evt_id evt_id; + enum mtk_fsm_flag fsm_flag; +}; + +#define PORT_NAME_LEN 20 + +enum handshake_info_id { + HS_ID_MD =3D 0, + HS_ID_SAP, + HS_ID_MAX +}; + +struct runtime_feature_info { + u8 feature; +}; + +struct fsm_hs_info { + unsigned char id; + void *ctrl_port; + char port_name[PORT_NAME_LEN]; + unsigned int mhccif_ch; + unsigned int fsm_flag_hs1; + unsigned int fsm_flag_hs2; + /* the feature that the device should support */ + struct runtime_feature_info query_ft_set[FEATURE_CNT]; + /* runtime data from device need to be parsed by host */ + void *rt_data; + unsigned int rt_data_len; +}; + +struct mtk_md_fsm { + struct mtk_md_dev *mdev; + struct task_struct *fsm_handler; + struct fsm_hs_info hs_info[HS_ID_MAX]; + unsigned int hs_done_flag; + unsigned long t_flag; + u32 last_dev_state; + enum mtk_fsm_state state; + unsigned int fsm_flag; + struct list_head evtq; + /* protect evtq */ + spinlock_t evtq_lock; + /* waitq for fsm blocking submit */ + wait_queue_head_t evt_waitq; + struct list_head pre_notifiers; + struct list_head post_notifiers; +}; + +struct mtk_fsm_evt { + struct list_head entry; + struct kref kref; + struct mtk_md_dev *mdev; + enum mtk_fsm_evt_id id; + unsigned int fsm_flag; + int status; + unsigned char mode; + unsigned int len; + void *data; +}; + +struct mtk_fsm_notifier { + struct list_head entry; + enum mtk_user_id id; + void (*cb)(struct mtk_fsm_param *param, void *data); + void *data; + enum mtk_fsm_prio prio; +}; + +int mtk_fsm_init(struct mtk_md_dev *mdev); +int mtk_fsm_exit(struct mtk_md_dev *mdev); +int mtk_fsm_start(struct mtk_md_dev *mdev); +int mtk_fsm_notifier_register(struct mtk_md_dev *mdev, enum mtk_user_id id, + void (*cb)(struct mtk_fsm_param *, void *data), + void *data, enum mtk_fsm_prio prio, bool is_pre); +int mtk_fsm_notifier_unregister(struct mtk_md_dev *mdev, enum mtk_user_id = id); +int mtk_fsm_evt_submit(struct mtk_md_dev *mdev, + enum mtk_fsm_evt_id id, enum mtk_fsm_flag flag, + void *data, unsigned int len, unsigned char mode); + +#endif /* __MTK_FSM_H__ */ diff --git a/drivers/net/wwan/t9xx/mtk_port.c b/drivers/net/wwan/t9xx/mtk_p= ort.c index c70a73a8d9de..c68437e58ea2 100644 --- a/drivers/net/wwan/t9xx/mtk_port.c +++ b/drivers/net/wwan/t9xx/mtk_port.c @@ -819,6 +819,71 @@ int mtk_port_ch_disable(struct mtk_port *port) return ret; } =20 +static void mtk_port_disable(struct mtk_port_mngr *port_mngr) +{ + struct mtk_port **ports; + int tbl_type; + int ret, idx; + + ports =3D kcalloc(port_mngr->port_cnt, sizeof(struct mtk_port *), GFP_KER= NEL); + if (!ports) + return; + + tbl_type =3D PORT_TBL_SAP; + do { + ret =3D radix_tree_gang_lookup(&port_mngr->port_tbl[tbl_type], + (void **)ports, 0, port_mngr->port_cnt); + for (idx =3D 0; idx < ret; idx++) + ports_ops[ports[idx]->info.type]->disable(ports[idx]); + } while (++tbl_type < PORT_TBL_MAX); + kfree(ports); +} + +void mtk_port_mngr_fsm_state_handler(struct mtk_fsm_param *fsm_param, void= *arg) +{ + struct mtk_port_mngr *port_mngr; + + if (!fsm_param || !arg) + return; + + port_mngr =3D arg; + + switch (fsm_param->to) { + case FSM_STATE_OFF: + mtk_port_disable(port_mngr); + break; + default: + break; + } +} + +void mtk_port_mngr_fsm_state_handler_late(struct mtk_fsm_param *fsm_param,= void *arg) +{ + struct mtk_port_mngr *port_mngr; + struct mtk_port *port; + + if (!fsm_param || !arg) + return; + + port_mngr =3D arg; + + switch (fsm_param->to) { + case FSM_STATE_BOOTUP: + if (fsm_param->fsm_flag & FSM_F_MD_HS_START) { + port =3D mtk_port_search_by_id(port_mngr, CCCI_CONTROL_RX); + if (port) + ports_ops[port->info.type]->enable(port); + } else if (fsm_param->fsm_flag & FSM_F_SAP_HS_START) { + port =3D mtk_port_search_by_id(port_mngr, CCCI_SAP_CONTROL_RX); + if (port) + ports_ops[port->info.type]->enable(port); + } + break; + default: + break; + } +} + int mtk_port_mngr_init(struct mtk_ctrl_blk *ctrl_blk, struct mtk_port_cfg = *port_cfg, int port_cnt) { struct mtk_port_mngr *port_mngr; diff --git a/drivers/net/wwan/t9xx/mtk_port.h b/drivers/net/wwan/t9xx/mtk_p= ort.h index bd4291408bc2..a201c0007878 100644 --- a/drivers/net/wwan/t9xx/mtk_port.h +++ b/drivers/net/wwan/t9xx/mtk_port.h @@ -152,6 +152,8 @@ int mtk_port_send_data(struct mtk_port *port, void *dat= a); int mtk_port_status_update(struct mtk_md_dev *mdev, void *data); int mtk_port_ch_enable(struct mtk_port *port); int mtk_port_ch_disable(struct mtk_port *port); +void mtk_port_mngr_fsm_state_handler(struct mtk_fsm_param *fsm_param, void= *arg); +void mtk_port_mngr_fsm_state_handler_late(struct mtk_fsm_param *fsm_param,= void *arg); int mtk_port_mngr_init(struct mtk_ctrl_blk *ctrl_blk, struct mtk_port_cfg = *port_cfg, int port_cnt); void mtk_port_mngr_exit(struct mtk_ctrl_blk *ctrl_blk); void mtk_port_trb_init(struct mtk_port *port, struct trb *trb, enum mtk_tr= b_cmd_type cmd, diff --git a/drivers/net/wwan/t9xx/mtk_utility.h b/drivers/net/wwan/t9xx/mt= k_utility.h new file mode 100644 index 000000000000..b72db3842d2d --- /dev/null +++ b/drivers/net/wwan/t9xx/mtk_utility.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only + * + * Copyright (c) 2022, MediaTek Inc. + */ + +#ifndef __MTK_UTILITY_H__ +#define __MTK_UTILITY_H__ + +#include +#include "mtk_dev.h" + +#define MTK_UEVENT_INFO_LEN 128 + +/* MTK uevent */ +enum mtk_uevent_id { + MTK_UEVENT_UNDEF =3D 0, + MTK_UEVENT_FSM =3D 1, + MTK_UEVENT_MINIDUMP =3D 2, + MTK_UEVENT_LOWPOWER =3D 3, + MTK_UEVENT_MAX +}; + +static inline void mtk_uevent_notify(struct device *dev, enum mtk_uevent_i= d id, const char *info) +{ + char buf[MTK_UEVENT_INFO_LEN]; + char *ext[2] =3D {NULL, NULL}; + + snprintf(buf, MTK_UEVENT_INFO_LEN, "%s:event_id=3D%d, info=3D%s", + dev->kobj.name, id, info); + ext[0] =3D buf; + kobject_uevent_env(&dev->kobj, KOBJ_CHANGE, ext); +} +#endif /* __MTK_UTILITY_H__ */ diff --git a/drivers/net/wwan/t9xx/pcie/mtk_cldma.c b/drivers/net/wwan/t9xx= /pcie/mtk_cldma.c index 7a0815aa2fc8..977258977dbe 100644 --- a/drivers/net/wwan/t9xx/pcie/mtk_cldma.c +++ b/drivers/net/wwan/t9xx/pcie/mtk_cldma.c @@ -34,12 +34,164 @@ #define CLDMA_RETRY_DELAY_MS (100) #define NO_BUDGET (0) =20 +static struct cldma_drv_info_desc cldma_drv_info_tbl[] =3D { + {0x01CA, &drv_ops_name(m9xx), &cldma_regs_name(m9xx)}, + {0, NULL}, +}; + +static void mtk_cldma_get_drv_info(struct cldma_drv_info *drv_info, u32 hw= _ver) +{ + struct cldma_drv_info_desc *p_drv_info; + u8 i; + + for (i =3D 0; (p_drv_info =3D &cldma_drv_info_tbl[i]) && p_drv_info && + p_drv_info->drv_ops && p_drv_info->hw_regs; i++) + if (p_drv_info->hw_ver =3D=3D hw_ver) { + drv_info->drv_ops =3D p_drv_info->drv_ops; + drv_info->hw_regs =3D p_drv_info->hw_regs; + } +} + +static int mtk_cldma_isr(int irq_id, void *param) +{ + struct cldma_drv_info *drv_info =3D param; + struct mtk_md_dev *mdev; + u32 tx_done, rx_done; + u32 tx_sta, rx_sta; + struct txq *txq; + struct rxq *rxq; + int i; + + mdev =3D drv_info->mdev; + drv_info->drv_ops->cldma_get_intr_status(drv_info, &tx_sta, &rx_sta); + tx_done =3D (tx_sta >> QUEUE_XFER_DONE) & 0xFF; + rx_done =3D (rx_sta >> QUEUE_XFER_DONE) & 0xFF; + + if (tx_done) { + for (i =3D 0; i < HW_QUEUE_NUM; i++) { + txq =3D drv_info->txq[i]; + if (!(tx_done & BIT(i)) || !txq) + continue; + queue_work(drv_info->wq, &txq->tx_done_work); + } + } + if (rx_done) { + for (i =3D 0; i < HW_QUEUE_NUM; i++) { + rxq =3D drv_info->rxq[i]; + if (!(rx_done & BIT(i)) || !rxq) + continue; + queue_work(drv_info->wq, &rxq->rx_done_work); + } + } + + mtk_pci_clear_irq(mdev, drv_info->pci_ext_irq_id); + mtk_pci_unmask_irq(mdev, drv_info->pci_ext_irq_id); + + return IRQ_HANDLED; +} + static const int mtk_cldma_hw_id_tbl[NR_CLDMA] =3D { [CLDMA0] =3D CLDMA0_HW_ID, [CLDMA1] =3D CLDMA1_HW_ID, - [CLDMA4] =3D CLDMA4_HW_ID, }; =20 +static int mtk_cldma_dev_init(struct cldma_dev *cd, int hif_id) +{ + char gpd_pool_name[DMA_POOL_NAME_LEN]; + char bd_pool_name[DMA_POOL_NAME_LEN]; + struct cldma_drv_info *drv_info; + struct cldma_hw_regs *hw_regs; + struct mtk_md_dev *mdev; + unsigned int flag; + int hw_id; + + if (!cd || hif_id >=3D NR_CLDMA) + return -EINVAL; + + if (cd->cldma_drv_info[hif_id]) + return 0; + + hw_id =3D mtk_cldma_hw_id_tbl[hif_id]; + mdev =3D cd->trans->mdev; + drv_info =3D devm_kzalloc(mdev->dev, sizeof(*drv_info), GFP_KERNEL); + if (!drv_info) + return -ENOMEM; + + drv_info->cd =3D cd; + drv_info->mdev =3D mdev; + drv_info->hif_id =3D hif_id; + drv_info->hw_id =3D hw_id; + mtk_cldma_get_drv_info(drv_info, mdev->hw_ver); + + if (!drv_info->drv_ops || !drv_info->hw_regs) { + dev_err((mdev)->dev, "Failed to find CLDMA Driver for PCI %x\n", mdev->h= w_ver); + goto err_free_drv_info; + } + + hw_regs =3D drv_info->hw_regs; + snprintf(gpd_pool_name, DMA_POOL_NAME_LEN, "cldma%d_gpd_pool_%s", + hw_id, mdev->dev_str); + snprintf(bd_pool_name, DMA_POOL_NAME_LEN, "cldma%d_bd_pool_%s", + hw_id, mdev->dev_str); + drv_info->gpd_dma_pool =3D dma_pool_create(gpd_pool_name, mdev->dev, + sizeof(union gpd), 4, 0); + if (!drv_info->gpd_dma_pool) { + dev_err((mdev)->dev, "Failed to alloc gpd dma pool for cldma%d\n", hw_id= ); + goto err_free_drv_info; + } + drv_info->bd_dma_pool =3D dma_pool_create(bd_pool_name, mdev->dev, + sizeof(union bd), 4, 0); + if (!drv_info->bd_dma_pool) { + dev_err((mdev)->dev, "Failed to alloc bd dma pool for cldma%d\n", hw_id); + goto err_destroy_gpd_pool; + } + + switch (hif_id) { + case CLDMA0: + drv_info->pci_ext_irq_id =3D mtk_pci_get_irq_id(mdev, MTK_IRQ_SRC_CLDMA0= ); + drv_info->base_addr =3D hw_regs->cldma0_base_addr; + break; + case CLDMA1: + drv_info->pci_ext_irq_id =3D mtk_pci_get_irq_id(mdev, MTK_IRQ_SRC_CLDMA1= ); + drv_info->base_addr =3D hw_regs->cldma1_base_addr; + break; + default: + goto err_destroy_dma_pool; + } + + flag =3D WQ_UNBOUND | WQ_MEM_RECLAIM | WQ_HIGHPRI; + drv_info->wq =3D alloc_workqueue("cldma%d_workq_%s", flag, 0, hw_id, mdev= ->dev_str); + if (!drv_info->wq) { + dev_err((mdev)->dev, "Failed to alloc work queue for cldma%d\n", hw_id); + goto err_destroy_dma_pool; + } + + drv_info->drv_ops->cldma_drv_init(drv_info); + + /* mask/clear PCI CLDMA L1 interrupt */ + mtk_pci_mask_irq(mdev, drv_info->pci_ext_irq_id); + mtk_pci_clear_irq(mdev, drv_info->pci_ext_irq_id); + + /* register CLDMA interrupt handler */ + mtk_pci_register_irq(mdev, drv_info->pci_ext_irq_id, mtk_cldma_isr, drv_i= nfo); + + /* unmask PCI CLDMA L1 interrupt */ + mtk_pci_unmask_irq(mdev, drv_info->pci_ext_irq_id); + + cd->cldma_drv_info[hif_id] =3D drv_info; + return 0; + + destroy_workqueue(drv_info->wq); +err_destroy_dma_pool: + dma_pool_destroy(drv_info->bd_dma_pool); +err_destroy_gpd_pool: + dma_pool_destroy(drv_info->gpd_dma_pool); +err_free_drv_info: + devm_kfree(mdev->dev, drv_info); + + return -EIO; +} + static inline void mtk_cldma_clr_bd_dsc(struct cldma_drv_info *drv_info, struct bd_dsc *bd_dsc_pool, int nr_bds) { @@ -853,6 +1005,44 @@ static void mtk_cldma_rxq_free(struct cldma_drv_info = *drv_info, u32 rxqno) devm_kfree(mdev->dev, rxq); } =20 +static int mtk_cldma_dev_exit(struct cldma_dev *cd, int hif_id) +{ + struct cldma_drv_info *drv_info; + struct mtk_md_dev *mdev; + int virq_id; + int i; + + if (!cd || hif_id >=3D NR_CLDMA) + return -EINVAL; + + if (!cd->cldma_drv_info[hif_id]) + return 0; + + /* free cldma descriptor */ + drv_info =3D cd->cldma_drv_info[hif_id]; + mdev =3D cd->trans->mdev; + virq_id =3D mtk_pci_get_virq_id(mdev, drv_info->pci_ext_irq_id); + mtk_pci_mask_irq(mdev, drv_info->pci_ext_irq_id); + synchronize_irq(virq_id); + for (i =3D 0; i < HW_QUEUE_NUM; i++) { + if (drv_info->txq[i]) + mtk_cldma_txq_free(drv_info, drv_info->txq[i]->txqno); + if (drv_info->rxq[i]) + mtk_cldma_rxq_free(drv_info, drv_info->rxq[i]->rxqno); + } + + flush_workqueue(drv_info->wq); + destroy_workqueue(drv_info->wq); + dma_pool_destroy(drv_info->bd_dma_pool); + dma_pool_destroy(drv_info->gpd_dma_pool); + mtk_pci_unregister_irq(mdev, drv_info->pci_ext_irq_id); + + devm_kfree(mdev->dev, drv_info); + cd->cldma_drv_info[hif_id] =3D NULL; + + return 0; +} + static int mtk_cldma_start_xfer(struct cldma_drv_info *drv_info, u32 qno) { struct cldma_drv_ops *drv_ops; @@ -1163,6 +1353,27 @@ int mtk_cldma_trb_process(void *dev, struct sk_buff = *skb) return trb_act_tbl[trb->cmd](cd, skb); } =20 +void mtk_cldma_fsm_state_listener(struct mtk_fsm_param *param, struct mtk_= ctrl_trans *trans) +{ + struct cldma_dev *cd =3D trans->dev; + int i; + + switch (param->to) { + case FSM_STATE_BOOTUP: + if (param->fsm_flag & FSM_F_SAP_HS_START) + mtk_cldma_dev_init(cd, CLDMA0); + else if (param->fsm_flag & FSM_F_MD_HS_START) + mtk_cldma_dev_init(cd, CLDMA1); + break; + case FSM_STATE_OFF: + for (i =3D 0; i < NR_CLDMA; i++) + mtk_cldma_dev_exit(cd, i); + break; + default: + break; + } +} + int mtk_cldma_check_ch_cfg(void *dev, struct queue_info *que) { struct cldma_drv_info *drv_info; diff --git a/drivers/net/wwan/t9xx/pcie/mtk_cldma.h b/drivers/net/wwan/t9xx= /pcie/mtk_cldma.h index 74ce4f2f0b30..4686f7b178e5 100644 --- a/drivers/net/wwan/t9xx/pcie/mtk_cldma.h +++ b/drivers/net/wwan/t9xx/pcie/mtk_cldma.h @@ -167,4 +167,7 @@ int mtk_cldma_check_ch_cfg(void *dev, struct queue_info= *que); #define drv_ops_name(NAME) cldma_drv_ops_##NAME #define cldma_regs_name(NAME) mtk_cldma_regs_##NAME =20 +extern struct cldma_drv_ops cldma_drv_ops_m9xx; +extern struct cldma_hw_regs mtk_cldma_regs_m9xx; + #endif diff --git a/drivers/net/wwan/t9xx/pcie/mtk_cldma_drv.h b/drivers/net/wwan/= t9xx/pcie/mtk_cldma_drv.h index 8763c23abf54..6de87b7ffd45 100644 --- a/drivers/net/wwan/t9xx/pcie/mtk_cldma_drv.h +++ b/drivers/net/wwan/t9xx/pcie/mtk_cldma_drv.h @@ -11,7 +11,6 @@ #define LINK_ERROR_VAL (0xFFFFFFFF) #define CLDMA0_HW_ID (0) #define CLDMA1_HW_ID (1) -#define CLDMA4_HW_ID (4) =20 struct cldma_hw_regs { u8 cldma_rx_skb_pool_max_size; @@ -36,7 +35,6 @@ struct cldma_hw_regs { u16 reg_cldma_l2rimsr0; u16 reg_cldma_l2rimsr1; u16 reg_cldma_int_mask; - u16 reg_cldma4_int_mask; u16 reg_cldma_slp_mem_ctl; u16 reg_cldma_busy_mask; u16 reg_cldma_ip_busy_to_pcie_mask; @@ -58,7 +56,6 @@ struct cldma_hw_regs { u32 rq_err_int_bitmask; u32 cldma0_base_addr; u32 cldma1_base_addr; - u32 cldma4_base_addr; u32 rq_active_start_err_int_bitmask; u32 reg_cldma_ul_start_addrl_0; u32 reg_cldma_ul_start_addrh_0; diff --git a/drivers/net/wwan/t9xx/pcie/mtk_cldma_drv_m9xx.c b/drivers/net/= wwan/t9xx/pcie/mtk_cldma_drv_m9xx.c index 240a9f58f658..9041c8f2f99c 100644 --- a/drivers/net/wwan/t9xx/pcie/mtk_cldma_drv_m9xx.c +++ b/drivers/net/wwan/t9xx/pcie/mtk_cldma_drv_m9xx.c @@ -33,7 +33,6 @@ struct cldma_hw_regs mtk_cldma_regs_m9xx =3D { .cldma0_base_addr =3D CLDMA0_BASE_ADDR, .cldma1_base_addr =3D CLDMA1_BASE_ADDR, - .cldma4_base_addr =3D CLDMA4_BASE_ADDR, .cldma_rx_skb_pool_max_size =3D CLDMA_RX_SKB_POOL_MAX_SIZE, .cldma_rx_skb_reload_threshold =3D CLDMA_RX_SKB_RELOAD_THRESHOLD, .tq_err_int_offset =3D TQ_ERR_INT_OFFSET, @@ -92,7 +91,6 @@ struct cldma_hw_regs mtk_cldma_regs_m9xx =3D { .reg_cldma_l3risar1 =3D REG_CLDMA_L3RISAR1, .reg_cldma_ip_busy =3D REG_CLDMA_IP_BUSY, .reg_cldma_int_mask =3D REG_CLDMA_INT_EAP_USIP_MASK, - .reg_cldma4_int_mask =3D REG_CLDMA_INT_WF_MASK, .reg_cldma_ip_busy_to_pcie_mask =3D REG_CLDMA_IP_BUSY_TO_PCIE_MASK, .reg_cldma_ip_busy_to_pcie_mask_set =3D REG_CLDMA_IP_BUSY_TO_PCIE_MASK_SE= T, .reg_cldma_ip_busy_to_pcie_mask_clr =3D REG_CLDMA_IP_BUSY_TO_PCIE_MASK_CL= R, @@ -134,10 +132,7 @@ static void mtk_cldma_drv_init_m9xx(struct cldma_drv_i= nfo *drv_info) ALLQ << 24); =20 /* enable interrupt to PCIe */ - if (drv_info->hw_id =3D=3D CLDMA4_HW_ID) - mtk_pci_write32(mdev, base + hw_regs->reg_cldma4_int_mask, 0); - else - mtk_pci_write32(mdev, base + hw_regs->reg_cldma_int_mask, 0); + mtk_pci_write32(mdev, base + hw_regs->reg_cldma_int_mask, 0); =20 /* disable illegal memory check */ mtk_pci_write32(mdev, base + hw_regs->reg_cldma_ul_dummy_0, 1); diff --git a/drivers/net/wwan/t9xx/pcie/mtk_cldma_drv_m9xx.h b/drivers/net/= wwan/t9xx/pcie/mtk_cldma_drv_m9xx.h index 2c63c43ff065..f113c4c1068a 100644 --- a/drivers/net/wwan/t9xx/pcie/mtk_cldma_drv_m9xx.h +++ b/drivers/net/wwan/t9xx/pcie/mtk_cldma_drv_m9xx.h @@ -8,7 +8,6 @@ =20 #define CLDMA0_BASE_ADDR (0x1021C000) #define CLDMA1_BASE_ADDR (0x1021E000) -#define CLDMA4_BASE_ADDR (0x10224000) =20 #define CLDMA_RX_SKB_POOL_MAX_SIZE (64) #define CLDMA_RX_SKB_RELOAD_THRESHOLD (16) @@ -80,7 +79,6 @@ #define REG_CLDMA_L2RIMSR1 (0x0800 + 0x00FC) =20 #define REG_CLDMA_INT_EAP_USIP_MASK (0x0800 + 0x011C) -#define REG_CLDMA_INT_WF_MASK (0x0800 + 0x0120) #define REG_CLDMA_RQ1_GPD_DONE_CNT (0x0800 + 0x0174) #define REG_CLDMA_TQ1_GPD_DONE_CNT (0x0800 + 0x0184) =20 diff --git a/drivers/net/wwan/t9xx/pcie/mtk_pci.c b/drivers/net/wwan/t9xx/p= cie/mtk_pci.c index 0a0ebfede45c..d8086c34416d 100644 --- a/drivers/net/wwan/t9xx/pcie/mtk_pci.c +++ b/drivers/net/wwan/t9xx/pcie/mtk_pci.c @@ -904,22 +904,34 @@ static int mtk_pci_dev_init(struct mtk_md_dev *mdev) { int ret; =20 - ret =3D mtk_trans_ctrl_init(mdev); + ret =3D mtk_fsm_init(mdev); if (ret) { - dev_err(mdev->dev, "Failed to initialize control plane: %d\n", ret); + dev_err(mdev->dev, "Failed to initialize FSM: %d\n", ret); return ret; } =20 + ret =3D mtk_trans_ctrl_init(mdev); + if (ret) + goto free_fsm; + return 0; +free_fsm: + mtk_fsm_exit(mdev); + return ret; } =20 static void mtk_pci_dev_exit(struct mtk_md_dev *mdev) { + mtk_fsm_evt_submit(mdev, FSM_EVT_DEV_RM, 0, NULL, 0, + EVT_MODE_BLOCKING | EVT_MODE_TOHEAD); mtk_trans_ctrl_exit(mdev); + mtk_fsm_exit(mdev); } =20 static int mtk_pci_dev_start(struct mtk_md_dev *mdev) { + mtk_fsm_evt_submit(mdev, FSM_EVT_DEV_ADD, 0, NULL, 0, 0); + mtk_fsm_start(mdev); return 0; } static const struct mtk_dev_ops pci_hw_ops =3D { diff --git a/drivers/net/wwan/t9xx/pcie/mtk_trans_ctrl.c b/drivers/net/wwan= /t9xx/pcie/mtk_trans_ctrl.c index 899b04403b18..18d2ad8a7c59 100644 --- a/drivers/net/wwan/t9xx/pcie/mtk_trans_ctrl.c +++ b/drivers/net/wwan/t9xx/pcie/mtk_trans_ctrl.c @@ -481,6 +481,15 @@ static int mtk_pcie_hif_submit_skb(struct mtk_md_dev *= mdev, struct sk_buff *skb, return 0; } =20 +static void mtk_pcie_hif_fsm_indication(struct mtk_md_dev *mdev, struct mt= k_fsm_param *param) +{ + struct mtk_ctrl_blk *ctrl_blk =3D mdev->ctrl_blk; + struct mtk_ctrl_trans *trans; + + trans =3D ctrl_blk->ctrl_hw_priv; + mtk_cldma_fsm_state_listener(param, trans); +} + static int mtk_pcie_hif_cmd_func(struct mtk_md_dev *mdev, int cmd, void *d= ata) { struct mtk_ctrl_blk *ctrl_blk =3D mdev->ctrl_blk; @@ -508,6 +517,7 @@ static struct mtk_ctrl_hif_ops pcie_ctrl_ops =3D { .init =3D mtk_pcie_hif_init, .exit =3D mtk_pcie_hif_exit, .submit_skb =3D mtk_pcie_hif_submit_skb, + .fsm_indication =3D mtk_pcie_hif_fsm_indication, .send_cmd =3D mtk_pcie_hif_cmd_func, }; =20 diff --git a/drivers/net/wwan/t9xx/pcie/mtk_trans_ctrl.h b/drivers/net/wwan= /t9xx/pcie/mtk_trans_ctrl.h index cca8e6f1532e..38b0f40d6b90 100644 --- a/drivers/net/wwan/t9xx/pcie/mtk_trans_ctrl.h +++ b/drivers/net/wwan/t9xx/pcie/mtk_trans_ctrl.h @@ -29,7 +29,6 @@ enum mtk_hif_id { CLDMA0, CLDMA1, - CLDMA4, NR_CLDMA }; =20 --=20 2.34.1 From nobody Wed Jun 10 17:22:13 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1C4EC3FADF6; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="lwW4E3FY" Received: by smtp.kernel.org (Postfix) with ESMTPS id 91838C4AF14; Wed, 10 Jun 2026 10:41:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1781088101; bh=enG7iyL04qv5Y6fIIXAvsWApzHRvvGpJR1IqjSoSwaI=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=lwW4E3FYKh+Yj3bp32hZDgj9dQSWSpQ13WUEmmW1v307TsFLPvw9cf0oKrbAiax2U AB/1XIE15fV5otYxFPw2qxZt63Fy3UWHrzo6/zOwiTYuwbuHVMLUcSIAMPA/b9/qFx rxzxat38JnsSXWsMdKJRJV3ufiC7x6YxZ2WyIrnTf+3GkbNjH8uF9B17931NflnWaW b17/CA9YXGSkwrnD54TciIwa9DVGGU6mr979Uc04QZ4snU0JDpM5E9pCxcs0CUFKhZ JoMMZsR0mkY1C6Sp6EAcdvkj7fKd8JZCTSq4WLH13UZ4sL/0RO8mGWdDkYrskqwzp+ /RDUkZDpTCydg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 89D7FCD8CB2; Wed, 10 Jun 2026 10:41:41 +0000 (UTC) From: Jack Wu via B4 Relay Date: Wed, 10 Jun 2026 18:41:09 +0800 Subject: [PATCH v2 6/7] net: wwan: t9xx: Add AT & MBIM WWAN ports Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260610-t9xx_driver_v1-v2-6-c65addf23b3f@compal.com> References: <20260610-t9xx_driver_v1-v2-0-c65addf23b3f@compal.com> In-Reply-To: <20260610-t9xx_driver_v1-v2-0-c65addf23b3f@compal.com> To: Loic Poulain , Sergey Ryazanov , Johannes Berg , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Jack Wu , Wen-Zhi Huang , Shi-Wei Yeh , Minano Tseng , Matthias Brugger , AngeloGioacchino Del Regno , Simon Horman , Jonathan Corbet , Shuah Khan Cc: linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-doc@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1781088082; l=14707; i=jackbb_wu@compal.com; s=20260526; h=from:subject:message-id; bh=sLA+K4d0nCKWOYPFV6TUunfp2xvnpTdHd4KA4x5+/5w=; b=DekjGbKLcvZz1GVgupsqLTWguKBkkF+WfQPAlljLk7SWsc4T5DbG3FU3kHbJXemAVzgknd+AA +QcnrwMFQRJC1/8ZnOuhl0u03kpQ3zlqMHeM2Uwm1vNWhGsV8jfrKc8 X-Developer-Key: i=jackbb_wu@compal.com; a=ed25519; pk=VH1prTWixNl8OEUPPSfII3p46MzJpQN8J3+ecE1tZXg= X-Endpoint-Received: by B4 Relay for jackbb_wu@compal.com/20260526 with auth_id=793 X-Original-From: Jack Wu Reply-To: jackbb_wu@compal.com From: Jack Wu Add AT & MBIM ports to the port infrastructure. The WWAN initialization method is responsible for creating the corresponding ports using the WWAN framework infrastructure. The implemented WWAN port operations are start, stop, tx, tx_blocking and tx_poll. Signed-off-by: Jack Wu --- drivers/net/wwan/t9xx/mtk_port.c | 26 ++ drivers/net/wwan/t9xx/mtk_port.h | 15 ++ drivers/net/wwan/t9xx/mtk_port_io.c | 337 +++++++++++++++++++++= +++- drivers/net/wwan/t9xx/mtk_port_io.h | 5 + drivers/net/wwan/t9xx/pcie/mtk_ctrl_cfg_m9xx.c | 8 + 5 files changed, 390 insertions(+), 1 deletion(-) diff --git a/drivers/net/wwan/t9xx/mtk_port.c b/drivers/net/wwan/t9xx/mtk_p= ort.c index c68437e58ea2..f28f046cf2c9 100644 --- a/drivers/net/wwan/t9xx/mtk_port.c +++ b/drivers/net/wwan/t9xx/mtk_port.c @@ -819,6 +819,29 @@ int mtk_port_ch_disable(struct mtk_port *port) return ret; } =20 +static int mtk_port_enable_by_type(struct mtk_port_mngr *port_mngr, int tb= l_type) +{ + struct mtk_port **ports; + int ret, idx; + + if (tbl_type < 0 || tbl_type >=3D PORT_TBL_MAX) + return -EINVAL; + + ports =3D kcalloc(port_mngr->port_cnt, sizeof(struct mtk_port *), GFP_KER= NEL); + if (!ports) + return -ENOMEM; + + ret =3D radix_tree_gang_lookup(&port_mngr->port_tbl[tbl_type], + (void **)ports, 0, port_mngr->port_cnt); + for (idx =3D 0; idx < ret; idx++) { + if (ports[idx]->enable) + ports_ops[ports[idx]->info.type]->enable(ports[idx]); + } + + kfree(ports); + return 0; +} + static void mtk_port_disable(struct mtk_port_mngr *port_mngr) { struct mtk_port **ports; @@ -852,6 +875,9 @@ void mtk_port_mngr_fsm_state_handler(struct mtk_fsm_par= am *fsm_param, void *arg) case FSM_STATE_OFF: mtk_port_disable(port_mngr); break; + case FSM_STATE_READY: + mtk_port_enable_by_type(port_mngr, PORT_TBL_MD); + break; default: break; } diff --git a/drivers/net/wwan/t9xx/mtk_port.h b/drivers/net/wwan/t9xx/mtk_p= ort.h index a201c0007878..cf561add6318 100644 --- a/drivers/net/wwan/t9xx/mtk_port.h +++ b/drivers/net/wwan/t9xx/mtk_port.h @@ -56,6 +56,10 @@ enum mtk_ccci_ch { /* to MD */ CCCI_CONTROL_RX =3D 0x2000, CCCI_CONTROL_TX =3D 0x2001, + CCCI_UART2_RX =3D 0x200A, + CCCI_UART2_TX =3D 0x200C, + CCCI_MBIM_RX =3D 0x20D0, + CCCI_MBIM_TX =3D 0x20D1, }; =20 enum mtk_port_flag { @@ -73,6 +77,7 @@ enum mtk_port_tbl { =20 enum mtk_port_type { PORT_TYPE_INTERNAL, + PORT_TYPE_WWAN, PORT_TYPE_MAX }; =20 @@ -81,6 +86,13 @@ struct mtk_internal_port { int (*recv_cb)(void *arg, struct sk_buff *skb); }; =20 +struct mtk_wwan_port { + /* w_lock protects wwan_port when recv data and disable port at the same = time */ + struct mutex w_lock; + int w_type; + void *w_port; +}; + struct mtk_port_cfg { enum mtk_ccci_ch tx_ch; enum mtk_ccci_ch rx_ch; @@ -108,8 +120,11 @@ struct mtk_port { wait_queue_head_t rx_wq; struct list_head stale_entry; char dev_str[MTK_DEV_STR_LEN]; + /* Serializes port write operations */ + struct mutex write_lock; struct mtk_port_mngr *port_mngr; struct mtk_internal_port i_priv; + struct mtk_wwan_port w_priv; }; =20 struct mtk_port_mngr { diff --git a/drivers/net/wwan/t9xx/mtk_port_io.c b/drivers/net/wwan/t9xx/mt= k_port_io.c index bbde0d950226..58655678d82b 100644 --- a/drivers/net/wwan/t9xx/mtk_port_io.c +++ b/drivers/net/wwan/t9xx/mtk_port_io.c @@ -3,6 +3,10 @@ * Copyright (c) 2022, MediaTek Inc. */ #include +#include +#include +#include +#include =20 #include "mtk_port_io.h" =20 @@ -39,6 +43,146 @@ static void mtk_port_struct_init(struct mtk_port *port) port->rx_buf_size =3D MTK_RX_BUF_SIZE; init_waitqueue_head(&port->trb_wq); init_waitqueue_head(&port->rx_wq); + mutex_init(&port->write_lock); +} + +static int mtk_port_copy_data_from(void *to, union user_buf from, unsigned= int len, + unsigned int offset, bool from_user_space) +{ + if (from_user_space) { + if (copy_from_user(to, from.ubuf + offset, len)) + return -EINVAL; + } else { + memcpy(to, from.kbuf + offset, len); + } + + return 0; +} + +static int mtk_port_common_write_frag_skb(struct mtk_port *port, struct sk= _buff *skb, + union user_buf buf, u32 packet_size, + u32 cur_pos, bool from_user_space) +{ + struct sk_buff *frag_skb, *tmp =3D NULL; + u32 frag_size; + int ret; + + frag_size =3D min(packet_size, port->tx_frag_size); + ret =3D mtk_port_copy_data_from(skb_put(skb, frag_size), + buf, frag_size, + cur_pos, from_user_space); + if (ret) { + dev_err(port->port_mngr->ctrl_blk->mdev->dev, + "Failed to copy skb for port(%s)\n", port->info.name); + goto err_reset_skb; + } + cur_pos +=3D frag_size; + packet_size -=3D frag_size; + if (!packet_size) + return cur_pos; + + while (packet_size > 0) { + frag_skb =3D __dev_alloc_skb(port->tx_mtu, GFP_KERNEL); + if (!frag_skb) { + ret =3D -ENOMEM; + goto err_free_frag_list; + } + + frag_size =3D min(packet_size, port->tx_frag_size); + ret =3D mtk_port_copy_data_from(skb_put(frag_skb, frag_size), + buf, frag_size, + cur_pos, from_user_space); + if (ret) { + dev_err(port->port_mngr->ctrl_blk->mdev->dev, + "Failed to copy frag_skb for port(%s)\n", port->info.name); + dev_kfree_skb_any(frag_skb); + goto err_free_frag_list; + } + skb->data_len +=3D frag_size; + skb->len +=3D frag_size; + cur_pos +=3D frag_size; + packet_size -=3D frag_size; + if (!tmp) + skb_shinfo(skb)->frag_list =3D frag_skb; + else + tmp->next =3D frag_skb; + tmp =3D frag_skb; + } + return cur_pos; + +err_free_frag_list: + frag_skb =3D skb_shinfo(skb)->frag_list; + while (frag_skb) { + tmp =3D frag_skb->next; + frag_skb->next =3D NULL; + dev_kfree_skb_any(frag_skb); + frag_skb =3D tmp; + } + skb_shinfo(skb)->frag_list =3D NULL; +err_reset_skb: + skb->data_len =3D 0; + return ret; +} + +static int mtk_port_common_write(struct mtk_port *port, union user_buf buf= , unsigned int len, + bool from_user_space) +{ + u32 packet_size, left_cnt =3D len, cur_pos; + struct sk_buff *skb; + int ret; + + if (len =3D=3D 0) + return -EINVAL; + +start_write: + ret =3D mtk_port_status_check(port); + if (ret) + goto end_write; + + skb =3D __dev_alloc_skb(port->tx_mtu, GFP_KERNEL); + if (!skb) { + ret =3D -ENOMEM; + goto end_write; + } + + skb_reserve(skb, sizeof(struct mtk_ccci_header)); + + packet_size =3D min_t(u32, left_cnt, port->tx_mtu - sizeof(struct mtk_ccc= i_header)); + cur_pos =3D len - left_cnt; + /* Support scatter gather transmission */ + if (port->tx_mtu > port->tx_frag_size) { + ret =3D mtk_port_common_write_frag_skb(port, skb, buf, packet_size, + cur_pos, from_user_space); + if (ret < 0) + goto err_free_skb; + } else { + ret =3D mtk_port_copy_data_from(skb_put(skb, packet_size), + buf, packet_size, + cur_pos, from_user_space); + if (ret) { + dev_err(port->port_mngr->ctrl_blk->mdev->dev, + "Failed to copy data for port(%s)\n", port->info.name); + goto err_free_skb; + } + } + + ret =3D mtk_port_send_data(port, skb); + if (ret < 0) { + if (ret =3D=3D -EINTR) + left_cnt -=3D packet_size; + goto end_write; + } + + left_cnt -=3D ret; + if (left_cnt) + goto start_write; + else + goto end_write; + +err_free_skb: + dev_kfree_skb_any(skb); +end_write: + return (len > left_cnt) ? (len - left_cnt) : ret; } =20 static int mtk_port_internal_init(struct mtk_port *port) @@ -101,7 +245,6 @@ static int mtk_port_internal_recv(struct mtk_port *port= , struct sk_buff *skb) return ret; =20 drop_data: - dev_kfree_skb_any(skb); return ret; } =20 @@ -233,6 +376,198 @@ static const struct port_ops port_internal_ops =3D { .recv =3D mtk_port_internal_recv, }; =20 +static int mtk_port_wwan_open(struct wwan_port *w_port) +{ + struct mtk_port *port; + int ret; + + port =3D wwan_port_get_drvdata(w_port); + ret =3D mtk_port_get_locked(port); + if (ret) + return ret; + + ret =3D mtk_port_common_open(port); + if (ret) + mtk_port_put_locked(port); + + return ret; +} + +static void mtk_port_wwan_close(struct wwan_port *w_port) +{ + struct mtk_port *port =3D wwan_port_get_drvdata(w_port); + + mtk_port_common_close(port); + mtk_port_put_locked(port); +} + +static int mtk_port_wwan_write(struct wwan_port *w_port, struct sk_buff *s= kb) +{ + struct mtk_port *port =3D wwan_port_get_drvdata(w_port); + union user_buf user_buf; + int ret; + + if (unlikely(!skb->len)) { + consume_skb(skb); + return 0; + } + + port->info.flags &=3D ~PORT_F_BLOCKING; + user_buf.kbuf =3D (void *)skb->data; + ret =3D mtk_port_common_write(port, user_buf, skb->len, false); + if (ret < 0) + return ret; + + consume_skb(skb); + return 0; +} + +static int mtk_port_wwan_write_blocking(struct wwan_port *w_port, struct s= k_buff *skb) +{ + struct mtk_port *port =3D wwan_port_get_drvdata(w_port); + union user_buf user_buf; + int ret; + + if (unlikely(!skb->len)) { + consume_skb(skb); + return 0; + } + + port->info.flags |=3D PORT_F_BLOCKING; + user_buf.kbuf =3D (void *)skb->data; + ret =3D mtk_port_common_write(port, user_buf, skb->len, false); + if (ret < 0) + return ret; + + consume_skb(skb); + return 0; +} + +static __poll_t mtk_port_wwan_poll(struct wwan_port *w_port, struct file *= file, + struct poll_table_struct *poll) +{ + struct mtk_port *port =3D wwan_port_get_drvdata(w_port); + union ctrl_hif_cmd_data hif_cmd; + struct mtk_ctrl_blk *ctrl_blk; + __poll_t mask =3D 0; + + poll_wait(file, &port->trb_wq, poll); + if (mtk_port_status_check(port)) + return EPOLLERR | EPOLLHUP; + + ctrl_blk =3D port->port_mngr->ctrl_blk; + hif_cmd.rx_ch =3D port->info.rx_ch; + if (!ctrl_blk->ops->send_cmd(ctrl_blk->mdev, HIF_CTRL_CMD_CHECK_TX_FULL, = &hif_cmd)) + mask |=3D EPOLLOUT | EPOLLWRNORM; + + return mask; +} + +static const struct wwan_port_ops wwan_ops =3D { + .start =3D mtk_port_wwan_open, + .stop =3D mtk_port_wwan_close, + .tx =3D mtk_port_wwan_write, + .tx_blocking =3D mtk_port_wwan_write_blocking, + .tx_poll =3D mtk_port_wwan_poll, +}; + +static int mtk_port_wwan_init(struct mtk_port *port) +{ + mtk_port_struct_init(port); + port->enable =3D false; + + mutex_init(&port->w_priv.w_lock); + + switch (port->info.rx_ch) { + case CCCI_MBIM_RX: + port->w_priv.w_type =3D WWAN_PORT_MBIM; + break; + case CCCI_UART2_RX: + port->w_priv.w_type =3D WWAN_PORT_AT; + break; + default: + port->w_priv.w_type =3D WWAN_PORT_UNKNOWN; + break; + } + + return 0; +} + +static void mtk_port_wwan_exit(struct mtk_port *port) +{ + if (test_bit(PORT_S_ENABLE, &port->status)) + ports_ops[port->info.type]->disable(port); +} + +static void mtk_port_wwan_enable(struct mtk_port *port) +{ + struct mtk_port_mngr *port_mngr; + int ret; + + port_mngr =3D port->port_mngr; + + if (test_bit(PORT_S_ENABLE, &port->status)) + return; + + ret =3D mtk_port_ch_enable(port); + if (ret && ret !=3D -EBUSY) + return; + + port->w_priv.w_port =3D wwan_create_port(port_mngr->ctrl_blk->mdev->dev, + port->w_priv.w_type, + &wwan_ops, NULL, port); + if (IS_ERR(port->w_priv.w_port)) { + dev_warn(port_mngr->ctrl_blk->mdev->dev, + "Failed to create wwan port for (%s)\n", port->info.name); + port->w_priv.w_port =3D NULL; + mtk_port_ch_disable(port); + return; + } + + set_bit(PORT_S_WR, &port->status); + set_bit(PORT_S_ENABLE, &port->status); +} + +static void mtk_port_wwan_disable(struct mtk_port *port) +{ + struct wwan_port *w_port; + + if (!test_and_clear_bit(PORT_S_ENABLE, &port->status)) + return; + + clear_bit(PORT_S_WR, &port->status); + w_port =3D port->w_priv.w_port; + mutex_lock(&port->w_priv.w_lock); + port->w_priv.w_port =3D NULL; + mutex_unlock(&port->w_priv.w_lock); + + mtk_port_ch_disable(port); + wwan_remove_port(w_port); +} + +static int mtk_port_wwan_recv(struct mtk_port *port, struct sk_buff *skb) +{ + mutex_lock(&port->w_priv.w_lock); + if (!port->w_priv.w_port) { + mutex_unlock(&port->w_priv.w_lock); + return -ENXIO; + } + + wwan_port_rx(port->w_priv.w_port, skb); + mutex_unlock(&port->w_priv.w_lock); + return 0; +} + +static const struct port_ops port_wwan_ops =3D { + .init =3D mtk_port_wwan_init, + .exit =3D mtk_port_wwan_exit, + .reset =3D mtk_port_reset, + .enable =3D mtk_port_wwan_enable, + .disable =3D mtk_port_wwan_disable, + .recv =3D mtk_port_wwan_recv, +}; + const struct port_ops *ports_ops[PORT_TYPE_MAX] =3D { &port_internal_ops, + &port_wwan_ops, }; diff --git a/drivers/net/wwan/t9xx/mtk_port_io.h b/drivers/net/wwan/t9xx/mt= k_port_io.h index 0c10e893b7e0..ea92cd22dba0 100644 --- a/drivers/net/wwan/t9xx/mtk_port_io.h +++ b/drivers/net/wwan/t9xx/mtk_port_io.h @@ -23,6 +23,11 @@ struct port_ops { int (*recv)(struct mtk_port *port, struct sk_buff *skb); }; =20 +union user_buf { + void __user *ubuf; + void *kbuf; +}; + void *mtk_port_internal_open(struct mtk_md_dev *mdev, char *name, int flag= ); int mtk_port_internal_close(void *i_port); int mtk_port_internal_write(void *i_port, struct sk_buff *skb); diff --git a/drivers/net/wwan/t9xx/pcie/mtk_ctrl_cfg_m9xx.c b/drivers/net/w= wan/t9xx/pcie/mtk_ctrl_cfg_m9xx.c index 8611561dd67c..aab09cab360c 100644 --- a/drivers/net/wwan/t9xx/pcie/mtk_ctrl_cfg_m9xx.c +++ b/drivers/net/wwan/t9xx/pcie/mtk_ctrl_cfg_m9xx.c @@ -16,6 +16,10 @@ static const int mtk_srv_cfg_m9xx[NR_CLDMA][HW_QUE_NUM] = =3D { =20 /* the number of RX GPDs should be at last two */ static const struct queue_info mtk_queue_info_m9xx[] =3D { + {CCCI_UART2_TX, CCCI_UART2_RX, CLDMA1, TXQ(5), RXQ(5), + Q_MTU_3_5K, Q_MTU_3_5K, TX_GPD_NUM, RX_GPD_NUM, Q_FRAG_3_5K, Q_FRAG_3_5K= , 0}, + {CCCI_MBIM_TX, CCCI_MBIM_RX, CLDMA1, TXQ(2), RXQ(2), + Q_MTU_3_5K, Q_MTU_3_5K, TX_GPD_NUM, RX_GPD_NUM, Q_FRAG_3_5K, Q_FRAG_3_5K= , 0}, {CCCI_CONTROL_TX, CCCI_CONTROL_RX, CLDMA1, TXQ(0), RXQ(0), Q_MTU_3_5K, Q_MTU_3_5K, TX_GPD_NUM, RX_GPD_NUM, Q_FRAG_3_5K, Q_FRAG_3_5K= , 0}, {CCCI_SAP_CONTROL_TX, CCCI_SAP_CONTROL_RX, CLDMA0, TXQ(0), RXQ(0), @@ -23,6 +27,10 @@ static const struct queue_info mtk_queue_info_m9xx[] =3D= { }; =20 static const struct mtk_port_cfg port_cfg_m9xx[] =3D { + {CCCI_UART2_TX, CCCI_UART2_RX, PORT_TYPE_WWAN, "AT", + PORT_F_ALLOW_DROP}, + {CCCI_MBIM_TX, CCCI_MBIM_RX, PORT_TYPE_WWAN, "MBIM", + PORT_F_ALLOW_DROP}, {CCCI_CONTROL_TX, CCCI_CONTROL_RX, PORT_TYPE_INTERNAL, "MDCTRL", PORT_F_ALLOW_DROP}, {CCCI_SAP_CONTROL_TX, CCCI_SAP_CONTROL_RX, PORT_TYPE_INTERNAL, "SAPCTRL", --=20 2.34.1 From nobody Wed Jun 10 17:22:13 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 308E63FAE11; Wed, 10 Jun 2026 10:41:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781088102; cv=none; b=JBIUvjCdrE44aDFUbjKIddQTzGdmok9ENG1n3s++qYHXZOyB/StjAPPy18+nsDV1Qob5uY4xPuscO9dVHRIGXUGAfumfbOiQ1NIWKsrgdZpbuS+1fQis/y/d/5PtcWErogPQD0lnKfh6OMQepeR9bFBl40QwyqnMb7m7TzU1Fj0= ARC-Message-Signature: i=1; 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b=WuwDP9zMYo9367Ie9idAzggtmWifUc6+YyLLsjQOtUo3lYOh4hFZR0AJkkBEvMsoj /iOmhGwMNKew9K3gcHy4tGtx9gUzErl0Ayry41co89GXVP7rUZizOZdYr0phKcrkd8 t3/vjtF4TTwENrJXzkL4oYBhm9O1mkAKIDseWVZXWBkDsjxT3dt3av0EW7BV2R1JiL OEDzF6a/yAB5pVG5pEcUUdiUrpqGN4gP9S2hXWpjuF6wIHLB05qvABK7mUmkZAzxut 45LZsPw9IqL3RR87KBmPRKOQ7pG91vxsv8sFirNpQ349vET/JTfXUmaE6KLquo7x+H HXgwPKOZ3UrCg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 97120CD98CC; Wed, 10 Jun 2026 10:41:41 +0000 (UTC) From: Jack Wu via B4 Relay Date: Wed, 10 Jun 2026 18:41:10 +0800 Subject: [PATCH v2 7/7] net: wwan: t9xx: Add maintainers entry Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260610-t9xx_driver_v1-v2-7-c65addf23b3f@compal.com> References: <20260610-t9xx_driver_v1-v2-0-c65addf23b3f@compal.com> In-Reply-To: <20260610-t9xx_driver_v1-v2-0-c65addf23b3f@compal.com> To: Loic Poulain , Sergey Ryazanov , Johannes Berg , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Jack Wu , Wen-Zhi Huang , Shi-Wei Yeh , Minano Tseng , Matthias Brugger , AngeloGioacchino Del Regno , Simon Horman , Jonathan Corbet , Shuah Khan Cc: linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-doc@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1781088082; l=817; i=jackbb_wu@compal.com; s=20260526; h=from:subject:message-id; bh=r28B5Pv3emoSo+1n1DcJ9EobPmHHNOtOYu07ftmyDY8=; b=7/u4iSOCzaThHIb9tIhHtOncLLXWosB85/NLc1LHLuef+2h3kaDN4IpR3k9QN/e5zvW22w0NV xTzWnd9RSqNB0D4CsmhnvIaevJHq22Co6Q8DkRqvlLZ/vgQnxE8VtBB X-Developer-Key: i=jackbb_wu@compal.com; a=ed25519; pk=VH1prTWixNl8OEUPPSfII3p46MzJpQN8J3+ecE1tZXg= X-Endpoint-Received: by B4 Relay for jackbb_wu@compal.com/20260526 with auth_id=793 X-Original-From: Jack Wu Reply-To: jackbb_wu@compal.com From: Jack Wu Add MAINTAINERS entry for the MediaTek T9XX 5G WWAN modem device driver. Signed-off-by: Jack Wu --- MAINTAINERS | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 461a3eed6129..8155d26bff03 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -16494,6 +16494,15 @@ L: netdev@vger.kernel.org S: Supported F: drivers/net/wwan/t7xx/ =20 +MEDIATEK T9XX 5G WWAN MODEM DRIVER +M: Jack Wu +R: Wen-Zhi Huang +R: Shi-Wei Yeh +R: Minano Tseng +L: netdev@vger.kernel.org +S: Supported +F: drivers/net/wwan/t9xx/ + MEDIATEK USB3 DRD IP DRIVER M: Chunfeng Yun L: linux-usb@vger.kernel.org --=20 2.34.1