From nobody Thu Jun 11 00:36:12 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4446A374A0A; Wed, 10 Jun 2026 08:22:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781079737; cv=none; b=RSdfpNGzaRHJxHri8GmJ+B4DBnoQW771DtGNWjd5aPvoSiHKgQY/1Qohxh9dCwJskXl4vuhFlaIp77aI/o2JnZyqSUbp64zcwjPtMiBPEoxupksxn9KObyDFORPyo9xJlK89kK+2Pe768qsMrbtedzOL/azey4T1EnRm5NvW15Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781079737; c=relaxed/simple; bh=vMA/TDrL6pX/37cIVwe+uCWPjNEkgQmBnrmcW+A7gxA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=EpiwMz3M7VwKVswM46K7u6iCty+nn6ka8wv0/cO7rFsxFtSm+MzxCRuPVgWIiUkVFtkXFuO03uMNrinsKJ7mJCo5IxzPnTq/FxBChIm9zbkUk3oUb3RuYav0oINSiJ4f9OrMM10KPVYc0U9nvR+EzrYSIBw7IXy73D5LO5bkK6w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=CrHszgjj; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="CrHszgjj" Received: by smtp.kernel.org (Postfix) with ESMTPS id E3F57C2BCB8; Wed, 10 Jun 2026 08:22:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1781079737; bh=vMA/TDrL6pX/37cIVwe+uCWPjNEkgQmBnrmcW+A7gxA=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=CrHszgjjpR0TFZA8WAqzc4kIFSNXpAVQg7ey6eavBL7ls3rRsCWJrldnkNdbAlpuX 834r6mXhxEhXRTM3mYNx7VA2ZtvIXn7qekzFUhrOMGq+FGag5/5LJe+sHxI661i9FS V9nuFmJ0xpbVLNZAvOtSTEnx2mp3ZnqfAUek4mpaqc1VjEg76vyct8OOe4ZX6fG+HX DcC5voPkqhLYWyneAlikN1Z6/n6tMUQfcIdULj7J2V3n1i9+2PD8Ytbv1d7zIxU6SY Sdyw6y2Cnf7U26MbBpCvsSuhbIRQyhxenpaXV0vFkaUj/ls6D3ybI0xZUS2mQERtfI YIwX5HecKsEcg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id DB82ECD8CB9; Wed, 10 Jun 2026 08:22:16 +0000 (UTC) From: Aleksa Paunovic via B4 Relay Date: Wed, 10 Jun 2026 10:22:13 +0200 Subject: [PATCH v8 1/3] dt-bindings: timer: mips,p8700-gcru Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260610-riscv-time-mmio-v8-1-a865206675c6@htecgroup.com> References: <20260610-riscv-time-mmio-v8-0-a865206675c6@htecgroup.com> In-Reply-To: <20260610-riscv-time-mmio-v8-0-a865206675c6@htecgroup.com> To: Daniel Lezcano , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Paul Walmsley , John Stultz , Stephen Boyd , Vivian Wang Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Djordje Todorovic , Aleksa Paunovic , Chao-ying Fu , Conor Dooley X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1781079735; l=1839; i=aleksa.paunovic@htecgroup.com; s=20250806; h=from:subject:message-id; bh=qlCmLDBO1Y2Dd5pfYZ/Ggi2QMtMAGxo3h0341eF3VPk=; b=OaAWvgTi5s6lRwqlpaZOA9PGdBjUjWweevujHSrREmyAkxHvWtniupncOQZTBjJ9xvZ9yQvXQ px6UC26oUVCAkR1X5S3PVorefAf04lMXeb6I819y8dC/sxQiw5sDR+X X-Developer-Key: i=aleksa.paunovic@htecgroup.com; a=ed25519; pk=Dn4KMnDdgyhlXJNspQQrlHJ04i7/irG29p2H27Avd+8= X-Endpoint-Received: by B4 Relay for aleksa.paunovic@htecgroup.com/20250806 with auth_id=476 X-Original-From: Aleksa Paunovic Reply-To: aleksa.paunovic@htecgroup.com From: Aleksa Paunovic Add dt-bindings for the GCR.U memory mapped timer device for RISC-V platforms. The GCR.U memory region contains shadow copies of the RISC-V mtime register and the hrtime Global Configuration Register. Signed-off-by: Aleksa Paunovic Acked-by: Conor Dooley --- .../devicetree/bindings/timer/mips,p8700-gcru.yaml | 38 ++++++++++++++++++= ++++ 1 file changed, 38 insertions(+) diff --git a/Documentation/devicetree/bindings/timer/mips,p8700-gcru.yaml b= /Documentation/devicetree/bindings/timer/mips,p8700-gcru.yaml new file mode 100644 index 0000000000000000000000000000000000000000..3498255762cce6b3f491292d340= d9639bb573e6d --- /dev/null +++ b/Documentation/devicetree/bindings/timer/mips,p8700-gcru.yaml @@ -0,0 +1,38 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/mips,p8700-gcru.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: GCR.U timer device for the MIPS P8700 platform + +maintainers: + - Aleksa Paunovic + +description: + The GCR.U memory region contains memory mapped shadow copies of + mtime and hrtime Global Configuration Registers, + which software can choose to make accessible from user mode. + +properties: + compatible: + const: mips,p8700-gcru + + reg: + items: + - description: Read-only shadow copy of the RISC-V mtime register. + - description: Read-only shadow copy of the P8700 high resolution ti= mer register. + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + timer@1617f000 { + compatible =3D "mips,p8700-gcru"; + reg =3D <0x1617f050 0x8>, + <0x1617f090 0x8>; + }; --=20 2.43.0 From nobody Thu Jun 11 00:36:12 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 443DC3164A1; Wed, 10 Jun 2026 08:22:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781079737; cv=none; b=L0v55bfooioSB3TjK5LgagdUzWZYqvL089r7HjsFiZZ9jDbyJoGjJZc7sG1cCu7b0SguUB+urflQVgKfILh/kFIeKxpn++/dyhq+C9z2LdM6Z5wcmYX5A3Q2QFjgeM0G6GNMkonuFm3zy8H1MAyOomYdX27t9VQ8+T8fsmzoPM8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781079737; c=relaxed/simple; bh=YSQJCU6UP8xSjWxbVovXreGZS/Xd6/2Gt8PJB5MgUBM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; 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Wed, 10 Jun 2026 08:22:16 +0000 (UTC) From: Aleksa Paunovic via B4 Relay Date: Wed, 10 Jun 2026 10:22:14 +0200 Subject: [PATCH v8 2/3] riscv: clocksource: Add readq options to clocksource mmio Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260610-riscv-time-mmio-v8-2-a865206675c6@htecgroup.com> References: <20260610-riscv-time-mmio-v8-0-a865206675c6@htecgroup.com> In-Reply-To: <20260610-riscv-time-mmio-v8-0-a865206675c6@htecgroup.com> To: Daniel Lezcano , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Paul Walmsley , John Stultz , Stephen Boyd , Vivian Wang Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Djordje Todorovic , Aleksa Paunovic , Chao-ying Fu X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1781079735; l=1938; i=aleksa.paunovic@htecgroup.com; s=20250806; h=from:subject:message-id; bh=xJr18GUgwDimiDlbxKI0yWHxvsNJAqXLsf1ztMWXw7U=; b=yv5D2RvaX+sHBRQBuSlIIRHz3jJTMIdXpatDDma79NEGCiv2+aRFC0J0r9pLUfMHguQVbone0 c0ySsuGxYzMDzaLESRDP3HwkEDEFXOW+38seVYnhH5YD5/qnmQ3mGGB X-Developer-Key: i=aleksa.paunovic@htecgroup.com; a=ed25519; pk=Dn4KMnDdgyhlXJNspQQrlHJ04i7/irG29p2H27Avd+8= X-Endpoint-Received: by B4 Relay for aleksa.paunovic@htecgroup.com/20250806 with auth_id=476 X-Original-From: Aleksa Paunovic Reply-To: aleksa.paunovic@htecgroup.com From: Aleksa Paunovic Add read functions for 64-bit register size to the generic mmio clocksource, covering both up and down counters. Signed-off-by: Aleksa Paunovic --- drivers/clocksource/mmio.c | 14 ++++++++++++++ include/linux/clocksource.h | 4 ++++ 2 files changed, 18 insertions(+) diff --git a/drivers/clocksource/mmio.c b/drivers/clocksource/mmio.c index 9de75153183124cc8997c6ab61d0c01d9b2637bc..f3b6f7e93ffbf0ed68e56c58c3d= 9f711d2193caa 100644 --- a/drivers/clocksource/mmio.c +++ b/drivers/clocksource/mmio.c @@ -17,6 +17,20 @@ static inline struct clocksource_mmio *to_mmio_clksrc(st= ruct clocksource *c) return container_of(c, struct clocksource_mmio, clksrc); } =20 +#if defined(CONFIG_64BIT) && defined(readq_relaxed) + +u64 clocksource_mmio_readq_up(struct clocksource *c) +{ + return (u64)readq_relaxed(to_mmio_clksrc(c)->reg); +} + +u64 clocksource_mmio_readq_down(struct clocksource *c) +{ + return ~(u64)readq_relaxed(to_mmio_clksrc(c)->reg) & c->mask; +} + +#endif + u64 clocksource_mmio_readl_up(struct clocksource *c) { return (u64)readl_relaxed(to_mmio_clksrc(c)->reg); diff --git a/include/linux/clocksource.h b/include/linux/clocksource.h index 65b7c41471c390463770c2da13694e58e83b84ea..39e0df5a0ab52cbb7016b53a4d7= 500f2697e2797 100644 --- a/include/linux/clocksource.h +++ b/include/linux/clocksource.h @@ -276,6 +276,10 @@ static inline void clocksource_arch_init(struct clocks= ource *cs) { } =20 extern int timekeeping_notify(struct clocksource *clock); =20 +#if defined(CONFIG_64BIT) && defined(readq_relaxed) +extern u64 clocksource_mmio_readq_up(struct clocksource *c); +extern u64 clocksource_mmio_readq_down(struct clocksource *c); +#endif extern u64 clocksource_mmio_readl_up(struct clocksource *); extern u64 clocksource_mmio_readl_down(struct clocksource *); extern u64 clocksource_mmio_readw_up(struct clocksource *); --=20 2.43.0 From nobody Thu Jun 11 00:36:12 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4E338383C64; Wed, 10 Jun 2026 08:22:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781079737; cv=none; b=Y1JD3wqXCRu9X8ece3AnRUCav4rcq/bbeNAYVH/sKg80Hor4m5QHQXV7T114ShTn/7NmgRZRSY48VHho+XWj5B0wugToMzqTnBCbfIZFpPe4TBu1gu8mpbvnn1Xet0KTj2RVKroxonGIaADnYR2B4Z9PjE3iKQiFrqkHjOUbSqk= ARC-Message-Signature: i=1; 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b=Zlr425dZrctCEuGpn628PkEr9kgJkuuucZhMiGPmwbNAO0uH9T6Yk5556we/hkZuh qHWLt2xNjhq5dXqOPL0neM253UUXPLx0RW6zUNYL7ARVJIeS96AoiaSZOJyiDbHBI2 ZZrQZMh3x9B2RWkds6cY41Mji7cjqManRAtmR5pNi8/UAMaoglzHfgWTP2mvAs7svd lqUUH6LA7m8nrsK7+LJOmcq2SRFxlqF5xLTVnYgv60grnEhSqDNOnpHjjBowKQzq2t W09omQUQck5iw02qhJRyRlvkGFMV5wjV1XMwBc/E85QNVVSzNrnPbnOAE/M89mzezI fs4ucf+1JBHPw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0E1DACD98C7; Wed, 10 Jun 2026 08:22:17 +0000 (UTC) From: Aleksa Paunovic via B4 Relay Date: Wed, 10 Jun 2026 10:22:15 +0200 Subject: [PATCH v8 3/3] riscv: clocksource: Add p8700-gcru driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260610-riscv-time-mmio-v8-3-a865206675c6@htecgroup.com> References: <20260610-riscv-time-mmio-v8-0-a865206675c6@htecgroup.com> In-Reply-To: <20260610-riscv-time-mmio-v8-0-a865206675c6@htecgroup.com> To: Daniel Lezcano , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Paul Walmsley , John Stultz , Stephen Boyd , Vivian Wang Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Djordje Todorovic , Aleksa Paunovic , Chao-ying Fu X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1781079735; l=3298; i=aleksa.paunovic@htecgroup.com; s=20250806; h=from:subject:message-id; bh=3gylppdlQket8tUc4qx/+ik8cQwg9RhMZJmHFwMxyPQ=; b=uDCOL6+Dxzcy5L1h16pwfheSZyHLGLn6ZfMU744la/Mt2QRAs94P4UDqL1hRtsHFlGO2ixIlJ bwKOisltlqTA6fGeffr0tonNYe8/lBFq6Psx8FwKL4QzDJoQHJc7M3A X-Developer-Key: i=aleksa.paunovic@htecgroup.com; a=ed25519; pk=Dn4KMnDdgyhlXJNspQQrlHJ04i7/irG29p2H27Avd+8= X-Endpoint-Received: by B4 Relay for aleksa.paunovic@htecgroup.com/20250806 with auth_id=476 X-Original-From: Aleksa Paunovic Reply-To: aleksa.paunovic@htecgroup.com From: Aleksa Paunovic Add a clocksource driver for the P8700 GCRU. Initialization uses helper functions provided by clocksource/mmio.c and timer-of.c. Since the GCRU does not support any kind of interrupts, the default RISC-V clockevent implementation should suffice. Signed-off-by: Aleksa Paunovic --- drivers/clocksource/Kconfig | 9 ++++++++ drivers/clocksource/Makefile | 1 + drivers/clocksource/timer-p8700.c | 47 +++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 57 insertions(+) diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index ffcd23668763fe7707a4e917bf240caadbb09a8c..a775a301f3f08ca97699e46aaf3= ccfaf99734e6b 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -672,6 +672,15 @@ config CLINT_TIMER This option enables the CLINT timer for RISC-V systems. The CLINT driver is usually used for NoMMU RISC-V systems. =20 +config P8700_TIMER + bool "MIPS P8700 timer driver" + depends on GENERIC_SCHED_CLOCK && RISCV && RISCV_SBI && 64BIT + select CLKSRC_MMIO + select TIMER_PROBE + select TIMER_OF + help + Enables support for MIPS P8700 timer driver. + config CSKY_MP_TIMER bool "SMP Timer for the C-SKY platform" if COMPILE_TEST depends on CSKY diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile index ec4452ee958f1a814c708aeba6412bea61d24892..fae9a58d6c8663a7c857b9ab7fd= ae05782b3551c 100644 --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile @@ -95,3 +95,4 @@ obj-$(CONFIG_CLKSRC_LOONGSON1_PWM) +=3D timer-loongson1-p= wm.o obj-$(CONFIG_EP93XX_TIMER) +=3D timer-ep93xx.o obj-$(CONFIG_RALINK_TIMER) +=3D timer-ralink.o obj-$(CONFIG_NXP_STM_TIMER) +=3D timer-nxp-stm.o +obj-$(CONFIG_P8700_TIMER) +=3D timer-p8700.o diff --git a/drivers/clocksource/timer-p8700.c b/drivers/clocksource/timer-= p8700.c new file mode 100644 index 0000000000000000000000000000000000000000..dd20b4e72fcdd77a6b33775f286= d0945c2a2b659 --- /dev/null +++ b/drivers/clocksource/timer-p8700.c @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2025 MIPS. + */ + +#include +#include +#include +#include +#include +#include + +#include "timer-of.h" + +static struct timer_of gcru_of =3D { .flags =3D TIMER_OF_BASE }; +static u64 __iomem *p8700_time_val __ro_after_init; + +static u64 notrace p8700_timer_sched_read(void) +{ + return (u64)readq_relaxed(p8700_time_val); +} + +static int __init p8700_timer_init(struct device_node *node) +{ + int error =3D 0; + + error =3D timer_of_init(node, &gcru_of); + if (error) + return error; + + p8700_time_val =3D timer_of_base(&gcru_of); + /* Now init the mmio timer with the address we got from DT */ + error =3D clocksource_mmio_init(p8700_time_val, "mips,p8700-gcru", + riscv_timebase, 450, 64, + clocksource_mmio_readq_up); + if (error) { + timer_of_cleanup(&gcru_of); + return error; + } + + /* Sched clock */ + sched_clock_register(p8700_timer_sched_read, 64, riscv_timebase); + + return error; +} + +TIMER_OF_DECLARE(p8700_timer, "mips,p8700-gcru", p8700_timer_init); --=20 2.43.0