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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2c24edc8acasm114618175ad.45.2026.06.10.01.51.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jun 2026 01:51:59 -0700 (PDT) From: Pragnesh Papaniya Date: Wed, 10 Jun 2026 14:21:28 +0530 Subject: [PATCH RFC v7 1/9] firmware: arm_scmi: Add QCOM Generic Vendor Protocol documentation Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260610-rfc_v7_scmi_memlat-v7-1-f3f68c608f25@oss.qualcomm.com> References: <20260610-rfc_v7_scmi_memlat-v7-0-f3f68c608f25@oss.qualcomm.com> In-Reply-To: <20260610-rfc_v7_scmi_memlat-v7-0-f3f68c608f25@oss.qualcomm.com> To: Sudeep Holla , Cristian Marussi , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sibi Sankar , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Dmitry Osipenko , Thierry Reding , Jonathan Hunter , Bjorn Andersson , Konrad Dybcio Cc: Pragnesh Papaniya , Rajendra Nayak , Pankaj Patil , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, arm-scmi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1781081505; l=40905; i=pragnesh.papaniya@oss.qualcomm.com; s=20260120; h=from:subject:message-id; bh=zvgtiOY9qUjQklvu4UM79+owpYtVrSbxEet9NtPp8R4=; b=GAtvnH7zwKmTtSpg2u3qO2YkWuFKMbIpUbicIcK2WPrXvry2dJ3dtB15O4IQTevm4lfj6aryw u+apweTqsJ2A9L7vaRb9dYU9zhUGs8jD0c05XqEVTTqST1tiWk0NRia X-Developer-Key: i=pragnesh.papaniya@oss.qualcomm.com; a=ed25519; pk=09P9nFmZLXJ9+4Jx10ZK5rIW0Fmk79A/DLErm6aVA0c= X-Authority-Analysis: v=2.4 cv=Gu1yPE1C c=1 sm=1 tr=0 ts=6a2925b2 cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=EUspDBNiAAAA:8 a=TLQOcO4xEgnVrnW6FtgA:9 a=QEXdDO2ut3YA:10 a=uG9DUKGECoFWVXl0Dc02:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjEwMDA4MyBTYWx0ZWRfXyr/KzbacVHTe QZcGPrguzrI+CYMCacoNJplS1+KaAok7MoInlrBAzQTUJ9M52NA1lJQ2OOr2T1tpnRYQVoIB2ZZ ZFpS/DNz80I/OQJdeasTcb6Crw8X8nWST/6g9zM1NdFkAYJ7n+IfmyQWXHm2J8R0edHY6yrqR3u OPIhp2+19x62KPWDQNfPbBkS/9klFfkp2XZGgtPKum044zWbJTmNRucpKJPj+pTPHa/RgDWm5F+ jA04LjPtpj2SAgg+pjTes96U2SmTD08Fch0CI1cWoWk8Mo1woXBQmT5UMzmXP0emT7G3CwJCmzJ Ki04dlLq1F8Z2pQ1H+DkDSiG4ckh7HhWSj25nqHbjMrYaUOhgBzPGAqdRuEzXJ1egPC99M3Y1va P15YGcbGbwE4+Tr9yBmtFTfbc2rGiHWj3CplTERbSGuugHt5H3MHXN13o9gKLc7uweDo3NCtqZo Pbshru2crc9U1Ru/LGQ== X-Proofpoint-ORIG-GUID: rsV2bqqYB7_h2h_ILTuyCNyf95SIc_Nz X-Proofpoint-GUID: rsV2bqqYB7_h2h_ILTuyCNyf95SIc_Nz X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-10_02,2026-06-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 lowpriorityscore=0 suspectscore=0 phishscore=0 adultscore=0 clxscore=1015 spamscore=0 bulkscore=0 malwarescore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605210000 definitions=main-2606100083 From: Sibi Sankar Add QCOM System Control Management Interface (SCMI) Generic Vendor Extensions Protocol documentation. It exposes Qualcomm SoC-specific features through (algorithm string, param_id) pairs carried over a small set of generic SET/GET/START/STOP commands, alongside the standard PROTOCOL_VERSION / _ATTRIBUTES / _MESSAGE_ATTRIBUTES handshake required by the Arm SCMI specification. Document the protocol so that drivers targeting it have a stable reference for command ids, payload layouts and status code semantics. The first algorithm covered is MEMLAT (memory latency governor), including its memory-group model (DDR, LLCC, DDR_QOS), event-map programming and per- monitor frequency voting tables. Signed-off-by: Sibi Sankar Co-developed-by: Pragnesh Papaniya Signed-off-by: Pragnesh Papaniya --- .../arm_scmi/vendors/qcom/qcom_generic.rst | 647 +++++++++++++++++= ++++ 1 file changed, 647 insertions(+) diff --git a/drivers/firmware/arm_scmi/vendors/qcom/qcom_generic.rst b/driv= ers/firmware/arm_scmi/vendors/qcom/qcom_generic.rst new file mode 100644 index 000000000000..ba0c64729790 --- /dev/null +++ b/drivers/firmware/arm_scmi/vendors/qcom/qcom_generic.rst @@ -0,0 +1,647 @@ +.. SPDX-License-Identifier: GPL-2.0 +.. include:: + +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D +QCOM System Control and Management Interface(SCMI) Vendor Protocols Extens= ion +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D + +:Copyright: |copy| Qualcomm Technologies, Inc. and/or its subsidiaries. + +:Author: + - Sibi Sankar + - Pragnesh Papaniya + +SCMI_GENERIC: System Control and Management Interface QCOM Generic Vendor = Protocol +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D + +This protocol is intended as a generic way of exposing a number of Qualcomm +SoC specific features through a mixture of pre-determined algorithm string= and +param_id pairs hosted on the SCMI controller. It implements an interface c= ompliant +with the Arm SCMI Specification with additional vendor specific commands as +detailed below. + +Supported algorithm strings are documented in their own sections after the +generic commands (currently: MEMLAT, see below). + +Commands: +_________ + +PROTOCOL_VERSION +~~~~~~~~~~~~~~~~ + +message_id: 0x0 +protocol_id: 0x80 + ++---------------+---------------------------------------------------------= -----+ +|Return values = | ++---------------+---------------------------------------------------------= -----+ +|Name |Description = | ++---------------+---------------------------------------------------------= -----+ +|int32 status |See ARM SCMI Specification for status code definitions. = | ++---------------+---------------------------------------------------------= -----+ +|uint32 version |For this revision of the specification, this value must b= e | +| |0x10000. = | ++---------------+---------------------------------------------------------= -----+ + +PROTOCOL_ATTRIBUTES +~~~~~~~~~~~~~~~~~~~ + +message_id: 0x1 +protocol_id: 0x80 + ++------------------+------------------------------------------------------= -----+ +|Return values = | ++------------------+------------------------------------------------------= -----+ +|Name |Description = | ++------------------+------------------------------------------------------= -----+ +|int32 status |See ARM SCMI Specification for status code definitions= . | ++------------------+------------------------------------------------------= -----+ +|uint32 attributes |Bits[31:16] Reserved, must be set to 0. = | +| |Bits[15:8] Number of agents in the system. Must match = the | +| |value reported by the standard BASE protocol's = | +| |PROTOCOL_ATTRIBUTES response. = | +| |Bits[7:0] Number of algorithmic strings supported by t= he | +| |system. Only "MEMLAT" is currently supported hence it = | +| |returns 1. = | ++------------------+------------------------------------------------------= -----+ + +PROTOCOL_MESSAGE_ATTRIBUTES +~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +message_id: 0x2 +protocol_id: 0x80 + ++------------------+------------------------------------------------------= -----+ +|Return values = | ++------------------+------------------------------------------------------= -----+ +|Name |Description = | ++------------------+------------------------------------------------------= -----+ +|int32 status |See ARM SCMI Specification for status code definitions= . | ++------------------+------------------------------------------------------= -----+ +|uint32 attributes |For all message IDs the parameter has a value of 0. = | ++------------------+------------------------------------------------------= -----+ + +QCOM_SCMI_SET_PARAM +~~~~~~~~~~~~~~~~~~~ + +message_id: 0x10 +protocol_id: 0x80 + ++------------------+------------------------------------------------------= -----+ +|Parameters = | ++------------------+------------------------------------------------------= -----+ +|Name |Description = | ++------------------+------------------------------------------------------= -----+ +|uint32 ext_id |Reserved, must be zero. = | ++------------------+------------------------------------------------------= -----+ +|uint32 algo_low |Lower 32-bit value of the algorithm string. = | ++------------------+------------------------------------------------------= -----+ +|uint32 algo_high |Upper 32-bit value of the algorithm string. = | ++------------------+------------------------------------------------------= -----+ +|uint32 param_id |Serves as the token message id for the algorithm strin= g | +| |and is used to set various parameters supported by it.= | ++------------------+------------------------------------------------------= -----+ +|uint32 buf[] |Serves as the payload for the specified param_id and = | +| |algorithm string pair. The payload size depends on the= | +| |(algorithm string, param_id) pair; see the per-algorit= hm | +| |sections below. = | ++------------------+------------------------------------------------------= -----+ +|Return values = | ++------------------+------------------------------------------------------= -----+ +|Name |Description = | ++------------------+------------------------------------------------------= -----+ +|int32 status |SUCCESS: if the param_id and buf[] is parsed successfu= lly | +| |by the chosen algorithm string. = | +| |NOT_SUPPORTED: if the algorithm string does not have a= ny | +| |matches. = | +| |INVALID_PARAMETERS: if the param_id and the buf[] pass= ed | +| |is rejected by the algorithm string. = | ++------------------+------------------------------------------------------= -----+ + +QCOM_SCMI_GET_PARAM +~~~~~~~~~~~~~~~~~~~ + +message_id: 0x11 +protocol_id: 0x80 + ++------------------+------------------------------------------------------= -----+ +|Parameters = | ++------------------+------------------------------------------------------= -----+ +|Name |Description = | ++------------------+------------------------------------------------------= -----+ +|uint32 ext_id |Reserved, must be zero. = | ++------------------+------------------------------------------------------= -----+ +|uint32 algo_low |Lower 32-bit value of the algorithm string. = | ++------------------+------------------------------------------------------= -----+ +|uint32 algo_high |Upper 32-bit value of the algorithm string. = | ++------------------+------------------------------------------------------= -----+ +|uint32 param_id |Serves as the token message id for the algorithm strin= g. | ++------------------+------------------------------------------------------= -----+ +|uint32 buf[] |Serves as the payload and store of value for the speci= fied | +| |param_id and algorithm string pair. The payload size = | +| |depends on the (algorithm string, param_id) pair; see = the | +| |per-algorithm sections below. The response payload is = | +| |returned in the same buffer, overwriting the request = | +| |contents on success. = | ++------------------+------------------------------------------------------= -----+ +|Return values = | ++------------------+------------------------------------------------------= -----+ +|Name |Description = | ++------------------+------------------------------------------------------= -----+ +|int32 status |SUCCESS: if the param_id and buf[] is parsed successfu= lly | +| |by the chosen algorithm string and the result is copie= d | +| |into buf[]. = | +| |NOT_SUPPORTED: if the algorithm string does not have a= ny | +| |matches. = | +| |INVALID_PARAMETERS: if the param_id and the buf[] pass= ed | +| |is rejected by the algorithm string. = | ++------------------+------------------------------------------------------= -----+ +|uint32 buf[] |Holds the payload of the result of the query, returned= in | +| |the same buffer used to send the request. Size depends= on | +| |the (algorithm string, param_id) pair. = | ++------------------+------------------------------------------------------= -----+ + +QCOM_SCMI_START_ACTIVITY +~~~~~~~~~~~~~~~~~~~~~~~~ + +message_id: 0x12 +protocol_id: 0x80 + +The activity to be started is defined by the algorithm string; see the +per-algorithm sections (e.g. MEMLAT_START_TIMER) for valid param_ids. + ++------------------+------------------------------------------------------= -----+ +|Parameters = | ++------------------+------------------------------------------------------= -----+ +|Name |Description = | ++------------------+------------------------------------------------------= -----+ +|uint32 ext_id |Reserved, must be zero. = | ++------------------+------------------------------------------------------= -----+ +|uint32 algo_low |Lower 32-bit value of the algorithm string. = | ++------------------+------------------------------------------------------= -----+ +|uint32 algo_high |Upper 32-bit value of the algorithm string. = | ++------------------+------------------------------------------------------= -----+ +|uint32 param_id |Serves as the token message id for the algorithm strin= g | +| |and is generally used to start the activity performed = by | +| |the algorithm string. = | ++------------------+------------------------------------------------------= -----+ +|uint32 buf[] |Serves as the payload for the specified param_id and = | +| |algorithm string pair. The payload size depends on the= | +| |(algorithm string, param_id) pair; see the per-algorit= hm | +| |sections below. = | ++------------------+------------------------------------------------------= -----+ +|Return values = | ++------------------+------------------------------------------------------= -----+ +|Name |Description = | ++------------------+------------------------------------------------------= -----+ +|int32 status |SUCCESS: if the activity performed by the algorithm st= ring | +| |starts successfully, or if it was already running. = | +| |NOT_SUPPORTED: if the algorithm string does not have a= ny | +| |matches. = | ++------------------+------------------------------------------------------= -----+ + +QCOM_SCMI_STOP_ACTIVITY +~~~~~~~~~~~~~~~~~~~~~~~ + +message_id: 0x13 +protocol_id: 0x80 + +The activity to be stopped is defined by the algorithm string; see the +per-algorithm sections (e.g. MEMLAT_STOP_TIMER) for valid param_ids. + ++------------------+------------------------------------------------------= -----+ +|Parameters = | ++------------------+------------------------------------------------------= -----+ +|Name |Description = | ++------------------+------------------------------------------------------= -----+ +|uint32 ext_id |Reserved, must be zero. = | ++------------------+------------------------------------------------------= -----+ +|uint32 algo_low |Lower 32-bit value of the algorithm string. = | ++------------------+------------------------------------------------------= -----+ +|uint32 algo_high |Upper 32-bit value of the algorithm string. = | ++------------------+------------------------------------------------------= -----+ +|uint32 param_id |Serves as the token message id for the algorithm strin= g | +| |and is generally used to stop the activity performed b= y | +| |the algorithm string. = | ++------------------+------------------------------------------------------= -----+ +|uint32 buf[] |Serves as the payload for the specified param_id and = | +| |algorithm string pair. The payload size depends on the= | +| |(algorithm string, param_id) pair; see the per-algorit= hm | +| |sections below. = | ++------------------+------------------------------------------------------= -----+ +|Return values = | ++------------------+------------------------------------------------------= -----+ +|Name |Description = | ++------------------+------------------------------------------------------= -----+ +|int32 status |SUCCESS: if the activity performed by the algorithm st= ring | +| |stops successfully, or if it was not running. = | +| |NOT_SUPPORTED: if the algorithm string does not have a= ny | +| |matches. = | ++------------------+------------------------------------------------------= -----+ + +MEMLAT: Memory Latency algorithm +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D + +The MEMLAT algorithm string (0x4D454D4C4154, ASCII "MEMLAT") is hosted on +the Qualcomm Generic Vendor Protocol and runs on the CPUCP firmware. The +6-byte value is treated as a 64-bit algorithm string and split into two +uint32 fields on the wire: algo_low carries its lower 32 bits and algo_high +its upper 32 bits. +It samples per-CPU performance counters at a configurable period, computes +per memory-group statistics (Instructions-Per-Miss, back-end stall, etc.), +and votes the resulting target frequency to the bus interconnect for DDR, +LLCC and DDR_QOS. Userspace control of the algorithm is exposed via +parameter IDs issued through QCOM_SCMI_SET_PARAM and QCOM_SCMI_GET_PARAM. + +The hw_type field carried in most payloads identifies the memory group: + ++----------+--------------------------------------------------------------+ +|hw_type |Group | ++----------+--------------------------------------------------------------+ +|0 |DDR | ++----------+--------------------------------------------------------------+ +|1 |LLCC | ++----------+--------------------------------------------------------------+ +|2 |DDR_QOS | ++----------+--------------------------------------------------------------+ + +All multi-byte fields below are little-endian, in line with the SCMI +specification. mon_idx selects a monitor within the group (0-based, less +than the firmware-supported maximum). All SET commands return the SCMI +status word; on success it carries SUCCESS, on lookup failure +INVALID_PARAMETERS, and on an unknown param_id NOT_SUPPORTED. + +Frequency units differ per command: MEMLAT_SET_MIN_FREQ and +MEMLAT_SET_MAX_FREQ take kHz for DDR/LLCC, whereas MEMLAT_MON_FREQ_MAP +expresses the resulting vote (v2) in MHz for DDR/LLCC. For DDR_QOS all of +these carry a raw level index (0 / 1) rather than a frequency. + +MEMLAT_SET_MEM_GROUP +~~~~~~~~~~~~~~~~~~~~ + +param_id: 0x10 (16) +command: QCOM_SCMI_SET_PARAM + +Allocates a new memory group on the firmware side and binds it to the +underlying interconnect path (DDR / LLCC / DDR_QOS). + ++------------------+------------------------------------------------------= -----+ +|Parameters = | ++------------------+------------------------------------------------------= -----+ +|Name |Description = | ++------------------+------------------------------------------------------= -----+ +|uint32 cpumask |Bitmask of HW CPU IDs that contribute counters to this= | +| |group (limited to 32 CPUs). = | ++------------------+------------------------------------------------------= -----+ +|uint32 hw_type |Memory group identifier (0 =3D DDR, 1 =3D LLCC, 2 =3D = DDR_QOS). | ++------------------+------------------------------------------------------= -----+ +|uint32 mon_type |Reserved for SET_MEM_GROUP (set to 0; populated only o= n | +| |SET_MONITOR). = | ++------------------+------------------------------------------------------= -----+ +|uint32 mon_idx |Reserved for SET_MEM_GROUP (set to 0). = | ++------------------+------------------------------------------------------= -----+ +|char mon_name[20] |Reserved for SET_MEM_GROUP (zero-filled). = | ++------------------+------------------------------------------------------= -----+ +|Return values = | ++------------------+------------------------------------------------------= -----+ +|int32 status |SUCCESS: group allocated. = | +| |BUSY: no free memory group slot (the firmware-supporte= d | +| |maximum number of groups is already configured). = | ++------------------+------------------------------------------------------= -----+ + +MEMLAT_SET_MONITOR +~~~~~~~~~~~~~~~~~~ + +param_id: 0x11 (17) +command: QCOM_SCMI_SET_PARAM + +Adds a monitor (a CPU subset that votes within an already-configured +group). + ++------------------+------------------------------------------------------= -----+ +|Parameters = | ++------------------+------------------------------------------------------= -----+ +|Name |Description = | ++------------------+------------------------------------------------------= -----+ +|uint32 cpumask |Bitmask of HW CPU IDs assigned to this monitor (must b= e a | +| |subset of the group's cpumask; limited to 32 CPUs). = | ++------------------+------------------------------------------------------= -----+ +|uint32 hw_type |Memory group identifier the monitor belongs to. = | ++------------------+------------------------------------------------------= -----+ +|uint32 mon_type |0 =3D IPM-based latency monitor, 1 =3D compute (stall-= only) | +| |monitor. = | ++------------------+------------------------------------------------------= -----+ +|uint32 mon_idx |Index of the monitor within the group. = | ++------------------+------------------------------------------------------= -----+ +|char mon_name[20] |Human-readable monitor name (NUL-terminated, used in = | +| |firmware log lines). = | ++------------------+------------------------------------------------------= -----+ +|Return values = | ++------------------+------------------------------------------------------= -----+ +|int32 status |SUCCESS: monitor created. = | +| |NOT_FOUND: hw_type does not match any configured group= , or | +| |the firmware-supported maximum number of monitors alre= ady | +| |exist for the group. = | ++------------------+------------------------------------------------------= -----+ + +MEMLAT_SET_COMMON_EV_MAP +~~~~~~~~~~~~~~~~~~~~~~~~ + +param_id: 0x12 (18) +command: QCOM_SCMI_SET_PARAM + +Configures the common counter IDs (instructions, cycles, stall, etc.) +that the firmware reads on every sample for every CPU. + ++------------------+------------------------------------------------------= -----+ +|Parameters = | ++------------------+------------------------------------------------------= -----+ +|Name |Description = | ++------------------+------------------------------------------------------= -----+ +|uint32 num_evs |Number of valid entries in cid[]. = | ++------------------+------------------------------------------------------= -----+ +|uint32 hw_type |Set to 0xFF (sentinel for the common-events case). = | ++------------------+------------------------------------------------------= -----+ +|uint8 cid[] |Array of CPUCP counter IDs indexed by INST/CYC/CONST_C= YC/ | +| |FE_STALL/BE_STALL. 0xFF marks an unused slot. = | ++------------------+------------------------------------------------------= -----+ +|Return values = | ++------------------+------------------------------------------------------= -----+ +|int32 status |SUCCESS / INVALID_PARAMETERS if num_evs exceeds the = | +| |firmware-supported maximum. = | ++------------------+------------------------------------------------------= -----+ + +MEMLAT_SET_GRP_EV_MAP +~~~~~~~~~~~~~~~~~~~~~ + +param_id: 0x13 (19) +command: QCOM_SCMI_SET_PARAM + +Configures the per-group event IDs (cache miss / writeback / access) +used by the IPM and write-back computations for the selected hw_type. + ++------------------+------------------------------------------------------= -----+ +|Parameters = | ++------------------+------------------------------------------------------= -----+ +|Name |Description = | ++------------------+------------------------------------------------------= -----+ +|uint32 num_evs |Number of valid entries in cid[]. = | ++------------------+------------------------------------------------------= -----+ +|uint32 hw_type |Memory group identifier. = | ++------------------+------------------------------------------------------= -----+ +|uint8 cid[] |Array of CPUCP counter IDs indexed by MISS/WB/ACC. 0xF= F | +| |marks an unused slot. = | ++------------------+------------------------------------------------------= -----+ +|Return values = | ++------------------+------------------------------------------------------= -----+ +|int32 status |SUCCESS / INVALID_PARAMETERS if hw_type is unknown or = | +| |num_evs exceeds the firmware-supported maximum. = | ++------------------+------------------------------------------------------= -----+ + +MEMLAT_IPM_CEIL +~~~~~~~~~~~~~~~ + +param_id: 0x17 (23) +command: QCOM_SCMI_SET_PARAM + +Sets the IPM (Instructions-Per-Miss) ceiling for a monitor. CPUs whose +IPM falls at or below this ceiling are considered memory-bound and +contribute their cpufreq into the monitor's voting pool. + ++------------------+------------------------------------------------------= -----+ +|Parameters = | ++------------------+------------------------------------------------------= -----+ +|Name |Description = | ++------------------+------------------------------------------------------= -----+ +|uint32 hw_type |Memory group identifier. = | ++------------------+------------------------------------------------------= -----+ +|uint32 mon_idx |Monitor index within the group. = | ++------------------+------------------------------------------------------= -----+ +|uint32 val |IPM ceiling (instructions per cache miss). = | ++------------------+------------------------------------------------------= -----+ +|Return values = | ++------------------+------------------------------------------------------= -----+ +|int32 status |SUCCESS / INVALID_PARAMETERS if (hw_type, mon_idx) doe= s | +| |not match a registered monitor. = | ++------------------+------------------------------------------------------= -----+ + +MEMLAT_BE_STALL_FLOOR +~~~~~~~~~~~~~~~~~~~~~ + +param_id: 0x19 (25) +command: QCOM_SCMI_SET_PARAM + +Sets the back-end stall floor (in milli-percent: 100000 =3D 100%) for a +monitor. CPUs whose back-end stall is at or above this floor are +eligible to contribute their cpufreq even if their IPM is above the +ceiling. + ++------------------+------------------------------------------------------= -----+ +|Parameters = | ++------------------+------------------------------------------------------= -----+ +|Name |Description = | ++------------------+------------------------------------------------------= -----+ +|uint32 hw_type |Memory group identifier. = | ++------------------+------------------------------------------------------= -----+ +|uint32 mon_idx |Monitor index within the group. = | ++------------------+------------------------------------------------------= -----+ +|uint32 val |Back-end stall floor in milli-percent (0..100000). = | ++------------------+------------------------------------------------------= -----+ +|Return values = | ++------------------+------------------------------------------------------= -----+ +|int32 status |SUCCESS / INVALID_PARAMETERS if (hw_type, mon_idx) doe= s | +| |not match a registered monitor. = | ++------------------+------------------------------------------------------= -----+ + +MEMLAT_SAMPLE_MS +~~~~~~~~~~~~~~~~ + +param_id: 0x1F (31) +command: QCOM_SCMI_SET_PARAM + +Sets the sampling period (in milliseconds) used by the firmware update +loop. + ++------------------+------------------------------------------------------= -----+ +|Parameters = | ++------------------+------------------------------------------------------= -----+ +|Name |Description = | ++------------------+------------------------------------------------------= -----+ +|int32 sample_ms |Sampling period in milliseconds. = | ++------------------+------------------------------------------------------= -----+ +|Return values = | ++------------------+------------------------------------------------------= -----+ +|int32 status |SUCCESS. = | ++------------------+------------------------------------------------------= -----+ + +MEMLAT_MON_FREQ_MAP +~~~~~~~~~~~~~~~~~~~ + +param_id: 0x20 (32) +command: QCOM_SCMI_SET_PARAM + +Programs the cpufreq to memfreq voting table for a single monitor. + ++------------------+------------------------------------------------------= -----+ +|Parameters = | ++------------------+------------------------------------------------------= -----+ +|Name |Description = | ++------------------+------------------------------------------------------= -----+ +|uint32 hw_type |Memory group identifier. = | ++------------------+------------------------------------------------------= -----+ +|uint32 mon_idx |Monitor index within the group. = | ++------------------+------------------------------------------------------= -----+ +|uint32 nr_rows |Number of valid rows in tbl[] (must not exceed the = | +| |firmware-supported maximum). = | ++------------------+------------------------------------------------------= -----+ +|struct { |Per-row mapping. v1 is the cpufreq trigger in MHz; v2 = is | +| uint16 v1; |the resulting memfreq vote (MHz for DDR/LLCC, a level = | +| uint16 v2; |index 0/1 for DDR_QOS). = | +|} tbl[] | = | ++------------------+------------------------------------------------------= -----+ +|Return values = | ++------------------+------------------------------------------------------= -----+ +|int32 status |SUCCESS / INVALID_PARAMETERS if (hw_type, mon_idx) is = | +| |unknown / OUT_OF_RANGE if nr_rows exceeds the = | +| |firmware-supported maximum. = | ++------------------+------------------------------------------------------= -----+ + +MEMLAT_SET_MIN_FREQ +~~~~~~~~~~~~~~~~~~~ + +param_id: 0x21 (33) +command: QCOM_SCMI_SET_PARAM + +Clamps a monitor's vote to a minimum value. Units are kHz for DDR/LLCC and +raw level index for DDR_QOS. + ++------------------+------------------------------------------------------= -----+ +|Parameters = | ++------------------+------------------------------------------------------= -----+ +|Name |Description = | ++------------------+------------------------------------------------------= -----+ +|uint32 hw_type |Memory group identifier. = | ++------------------+------------------------------------------------------= -----+ +|uint32 mon_idx |Monitor index within the group. = | ++------------------+------------------------------------------------------= -----+ +|uint32 val |Minimum frequency: kHz for DDR/LLCC, level for DDR_QOS= . | ++------------------+------------------------------------------------------= -----+ +|Return values = | ++------------------+------------------------------------------------------= -----+ +|int32 status |SUCCESS / INVALID_PARAMETERS if (hw_type, mon_idx) doe= s | +| |not match a registered monitor. = | ++------------------+------------------------------------------------------= -----+ + +MEMLAT_SET_MAX_FREQ +~~~~~~~~~~~~~~~~~~~ + +param_id: 0x22 (34) +command: QCOM_SCMI_SET_PARAM + +Clamps a monitor's vote to a maximum value. Units identical to +MEMLAT_SET_MIN_FREQ. + ++------------------+------------------------------------------------------= -----+ +|Parameters = | ++------------------+------------------------------------------------------= -----+ +|Name |Description = | ++------------------+------------------------------------------------------= -----+ +|uint32 hw_type |Memory group identifier. = | ++------------------+------------------------------------------------------= -----+ +|uint32 mon_idx |Monitor index within the group. = | ++------------------+------------------------------------------------------= -----+ +|uint32 val |Maximum frequency: kHz for DDR/LLCC, level for DDR_QOS= . | ++------------------+------------------------------------------------------= -----+ +|Return values = | ++------------------+------------------------------------------------------= -----+ +|int32 status |SUCCESS / INVALID_PARAMETERS if (hw_type, mon_idx) doe= s | +| |not match a registered monitor. = | ++------------------+------------------------------------------------------= -----+ + +MEMLAT_GET_CUR_FREQ +~~~~~~~~~~~~~~~~~~~ + +param_id: 0x23 (35) +command: QCOM_SCMI_GET_PARAM + +Reads the current target frequency that the firmware is voting for the +selected (hw_type, mon_idx) tuple. The response payload is returned in +the same buffer used to send the request, overwriting it on success. + ++------------------+------------------------------------------------------= -----+ +|Parameters = | ++------------------+------------------------------------------------------= -----+ +|Name |Description = | ++------------------+------------------------------------------------------= -----+ +|uint32 hw_type |Memory group identifier. = | ++------------------+------------------------------------------------------= -----+ +|uint32 mon_idx |Monitor index within the group. = | ++------------------+------------------------------------------------------= -----+ +|Return values = | ++------------------+------------------------------------------------------= -----+ +|int32 status |SUCCESS / INVALID_PARAMETERS if (hw_type, mon_idx) doe= s | +| |not match a registered monitor. = | ++------------------+------------------------------------------------------= -----+ +|uint32 cur_freq |Current target frequency in kHz for DDR/LLCC; raw leve= l | +| |(0/1) for DDR_QOS. = | ++------------------+------------------------------------------------------= -----+ + +MEMLAT_START_TIMER +~~~~~~~~~~~~~~~~~~ + +param_id: 0x24 (36) +command: QCOM_SCMI_START_ACTIVITY + +Starts the firmware sampling and voting loop at the configured +sample_ms interval. Has no payload beyond the QCOM_SCMI_START_ACTIVITY +header. + ++------------------+------------------------------------------------------= -----+ +|Return values = | ++------------------+------------------------------------------------------= -----+ +|int32 status |SUCCESS: timer started (or was already running). = | +| |GENERIC_ERROR: events not yet initialized = | +| |(MEMLAT_SET_GRP_EV_MAP not called for any group). = | +| |NOT_SUPPORTED: invalid param_id under START_ACTIVITY. = | ++------------------+------------------------------------------------------= -----+ + +MEMLAT_STOP_TIMER +~~~~~~~~~~~~~~~~~ + +param_id: 0x25 (37) +command: QCOM_SCMI_STOP_ACTIVITY + +Suspends the firmware sampling and voting loop. Has no payload beyond +the QCOM_SCMI_STOP_ACTIVITY header. The configured monitors and freq +maps are retained, so a subsequent MEMLAT_START_TIMER resumes voting +without re-programming. + ++------------------+------------------------------------------------------= -----+ +|Return values = | ++------------------+------------------------------------------------------= -----+ +|int32 status |SUCCESS: timer stopped (or was already stopped). = | +| |NOT_SUPPORTED: invalid param_id under STOP_ACTIVITY. = | ++------------------+------------------------------------------------------= -----+ + +MEMLAT_SET_EFFECTIVE_FREQ_METHOD +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +param_id: 0x27 (39) +command: QCOM_SCMI_SET_PARAM + +Selects the algorithm used to derive the per-CPU effective frequency +from the cycle counters. + ++------------------+------------------------------------------------------= -----+ +|Parameters = | ++------------------+------------------------------------------------------= -----+ +|Name |Description = | ++------------------+------------------------------------------------------= -----+ +|int32 method |0: const-cycles method (CPU cycles / const-cycles, sca= led | +| |by the cluster's max frequency). = | +| |1: legacy method (CPU cycles / sampling-window time). = | ++------------------+------------------------------------------------------= -----+ +|Return values = | ++------------------+------------------------------------------------------= -----+ +|int32 status |SUCCESS / INVALID_PARAMETERS if method is not 0 or 1. = | ++------------------+------------------------------------------------------= -----+ --=20 2.34.1 From nobody Fri Jul 24 21:55:29 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EFEF03B14B6 for ; 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Signed-off-by: Pragnesh Papaniya --- .../devicetree/bindings/firmware/arm,scmi.yaml | 1 + .../bindings/firmware/qcom,generic-scmi.yaml | 27 ++++++++++++++++++= ++++ 2 files changed, 28 insertions(+) diff --git a/Documentation/devicetree/bindings/firmware/arm,scmi.yaml b/Doc= umentation/devicetree/bindings/firmware/arm,scmi.yaml index d06cca9273c4..aedc57dd3b38 100644 --- a/Documentation/devicetree/bindings/firmware/arm,scmi.yaml +++ b/Documentation/devicetree/bindings/firmware/arm,scmi.yaml @@ -24,6 +24,7 @@ description: | =20 anyOf: - $ref: /schemas/firmware/nxp,imx95-scmi.yaml + - $ref: /schemas/firmware/qcom,generic-scmi.yaml =20 properties: $nodename: diff --git a/Documentation/devicetree/bindings/firmware/qcom,generic-scmi.y= aml b/Documentation/devicetree/bindings/firmware/qcom,generic-scmi.yaml new file mode 100644 index 000000000000..077653dc1cda --- /dev/null +++ b/Documentation/devicetree/bindings/firmware/qcom,generic-scmi.yaml @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/firmware/qcom,generic-scmi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm System Control and Management Interface(SCMI) Vendor Proto= cols Extension + +maintainers: + - Sibi Sankar + - Pragnesh Papaniya + +properties: + protocol@80: + description: + SCMI Qualcomm Generic Vendor Protocol which exposes a number of + Qualcomm SoC specific features (such as memory bus scaling) through + a mixture of pre-determined algorithm strings and param_id pairs + hosted on the SCMI controller. + $ref: '/schemas/firmware/arm,scmi.yaml#/$defs/protocol-node' + unevaluatedProperties: false + + properties: + reg: + const: 0x80 + +additionalProperties: true --=20 2.34.1 From nobody Fri Jul 24 21:55:29 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DCD003B27EE for ; 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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2c24edc8acasm114618175ad.45.2026.06.10.01.52.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jun 2026 01:52:14 -0700 (PDT) From: Pragnesh Papaniya Date: Wed, 10 Jun 2026 14:21:30 +0530 Subject: [PATCH RFC v7 3/9] firmware: arm_scmi: vendors: Add QCOM SCMI Generic Extensions Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260610-rfc_v7_scmi_memlat-v7-3-f3f68c608f25@oss.qualcomm.com> References: <20260610-rfc_v7_scmi_memlat-v7-0-f3f68c608f25@oss.qualcomm.com> In-Reply-To: <20260610-rfc_v7_scmi_memlat-v7-0-f3f68c608f25@oss.qualcomm.com> To: Sudeep Holla , Cristian Marussi , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sibi Sankar , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Dmitry Osipenko , Thierry Reding , Jonathan Hunter , Bjorn Andersson , Konrad Dybcio Cc: Pragnesh Papaniya , Rajendra Nayak , Pankaj Patil , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, arm-scmi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, Amir Vajid , Ramakrishna Gottimukkula X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1781081505; l=10720; i=pragnesh.papaniya@oss.qualcomm.com; s=20260120; h=from:subject:message-id; bh=teXO5koBrmv3aA4ZyAeyCgjEEP97zvPys0ur9lr68Q4=; b=Y5L4HL88UbeNsfsuiEHNiHQ2Mt5BmhyjqEHH/Io11WTARLldgiF907aIgcqU5CKmAxXNOsp7U 7MFapu/mQTKBEVm5GtRmtxujsJAFDWqgIPrxe8Foi32nFbBauMBha1m X-Developer-Key: i=pragnesh.papaniya@oss.qualcomm.com; a=ed25519; pk=09P9nFmZLXJ9+4Jx10ZK5rIW0Fmk79A/DLErm6aVA0c= X-Authority-Analysis: v=2.4 cv=TeamcxQh c=1 sm=1 tr=0 ts=6a2925c0 cx=c_pps a=vVfyC5vLCtgYJKYeQD43oA==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=EUspDBNiAAAA:8 a=xTFWSTIUIKHfy7pKroIA:9 a=QEXdDO2ut3YA:10 a=rl5im9kqc5Lf4LNbBjHf:22 X-Proofpoint-GUID: gA6OGw1HQAASZPUJdacrW4k9HQaxn5H4 X-Proofpoint-ORIG-GUID: gA6OGw1HQAASZPUJdacrW4k9HQaxn5H4 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjEwMDA4MyBTYWx0ZWRfX0ZpNM+hjDLv6 +s1jgx8vWq2Hg2udrQUsPQ77AO5pnhgkvy2rPgrnkppTmGvxxzN1Yd4KJt63zN1SO4yCEH8Flsa HjxQvRKUPE064o1aA00Bm2VEP54aENSI0teIuPlbDklmYMfC0y7qnyfciyIyBzsDMN8oUJPelK2 Yg2TnbhDYDOUmtCFjbEBcFzwUMAAZKNa/3dT6rbh6Z5+i+gkqx4ya7r+30d2PUOyELgsc5Yw0RB G2Rc5Ss+kfP7cwU/Iw/H9JImajUMbcnNKmHjXxplI+89PDuhPao7fDN92o865xAaPx5HRl9ArCP 2AvsFf9gnUJ7kT3CbhNkc2hAFyMiywgVhvsXgEEEq0ttQbYLz8jZlyZy1HmnRgqW+B9xSK9nw5v LQc9BUs+KnkSuSioEh2hUBNUTfd9jUwy3aEgTgGO0diN7xCinaf/jNZAgrnbzQOg8DUC5c4DESO jOJhTE/UOmfHo2jC/nw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-10_02,2026-06-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 suspectscore=0 malwarescore=0 phishscore=0 spamscore=0 impostorscore=0 clxscore=1015 priorityscore=1501 bulkscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605210000 definitions=main-2606100083 From: Sibi Sankar The QCOM SCMI Generic Extensions Protocol provides a generic way of exposing a number of Qualcomm SoC specific features (like memory bus scaling) through a mixture of pre-determined algorithm strings and param_id pairs hosted on the SCMI controller. Co-developed-by: Amir Vajid Signed-off-by: Amir Vajid Co-developed-by: Ramakrishna Gottimukkula Signed-off-by: Ramakrishna Gottimukkula Signed-off-by: Sibi Sankar Signed-off-by: Pragnesh Papaniya --- drivers/firmware/arm_scmi/Kconfig | 1 + drivers/firmware/arm_scmi/Makefile | 1 + drivers/firmware/arm_scmi/vendors/qcom/Kconfig | 15 ++ drivers/firmware/arm_scmi/vendors/qcom/Makefile | 2 + .../arm_scmi/vendors/qcom/qcom-generic-ext.c | 153 +++++++++++++++++= ++++ include/linux/scmi_qcom_protocol.h | 37 +++++ 6 files changed, 209 insertions(+) diff --git a/drivers/firmware/arm_scmi/Kconfig b/drivers/firmware/arm_scmi/= Kconfig index e3fb36825978..a52f4d1b8b2c 100644 --- a/drivers/firmware/arm_scmi/Kconfig +++ b/drivers/firmware/arm_scmi/Kconfig @@ -84,6 +84,7 @@ config ARM_SCMI_QUIRKS =20 source "drivers/firmware/arm_scmi/transports/Kconfig" source "drivers/firmware/arm_scmi/vendors/imx/Kconfig" +source "drivers/firmware/arm_scmi/vendors/qcom/Kconfig" =20 endif #ARM_SCMI_PROTOCOL =20 diff --git a/drivers/firmware/arm_scmi/Makefile b/drivers/firmware/arm_scmi= /Makefile index 780cd62b2f78..5a0e003c2477 100644 --- a/drivers/firmware/arm_scmi/Makefile +++ b/drivers/firmware/arm_scmi/Makefile @@ -13,6 +13,7 @@ scmi-module-objs :=3D $(scmi-driver-y) $(scmi-protocols-y= ) $(scmi-transport-y) =20 obj-$(CONFIG_ARM_SCMI_PROTOCOL) +=3D transports/ obj-$(CONFIG_ARM_SCMI_PROTOCOL) +=3D vendors/imx/ +obj-$(CONFIG_ARM_SCMI_PROTOCOL) +=3D vendors/qcom/ =20 obj-$(CONFIG_ARM_SCMI_PROTOCOL) +=3D scmi-core.o obj-$(CONFIG_ARM_SCMI_PROTOCOL) +=3D scmi-module.o diff --git a/drivers/firmware/arm_scmi/vendors/qcom/Kconfig b/drivers/firmw= are/arm_scmi/vendors/qcom/Kconfig new file mode 100644 index 000000000000..8aa0efd6a03d --- /dev/null +++ b/drivers/firmware/arm_scmi/vendors/qcom/Kconfig @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0-only +menu "ARM SCMI QCOM Vendor Protocols" + +config QCOM_SCMI_GENERIC_EXT + tristate "Qualcomm Technologies, Inc. SCMI Generic Vendor Protocol" + depends on ARM_SCMI_PROTOCOL || (COMPILE_TEST && OF) + help + The QCOM SCMI vendor protocol provides a generic way of exposing + a number of Qualcomm SoC specific features (like memory bus scaling) + through a mixture of pre-determined algorithm strings and param_id + pairs hosted on the SCMI controller. + + This driver defines/documents the message IDs used for this + communication and also exposes the operations used by the clients. +endmenu diff --git a/drivers/firmware/arm_scmi/vendors/qcom/Makefile b/drivers/firm= ware/arm_scmi/vendors/qcom/Makefile new file mode 100644 index 000000000000..6b98fabbebb8 --- /dev/null +++ b/drivers/firmware/arm_scmi/vendors/qcom/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-only +obj-$(CONFIG_QCOM_SCMI_GENERIC_EXT) +=3D qcom-generic-ext.o diff --git a/drivers/firmware/arm_scmi/vendors/qcom/qcom-generic-ext.c b/dr= ivers/firmware/arm_scmi/vendors/qcom/qcom-generic-ext.c new file mode 100644 index 000000000000..77c07272c09d --- /dev/null +++ b/drivers/firmware/arm_scmi/vendors/qcom/qcom-generic-ext.c @@ -0,0 +1,153 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include + +#include "../../common.h" + +/* + * This protocol is intended as a generic way of exposing a number of Qual= comm + * SoC specific features through a mixture of pre-determined algorithm str= ing + * and param_id pairs hosted on the SCMI controller. + * + * The QCOM SCMI Vendor Protocol has the protocol id as 0x80 and vendor id= set + * to Qualcomm and the supported version is set to 0x10000. The PROTOCOL_V= ERSION + * command returns version 1.0. + */ + +/** + * enum qcom_generic_ext_protocol_cmd - vendor specific commands supported= by SCMI Qualcomm + * generic vendor protocol. + * + * @QCOM_SCMI_SET_PARAM: is used to set the parameter of a specific algo_s= tr hosted on + * QCOM SCMI Vendor Protocol. The tx len depends on the algo_str used. + * @QCOM_SCMI_GET_PARAM: is used to get parameter information of a specifi= c algo_str + * hosted on QCOM SCMI Vendor Protocol. The tx and rx len depends + * on the algo_str used. + * @QCOM_SCMI_START_ACTIVITY: is used to start the activity performed by t= he algo_str. + * @QCOM_SCMI_STOP_ACTIVITY: is used to stop a pre-existing activity perfo= rmed by the algo_str. + */ +enum qcom_generic_ext_protocol_cmd { + QCOM_SCMI_SET_PARAM =3D 0x10, + QCOM_SCMI_GET_PARAM =3D 0x11, + QCOM_SCMI_START_ACTIVITY =3D 0x12, + QCOM_SCMI_STOP_ACTIVITY =3D 0x13, +}; + +/** + * struct qcom_scmi_msg - represents the various parameters to be populated + * for using the QCOM SCMI Vendor Protocol + * + * @ext_id: reserved, must be zero + * @algo_low: lower 32 bits of the algo_str + * @algo_high: upper 32 bits of the algo_str + * @param_id: serves as token message id to the specific algo_str + * @buf: serves as the payload to the specified param_id and algo_str pair + */ +struct qcom_scmi_msg { + __le32 ext_id; + __le32 algo_low; + __le32 algo_high; + __le32 param_id; + __le32 buf[]; +}; + +static int qcom_scmi_common_xfer(const struct scmi_protocol_handle *ph, + enum qcom_generic_ext_protocol_cmd cmd_id, void *buf, + size_t buf_len, u64 algo_str, u32 param_id, size_t rx_size) +{ + struct scmi_xfer *t; + struct qcom_scmi_msg *msg; + int ret; + + /* Reject calls where rx_size exceeds buf_len. */ + if (rx_size > buf_len) + return -EINVAL; + + ret =3D ph->xops->xfer_get_init(ph, cmd_id, buf_len + sizeof(*msg), rx_si= ze, &t); + if (ret) + return ret; + + msg =3D t->tx.buf; + msg->ext_id =3D 0; + msg->algo_low =3D cpu_to_le32(lower_32_bits(algo_str)); + msg->algo_high =3D cpu_to_le32(upper_32_bits(algo_str)); + msg->param_id =3D cpu_to_le32(param_id); + memcpy(msg->buf, buf, buf_len); + + ret =3D ph->xops->do_xfer(ph, t); + if (!ret && rx_size) + /* + * Response is returned into the caller's @buf, replacing the + * tx payload. Callers using the same on-stack struct for both + * directions must not rely on tx contents after this point. + */ + memcpy(buf, t->rx.buf, t->rx.len); + ph->xops->xfer_put(ph, t); + + return ret; +} + +static int qcom_scmi_set_param(const struct scmi_protocol_handle *ph, void= *buf, size_t buf_len, + u64 algo_str, u32 param_id) +{ + return qcom_scmi_common_xfer(ph, QCOM_SCMI_SET_PARAM, buf, buf_len, algo_= str, + param_id, 0); +} + +static int qcom_scmi_get_param(const struct scmi_protocol_handle *ph, void= *buf, size_t buf_len, + u64 algo_str, u32 param_id, size_t rx_size) +{ + return qcom_scmi_common_xfer(ph, QCOM_SCMI_GET_PARAM, buf, buf_len, algo_= str, + param_id, rx_size); +} + +static int qcom_scmi_start_activity(const struct scmi_protocol_handle *ph,= void *buf, + size_t buf_len, u64 algo_str, u32 param_id) +{ + return qcom_scmi_common_xfer(ph, QCOM_SCMI_START_ACTIVITY, buf, buf_len, = algo_str, + param_id, 0); +} + +static int qcom_scmi_stop_activity(const struct scmi_protocol_handle *ph, = void *buf, + size_t buf_len, u64 algo_str, u32 param_id) +{ + return qcom_scmi_common_xfer(ph, QCOM_SCMI_STOP_ACTIVITY, buf, buf_len, a= lgo_str, + param_id, 0); +} + +static const struct qcom_generic_ext_ops qcom_proto_ops =3D { + .set_param =3D qcom_scmi_set_param, + .get_param =3D qcom_scmi_get_param, + .start_activity =3D qcom_scmi_start_activity, + .stop_activity =3D qcom_scmi_stop_activity, +}; + +static int qcom_generic_ext_protocol_init(const struct scmi_protocol_handl= e *ph) +{ + dev_dbg(ph->dev, "QCOM Generic Vendor Version %d.%d\n", + PROTOCOL_REV_MAJOR(ph->version), PROTOCOL_REV_MINOR(ph->version)); + + return 0; +} + +static const struct scmi_protocol qcom_generic_ext =3D { + .id =3D SCMI_PROTOCOL_QCOM_GENERIC, + .owner =3D THIS_MODULE, + .instance_init =3D &qcom_generic_ext_protocol_init, + .ops =3D &qcom_proto_ops, + .vendor_id =3D "Qualcomm", + .supported_version =3D 0x10000, +}; +module_scmi_protocol(qcom_generic_ext); + +MODULE_ALIAS("scmi-protocol-" __stringify(SCMI_PROTOCOL_QCOM_GENERIC) "-Qu= alcomm"); +MODULE_AUTHOR("Sibi Sankar "); +MODULE_DESCRIPTION("QCOM SCMI Generic Vendor Protocol"); +MODULE_LICENSE("GPL"); diff --git a/include/linux/scmi_qcom_protocol.h b/include/linux/scmi_qcom_p= rotocol.h new file mode 100644 index 000000000000..41632ee7bbc7 --- /dev/null +++ b/include/linux/scmi_qcom_protocol.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * SCMI Message Protocol driver QCOM extension header + * + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _LINUX_SCMI_QCOM_PROTOCOL_H +#define _LINUX_SCMI_QCOM_PROTOCOL_H + +#include + +#define SCMI_PROTOCOL_QCOM_GENERIC 0x80 + +struct scmi_protocol_handle; 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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2c24edc8acasm114618175ad.45.2026.06.10.01.52.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jun 2026 01:52:21 -0700 (PDT) From: Pragnesh Papaniya Date: Wed, 10 Jun 2026 14:21:31 +0530 Subject: [PATCH RFC v7 4/9] PM / devfreq: Add new target_freq attribute flag for governors Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260610-rfc_v7_scmi_memlat-v7-4-f3f68c608f25@oss.qualcomm.com> References: <20260610-rfc_v7_scmi_memlat-v7-0-f3f68c608f25@oss.qualcomm.com> In-Reply-To: <20260610-rfc_v7_scmi_memlat-v7-0-f3f68c608f25@oss.qualcomm.com> To: Sudeep Holla , Cristian Marussi , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sibi Sankar , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Dmitry Osipenko , Thierry Reding , Jonathan Hunter , Bjorn Andersson , Konrad Dybcio Cc: Pragnesh Papaniya , Rajendra Nayak , Pankaj Patil , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, arm-scmi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1781081505; l=7702; i=pragnesh.papaniya@oss.qualcomm.com; s=20260120; h=from:subject:message-id; bh=37NxbrW1EfFxbpoUejE/ZkFqRHFRkvYdYd39MI8qo+s=; b=W2YwkcFEZ5IJT5/BN4jcRVsu+M3gLs8KmACdb/DaAC0FZxActyPflb7dcQI3MNy0IpcPTz95u UBtczXw4hFBDkwsTXTzL3xmtnru2Kr0uwjm8jtUQ4lPWKylW53WgoTs X-Developer-Key: i=pragnesh.papaniya@oss.qualcomm.com; a=ed25519; pk=09P9nFmZLXJ9+4Jx10ZK5rIW0Fmk79A/DLErm6aVA0c= X-Proofpoint-GUID: LE_FekuL_UfVPzxzUx7aXrxT_vHuM8fI X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjEwMDA4MyBTYWx0ZWRfXzjkCWuatrMln nvYcnu+LHZ4xFaIicD3Gu7K63KZloPnpZ5ei28XvEfUjDqQuVEL3bLh9jdYybJtI8l2L7RNL2wG nfwG+ecCAKH1KdQsSU07akT4bsNahgCCaHhKpf5D5qcsRv1j9cBfcD05qbC34q5+bqQwplPUUH/ c4p7voj7ds3l6MbAVZ3dd+fRv/xNuw/fTMICaXckdD7u0madR3Q12vDxthj9oIvtgTRKE71QTrR zvFYu1RoXDuRsbxV9CsAZ7KYqwdQCwmC1VkQrAVoQDHvMOq066mok5QIsafz5tIwp9LjO8IO7dO 4FuuLvC/EQarATorWNBcLnO8a+oFZ8d+GS6wstUi3+1njAojqKU60F607L9figfFsFtca2VWJVQ gzhoTrZEPLeUWsl7Ft+ajYc8ynI8yB+qv7ist24C8qYDk/SXrYc+KH+1TAbCSFqPoLhx2/ROBym NNZRzapRN5W5lc+LjKw== X-Proofpoint-ORIG-GUID: LE_FekuL_UfVPzxzUx7aXrxT_vHuM8fI X-Authority-Analysis: v=2.4 cv=Md1cfZ/f c=1 sm=1 tr=0 ts=6a2925c7 cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=EUspDBNiAAAA:8 a=hD80L64hAAAA:8 a=WcTcrbn6WVXM4q_icv8A:9 a=QEXdDO2ut3YA:10 a=GvdueXVYPmCkWapjIL-Q:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-10_02,2026-06-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 phishscore=0 priorityscore=1501 adultscore=0 bulkscore=0 impostorscore=0 spamscore=0 malwarescore=0 clxscore=1015 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605210000 definitions=main-2606100083 From: Sibi Sankar The target_freq sysfs attribute exposes a governor's predicted next target frequency. Not every devfreq governor has a meaningful value to report there; some merely observe an externally-driven device. Add a DEVFREQ_GOV_ATTR_TARGET_FREQ attribute flag that governors with a meaningful target frequency must opt in to. Gate the existing target_freq sysfs read on the flag and return -EINVAL when the active governor does not advertise it. Tag all in-tree governors that already populate previous_freq via get_target_freq() so visible behaviour stays unchanged for in-tree users. Out-of-tree governors that drive frequency updates and want to keep target_freq readable need to set the new flag. Signed-off-by: Sibi Sankar Signed-off-by: Pragnesh Papaniya --- Documentation/ABI/testing/sysfs-class-devfreq | 8 ++++++++ drivers/devfreq/devfreq.c | 6 ++++++ drivers/devfreq/governor_passive.c | 1 + drivers/devfreq/governor_performance.c | 1 + drivers/devfreq/governor_powersave.c | 1 + drivers/devfreq/governor_simpleondemand.c | 1 + drivers/devfreq/governor_userspace.c | 1 + drivers/devfreq/hisi_uncore_freq.c | 1 + drivers/devfreq/tegra30-devfreq.c | 3 ++- include/linux/devfreq-governor.h | 3 +++ 10 files changed, 25 insertions(+), 1 deletion(-) diff --git a/Documentation/ABI/testing/sysfs-class-devfreq b/Documentation/= ABI/testing/sysfs-class-devfreq index df8ba88b9f6a..5be9940a5853 100644 --- a/Documentation/ABI/testing/sysfs-class-devfreq +++ b/Documentation/ABI/testing/sysfs-class-devfreq @@ -37,6 +37,14 @@ Description: The /sys/class/devfreq/.../target_freq shows the next governor predicted target frequency of the corresponding devfreq object. =20 + Reading this attribute returns -EINVAL when the active + governor does not advertise DEVFREQ_GOV_ATTR_TARGET_FREQ. + All in-tree governors that drive frequency transitions tag + this attribute, so existing in-tree behaviour is unchanged. + Out-of-tree governors that previously relied on the + unconditional read of df->previous_freq must opt in by + setting DEVFREQ_GOV_ATTR_TARGET_FREQ in their attrs field. + What: /sys/class/devfreq/.../trans_stat Date: October 2012 Contact: MyungJoo Ham diff --git a/drivers/devfreq/devfreq.c b/drivers/devfreq/devfreq.c index f08fc6966eae..2f27a239e34a 100644 --- a/drivers/devfreq/devfreq.c +++ b/drivers/devfreq/devfreq.c @@ -1530,6 +1530,12 @@ static ssize_t target_freq_show(struct device *dev, { struct devfreq *df =3D to_devfreq(dev); =20 + guard(mutex)(&devfreq_list_lock); + + if (!df->profile || !df->governor || + !IS_SUPPORTED_ATTR(df->governor->attrs, TARGET_FREQ)) + return -EINVAL; + return sprintf(buf, "%lu\n", df->previous_freq); } static DEVICE_ATTR_RO(target_freq); diff --git a/drivers/devfreq/governor_passive.c b/drivers/devfreq/governor_= passive.c index d7feecd900f1..b75e4bbee4b1 100644 --- a/drivers/devfreq/governor_passive.c +++ b/drivers/devfreq/governor_passive.c @@ -448,6 +448,7 @@ static int devfreq_passive_event_handler(struct devfreq= *devfreq, =20 static struct devfreq_governor devfreq_passive =3D { .name =3D DEVFREQ_GOV_PASSIVE, + .attrs =3D DEVFREQ_GOV_ATTR_TARGET_FREQ, .flags =3D DEVFREQ_GOV_FLAG_IMMUTABLE, .get_target_freq =3D devfreq_passive_get_target_freq, .event_handler =3D devfreq_passive_event_handler, diff --git a/drivers/devfreq/governor_performance.c b/drivers/devfreq/gover= nor_performance.c index fdb22bf512cf..b9ec587f582c 100644 --- a/drivers/devfreq/governor_performance.c +++ b/drivers/devfreq/governor_performance.c @@ -37,6 +37,7 @@ static int devfreq_performance_handler(struct devfreq *de= vfreq, =20 static struct devfreq_governor devfreq_performance =3D { .name =3D DEVFREQ_GOV_PERFORMANCE, + .attrs =3D DEVFREQ_GOV_ATTR_TARGET_FREQ, .get_target_freq =3D devfreq_performance_func, .event_handler =3D devfreq_performance_handler, }; diff --git a/drivers/devfreq/governor_powersave.c b/drivers/devfreq/governo= r_powersave.c index ee2d6ec8a512..69eab1d0a7fc 100644 --- a/drivers/devfreq/governor_powersave.c +++ b/drivers/devfreq/governor_powersave.c @@ -37,6 +37,7 @@ static int devfreq_powersave_handler(struct devfreq *devf= req, =20 static struct devfreq_governor devfreq_powersave =3D { .name =3D DEVFREQ_GOV_POWERSAVE, + .attrs =3D DEVFREQ_GOV_ATTR_TARGET_FREQ, .get_target_freq =3D devfreq_powersave_func, .event_handler =3D devfreq_powersave_handler, }; diff --git a/drivers/devfreq/governor_simpleondemand.c b/drivers/devfreq/go= vernor_simpleondemand.c index ac9c5e9e51a4..65ff9d912ef9 100644 --- a/drivers/devfreq/governor_simpleondemand.c +++ b/drivers/devfreq/governor_simpleondemand.c @@ -118,6 +118,7 @@ static int devfreq_simple_ondemand_handler(struct devfr= eq *devfreq, static struct devfreq_governor devfreq_simple_ondemand =3D { .name =3D DEVFREQ_GOV_SIMPLE_ONDEMAND, .attrs =3D DEVFREQ_GOV_ATTR_POLLING_INTERVAL + | DEVFREQ_GOV_ATTR_TARGET_FREQ | DEVFREQ_GOV_ATTR_TIMER, .get_target_freq =3D devfreq_simple_ondemand_func, .event_handler =3D devfreq_simple_ondemand_handler, diff --git a/drivers/devfreq/governor_userspace.c b/drivers/devfreq/governo= r_userspace.c index 3906ebedbae8..d1b765a7b8e5 100644 --- a/drivers/devfreq/governor_userspace.c +++ b/drivers/devfreq/governor_userspace.c @@ -135,6 +135,7 @@ static int devfreq_userspace_handler(struct devfreq *de= vfreq, =20 static struct devfreq_governor devfreq_userspace =3D { .name =3D DEVFREQ_GOV_USERSPACE, + .attrs =3D DEVFREQ_GOV_ATTR_TARGET_FREQ, .get_target_freq =3D devfreq_userspace_func, .event_handler =3D devfreq_userspace_handler, }; diff --git a/drivers/devfreq/hisi_uncore_freq.c b/drivers/devfreq/hisi_unco= re_freq.c index 4d00d813c8ac..0800116e3334 100644 --- a/drivers/devfreq/hisi_uncore_freq.c +++ b/drivers/devfreq/hisi_uncore_freq.c @@ -399,6 +399,7 @@ static struct devfreq_governor hisi_platform_governor = =3D { * Set interrupt_driven to skip the devfreq monitor mechanism, though * this governor is not interrupt-driven. */ + .attrs =3D DEVFREQ_GOV_ATTR_TARGET_FREQ, .flags =3D DEVFREQ_GOV_FLAG_IRQ_DRIVEN, .get_target_freq =3D hisi_platform_gov_func, .event_handler =3D hisi_platform_gov_handler, diff --git a/drivers/devfreq/tegra30-devfreq.c b/drivers/devfreq/tegra30-de= vfreq.c index 401aac6a9f07..fcb278c4a74c 100644 --- a/drivers/devfreq/tegra30-devfreq.c +++ b/drivers/devfreq/tegra30-devfreq.c @@ -776,7 +776,8 @@ static int tegra_governor_event_handler(struct devfreq = *devfreq, =20 static struct devfreq_governor tegra_devfreq_governor =3D { .name =3D "tegra_actmon", - .attrs =3D DEVFREQ_GOV_ATTR_POLLING_INTERVAL, + .attrs =3D DEVFREQ_GOV_ATTR_POLLING_INTERVAL + | DEVFREQ_GOV_ATTR_TARGET_FREQ, .flags =3D DEVFREQ_GOV_FLAG_IMMUTABLE | DEVFREQ_GOV_FLAG_IRQ_DRIVEN, .get_target_freq =3D tegra_governor_get_target, diff --git a/include/linux/devfreq-governor.h b/include/linux/devfreq-gover= nor.h index dfdd0160a29f..2853f571dfdf 100644 --- a/include/linux/devfreq-governor.h +++ b/include/linux/devfreq-governor.h @@ -43,9 +43,12 @@ * : Indicate polling_interval sysfs attribute * - DEVFREQ_GOV_ATTR_TIMER * : Indicate timer sysfs attribute + * - DEVFREQ_GOV_ATTR_TARGET_FREQ + * : Indicate the target freq sysfs attribute */ #define DEVFREQ_GOV_ATTR_POLLING_INTERVAL BIT(0) #define DEVFREQ_GOV_ATTR_TIMER BIT(1) +#define DEVFREQ_GOV_ATTR_TARGET_FREQ BIT(2) =20 /** * struct devfreq_governor - Devfreq policy governor --=20 2.34.1 From nobody Fri Jul 24 21:55:29 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D2E5C3B9D99 for ; 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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2c24edc8acasm114618175ad.45.2026.06.10.01.52.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jun 2026 01:52:28 -0700 (PDT) From: Pragnesh Papaniya Date: Wed, 10 Jun 2026 14:21:32 +0530 Subject: [PATCH RFC v7 5/9] PM / devfreq: Add new track_remote flag for governors Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260610-rfc_v7_scmi_memlat-v7-5-f3f68c608f25@oss.qualcomm.com> References: <20260610-rfc_v7_scmi_memlat-v7-0-f3f68c608f25@oss.qualcomm.com> In-Reply-To: <20260610-rfc_v7_scmi_memlat-v7-0-f3f68c608f25@oss.qualcomm.com> To: Sudeep Holla , Cristian Marussi , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sibi Sankar , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Dmitry Osipenko , Thierry Reding , Jonathan Hunter , Bjorn Andersson , Konrad Dybcio Cc: Pragnesh Papaniya , Rajendra Nayak , Pankaj Patil , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, arm-scmi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1781081505; l=3562; i=pragnesh.papaniya@oss.qualcomm.com; s=20260120; h=from:subject:message-id; bh=i8JmP8t0IIDx2YuhJ586pU9J0+L8gn09QqoMvPwEzvk=; b=SjTlP3ljJexiSuNiz3k1DP81x2Nsjn02FN9iDLP4o7nw/yM9wDBLOmgzsNAF1zQPVffbuYZwV fiaFkBpgVjuBwr4NTgxGOi3wvNISInadO5xNeaHkiIXZp5iXDIa9ywS X-Developer-Key: i=pragnesh.papaniya@oss.qualcomm.com; a=ed25519; pk=09P9nFmZLXJ9+4Jx10ZK5rIW0Fmk79A/DLErm6aVA0c= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjEwMDA4MyBTYWx0ZWRfX5ssE+heRIal3 ssATuWMAhW5d4XtBJEZKH0Ug2Jp4bebPRwsCW5z7I4eEfyEqllnEuhN3k5AE+D7X3QvbW0sBUE8 eb/fjsdyQrDGXMrX5bVWvmWKSBp3Xbke7CRmT9sH71sYS+9f2HmxHxL6E2xSGz9rSyalPHyWCEb KxOmysOF74ScYSM7f0SQYm7Ffva/u9phTaYo4h6EPirKaYNkP7Sga2smXIKuReSHDIZVndp3/Hh iC2XoAPyWXnhDwh/sEsXpj+uPkZHmzDLO4kMtHEDg6KAhl7wF+6J2cYaSiW9fq6G5PlFDRY6Ssa Vw1Umw8u7BzFbbh5TGH0NVVJ2qCmB4XDG/JAC2MT5KuGmhmUlcf+Mt8ou+UO68EWVicTg1223Bn 8U/aBp44CsOd9rtgxyQWvFqaHr9lAtlpyYKyl2THewarvqmd/r5MyWaYodvxsWWeQpMlusTzafj QpGFhcp+RhWKRDlePJg== X-Proofpoint-ORIG-GUID: 7zFS8p2y7n_f-XyUUtzBNj7v7tZ4LhlV X-Proofpoint-GUID: 7zFS8p2y7n_f-XyUUtzBNj7v7tZ4LhlV X-Authority-Analysis: v=2.4 cv=DNG/JSNb c=1 sm=1 tr=0 ts=6a2925ce cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=EUspDBNiAAAA:8 a=_Sn8c3TY04LLovrI2V0A:9 a=QEXdDO2ut3YA:10 a=uG9DUKGECoFWVXl0Dc02:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-10_02,2026-06-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 malwarescore=0 spamscore=0 impostorscore=0 priorityscore=1501 adultscore=0 phishscore=0 clxscore=1015 suspectscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605210000 definitions=main-2606100083 From: Sibi Sankar Some devfreq governors need to track frequency changes performed on remote devices rather than driving the frequency updates themselves. In such cases, the device's frequency is already updated by an external entity and devfreq only needs to keep its transition statistics and notifier subscribers in sync. Add a new DEVFREQ_GOV_FLAG_TRACK_REMOTE governor flag. When set, devfreq_set_target() skips the profile->target() update sequence but still emits the DEVFREQ_PRECHANGE/DEVFREQ_POSTCHANGE notification pair and the devfreq_frequency trace event, so transition-notifier subscribers (passive governor, devfreq cooling, etc.) and tracing observe the remote frequency change exactly as they would on the normal path, and the transition statistics are refreshed. Signed-off-by: Sibi Sankar Signed-off-by: Pragnesh Papaniya --- drivers/devfreq/devfreq.c | 21 +++++++++++++++++++++ include/linux/devfreq-governor.h | 5 +++++ 2 files changed, 26 insertions(+) diff --git a/drivers/devfreq/devfreq.c b/drivers/devfreq/devfreq.c index 2f27a239e34a..71c6ced9e4e1 100644 --- a/drivers/devfreq/devfreq.c +++ b/drivers/devfreq/devfreq.c @@ -348,6 +348,26 @@ static int devfreq_set_target(struct devfreq *devfreq,= unsigned long new_freq, unsigned long cur_freq; int err =3D 0; =20 + /* + * When a remote agent (e.g. firmware) owns the frequency, skip the + * local profile->target() call. Still emit the PRECHANGE/POSTCHANGE + * pair and the trace event so that transition-notifier subscribers + * (passive governor, devfreq cooling, etc.) and tracing observe the + * frequency change exactly as they would on the normal path. + */ + if (devfreq->governor && + IS_SUPPORTED_FLAG(devfreq->governor->flags, TRACK_REMOTE)) { + freqs.old =3D devfreq->previous_freq; + freqs.new =3D new_freq; + devfreq_notify_transition(devfreq, &freqs, DEVFREQ_PRECHANGE); + + if (trace_devfreq_frequency_enabled() && new_freq !=3D freqs.old) + trace_devfreq_frequency(devfreq, new_freq, freqs.old); + + devfreq_notify_transition(devfreq, &freqs, DEVFREQ_POSTCHANGE); + goto update_status; + } + if (devfreq->profile->get_cur_freq) devfreq->profile->get_cur_freq(devfreq->dev.parent, &cur_freq); else @@ -375,6 +395,7 @@ static int devfreq_set_target(struct devfreq *devfreq, = unsigned long new_freq, freqs.new =3D new_freq; devfreq_notify_transition(devfreq, &freqs, DEVFREQ_POSTCHANGE); =20 +update_status: if (devfreq_update_status(devfreq, new_freq)) dev_warn(&devfreq->dev, "Couldn't update frequency transition information.\n"); diff --git a/include/linux/devfreq-governor.h b/include/linux/devfreq-gover= nor.h index 2853f571dfdf..e4f7b6cb07bc 100644 --- a/include/linux/devfreq-governor.h +++ b/include/linux/devfreq-governor.h @@ -33,9 +33,14 @@ * : This governor is never changeable to other governors. * - DEVFREQ_GOV_FLAG_IRQ_DRIVEN * : The devfreq won't schedule the work for this governor. + * - DEVFREQ_GOV_FLAG_TRACK_REMOTE + * : The governor only tracks frequency changes performed by a remote + * agent (e.g. firmware); devfreq skips the local profile->target() + * call and just keeps its statistics and notifiers in sync. */ #define DEVFREQ_GOV_FLAG_IMMUTABLE BIT(0) #define DEVFREQ_GOV_FLAG_IRQ_DRIVEN BIT(1) +#define DEVFREQ_GOV_FLAG_TRACK_REMOTE BIT(2) =20 /* * Definition of governor attribute flags except for common sysfs attribut= es --=20 2.34.1 From nobody Fri Jul 24 21:55:29 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 448C33BE15D for ; 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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2c24edc8acasm114618175ad.45.2026.06.10.01.52.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jun 2026 01:52:36 -0700 (PDT) From: Pragnesh Papaniya Date: Wed, 10 Jun 2026 14:21:33 +0530 Subject: [PATCH RFC v7 6/9] PM / devfreq: Add a governor for tracking remote device frequencies Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260610-rfc_v7_scmi_memlat-v7-6-f3f68c608f25@oss.qualcomm.com> References: <20260610-rfc_v7_scmi_memlat-v7-0-f3f68c608f25@oss.qualcomm.com> In-Reply-To: <20260610-rfc_v7_scmi_memlat-v7-0-f3f68c608f25@oss.qualcomm.com> To: Sudeep Holla , Cristian Marussi , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sibi Sankar , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Dmitry Osipenko , Thierry Reding , Jonathan Hunter , Bjorn Andersson , Konrad Dybcio Cc: Pragnesh Papaniya , Rajendra Nayak , Pankaj Patil , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, arm-scmi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1781081505; l=4893; i=pragnesh.papaniya@oss.qualcomm.com; s=20260120; h=from:subject:message-id; bh=xZowMXSIo/yjYoix7dfxNcBQFvLyEboivbRIq1BkEFU=; b=XGGVsmcuQqsb7xxvF7kkpvKNz7arqGm5Q77SCmhmuZWxjWFRBwfyljemBijVv02n419Asznfo ce5/XapDYe0BqR8iEbYjxr25/B4xeON8mbI0zhXc5GM+c20jwuEccS4 X-Developer-Key: i=pragnesh.papaniya@oss.qualcomm.com; a=ed25519; pk=09P9nFmZLXJ9+4Jx10ZK5rIW0Fmk79A/DLErm6aVA0c= X-Proofpoint-GUID: nMP-9icehPe4oRBZw3zejl-yVLRHNbnw X-Authority-Analysis: v=2.4 cv=ebYNubEH c=1 sm=1 tr=0 ts=6a2925d5 cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=EUspDBNiAAAA:8 a=DkxomDJNIKAFLi0tgcIA:9 a=QEXdDO2ut3YA:10 a=GvdueXVYPmCkWapjIL-Q:22 X-Proofpoint-ORIG-GUID: nMP-9icehPe4oRBZw3zejl-yVLRHNbnw X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjEwMDA4MyBTYWx0ZWRfXwDa03IBLSwLM iVW6qVNSq2JfGIQyhKIyaPnCEoAPWawYKG/5x2fHHfiDD9kr77ezbW/RGza43zLjVmARteVrswA +r5gkdqvoiBGZZ9laFJK9zvhIKqW6x0j9NjkZNQXG9dbQeq2H/sC0gcjQPNBgGn4ItxPR+txavi bs1AsVyi1wf3I08RfBZshy9sWNXZviMCxcJ3thKkS9Usrm7BruEuhsURJy/WOz967Pndr8YsTJu C5cYPcw3fvTXvLIiJpH6Zzpl8YSwiPZNxyvmoaYG/piKraDgvOyedNj4II9iuTqiEJGGL8kh4j8 ANSBKSkKiqITLJ2t4gcuRBM7K5RNA46HJN2dzZ0gmqnWoAcW991etIUxFdRc+dUtazKYLRLVBVa XlibLXHduVonXqU/7567GeTLYaxRirAeE+x/X14pPSJztP8SxEGA2XZKVbuRaENaJ9jVFcbaKcH tZb9JDeznqzNLMEGrjw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-10_02,2026-06-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 impostorscore=0 spamscore=0 bulkscore=0 clxscore=1015 suspectscore=0 phishscore=0 adultscore=0 lowpriorityscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605210000 definitions=main-2606100083 From: Sibi Sankar On SoCs where the governor and the mechanism to control the frequency for devices like caches is hosted on the System Control Processor (SCP), there exists a need to track the frequency changes in a reliable way and provide ways to tweak parameters on the remote governor. Add a new "remote" devfreq governor that uses the track_remote flag to expose the remote device's frequency to userspace via trans_stat. The governor deliberately does not advertise the DEVFREQ_GOV_ATTR_TARGET_FREQ attribute since the kernel cannot set the frequency on a remote-managed device; reads of the target_freq sysfs node therefore return -EINVAL. Signed-off-by: Sibi Sankar Signed-off-by: Pragnesh Papaniya --- drivers/devfreq/Kconfig | 8 +++++ drivers/devfreq/Makefile | 1 + drivers/devfreq/governor_remote.c | 73 +++++++++++++++++++++++++++++++++++= ++++ include/linux/devfreq.h | 1 + 4 files changed, 83 insertions(+) diff --git a/drivers/devfreq/Kconfig b/drivers/devfreq/Kconfig index c999c4a1e567..2caa87554914 100644 --- a/drivers/devfreq/Kconfig +++ b/drivers/devfreq/Kconfig @@ -56,6 +56,14 @@ config DEVFREQ_GOV_POWERSAVE the DEVFREQ framework returns the lowest frequency available at any time. =20 +config DEVFREQ_GOV_REMOTE + tristate "Remote" + help + A simple governor to track the frequency of devices whose + dvfs control lies outside the kernel. This governor acts + as an observer and provides for ways to track frequency and + set/get information related to the remote dvfs device. + config DEVFREQ_GOV_USERSPACE tristate "Userspace" help diff --git a/drivers/devfreq/Makefile b/drivers/devfreq/Makefile index 404179d79a9d..cde57c8cda76 100644 --- a/drivers/devfreq/Makefile +++ b/drivers/devfreq/Makefile @@ -4,6 +4,7 @@ obj-$(CONFIG_PM_DEVFREQ_EVENT) +=3D devfreq-event.o obj-$(CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND) +=3D governor_simpleondemand.o obj-$(CONFIG_DEVFREQ_GOV_PERFORMANCE) +=3D governor_performance.o obj-$(CONFIG_DEVFREQ_GOV_POWERSAVE) +=3D governor_powersave.o +obj-$(CONFIG_DEVFREQ_GOV_REMOTE) +=3D governor_remote.o obj-$(CONFIG_DEVFREQ_GOV_USERSPACE) +=3D governor_userspace.o obj-$(CONFIG_DEVFREQ_GOV_PASSIVE) +=3D governor_passive.o =20 diff --git a/drivers/devfreq/governor_remote.c b/drivers/devfreq/governor_r= emote.c new file mode 100644 index 000000000000..df3819757e56 --- /dev/null +++ b/drivers/devfreq/governor_remote.c @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include + +static int devfreq_remote_track_func(struct devfreq *devfreq, unsigned lon= g *freq) +{ + if (!devfreq->profile->get_cur_freq) + return -ENXIO; + + return devfreq->profile->get_cur_freq(devfreq->dev.parent, freq); +} + +static int devfreq_remote_track_handler(struct devfreq *devfreq, unsigned = int event, void *data) +{ + switch (event) { + case DEVFREQ_GOV_START: + devfreq_monitor_start(devfreq); + break; + + case DEVFREQ_GOV_STOP: + devfreq_monitor_stop(devfreq); + break; + + case DEVFREQ_GOV_UPDATE_INTERVAL: + devfreq_update_interval(devfreq, (unsigned int *)data); + break; + + case DEVFREQ_GOV_SUSPEND: + devfreq_monitor_suspend(devfreq); + break; + + case DEVFREQ_GOV_RESUME: + devfreq_monitor_resume(devfreq); + break; + } + + return 0; +} + +static struct devfreq_governor devfreq_remote_track =3D { + .name =3D DEVFREQ_GOV_REMOTE, + .attrs =3D DEVFREQ_GOV_ATTR_POLLING_INTERVAL + | DEVFREQ_GOV_ATTR_TIMER, + .flags =3D DEVFREQ_GOV_FLAG_IMMUTABLE + | DEVFREQ_GOV_FLAG_TRACK_REMOTE, + .get_target_freq =3D devfreq_remote_track_func, + .event_handler =3D devfreq_remote_track_handler, +}; + +static int __init devfreq_remote_track_init(void) +{ + return devfreq_add_governor(&devfreq_remote_track); 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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2c24edc8acasm114618175ad.45.2026.06.10.01.52.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jun 2026 01:52:43 -0700 (PDT) From: Pragnesh Papaniya Date: Wed, 10 Jun 2026 14:21:34 +0530 Subject: [PATCH RFC v7 7/9] PM / devfreq: Introduce the QCOM SCMI Memlat devfreq driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260610-rfc_v7_scmi_memlat-v7-7-f3f68c608f25@oss.qualcomm.com> References: <20260610-rfc_v7_scmi_memlat-v7-0-f3f68c608f25@oss.qualcomm.com> In-Reply-To: <20260610-rfc_v7_scmi_memlat-v7-0-f3f68c608f25@oss.qualcomm.com> To: Sudeep Holla , Cristian Marussi , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sibi Sankar , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Dmitry Osipenko , Thierry Reding , Jonathan Hunter , Bjorn Andersson , Konrad Dybcio Cc: Pragnesh Papaniya , Rajendra Nayak , Pankaj Patil , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, arm-scmi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, Amir Vajid , Ramakrishna Gottimukkula X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1781081505; l=41524; i=pragnesh.papaniya@oss.qualcomm.com; s=20260120; h=from:subject:message-id; bh=9HpSEzN3z9wGdtTNEYwr4Xz5y1MGY13Rr9W42hE+bYA=; b=KW9odDUxxPymfdgUdSOOdEzG1Y+z9KGaZlIAIFeYe41p3XNuXTlZwufcEf4Fh74boX/0ELzF3 YFWf5g0aI4FCb3QJv8xfuvoqpbC0B11u7THpVUXVHqp8NiIqwzJi2Li X-Developer-Key: i=pragnesh.papaniya@oss.qualcomm.com; a=ed25519; pk=09P9nFmZLXJ9+4Jx10ZK5rIW0Fmk79A/DLErm6aVA0c= X-Authority-Analysis: v=2.4 cv=Gu1yPE1C c=1 sm=1 tr=0 ts=6a2925de cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=EUspDBNiAAAA:8 a=cq_nS-vLBsE7nuxwGFYA:9 a=QEXdDO2ut3YA:10 a=324X-CrmTo6CU4MGRt3R:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjEwMDA4MyBTYWx0ZWRfX6tdU9hcf1flp bwi9uM/wfNH/TGlF3mvtzO+91/XzX788+LtCfAILHYehg/L71cjWyFNPkimMtMoQKDfr1yUFXIV t8zIIfzuDRGpmUEdWEcnsATsE/R5pJFlhkAghjWpPiLBKO1LNVVDM+E26vLjUup2ma8FZn8ca49 GZWUqXZrMcJ11NfcQT8tTJtf/YSKejlZ+Ck9jORmE3Y/6zt/Ao8ZQ+uRrA5a8pduMkihDWAFaVd MoDhFhs1SE8Ipp9uqdQmj4195WmTgmgd/kvo+HO4QKLyWARCMWHT+ZYRE6IPdPZNQ/ElKdngsAA qnmDv2vVlLTb2Y+DtBN4h5v8ZMha8h1moj0fGjHGXC6PXvTM8kb36xVcymtrhMHroilDu1a/Mnh 5UkSqa8ZEmRN8yPVmRqNYo4q/xFTlN8+Ziuiiz63yvrr9cm5mSvnf0mnjYv1LrvLV43x9faqF86 PBUfXmoWpCiQQgabxVg== X-Proofpoint-ORIG-GUID: QLmKwerXpJ4VF3u3uRVSY3O3Imtf6jrI X-Proofpoint-GUID: QLmKwerXpJ4VF3u3uRVSY3O3Imtf6jrI X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-10_02,2026-06-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 lowpriorityscore=0 suspectscore=0 phishscore=0 adultscore=0 clxscore=1015 spamscore=0 bulkscore=0 malwarescore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605210000 definitions=main-2606100083 From: Sibi Sankar On Qualcomm Glymur, Mahua and X1E/X1P (Hamoa) SoCs, the memlat governor and the mechanism to control the various caches and RAM is hosted on the CPU Control Processor (CPUCP), and configuration and control of this governor is exposed through the QCOM SCMI Generic Extension Protocol, addressed via the "MEMLAT" algorithm string. Introduce a devfreq SCMI client driver that uses the MEMLAT algorithm string to detect memory-latency-bound workloads and control the frequency/level of the memory buses (DDR, LLCC and DDR_QOS). Model each bus as a devfreq device using the remote devfreq governor. This provides basic insight into device operation via trans_stat and allows further tuning of the remote governor's parameters from userspace. Co-developed-by: Amir Vajid Signed-off-by: Amir Vajid Co-developed-by: Ramakrishna Gottimukkula Signed-off-by: Ramakrishna Gottimukkula Signed-off-by: Sibi Sankar Co-developed-by: Pragnesh Papaniya Signed-off-by: Pragnesh Papaniya --- drivers/devfreq/Kconfig | 13 + drivers/devfreq/Makefile | 1 + drivers/devfreq/scmi-qcom-memlat-cfg.h | 573 +++++++++++++++++++++++++= ++ drivers/devfreq/scmi-qcom-memlat-devfreq.c | 616 +++++++++++++++++++++++++= ++++ 4 files changed, 1203 insertions(+) diff --git a/drivers/devfreq/Kconfig b/drivers/devfreq/Kconfig index 2caa87554914..98b5a50d3189 100644 --- a/drivers/devfreq/Kconfig +++ b/drivers/devfreq/Kconfig @@ -169,6 +169,19 @@ config ARM_SUN8I_A33_MBUS_DEVFREQ This adds the DEVFREQ driver for the MBUS controller in some Allwinner sun8i (A33 through H3) and sun50i (A64 and H5) SoCs. =20 +config SCMI_QCOM_MEMLAT_DEVFREQ + tristate "Qualcomm Technologies Inc. SCMI client driver" + depends on QCOM_SCMI_GENERIC_EXT || COMPILE_TEST + select DEVFREQ_GOV_REMOTE + help + This driver uses the MEMLAT (memory latency) algorithm string + hosted on QCOM SCMI Vendor Protocol to detect memory latency + workloads and control frequency/level of the various memory + buses (DDR/LLCC/DDR_QOS). + + This driver defines/documents the parameter IDs used while configuring + the memory buses. + source "drivers/devfreq/event/Kconfig" =20 endif # PM_DEVFREQ diff --git a/drivers/devfreq/Makefile b/drivers/devfreq/Makefile index cde57c8cda76..b11f94e2f485 100644 --- a/drivers/devfreq/Makefile +++ b/drivers/devfreq/Makefile @@ -17,6 +17,7 @@ obj-$(CONFIG_ARM_MEDIATEK_CCI_DEVFREQ) +=3D mtk-cci-devfr= eq.o obj-$(CONFIG_ARM_RK3399_DMC_DEVFREQ) +=3D rk3399_dmc.o obj-$(CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ) +=3D sun8i-a33-mbus.o obj-$(CONFIG_ARM_TEGRA_DEVFREQ) +=3D tegra30-devfreq.o +obj-$(CONFIG_SCMI_QCOM_MEMLAT_DEVFREQ) +=3D scmi-qcom-memlat-devfreq.o =20 # DEVFREQ Event Drivers obj-$(CONFIG_PM_DEVFREQ_EVENT) +=3D event/ diff --git a/drivers/devfreq/scmi-qcom-memlat-cfg.h b/drivers/devfreq/scmi-= qcom-memlat-cfg.h new file mode 100644 index 000000000000..1ab8b61ea271 --- /dev/null +++ b/drivers/devfreq/scmi-qcom-memlat-cfg.h @@ -0,0 +1,573 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef __DRIVERS_DEVFREQ_SCMI_QCOM_MEMLAT_CONFIG_H__ +#define __DRIVERS_DEVFREQ_SCMI_QCOM_MEMLAT_CONFIG_H__ + +/* + * Memlat Effective Frequency Calculation Method + * CPUCP_EFFECTIVE_FREQ_METHOD_0 - Uses CPU Cycles and CONST Cycles to cal= culate + * CPUCP_EFFECTIVE_FREQ_METHOD_1 - Uses CPU Cycles and time period + */ +#define CPUCP_EFFECTIVE_FREQ_CALC_METHOD_0 0 +#define CPUCP_EFFECTIVE_FREQ_CALC_METHOD_1 1 + +#define EV_CPU_CYCLES 0 +#define EV_CNT_CYCLES 1 +#define EV_INST_RETIRED 2 +#define EV_STALL_BACKEND_MEM 3 +#define EV_L2_D_RFILL 5 +#define INVALID_IDX 0xff + +#define MEMLAT_ALGO_STR 0x4D454D4C4154ULL /* MEMLAT */ + +struct scmi_qcom_map_table { + unsigned int cpu_freq; + unsigned int mem_freq; +}; + +struct scmi_qcom_opp_data { + unsigned long freq; + unsigned int level; +}; + +struct scmi_qcom_memory_range { + unsigned int min_freq; + unsigned int max_freq; +}; + +enum common_ev_idx { + INST_IDX, + CYC_IDX, + CONST_CYC_IDX, + FE_STALL_IDX, + BE_STALL_IDX, + NUM_COMMON_EVS +}; + +enum grp_ev_idx { + MISS_IDX, + WB_IDX, + ACC_IDX, + NUM_GRP_EVS +}; + +/* + * CPUCP firmware identifies memory groups by a small integer (the hw_type + * carried in node_msg / scalar_param_msg / map_param_msg / ev_map_msg). T= he + * encoding is shared between the cfg tables below and scmi_qcom_devfreq_g= et_cur_freq() + * which special-cases DDR_QOS as a level-based bus rather than a frequenc= y-scaled one. + */ +enum scmi_qcom_memlat_hw_type { + MEMLAT_HW_DDR =3D 0, + MEMLAT_HW_LLCC =3D 1, + MEMLAT_HW_DDR_QOS_COMPUTE =3D 2, +}; + +struct scmi_qcom_monitor_cfg { + const struct scmi_qcom_map_table *table; + const char *name; + u32 be_stall_floor; + u32 cpu_mask; + u32 ipm_ceil; + int table_len; +}; + +struct scmi_qcom_memory_cfg { + const struct scmi_qcom_monitor_cfg *monitor_cfg; + const struct scmi_qcom_opp_data *mem_table; + struct scmi_qcom_memory_range memory_range; + const u32 *grp_ev; + const char *name; + u32 memory_type; + int monitor_cnt; + int num_opps; +}; + +struct scmi_qcom_memlat_cfg_data { + const struct scmi_qcom_memory_cfg *memory_cfg; + const u32 *common_ev; + u32 cpucp_freq_method; + u32 cpucp_sample_ms; + int memory_cnt; +}; + +static const u32 glymur_common_ev[NUM_COMMON_EVS] =3D { + [INST_IDX] =3D EV_INST_RETIRED, + [CYC_IDX] =3D EV_CPU_CYCLES, + [CONST_CYC_IDX] =3D EV_CNT_CYCLES, + [FE_STALL_IDX] =3D INVALID_IDX, + [BE_STALL_IDX] =3D EV_STALL_BACKEND_MEM, +}; + +static const u32 glymur_ddr_grp_ev[NUM_GRP_EVS] =3D { + [MISS_IDX] =3D EV_L2_D_RFILL, + [WB_IDX] =3D INVALID_IDX, + [ACC_IDX] =3D INVALID_IDX, +}; + +static const u32 glymur_llcc_grp_ev[NUM_GRP_EVS] =3D { + [MISS_IDX] =3D EV_L2_D_RFILL, + [WB_IDX] =3D INVALID_IDX, + [ACC_IDX] =3D INVALID_IDX, +}; + +static const u32 glymur_ddr_qos_grp_ev[NUM_GRP_EVS] =3D { + [MISS_IDX] =3D EV_L2_D_RFILL, + [WB_IDX] =3D INVALID_IDX, + [ACC_IDX] =3D INVALID_IDX, +}; + +static const u32 hamoa_common_ev[NUM_COMMON_EVS] =3D { + [INST_IDX] =3D EV_INST_RETIRED, + [CYC_IDX] =3D EV_CPU_CYCLES, + [CONST_CYC_IDX] =3D EV_CNT_CYCLES, + [FE_STALL_IDX] =3D INVALID_IDX, + [BE_STALL_IDX] =3D EV_STALL_BACKEND_MEM, +}; + +static const u32 hamoa_ddr_grp_ev[NUM_GRP_EVS] =3D { + [MISS_IDX] =3D EV_L2_D_RFILL, + [WB_IDX] =3D INVALID_IDX, + [ACC_IDX] =3D INVALID_IDX, +}; + +static const u32 hamoa_llcc_grp_ev[NUM_GRP_EVS] =3D { + [MISS_IDX] =3D EV_L2_D_RFILL, + [WB_IDX] =3D INVALID_IDX, + [ACC_IDX] =3D INVALID_IDX, +}; + +static const u32 hamoa_ddr_qos_grp_ev[NUM_GRP_EVS] =3D { + [MISS_IDX] =3D EV_L2_D_RFILL, + [WB_IDX] =3D INVALID_IDX, + [ACC_IDX] =3D INVALID_IDX, +}; + +static const struct scmi_qcom_opp_data glymur_llcc_table[] =3D { + { .freq =3D 315000000 }, + { .freq =3D 479000000 }, + { .freq =3D 545000000 }, + { .freq =3D 725000000 }, + { .freq =3D 840000000 }, + { .freq =3D 959000000 }, + { .freq =3D 1090000000 }, + { .freq =3D 1211000000 }, +}; + +static const struct scmi_qcom_opp_data hamoa_llcc_table[] =3D { + { .freq =3D 300000000 }, + { .freq =3D 466000000 }, + { .freq =3D 600000000 }, + { .freq =3D 806000000 }, + { .freq =3D 933000000 }, + { .freq =3D 1066000000 }, +}; + +static const struct scmi_qcom_opp_data glymur_ddr_table[] =3D { + { .freq =3D 200000000 }, + { .freq =3D 547000000 }, + { .freq =3D 1353000000 }, + { .freq =3D 1555000000 }, + { .freq =3D 1708000000 }, + { .freq =3D 2092000000 }, + { .freq =3D 2736000000 }, + { .freq =3D 3187000000 }, + { .freq =3D 3686000000 }, + { .freq =3D 4224000000 }, + { .freq =3D 4761000000 }, +}; + +static const struct scmi_qcom_opp_data hamoa_ddr_table[] =3D { + { .freq =3D 200000000 }, + { .freq =3D 547000000 }, + { .freq =3D 768000000 }, + { .freq =3D 1555000000 }, + { .freq =3D 1708000000 }, + { .freq =3D 2092000000 }, + { .freq =3D 2736000000 }, + { .freq =3D 3187000000 }, + { .freq =3D 3686000000 }, + { .freq =3D 4224000000 }, +}; + +/* + * DDR_QOS is a level-based bus (0 =3D nominal, 1 =3D boost), not a + * frequency-scaled one. The OPP entries below use synthetic frequencies + * (1 / 100) purely as distinct devfreq keys so trans_stat can show + * level transitions. scmi_qcom_devfreq_get_cur_freq() maps the firmware + * level back to the matching key. + */ +static const struct scmi_qcom_opp_data glymur_ddr_qos_table[] =3D { + { .freq =3D 1, .level =3D 0 }, + { .freq =3D 100, .level =3D 1 }, +}; + +static const struct scmi_qcom_memory_cfg glymur_memory_cfg[] =3D { + { + .memory_type =3D MEMLAT_HW_DDR, + .name =3D "ddr", + .mem_table =3D glymur_ddr_table, + .num_opps =3D ARRAY_SIZE(glymur_ddr_table), + .grp_ev =3D glymur_ddr_grp_ev, + .monitor_cnt =3D 4, + .memory_range =3D { .min_freq =3D 547000, .max_freq =3D 4761000}, + .monitor_cfg =3D (const struct scmi_qcom_monitor_cfg[]) { + { + .name =3D "mon_0", + .cpu_mask =3D 0x3f, + .ipm_ceil =3D 60000000, + .be_stall_floor =3D 1, + .table_len =3D 8, + .table =3D (const struct scmi_qcom_map_table[]) { + { .cpu_freq =3D 960, .mem_freq =3D 547000 }, + { .cpu_freq =3D 1133, .mem_freq =3D 1353000 }, + { .cpu_freq =3D 1594, .mem_freq =3D 1555000 }, + { .cpu_freq =3D 1920, .mem_freq =3D 1708000 }, + { .cpu_freq =3D 2228, .mem_freq =3D 2736000 }, + { .cpu_freq =3D 2362, .mem_freq =3D 3187000 }, + { .cpu_freq =3D 2650, .mem_freq =3D 3686000 }, + { .cpu_freq =3D 2938, .mem_freq =3D 4761000 }, + } + }, + { + .name =3D "mon_1", + .cpu_mask =3D 0xfc0, + .ipm_ceil =3D 60000000, + .be_stall_floor =3D 1, + .table_len =3D 8, + .table =3D (const struct scmi_qcom_map_table[]) { + { .cpu_freq =3D 356, .mem_freq =3D 547000 }, + { .cpu_freq =3D 1018, .mem_freq =3D 1353000 }, + { .cpu_freq =3D 1536, .mem_freq =3D 1555000 }, + { .cpu_freq =3D 1748, .mem_freq =3D 1708000 }, + { .cpu_freq =3D 2324, .mem_freq =3D 2736000 }, + { .cpu_freq =3D 2496, .mem_freq =3D 3187000 }, + { .cpu_freq =3D 2900, .mem_freq =3D 3686000 }, + { .cpu_freq =3D 3514, .mem_freq =3D 4761000 }, + } + }, + { + .name =3D "mon_2", + .cpu_mask =3D 0x3f000, + .ipm_ceil =3D 60000000, + .be_stall_floor =3D 1, + .table_len =3D 8, + .table =3D (const struct scmi_qcom_map_table[]) { + { .cpu_freq =3D 356, .mem_freq =3D 547000 }, + { .cpu_freq =3D 1018, .mem_freq =3D 1353000 }, + { .cpu_freq =3D 1536, .mem_freq =3D 1555000 }, + { .cpu_freq =3D 1748, .mem_freq =3D 1708000 }, + { .cpu_freq =3D 2324, .mem_freq =3D 2736000 }, + { .cpu_freq =3D 2496, .mem_freq =3D 3187000 }, + { .cpu_freq =3D 2900, .mem_freq =3D 3686000 }, + { .cpu_freq =3D 3514, .mem_freq =3D 4761000 }, + } + }, + { + .name =3D "mon_3", + .cpu_mask =3D 0x3ffff, + .table_len =3D 4, + .table =3D (const struct scmi_qcom_map_table[]) { + { .cpu_freq =3D 2823, .mem_freq =3D 547000 }, + { .cpu_freq =3D 3034, .mem_freq =3D 1555000 }, + { .cpu_freq =3D 3226, .mem_freq =3D 1708000 }, + { .cpu_freq =3D 5012, .mem_freq =3D 2092000 }, + } + }, + }, + }, + { + .memory_type =3D MEMLAT_HW_LLCC, + .name =3D "llcc", + .mem_table =3D glymur_llcc_table, + .num_opps =3D ARRAY_SIZE(glymur_llcc_table), + .grp_ev =3D glymur_llcc_grp_ev, + .monitor_cnt =3D 3, + .memory_range =3D { .min_freq =3D 315000, .max_freq =3D 1211000}, + .monitor_cfg =3D (const struct scmi_qcom_monitor_cfg[]) { + { + .name =3D "mon_0", + .cpu_mask =3D 0x3f, + .ipm_ceil =3D 60000000, + .be_stall_floor =3D 1, + .table_len =3D 7, + .table =3D (const struct scmi_qcom_map_table[]) { + { .cpu_freq =3D 960, .mem_freq =3D 315000 }, + { .cpu_freq =3D 1113, .mem_freq =3D 479000 }, + { .cpu_freq =3D 1594, .mem_freq =3D 545000 }, + { .cpu_freq =3D 1920, .mem_freq =3D 725000 }, + { .cpu_freq =3D 2362, .mem_freq =3D 840000 }, + { .cpu_freq =3D 2650, .mem_freq =3D 959000 }, + { .cpu_freq =3D 2938, .mem_freq =3D 1211000 }, + } + }, + { + .name =3D "mon_1", + .cpu_mask =3D 0xfc0, + .ipm_ceil =3D 60000000, + .be_stall_floor =3D 1, + .table_len =3D 7, + .table =3D (const struct scmi_qcom_map_table[]) { + { .cpu_freq =3D 356, .mem_freq =3D 315000 }, + { .cpu_freq =3D 1018, .mem_freq =3D 479000 }, + { .cpu_freq =3D 1536, .mem_freq =3D 545000 }, + { .cpu_freq =3D 1748, .mem_freq =3D 725000 }, + { .cpu_freq =3D 2496, .mem_freq =3D 840000 }, + { .cpu_freq =3D 2900, .mem_freq =3D 959000 }, + { .cpu_freq =3D 3514, .mem_freq =3D 1211000 }, + } + }, + { + .name =3D "mon_2", + .cpu_mask =3D 0x3f000, + .ipm_ceil =3D 60000000, + .be_stall_floor =3D 1, + .table_len =3D 7, + .table =3D (const struct scmi_qcom_map_table[]) { + { .cpu_freq =3D 356, .mem_freq =3D 315000 }, + { .cpu_freq =3D 1018, .mem_freq =3D 479000 }, + { .cpu_freq =3D 1536, .mem_freq =3D 545000 }, + { .cpu_freq =3D 1748, .mem_freq =3D 725000 }, + { .cpu_freq =3D 2496, .mem_freq =3D 840000 }, + { .cpu_freq =3D 2900, .mem_freq =3D 959000 }, + { .cpu_freq =3D 3514, .mem_freq =3D 1211000 }, + } + }, + }, + }, + { + .memory_type =3D MEMLAT_HW_DDR_QOS_COMPUTE, + .name =3D "ddr-qos", + .monitor_cnt =3D 3, + .mem_table =3D glymur_ddr_qos_table, + .num_opps =3D ARRAY_SIZE(glymur_ddr_qos_table), + .grp_ev =3D glymur_ddr_qos_grp_ev, + .memory_range =3D { .min_freq =3D 0, .max_freq =3D 1}, + .monitor_cfg =3D (const struct scmi_qcom_monitor_cfg[]) { + { + .name =3D "mon_0", + .cpu_mask =3D 0x3f, + .ipm_ceil =3D 80000000, + .be_stall_floor =3D 1, + .table_len =3D 2, + .table =3D (const struct scmi_qcom_map_table[]) { + { .cpu_freq =3D 2362, .mem_freq =3D 0 }, + { .cpu_freq =3D 2938, .mem_freq =3D 1 }, + } + }, + { + .name =3D "mon_1", + .cpu_mask =3D 0xfc0, + .ipm_ceil =3D 80000000, + .be_stall_floor =3D 1, + .table_len =3D 2, + .table =3D (const struct scmi_qcom_map_table[]) { + { .cpu_freq =3D 2496, .mem_freq =3D 0 }, + { .cpu_freq =3D 3514, .mem_freq =3D 1 }, + } + }, + { + .name =3D "mon_2", + .cpu_mask =3D 0x3f000, + .ipm_ceil =3D 80000000, + .be_stall_floor =3D 1, + .table_len =3D 2, + .table =3D (const struct scmi_qcom_map_table[]) { + { .cpu_freq =3D 2496, .mem_freq =3D 0 }, + { .cpu_freq =3D 3514, .mem_freq =3D 1 }, + } + }, + }, + }, +}; + +static const struct scmi_qcom_memory_cfg hamoa_memory_cfg[] =3D { + { + .memory_type =3D MEMLAT_HW_DDR, + .name =3D "ddr", + .mem_table =3D hamoa_ddr_table, + .num_opps =3D ARRAY_SIZE(hamoa_ddr_table), + .grp_ev =3D hamoa_ddr_grp_ev, + .monitor_cnt =3D 4, + .memory_range =3D { .min_freq =3D 200000, .max_freq =3D 4224000}, + .monitor_cfg =3D (const struct scmi_qcom_monitor_cfg[]) { + { + .name =3D "mon_0", + .cpu_mask =3D 0xf, + .ipm_ceil =3D 20000000, + .be_stall_floor =3D 1, + .table_len =3D 6, + .table =3D (const struct scmi_qcom_map_table[]) { + { .cpu_freq =3D 999, .mem_freq =3D 547000 }, + { .cpu_freq =3D 1440, .mem_freq =3D 768000 }, + { .cpu_freq =3D 1671, .mem_freq =3D 1555000 }, + { .cpu_freq =3D 2189, .mem_freq =3D 2092000 }, + { .cpu_freq =3D 2516, .mem_freq =3D 3187000 }, + { .cpu_freq =3D 3860, .mem_freq =3D 4224000 }, + } + }, + { + .name =3D "mon_1", + .cpu_mask =3D 0xf0, + .ipm_ceil =3D 20000000, + .be_stall_floor =3D 1, + .table_len =3D 6, + .table =3D (const struct scmi_qcom_map_table[]) { + { .cpu_freq =3D 999, .mem_freq =3D 547000 }, + { .cpu_freq =3D 1440, .mem_freq =3D 768000 }, + { .cpu_freq =3D 1671, .mem_freq =3D 1555000 }, + { .cpu_freq =3D 2189, .mem_freq =3D 2092000 }, + { .cpu_freq =3D 2516, .mem_freq =3D 3187000 }, + { .cpu_freq =3D 3860, .mem_freq =3D 4224000 }, + } + }, + { + .name =3D "mon_2", + .cpu_mask =3D 0xf00, + .ipm_ceil =3D 20000000, + .be_stall_floor =3D 1, + .table_len =3D 6, + .table =3D (const struct scmi_qcom_map_table[]) { + { .cpu_freq =3D 999, .mem_freq =3D 547000 }, + { .cpu_freq =3D 1440, .mem_freq =3D 768000 }, + { .cpu_freq =3D 1671, .mem_freq =3D 1555000 }, + { .cpu_freq =3D 2189, .mem_freq =3D 2092000 }, + { .cpu_freq =3D 2516, .mem_freq =3D 3187000 }, + { .cpu_freq =3D 3860, .mem_freq =3D 4224000 }, + } + }, + { + .name =3D "mon_3", + .cpu_mask =3D 0xfff, + .table_len =3D 4, + .table =3D (const struct scmi_qcom_map_table[]) { + { .cpu_freq =3D 1440, .mem_freq =3D 547000 }, + { .cpu_freq =3D 2189, .mem_freq =3D 768000 }, + { .cpu_freq =3D 2516, .mem_freq =3D 1555000 }, + { .cpu_freq =3D 3860, .mem_freq =3D 2092000 }, + } + }, + }, + }, + { + .memory_type =3D MEMLAT_HW_LLCC, + .name =3D "llcc", + .mem_table =3D hamoa_llcc_table, + .num_opps =3D ARRAY_SIZE(hamoa_llcc_table), + .grp_ev =3D hamoa_llcc_grp_ev, + .monitor_cnt =3D 3, + .memory_range =3D { .min_freq =3D 300000, .max_freq =3D 1066000}, + .monitor_cfg =3D (const struct scmi_qcom_monitor_cfg[]) { + { + .name =3D "mon_0", + .cpu_mask =3D 0xf, + .ipm_ceil =3D 20000000, + .be_stall_floor =3D 1, + .table_len =3D 6, + .table =3D (const struct scmi_qcom_map_table[]) { + { .cpu_freq =3D 999, .mem_freq =3D 300000 }, + { .cpu_freq =3D 1440, .mem_freq =3D 466000 }, + { .cpu_freq =3D 1671, .mem_freq =3D 600000 }, + { .cpu_freq =3D 2189, .mem_freq =3D 806000 }, + { .cpu_freq =3D 2516, .mem_freq =3D 933000 }, + { .cpu_freq =3D 3860, .mem_freq =3D 1066000 }, + } + }, + { + .name =3D "mon_1", + .cpu_mask =3D 0xf0, + .ipm_ceil =3D 20000000, + .be_stall_floor =3D 1, + .table_len =3D 6, + .table =3D (const struct scmi_qcom_map_table[]) { + { .cpu_freq =3D 999, .mem_freq =3D 300000 }, + { .cpu_freq =3D 1440, .mem_freq =3D 466000 }, + { .cpu_freq =3D 1671, .mem_freq =3D 600000 }, + { .cpu_freq =3D 2189, .mem_freq =3D 806000 }, + { .cpu_freq =3D 2516, .mem_freq =3D 933000 }, + { .cpu_freq =3D 3860, .mem_freq =3D 1066000 }, + } + }, + { + .name =3D "mon_2", + .cpu_mask =3D 0xf00, + .ipm_ceil =3D 20000000, + .be_stall_floor =3D 1, + .table_len =3D 6, + .table =3D (const struct scmi_qcom_map_table[]) { + { .cpu_freq =3D 999, .mem_freq =3D 300000 }, + { .cpu_freq =3D 1440, .mem_freq =3D 466000 }, + { .cpu_freq =3D 1671, .mem_freq =3D 600000 }, + { .cpu_freq =3D 2189, .mem_freq =3D 806000 }, + { .cpu_freq =3D 2516, .mem_freq =3D 933000 }, + { .cpu_freq =3D 3860, .mem_freq =3D 1066000 }, + } + }, + }, + }, + { + .memory_type =3D MEMLAT_HW_DDR_QOS_COMPUTE, + .name =3D "ddr-qos", + .monitor_cnt =3D 3, + .mem_table =3D glymur_ddr_qos_table, + .num_opps =3D ARRAY_SIZE(glymur_ddr_qos_table), + .grp_ev =3D hamoa_ddr_qos_grp_ev, + .memory_range =3D { .min_freq =3D 0, .max_freq =3D 1}, + .monitor_cfg =3D (const struct scmi_qcom_monitor_cfg[]) { + { + .name =3D "mon_0", + .cpu_mask =3D 0xf, + .ipm_ceil =3D 20000000, + .be_stall_floor =3D 1, + .table_len =3D 2, + .table =3D (const struct scmi_qcom_map_table[]) { + { .cpu_freq =3D 2189, .mem_freq =3D 0 }, + { .cpu_freq =3D 3860, .mem_freq =3D 1 }, + } + }, + { + .name =3D "mon_1", + .cpu_mask =3D 0xf0, + .ipm_ceil =3D 20000000, + .be_stall_floor =3D 1, + .table_len =3D 2, + .table =3D (const struct scmi_qcom_map_table[]) { + { .cpu_freq =3D 2189, .mem_freq =3D 0 }, + { .cpu_freq =3D 3860, .mem_freq =3D 1 }, + } + }, + { + .name =3D "mon_2", + .cpu_mask =3D 0xf00, + .ipm_ceil =3D 20000000, + .be_stall_floor =3D 1, + .table_len =3D 2, + .table =3D (const struct scmi_qcom_map_table[]) { + { .cpu_freq =3D 2189, .mem_freq =3D 0 }, + { .cpu_freq =3D 3860, .mem_freq =3D 1 }, + } + }, + }, + }, +}; + +static const struct scmi_qcom_memlat_cfg_data glymur_memlat_data =3D { + .memory_cfg =3D glymur_memory_cfg, + .common_ev =3D glymur_common_ev, + .cpucp_freq_method =3D CPUCP_EFFECTIVE_FREQ_CALC_METHOD_1, + .cpucp_sample_ms =3D 4, + .memory_cnt =3D ARRAY_SIZE(glymur_memory_cfg), +}; + +static const struct scmi_qcom_memlat_cfg_data hamoa_memlat_data =3D { + .memory_cfg =3D hamoa_memory_cfg, + .common_ev =3D hamoa_common_ev, + .cpucp_freq_method =3D CPUCP_EFFECTIVE_FREQ_CALC_METHOD_1, + .cpucp_sample_ms =3D 4, + .memory_cnt =3D ARRAY_SIZE(hamoa_memory_cfg), +}; + +#endif diff --git a/drivers/devfreq/scmi-qcom-memlat-devfreq.c b/drivers/devfreq/s= cmi-qcom-memlat-devfreq.c new file mode 100644 index 000000000000..99ae229acfdc --- /dev/null +++ b/drivers/devfreq/scmi-qcom-memlat-devfreq.c @@ -0,0 +1,616 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MAX_NAME_LEN 20 +#define MAX_MAP_ENTRIES 10 + +#include "scmi-qcom-memlat-cfg.h" + +/** + * enum scmi_memlat_protocol_cmd - parameter_ids supported by the "MEMLAT"= algo_str hosted + * by the Qualcomm Generic Vendor Protocol= on the SCMI controller. + * + * MEMLAT (Memory Latency) monitors the counters to detect memory latency = bound workloads + * and scales the frequency/levels of the memory buses accordingly. + * + * @MEMLAT_SET_MEM_GROUP: initializes the frequency/level scaling function= s for the memory bus. + * @MEMLAT_SET_MONITOR: configures the monitor to work on a specific memor= y bus. + * @MEMLAT_SET_COMMON_EV_MAP: set up common counters used to monitor the c= pu frequency. + * @MEMLAT_SET_GRP_EV_MAP: set up any specific counters used to monitor th= e memory bus. + * @MEMLAT_IPM_CEIL: set the IPM (Instruction Per Misses) ceiling per moni= tor. + * @MEMLAT_BE_STALL_FLOOR: set the back-end stall floor per monitor. + * @MEMLAT_SAMPLE_MS: set the sampling period for all the monitors. + * @MEMLAT_MON_FREQ_MAP: setup the cpufreq to memfreq map. + * @MEMLAT_SET_MIN_FREQ: set the min frequency of the memory bus. + * @MEMLAT_SET_MAX_FREQ: set the max frequency of the memory bus. + * @MEMLAT_GET_CUR_FREQ: query the current frequency/level of the memory b= us. + * @MEMLAT_START_TIMER: start all the monitors with the requested sampling= period. + * @MEMLAT_STOP_TIMER: stop all the running monitors. + * @MEMLAT_SET_EFFECTIVE_FREQ_METHOD: set the method used to determine cpu= frequency. + */ +enum scmi_memlat_protocol_cmd { + MEMLAT_SET_MEM_GROUP =3D 16, + MEMLAT_SET_MONITOR, + MEMLAT_SET_COMMON_EV_MAP, + MEMLAT_SET_GRP_EV_MAP, + MEMLAT_IPM_CEIL =3D 23, + MEMLAT_BE_STALL_FLOOR =3D 25, + MEMLAT_SAMPLE_MS =3D 31, + MEMLAT_MON_FREQ_MAP, + MEMLAT_SET_MIN_FREQ, + MEMLAT_SET_MAX_FREQ, + MEMLAT_GET_CUR_FREQ, + MEMLAT_START_TIMER =3D 36, + MEMLAT_STOP_TIMER, + MEMLAT_SET_EFFECTIVE_FREQ_METHOD =3D 39, +}; + +struct cpucp_map_table { + __le16 v1; + __le16 v2; +}; + +struct map_param_msg { + __le32 hw_type; + __le32 mon_idx; + __le32 nr_rows; + struct cpucp_map_table tbl[MAX_MAP_ENTRIES]; +} __packed; + +struct node_msg { + __le32 cpumask; + __le32 hw_type; + __le32 mon_type; + __le32 mon_idx; + char mon_name[MAX_NAME_LEN]; +}; + +struct scalar_param_msg { + __le32 hw_type; + __le32 mon_idx; + __le32 val; +}; + +struct ev_map_msg { + __le32 num_evs; + __le32 hw_type; + __le32 cid[NUM_COMMON_EVS]; +}; + +struct scmi_qcom_memlat_map { + unsigned int cpufreq_mhz; + unsigned int memfreq_khz; +}; + +struct scmi_qcom_monitor_info { + struct scmi_qcom_memlat_map *freq_map; + char name[MAX_NAME_LEN]; + u32 mon_idx; + u32 mon_type; + u32 ipm_ceil; + u32 be_stall_floor; + u32 mask; + u32 freq_map_len; +}; + +struct scmi_qcom_memory_info { + struct scmi_qcom_monitor_info **monitor; + u32 hw_type; + int monitor_cnt; + u32 min_freq; + u32 max_freq; + struct devfreq_dev_profile profile; + struct devfreq *devfreq; + struct platform_device *pdev; + struct scmi_protocol_handle *ph; + const struct qcom_generic_ext_ops *ops; +}; + +struct scmi_qcom_memlat_info { + struct scmi_protocol_handle *ph; + const struct qcom_generic_ext_ops *ops; + const struct scmi_qcom_memlat_cfg_data *cfg_data; + struct scmi_qcom_memory_info **memory; + u32 cpucp_freq_method; + u32 cpucp_sample_ms; + int memory_cnt; +}; + +static int configure_cpucp_common_events(struct scmi_qcom_memlat_info *inf= o, + const struct scmi_qcom_memlat_cfg_data *cfg_data) +{ + const struct qcom_generic_ext_ops *ops =3D info->ops; + struct ev_map_msg msg =3D {}; + int i; + + msg.num_evs =3D cpu_to_le32(NUM_COMMON_EVS); + /* Common events apply to all groups; INVALID_IDX flags "no specific grou= p". */ + msg.hw_type =3D cpu_to_le32(INVALID_IDX); + for (i =3D 0; i < NUM_COMMON_EVS; i++) + msg.cid[i] =3D cpu_to_le32(cfg_data->common_ev[i]); + + return ops->set_param(info->ph, &msg, sizeof(msg), MEMLAT_ALGO_STR, + MEMLAT_SET_COMMON_EV_MAP); +} + +static int configure_cpucp_grp(struct device *dev, struct scmi_qcom_memlat= _info *info, + const struct scmi_qcom_memlat_cfg_data *cfg_data, + int memory_index) +{ + const u32 *grp_ev =3D cfg_data->memory_cfg[memory_index].grp_ev; + struct scmi_qcom_memory_info *memory =3D info->memory[memory_index]; + const struct qcom_generic_ext_ops *ops =3D info->ops; + struct ev_map_msg ev_msg =3D {}; + struct node_msg msg =3D {}; + int ret; + int i; + + msg.cpumask =3D cpu_to_le32(*cpumask_bits(cpu_possible_mask)); + msg.hw_type =3D cpu_to_le32(memory->hw_type); + msg.mon_type =3D 0; + msg.mon_idx =3D 0; + ret =3D ops->set_param(info->ph, &msg, sizeof(msg), MEMLAT_ALGO_STR, MEML= AT_SET_MEM_GROUP); + if (ret < 0) + return dev_err_probe(dev, ret, "failed to configure mem type %d\n", + memory->hw_type); + + ev_msg.num_evs =3D cpu_to_le32(NUM_GRP_EVS); + ev_msg.hw_type =3D cpu_to_le32(memory->hw_type); + for (i =3D 0; i < NUM_GRP_EVS; i++) + ev_msg.cid[i] =3D cpu_to_le32(grp_ev[i]); + + ret =3D ops->set_param(info->ph, &ev_msg, sizeof(ev_msg), MEMLAT_ALGO_STR, + MEMLAT_SET_GRP_EV_MAP); + if (ret < 0) + return dev_err_probe(dev, ret, "failed to configure event map for mem ty= pe %d\n", + memory->hw_type); + + return ret; +} + +static int configure_cpucp_mon(struct device *dev, struct scmi_qcom_memlat= _info *info, + int memory_index, int monitor_index) +{ + const struct qcom_generic_ext_ops *ops =3D info->ops; + struct scmi_qcom_memory_info *memory =3D info->memory[memory_index]; + struct scmi_qcom_monitor_info *monitor =3D memory->monitor[monitor_index]; + struct scalar_param_msg scalar_msg =3D {}; + struct map_param_msg map_msg =3D {}; + struct node_msg msg =3D {}; + int ret; + int i; + + msg.cpumask =3D cpu_to_le32(monitor->mask); + msg.hw_type =3D cpu_to_le32(memory->hw_type); + msg.mon_type =3D cpu_to_le32(monitor->mon_type); + msg.mon_idx =3D cpu_to_le32(monitor->mon_idx); + strscpy(msg.mon_name, monitor->name, sizeof(msg.mon_name)); + ret =3D ops->set_param(info->ph, &msg, sizeof(msg), MEMLAT_ALGO_STR, MEML= AT_SET_MONITOR); + if (ret < 0) + return dev_err_probe(dev, ret, "failed to configure monitor %s\n", + monitor->name); + + scalar_msg.hw_type =3D cpu_to_le32(memory->hw_type); + scalar_msg.mon_idx =3D cpu_to_le32(monitor->mon_idx); + scalar_msg.val =3D cpu_to_le32(monitor->ipm_ceil); + ret =3D ops->set_param(info->ph, &scalar_msg, sizeof(scalar_msg), MEMLAT_= ALGO_STR, + MEMLAT_IPM_CEIL); + if (ret < 0) + return dev_err_probe(dev, ret, "failed to set ipm ceil for %s\n", + monitor->name); + + scalar_msg.hw_type =3D cpu_to_le32(memory->hw_type); + scalar_msg.mon_idx =3D cpu_to_le32(monitor->mon_idx); + scalar_msg.val =3D cpu_to_le32(monitor->be_stall_floor); + ret =3D ops->set_param(info->ph, &scalar_msg, sizeof(scalar_msg), MEMLAT_= ALGO_STR, + MEMLAT_BE_STALL_FLOOR); + if (ret < 0) + return dev_err_probe(dev, ret, "failed to set be_stall_floor for %s\n", + monitor->name); + + map_msg.hw_type =3D cpu_to_le32(memory->hw_type); + map_msg.mon_idx =3D cpu_to_le32(monitor->mon_idx); + map_msg.nr_rows =3D cpu_to_le32(monitor->freq_map_len); + for (i =3D 0; i < monitor->freq_map_len; i++) { + map_msg.tbl[i].v1 =3D cpu_to_le16(monitor->freq_map[i].cpufreq_mhz); + + /* + * Wire format v2 is u16 in MHz; convert from kHz. For DDR_QOS + * the table holds level indices (0 / 1) rather than real + * frequencies, so pass them through unchanged. + */ + if (monitor->freq_map[i].memfreq_khz > 1) + map_msg.tbl[i].v2 =3D cpu_to_le16(monitor->freq_map[i].memfreq_khz / 10= 00); + else + map_msg.tbl[i].v2 =3D cpu_to_le16(monitor->freq_map[i].memfreq_khz); + } + ret =3D ops->set_param(info->ph, &map_msg, sizeof(map_msg), MEMLAT_ALGO_S= TR, + MEMLAT_MON_FREQ_MAP); + if (ret < 0) + return dev_err_probe(dev, ret, "failed to configure freq_map for %s\n", + monitor->name); + + scalar_msg.hw_type =3D cpu_to_le32(memory->hw_type); + scalar_msg.mon_idx =3D cpu_to_le32(monitor->mon_idx); + scalar_msg.val =3D cpu_to_le32(memory->min_freq); + ret =3D ops->set_param(info->ph, &scalar_msg, sizeof(scalar_msg), MEMLAT_= ALGO_STR, + MEMLAT_SET_MIN_FREQ); + if (ret < 0) + return dev_err_probe(dev, ret, "failed to set min_freq for %s\n", + monitor->name); + + scalar_msg.hw_type =3D cpu_to_le32(memory->hw_type); + scalar_msg.mon_idx =3D cpu_to_le32(monitor->mon_idx); + scalar_msg.val =3D cpu_to_le32(memory->max_freq); + ret =3D ops->set_param(info->ph, &scalar_msg, sizeof(scalar_msg), MEMLAT_= ALGO_STR, + MEMLAT_SET_MAX_FREQ); + if (ret < 0) + return dev_err_probe(dev, ret, "failed to set max_freq for %s\n", monito= r->name); + + return ret; +} + +static int scmi_qcom_devfreq_get_cur_freq(struct device *dev, unsigned lon= g *freq) +{ + struct scmi_qcom_memory_info *memory =3D dev_get_drvdata(dev); + const struct qcom_generic_ext_ops *ops =3D memory->ops; + struct scalar_param_msg scalar_msg =3D {}; + u32 max_freq_khz =3D 0; + __le32 cur_freq; + int ret, i; + + /* + * MEMLAT_GET_CUR_FREQ returns target_freq for a single (hw_type, + * mon_idx) tuple. The bus's actual voted frequency is the max across + * all configured monitors in the group, so query each one and pick + * the highest vote. + */ + for (i =3D 0; i < memory->monitor_cnt; i++) { + scalar_msg.hw_type =3D cpu_to_le32(memory->hw_type); + scalar_msg.mon_idx =3D cpu_to_le32(memory->monitor[i]->mon_idx); + scalar_msg.val =3D 0; + + ret =3D ops->get_param(memory->ph, &scalar_msg, sizeof(scalar_msg), + MEMLAT_ALGO_STR, MEMLAT_GET_CUR_FREQ, + sizeof(cur_freq)); + if (ret < 0) { + dev_err(dev, "failed to get current frequency for %s\n", + memory->monitor[i]->name); + return ret; + } + + /* qcom_scmi_common_xfer() returns the response into the same tx buffer.= */ + memcpy(&cur_freq, &scalar_msg, sizeof(cur_freq)); + if (le32_to_cpu(cur_freq) > max_freq_khz) + max_freq_khz =3D le32_to_cpu(cur_freq); + } + + /* + * Frequency-scaled buses (DDR/LLCC) report cur_freq in kHz; convert + * to Hz to match the devfreq OPP table units. Level-based buses + * (e.g. DDR_QOS_COMPUTE) configure max_freq =3D=3D 1 because the firmware + * reports a 0/1 level rather than a frequency, and the matching + * synthetic OPP keys (1 / 100) live in glymur_ddr_qos_table. + */ + if (memory->max_freq > 1) + *freq =3D max_freq_khz * 1000UL; + else + *freq =3D max_freq_khz ? 100 : 1; + + return 0; +} + +static void scmi_qcom_memlat_unwind(struct scmi_qcom_memlat_info *info, in= t count) +{ + for (int i =3D 0; i < count; i++) { + struct scmi_qcom_memory_info *memory =3D info->memory[i]; + + if (IS_ERR_OR_NULL(memory) || IS_ERR_OR_NULL(memory->pdev)) + continue; + + dev_pm_opp_remove_all_dynamic(&memory->pdev->dev); + platform_device_unregister(memory->pdev); + } +} + +static int scmi_qcom_memlat_configure_events(struct scmi_device *sdev, + struct scmi_qcom_memlat_info *info) +{ + const struct qcom_generic_ext_ops *ops =3D info->ops; + struct scmi_protocol_handle *ph =3D info->ph; + __le32 sample_ms, freq_method; + int i, j, ret; + + /* Configure common events ids */ + ret =3D configure_cpucp_common_events(info, info->cfg_data); + if (ret < 0) + return dev_err_probe(&sdev->dev, ret, "failed to configure common events= \n"); + + for (i =3D 0; i < info->memory_cnt; i++) { + /* Configure per group parameters */ + ret =3D configure_cpucp_grp(&sdev->dev, info, info->cfg_data, i); + if (ret < 0) + return ret; + + for (j =3D 0; j < info->memory[i]->monitor_cnt; j++) { + /* Configure per monitor parameters */ + ret =3D configure_cpucp_mon(&sdev->dev, info, i, j); + if (ret < 0) + return ret; + } + } + + /* Set loop sampling time */ + sample_ms =3D cpu_to_le32(info->cpucp_sample_ms); + ret =3D ops->set_param(ph, &sample_ms, sizeof(sample_ms), + MEMLAT_ALGO_STR, MEMLAT_SAMPLE_MS); + if (ret < 0) + return dev_err_probe(&sdev->dev, ret, "failed to set sample_ms\n"); + + /* Set the effective cpu frequency calculation method */ + freq_method =3D cpu_to_le32(info->cpucp_freq_method); + ret =3D ops->set_param(ph, &freq_method, sizeof(freq_method), + MEMLAT_ALGO_STR, MEMLAT_SET_EFFECTIVE_FREQ_METHOD); + if (ret < 0) + return dev_err_probe(&sdev->dev, ret, + "failed to set effective frequency calc method\n"); + + /* Start sampling and voting timer */ + ret =3D ops->start_activity(ph, NULL, 0, MEMLAT_ALGO_STR, MEMLAT_START_TI= MER); + if (ret < 0) + return dev_err_probe(&sdev->dev, ret, "failed to start memory group time= r\n"); + + for (i =3D 0; i < info->memory_cnt; i++) { + struct scmi_qcom_memory_info *memory =3D info->memory[i]; + struct platform_device *pdev =3D memory->pdev; + struct devfreq_dev_profile *profile =3D &memory->profile; + + /* sampling time should be double the devfreq observing time */ + profile->polling_ms =3D max(1U, info->cpucp_sample_ms / 2); + profile->get_cur_freq =3D scmi_qcom_devfreq_get_cur_freq; + profile->initial_freq =3D memory->min_freq > 1 ? + (memory->min_freq * 1000UL) : memory->min_freq; + + platform_set_drvdata(pdev, memory); + + memory->devfreq =3D devm_devfreq_add_device(&pdev->dev, profile, + DEVFREQ_GOV_REMOTE, NULL); + if (IS_ERR(memory->devfreq)) { + dev_err(&sdev->dev, "failed to add devfreq device\n"); + /* Stop sampling and voting timer */ + ret =3D ops->stop_activity(ph, NULL, 0, MEMLAT_ALGO_STR, MEMLAT_STOP_TI= MER); + if (ret < 0) + dev_err_probe(&sdev->dev, ret, + "failed to stop memory group timer\n"); + return PTR_ERR(memory->devfreq); + } + } + + return 0; +} + +static struct scmi_qcom_memlat_map * +scmi_qcom_parse_memlat_map(struct device *dev, const struct scmi_qcom_moni= tor_cfg *mon_cfg) +{ + struct scmi_qcom_memlat_map *map_table; + const struct scmi_qcom_map_table *table; + + if (mon_cfg->table_len > MAX_MAP_ENTRIES) + return ERR_PTR(-EINVAL); + + map_table =3D devm_kcalloc(dev, mon_cfg->table_len, sizeof(*map_table), + GFP_KERNEL); + if (!map_table) + return ERR_PTR(-ENOMEM); + + for (int i =3D 0; i < mon_cfg->table_len; i++) { + table =3D &mon_cfg->table[i]; + + map_table[i].cpufreq_mhz =3D table->cpu_freq; + map_table[i].memfreq_khz =3D table->mem_freq; + } + + return map_table; +} + +static const struct of_device_id scmi_qcom_memlat_configs[] =3D { + { .compatible =3D "qcom,glymur", .data =3D &glymur_memlat_data}, + { .compatible =3D "qcom,mahua", .data =3D &glymur_memlat_data}, + { .compatible =3D "qcom,x1e80100", .data =3D &hamoa_memlat_data}, + { .compatible =3D "qcom,x1p42100", .data =3D &hamoa_memlat_data}, + { } +}; + +static int scmi_qcom_memlat_parse_cfg(struct scmi_device *sdev, struct scm= i_qcom_memlat_info *info) +{ + const struct scmi_qcom_memlat_cfg_data *cfg_data; + struct scmi_qcom_monitor_info *monitor; + struct scmi_qcom_memory_info *memory; + int ret, i, j; + + cfg_data =3D of_machine_get_match_data(scmi_qcom_memlat_configs); + if (!cfg_data) { + /* + * The SCMI generic-ext protocol can bind on Qualcomm SoCs that + * do not ship CPUCP memlat. Bail out quietly in that case rather + * than printing an error on every such system. + */ + dev_dbg(&sdev->dev, "no memlat config data for this platform\n"); + return -ENODEV; + } + + info->memory =3D devm_kcalloc(&sdev->dev, cfg_data->memory_cnt, + sizeof(*info->memory), GFP_KERNEL); + if (!info->memory) + return -ENOMEM; + + for (i =3D 0; i < cfg_data->memory_cnt; i++) { + const struct scmi_qcom_memory_cfg *memory_cfg =3D &cfg_data->memory_cfg[= i]; + struct platform_device_info pdevinfo =3D { 0 }; + + pdevinfo.parent =3D &sdev->dev; + pdevinfo.name =3D memory_cfg->name; + pdevinfo.id =3D PLATFORM_DEVID_NONE; + + memory =3D devm_kzalloc(&sdev->dev, sizeof(*memory), GFP_KERNEL); + if (!memory) + return -ENOMEM; + + memory->ops =3D info->ops; + memory->ph =3D info->ph; + memory->hw_type =3D memory_cfg->memory_type; + memory->monitor_cnt =3D memory_cfg->monitor_cnt; + memory->min_freq =3D memory_cfg->memory_range.min_freq; + memory->max_freq =3D memory_cfg->memory_range.max_freq; + + memory->pdev =3D platform_device_register_full(&pdevinfo); + if (IS_ERR(memory->pdev)) + return dev_err_probe(&sdev->dev, PTR_ERR(memory->pdev), + "failed to register platform device\n"); + + info->memory[i] =3D memory; + /* Track progress so probe() can unwind on a later failure. */ + info->memory_cnt =3D i + 1; + + for (j =3D 0; j < memory_cfg->num_opps; j++) { + const struct scmi_qcom_opp_data *table =3D &memory_cfg->mem_table[j]; + struct platform_device *pdev =3D memory->pdev; + struct dev_pm_opp_data data =3D {}; + + data.freq =3D table->freq; + data.level =3D table->level; + + ret =3D dev_pm_opp_add_dynamic(&pdev->dev, &data); + if (ret) + return dev_err_probe(&sdev->dev, ret, "failed to add OPP\n"); + } + + memory->monitor =3D devm_kcalloc(&sdev->dev, memory_cfg->monitor_cnt, + sizeof(*memory->monitor), GFP_KERNEL); + if (!memory->monitor) + return -ENOMEM; + + for (j =3D 0; j < memory_cfg->monitor_cnt; j++) { + const struct scmi_qcom_monitor_cfg *mon_cfg =3D &memory_cfg->monitor_cf= g[j]; + + monitor =3D devm_kzalloc(&sdev->dev, sizeof(*monitor), GFP_KERNEL); + if (!monitor) + return -ENOMEM; + + monitor->ipm_ceil =3D mon_cfg->ipm_ceil; + /* mon_type 0 =3D IPM-based latency monitor; 1 =3D stall-only (compute)= */ + monitor->mon_type =3D monitor->ipm_ceil ? 0 : 1; + monitor->be_stall_floor =3D mon_cfg->be_stall_floor; + monitor->mask =3D mon_cfg->cpu_mask; + monitor->freq_map_len =3D mon_cfg->table_len; + + monitor->freq_map =3D scmi_qcom_parse_memlat_map(&sdev->dev, mon_cfg); + if (IS_ERR(monitor->freq_map)) + return dev_err_probe(&sdev->dev, PTR_ERR(monitor->freq_map), + "failed to populate cpufreq-memfreq map\n"); + + strscpy(monitor->name, mon_cfg->name, sizeof(monitor->name)); + monitor->mon_idx =3D j; + memory->monitor[j] =3D monitor; + } + } + + info->cfg_data =3D cfg_data; + info->cpucp_freq_method =3D cfg_data->cpucp_freq_method; + info->cpucp_sample_ms =3D cfg_data->cpucp_sample_ms; + + return 0; +} + +static int scmi_qcom_devfreq_memlat_probe(struct scmi_device *sdev) +{ + const struct scmi_handle *handle =3D sdev->handle; + const struct qcom_generic_ext_ops *ops; + struct scmi_qcom_memlat_info *info; + struct scmi_protocol_handle *ph; + int ret; + + if (!handle) + return -ENODEV; + + info =3D devm_kzalloc(&sdev->dev, sizeof(*info), GFP_KERNEL); + if (!info) + return -ENOMEM; + + ops =3D handle->devm_protocol_get(sdev, SCMI_PROTOCOL_QCOM_GENERIC, &ph); + if (IS_ERR(ops)) + return PTR_ERR(ops); + + info->ops =3D ops; + info->ph =3D ph; + + ret =3D scmi_qcom_memlat_parse_cfg(sdev, info); + if (ret) { + scmi_qcom_memlat_unwind(info, info->memory_cnt); + return ret; + } + + ret =3D scmi_qcom_memlat_configure_events(sdev, info); + if (ret) { + scmi_qcom_memlat_unwind(info, info->memory_cnt); + return ret; + } + + dev_set_drvdata(&sdev->dev, info); + + return ret; +} + +static void scmi_qcom_devfreq_memlat_remove(struct scmi_device *sdev) +{ + struct scmi_qcom_memlat_info *info =3D dev_get_drvdata(&sdev->dev); + struct scmi_protocol_handle *ph; + const struct qcom_generic_ext_ops *ops; + int ret; + + if (!info) + return; + + ph =3D info->ph; + ops =3D info->ops; + + ret =3D ops->stop_activity(ph, NULL, 0, MEMLAT_ALGO_STR, MEMLAT_STOP_TIME= R); + if (ret < 0) + dev_err(&sdev->dev, "failed to stop memory group timer\n"); + + scmi_qcom_memlat_unwind(info, info->memory_cnt); +} + +static const struct scmi_device_id scmi_id_table[] =3D { + { SCMI_PROTOCOL_QCOM_GENERIC, "qcom-generic-ext" }, + { }, +}; +MODULE_DEVICE_TABLE(scmi, scmi_id_table); + +static struct scmi_driver scmi_qcom_devfreq_memlat_driver =3D { + .name =3D "scmi-qcom-devfreq-memlat", + .probe =3D scmi_qcom_devfreq_memlat_probe, + .remove =3D scmi_qcom_devfreq_memlat_remove, + .id_table =3D scmi_id_table, +}; +module_scmi_driver(scmi_qcom_devfreq_memlat_driver); + +MODULE_AUTHOR("Pragnesh Papaniya "); +MODULE_DESCRIPTION("SCMI QCOM DEVFREQ MEMLAT driver"); +MODULE_LICENSE("GPL"); --=20 2.34.1 From nobody Fri Jul 24 21:55:29 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5137E3C1082 for ; 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Add the CPUCP mailbox and SCMI nodes required for the QCOM SCMI Generic Extension protocol to probe and get functional bus dvfs on Glymur/Mahua SoCs. Signed-off-by: Sibi Sankar Signed-off-by: Pragnesh Papaniya --- arch/arm64/boot/dts/qcom/glymur.dtsi | 41 ++++++++++++++++++++++++++++++++= ++++ 1 file changed, 41 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qco= m/glymur.dtsi index 20b49af7298e..c0edbfefc39a 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -396,6 +396,20 @@ scmi_perf: protocol@13 { #power-domain-cells =3D <1>; }; }; + + cpucp_scmi: scmi-1 { + compatible =3D "arm,scmi"; + mboxes =3D <&cpucp_mbox 0>, <&cpucp_mbox 2>; + mbox-names =3D "tx", "rx"; + shmem =3D <&cpucp_scp_lpri0>, <&cpucp_scp_lpri1>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + scmi_vendor: protocol@80 { + reg =3D <0x80>; + }; + }; }; =20 clk_virt: interconnect-0 { @@ -6919,6 +6933,13 @@ pdp0_mbox: mailbox@17610000 { #mbox-cells =3D <1>; }; =20 + cpucp_mbox: mailbox@17620000 { + compatible =3D "qcom,glymur-cpucp-mbox", "qcom,x1e80100-cpucp-mbox"; + reg =3D <0x0 0x17620000 0 0x8000>, <0 0x18830000 0 0x8000>; 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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2c24edc8acasm114618175ad.45.2026.06.10.01.52.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jun 2026 01:52:58 -0700 (PDT) From: Pragnesh Papaniya Date: Wed, 10 Jun 2026 14:21:36 +0530 Subject: [PATCH RFC v7 9/9] arm64: dts: qcom: hamoa: Enable LLCC/DDR/DDR_QOS DVFS Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260610-rfc_v7_scmi_memlat-v7-9-f3f68c608f25@oss.qualcomm.com> References: <20260610-rfc_v7_scmi_memlat-v7-0-f3f68c608f25@oss.qualcomm.com> In-Reply-To: <20260610-rfc_v7_scmi_memlat-v7-0-f3f68c608f25@oss.qualcomm.com> To: Sudeep Holla , Cristian Marussi , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sibi Sankar , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Dmitry Osipenko , Thierry Reding , Jonathan Hunter , Bjorn Andersson , Konrad Dybcio Cc: Pragnesh Papaniya , Rajendra Nayak , Pankaj Patil , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, arm-scmi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1781081505; l=1003; i=pragnesh.papaniya@oss.qualcomm.com; s=20260120; h=from:subject:message-id; bh=pXpBJ2FMnY6lmbenFJPBDk6Hui+mpMlqsnwiYYUFJmo=; b=uT4AQ8s4GwpWbVI++rigQjrmSyRqAQMCzp8wBbLKhIUF3mfkUffjvFW1pE/JgbPI1qyccp7MQ 4sSndpiP+qnBIfJzgN8ufxlztds4HuRMkws/Lip7QRcUDuuys14yYEs X-Developer-Key: i=pragnesh.papaniya@oss.qualcomm.com; a=ed25519; pk=09P9nFmZLXJ9+4Jx10ZK5rIW0Fmk79A/DLErm6aVA0c= X-Authority-Analysis: v=2.4 cv=Gu1yPE1C c=1 sm=1 tr=0 ts=6a2925eb cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=EUspDBNiAAAA:8 a=8E_iI_7X9U7aA52Mj5gA:9 a=QEXdDO2ut3YA:10 a=1OuFwYUASf3TG4hYMiVC:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjEwMDA4MyBTYWx0ZWRfXwLTKkxlDV71G UwDJZ51gcz8ywceo5Hhfqb1GTfUsBRTAzut27tNkuvhHl/YuydYLnaUw6DwBEbX93gTV0euInOL sfY2W/K0dzhTDCuqZ4cHq38peSMZ1AYdv4ftldKejAHuI+jPzM7fg6rXLzMMV2NqJvJqlDT2+Ew Of6d3XFQtJYyvpty0EgR+M/PJQNRAOh2Ha0HIArnwM5QrR2MNmBT/1UMaZnBwQTzwdDuM0kKyMJ 6xh0fJm/kdMVOK/0t6p5EIfgMkuoCeArYc+Nl2ORTn5pfHmz3QkFlVC+kLavTTi2d6VOP3rijUr hr5EIhcbaZoBVe5IkVZQUbc7SUPCA1VGhyIeGzesla4l4DCwsOSeEvC0FR5Q00IItkwtbqpngLU u2ePRBlehQ3eZw6aMPFCNiy0vEB/AJkDOvO4mwmyshpDI7IXClbFUbM6S8vtEaCex/krGHSBFoJ EpvE2mnKmYjxNIXoHnw== X-Proofpoint-ORIG-GUID: QIcr7Vxw7e2VZu_ywaJwJEy7inLJ8H2F X-Proofpoint-GUID: QIcr7Vxw7e2VZu_ywaJwJEy7inLJ8H2F X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-10_02,2026-06-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 lowpriorityscore=0 suspectscore=0 phishscore=0 adultscore=0 clxscore=1015 spamscore=0 bulkscore=0 malwarescore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605210000 definitions=main-2606100083 From: Sibi Sankar On Qualcomm Hamoa SoCs, the memlat governor and the mechanism for controlling the LLCC and DDR/DDR_QOS frequencies run on the CPU Control Processor (CPUCP) and are exposed via the QCOM SCMI Generic Extension protocol. Add the SCMI vendor protocol node required for the QCOM SCMI Generic Extension protocol to probe get functional bus dvfs on Hamoa/Purwa SoCs. Signed-off-by: Sibi Sankar Signed-off-by: Pragnesh Papaniya --- arch/arm64/boot/dts/qcom/hamoa.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom= /hamoa.dtsi index 4ba751a65142..abd3e4bb9372 100644 --- a/arch/arm64/boot/dts/qcom/hamoa.dtsi +++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi @@ -338,6 +338,10 @@ scmi_dvfs: protocol@13 { reg =3D <0x13>; #power-domain-cells =3D <1>; }; + + scmi_vendor: protocol@80 { + reg =3D <0x80>; + }; }; }; =20 --=20 2.34.1