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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-c85df03498csm23896099a12.1.2026.06.10.04.16.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jun 2026 04:16:26 -0700 (PDT) From: Varadarajan Narayanan Date: Wed, 10 Jun 2026 16:46:08 +0530 Subject: [PATCH v3 1/2] dt-bindings: phy: qcom,ipq8074-qmp-pcie: Document the ipq5210 QMP PCIe PHY Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260610-pcie-phy-v3-1-334011b378d6@oss.qualcomm.com> References: <20260610-pcie-phy-v3-0-334011b378d6@oss.qualcomm.com> In-Reply-To: <20260610-pcie-phy-v3-0-334011b378d6@oss.qualcomm.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Varadarajan Narayanan X-Mailer: b4 0.14.3 X-Proofpoint-GUID: cz_GV3mMSXgrYtNJNGJLfo5ttPNApoJj X-Proofpoint-ORIG-GUID: cz_GV3mMSXgrYtNJNGJLfo5ttPNApoJj X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjEwMDEwNyBTYWx0ZWRfXx8G3vEH3jPX7 0rlcteVIitjyiB584rOpbGxYlBVZiWC5eBjLOjIhtL1EgT1UDsxFn5sfKTE8/rJRgddBWHhfO7h 6CjlnN3kVKOhlJdulrY937GgisTEHEFhFA2cTIs3IJxXT+H0UO0J33eql0aPaA66tgLjbvk/TvJ 2x7B5VEdqmuF0wDBCJ9UUh5niyHo6MXFr5/Np2Sni4VNg8wDAGrdPxliWmR52K0mZjv33N8/9sS RjnzENhnWDaNQebWvASGsUqt6P0xP7mmFTLvZ3ufSdjFsDxl9Pdq+d7damDWuA6Kbz/sn0aaYWr UuxVcvRCsnlEbymgyZcmV23UvaRZT5iCJaSAK0pwSUfv3i53ZT8kKIwdE7SCILfXRa/m6tJ+NfQ cQw4UHjgpYxXAuCaay0yXGloaHByCvtlMiPQO/mwICq38actYSw3p5FEZFvfTRX0n42lC2k3Xvs hEFLMPD8WGREtjQv9nw== X-Authority-Analysis: v=2.4 cv=epLvCIpX c=1 sm=1 tr=0 ts=6a29478c cx=c_pps a=0uOsjrqzRL749jD1oC5vDA==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=EUspDBNiAAAA:8 a=EF49ANZLUTmcXe5zpi4A:9 a=QEXdDO2ut3YA:10 a=mQ_c8vxmzFEMiUWkPHU9:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-10_02,2026-06-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 clxscore=1015 bulkscore=0 suspectscore=0 malwarescore=0 priorityscore=1501 phishscore=0 adultscore=0 lowpriorityscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605210000 definitions=main-2606100107 Document the PCIe phys on the ipq5210 platform. The 2 lane phy uses the ipq9574 as fallback. The single lane phy is documented separately. The ipq5210 has one dual lane and one single lane PCIe phy. The dual lane phy is similar to the dual lane phy present in ipq9574. Hence qcom,ipq5210-qmp-gen3x2-pcie-phy is documented with ipq9574's dual lane phy as fallback compatible. The single lane phy (qcom,ipq5210-qmp-gen3x1-pcie-phy) is documented as specific compatible. Signed-off-by: Varadarajan Narayanan --- Documentation/devicetree/bindings/phy/qcom,ipq8074-qmp-pcie-phy.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/qcom,ipq8074-qmp-pcie-ph= y.yaml b/Documentation/devicetree/bindings/phy/qcom,ipq8074-qmp-pcie-phy.ya= ml index f60804687412..fc155ad5fa6d 100644 --- a/Documentation/devicetree/bindings/phy/qcom,ipq8074-qmp-pcie-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,ipq8074-qmp-pcie-phy.yaml @@ -17,6 +17,7 @@ properties: compatible: oneOf: - enum: + - qcom,ipq5210-qmp-gen3x1-pcie-phy - qcom,ipq6018-qmp-pcie-phy - qcom,ipq8074-qmp-gen3-pcie-phy - qcom,ipq8074-qmp-pcie-phy @@ -28,6 +29,7 @@ properties: - const: qcom,ipq9574-qmp-gen3x1-pcie-phy - items: - enum: + - qcom,ipq5210-qmp-gen3x2-pcie-phy - qcom,ipq5424-qmp-gen3x2-pcie-phy - const: qcom,ipq9574-qmp-gen3x2-pcie-phy =20 --=20 2.34.1 From nobody Fri Jun 12 15:49:06 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D48BC405840 for ; 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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-c85df03498csm23896099a12.1.2026.06.10.04.16.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jun 2026 04:16:30 -0700 (PDT) From: Varadarajan Narayanan Date: Wed, 10 Jun 2026 16:46:09 +0530 Subject: [PATCH v3 2/2] phy: qcom-qmp-pcie: Add support for ipq5210 PCIe phys Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260610-pcie-phy-v3-2-334011b378d6@oss.qualcomm.com> References: <20260610-pcie-phy-v3-0-334011b378d6@oss.qualcomm.com> In-Reply-To: <20260610-pcie-phy-v3-0-334011b378d6@oss.qualcomm.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Varadarajan Narayanan X-Mailer: b4 0.14.3 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjEwMDEwNyBTYWx0ZWRfXwQ3pXzxsa4aO DGBTDygRS+3nsjGltthFJymif/zn/q1g47iJIuDhtB/MiwJhnpbze6gBmf/eNJgQN6V5hHe9ZQM RhKsFHnGNP6OBc/ECtsx9fiGGPfRFgEkL1NCM+PnZudzcAgL2tPJp79z/966rl44ceprguXZHXe 2uKnGxqkPsMnGQ0Vqyn0tCv3CLemcBQ3AzmrMftE3EhQkDIizzCm/7yRuXwx4lluID2xV0pYG2M 5YuIfxNIbPwifMrbHC4ljdeIQRrks/PBlnTMaHFediUrd/pIAOR9krllwvaTBa7FW3t3iOjD39U 1xQtkokqZhs+Wj3T7SCClwHSiVRmYASPYNQiz3MVJiKsDqJQwRs+EzLFYR7IXDCzVqfp3SZ5Lj7 kfgEta1c7bFaUaC6Bys89OuQu9VfM8Jfuml+d+yZXtEJe5oYgIdHIbhZm1C325fgVC6Ku+o1rks z25PeuhEeDiBajaQ5dQ== X-Authority-Analysis: v=2.4 cv=Xce5Co55 c=1 sm=1 tr=0 ts=6a29478f cx=c_pps a=Oh5Dbbf/trHjhBongsHeRQ==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=EUspDBNiAAAA:8 a=lQuujfteSIboIXYB3dUA:9 a=QEXdDO2ut3YA:10 a=_Vgx9l1VpLgwpw_dHYaR:22 X-Proofpoint-ORIG-GUID: Nrh0IpsmBaRQhaLUj5oD7Q4tyxdk2KHz X-Proofpoint-GUID: Nrh0IpsmBaRQhaLUj5oD7Q4tyxdk2KHz X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-10_02,2026-06-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 phishscore=0 malwarescore=0 impostorscore=0 adultscore=0 priorityscore=1501 lowpriorityscore=0 suspectscore=0 bulkscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605210000 definitions=main-2606100107 Add support for a PCIe phys found on Qualcomm ipq5210 platform. Signed-off-by: Varadarajan Narayanan Reviewed-by: Dmitry Baryshkov --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 129 +++++++++++++++++++++++++++= ++++ 1 file changed, 129 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcom= m/phy-qcom-qmp-pcie.c index 75afbd15aaf4..2bf00e0e125a 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -514,6 +514,89 @@ static const struct qmp_phy_init_tbl ipq8074_pcie_gen3= _pcs_misc_tbl[] =3D { QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), }; =20 +static const struct qmp_phy_init_tbl ipq5210_gen3x1_pcie_ep_serdes_tbl[] = =3D { + QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TIMER, 0x02), + QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18), + QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07), + QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xff), + QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x04), + QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xff), + QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x09), + QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x23), + QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x23), + QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x10), + QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x10), + QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x01), + QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x01), + QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01), + QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x00), + QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20), + QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42), + QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x19), + QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x14), + QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xfe), + QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE0, 0x03), + QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xfe), + QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE1, 0x03), + QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24), + QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02), + QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4), + QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03), + QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01), + QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00), + QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06), + QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05), + QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08), + QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x07), + QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x10), +}; + +static const struct qmp_phy_init_tbl ipq5210_gen3x1_pcie_ep_rx_tbl[] =3D { + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x61), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1e), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xf0), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x2f), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xd3), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x40), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x09), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x09), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), +}; + +static const struct qmp_phy_init_tbl ipq5210_gen3x1_pcie_ep_pcs_misc_tbl[]= =3D { + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x04), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG1, 0x11), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG1, 0x02), + QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG4, 0xff), +}; + static const struct qmp_phy_init_tbl ipq9574_gen3x1_pcie_serdes_tbl[] =3D { QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18), QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01), @@ -3613,6 +3696,49 @@ static const struct qmp_phy_cfg ipq6018_pciephy_cfg = =3D { .phy_status =3D PHYSTATUS, }; =20 +static const struct qmp_phy_cfg ipq5210_gen3x1_pciephy_cfg =3D { + .lanes =3D 1, + + .offsets =3D &qmp_pcie_offsets_v4x1, + + .tbls =3D { + .serdes =3D ipq9574_gen3x1_pcie_serdes_tbl, + .serdes_num =3D ARRAY_SIZE(ipq9574_gen3x1_pcie_serdes_tbl), + .tx =3D ipq8074_pcie_gen3_tx_tbl, + .tx_num =3D ARRAY_SIZE(ipq8074_pcie_gen3_tx_tbl), + .rx =3D ipq9574_pcie_rx_tbl, + .rx_num =3D ARRAY_SIZE(ipq9574_pcie_rx_tbl), + .pcs =3D ipq9574_gen3x1_pcie_pcs_tbl, + .pcs_num =3D ARRAY_SIZE(ipq9574_gen3x1_pcie_pcs_tbl), + .pcs_misc =3D ipq9574_gen3x1_pcie_pcs_misc_tbl, + .pcs_misc_num =3D ARRAY_SIZE(ipq9574_gen3x1_pcie_pcs_misc_tbl), + }, + + .tbls_ep =3D &(const struct qmp_phy_cfg_tbls) { + .serdes =3D ipq5210_gen3x1_pcie_ep_serdes_tbl, + .serdes_num =3D ARRAY_SIZE(ipq5210_gen3x1_pcie_ep_serdes_tbl), + .tx =3D ipq6018_pcie_tx_tbl, + .tx_num =3D ARRAY_SIZE(ipq6018_pcie_tx_tbl), + .rx =3D ipq5210_gen3x1_pcie_ep_rx_tbl, + .rx_num =3D ARRAY_SIZE(ipq5210_gen3x1_pcie_ep_rx_tbl), + .pcs =3D ipq6018_pcie_pcs_tbl, + .pcs_num =3D ARRAY_SIZE(ipq6018_pcie_pcs_tbl), + .pcs_misc =3D ipq5210_gen3x1_pcie_ep_pcs_misc_tbl, + .pcs_misc_num =3D ARRAY_SIZE(ipq5210_gen3x1_pcie_ep_pcs_misc_tbl), + }, + + .reset_list =3D ipq8074_pciephy_reset_l, + .num_resets =3D ARRAY_SIZE(ipq8074_pciephy_reset_l), + .vreg_list =3D NULL, + .num_vregs =3D 0, + .regs =3D pciephy_v4_regs_layout, + + .pwrdn_ctrl =3D SW_PWRDN | REFCLK_DRV_DSBL, + .phy_status =3D PHYSTATUS, + + .pipe_clock_rate =3D 250000000, +}; + static const struct qmp_phy_cfg ipq9574_gen3x1_pciephy_cfg =3D { .lanes =3D 1, =20 @@ -5404,6 +5530,9 @@ static const struct of_device_id qmp_pcie_of_match_ta= ble[] =3D { }, { .compatible =3D "qcom,glymur-qmp-gen5x4-pcie-phy", .data =3D &glymur_qmp_gen5x4_pciephy_cfg, + }, { + .compatible =3D "qcom,ipq5210-qmp-gen3x1-pcie-phy", + .data =3D &ipq5210_gen3x1_pciephy_cfg, }, { .compatible =3D "qcom,ipq6018-qmp-pcie-phy", .data =3D &ipq6018_pciephy_cfg, --=20 2.34.1