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This stream ID is defined in the device tree with the associated firmware function ID in the iommu-map property. To create this mapping, a separate child device is needed so the firmware memory can be isolated in its own IOMMU context. Introduce a new bus called iris-vpu-bus. This creates a dynamic device, and its dma_configure() callback calls of_dma_configure_id() with the function ID provided by the client to map the corresponding stream ID. This sets up a dedicated IOMMU context for the child device. Reviewed-by: Vishnu Reddy Signed-off-by: Vikash Garodia Reviewed-by: Dmitry Baryshkov Signed-off-by: Vishnu Reddy --- MAINTAINERS | 1 + drivers/media/platform/qcom/iris/Kconfig | 4 ++ drivers/media/platform/qcom/iris/Makefile | 1 + drivers/media/platform/qcom/iris/iris_vpu_bus.c | 61 +++++++++++++++++++++= ++++ include/linux/iris_vpu_bus.h | 25 ++++++++++ 5 files changed, 92 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index a727d4920fae..92d26cf491b0 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -22262,6 +22262,7 @@ L: linux-arm-msm@vger.kernel.org S: Maintained F: Documentation/devicetree/bindings/media/qcom,*-iris.yaml F: drivers/media/platform/qcom/iris/ +F: include/linux/iris_vpu_bus.h =20 QUALCOMM NAND CONTROLLER DRIVER M: Manivannan Sadhasivam diff --git a/drivers/media/platform/qcom/iris/Kconfig b/drivers/media/platf= orm/qcom/iris/Kconfig index af78a1775937..76c9fcd253df 100644 --- a/drivers/media/platform/qcom/iris/Kconfig +++ b/drivers/media/platform/qcom/iris/Kconfig @@ -1,3 +1,6 @@ +config QCOM_IRIS_VPU_BUS + bool + config VIDEO_QCOM_IRIS tristate "Qualcomm iris V4L2 decoder driver" depends on VIDEO_DEV @@ -5,6 +8,7 @@ config VIDEO_QCOM_IRIS select V4L2_MEM2MEM_DEV select QCOM_MDT_LOADER select QCOM_SCM + select QCOM_IRIS_VPU_BUS select QCOM_UBWC_CONFIG select VIDEOBUF2_DMA_CONTIG help diff --git a/drivers/media/platform/qcom/iris/Makefile b/drivers/media/plat= form/qcom/iris/Makefile index 48e415cbc439..6deadd531c8e 100644 --- a/drivers/media/platform/qcom/iris/Makefile +++ b/drivers/media/platform/qcom/iris/Makefile @@ -30,3 +30,4 @@ qcom-iris-objs +=3D iris_buffer.o \ iris_vpu_common.o \ =20 obj-$(CONFIG_VIDEO_QCOM_IRIS) +=3D qcom-iris.o +obj-$(CONFIG_QCOM_IRIS_VPU_BUS) +=3D iris_vpu_bus.o diff --git a/drivers/media/platform/qcom/iris/iris_vpu_bus.c b/drivers/medi= a/platform/qcom/iris/iris_vpu_bus.c new file mode 100644 index 000000000000..e3327b227332 --- /dev/null +++ b/drivers/media/platform/qcom/iris/iris_vpu_bus.c @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include + +static int iris_vpu_bus_dma_configure(struct device *dev) +{ + const u32 *iommu_fid =3D (const u32 *)dev_get_platdata(dev); + + return of_dma_configure_id(dev, dev->parent->of_node, true, iommu_fid); +} + +const struct bus_type iris_vpu_bus_type =3D { + .name =3D "iris-vpu-bus", + .dma_configure =3D iris_vpu_bus_dma_configure, +}; +EXPORT_SYMBOL_GPL(iris_vpu_bus_type); + +static void iris_vpu_bus_release_device(struct device *dev) +{ + kfree(dev); +} + +struct device *iris_vpu_bus_create_device(struct device *parent_device, co= nst char *name, + u64 dma_mask, const u32 *iommu_fid) +{ + struct device *dev; + int ret; + + dev =3D kzalloc_obj(*dev); + if (!dev) + return ERR_PTR(-ENOMEM); + + dev->release =3D iris_vpu_bus_release_device; + dev->bus =3D &iris_vpu_bus_type; + dev->parent =3D parent_device; + dev->coherent_dma_mask =3D dma_mask; + dev->dma_mask =3D &dev->coherent_dma_mask; + dev->platform_data =3D (void *)iommu_fid; + dev_set_name(dev, "%s", name); + + ret =3D device_register(dev); + if (ret) { + put_device(dev); + return ERR_PTR(ret); + } + + return dev; +} +EXPORT_SYMBOL_GPL(iris_vpu_bus_create_device); + +static int __init iris_vpu_bus_init(void) +{ + return bus_register(&iris_vpu_bus_type); +} +postcore_initcall(iris_vpu_bus_init); diff --git a/include/linux/iris_vpu_bus.h b/include/linux/iris_vpu_bus.h new file mode 100644 index 000000000000..62af9ee7e288 --- /dev/null +++ b/include/linux/iris_vpu_bus.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) Qualcomm Innovation Center, Inc. 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Reviewed-by: Vishnu Reddy Reviewed-by: Dmitry Baryshkov Signed-off-by: Vikash Garodia Signed-off-by: Vishnu Reddy --- drivers/iommu/iommu.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c index e8f13dcebbde..fe51600953ce 100644 --- a/drivers/iommu/iommu.c +++ b/drivers/iommu/iommu.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -200,6 +201,9 @@ static const struct bus_type * const iommu_buses[] =3D { #ifdef CONFIG_CDX_BUS &cdx_bus_type, #endif +#ifdef CONFIG_QCOM_IRIS_VPU_BUS + &iris_vpu_bus_type, +#endif }; =20 /* --=20 2.34.1 From nobody Fri Jun 12 11:18:18 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9AD52376A1F for ; Wed, 10 Jun 2026 06:30:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Glymur is a new generation of video IP that introduces a dual-core architecture. The second core brings its own power domain, clocks, and reset lines, requiring additional power domains and clocks in the power sequence. The current maxItems constraints for clocks and power-domains in the common venus schema were sized for platforms available at the time of authoring. The glymur platform introduces a dual core architecture that requires more clocks and power domains, exceeding these limits. Raise maxItems for clocks, clock-names, power-domains and power-domain-names to accommodate the glymur platform. The glymur platform-specific schema have fixed constraints for these properties, so the common schema only acts as an upper bound. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Vishnu Reddy --- .../bindings/media/qcom,glymur-iris.yaml | 208 +++++++++++++++++= ++++ .../bindings/media/qcom,venus-common.yaml | 8 +- include/dt-bindings/media/qcom,glymur-iris.h | 11 ++ 3 files changed, 223 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/media/qcom,glymur-iris.yaml = b/Documentation/devicetree/bindings/media/qcom,glymur-iris.yaml new file mode 100644 index 000000000000..a1c4a045291d --- /dev/null +++ b/Documentation/devicetree/bindings/media/qcom,glymur-iris.yaml @@ -0,0 +1,208 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/qcom,glymur-iris.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Glymur SoC Iris video encoder and decoder + +maintainers: + - Vishnu Reddy + +description: + The Iris video processing unit on Qualcomm Glymur SoC is a video encode = and + decode accelerator. + +properties: + compatible: + const: qcom,glymur-iris + + clocks: + maxItems: 9 + + clock-names: + items: + - const: core_iface + - const: core + - const: vcodec0_core + - const: vcodec0_iface + - const: core_freerun + - const: vcodec0_core_freerun + - const: vcodec1_iface + - const: vcodec1_core + - const: vcodec1_core_freerun + + dma-coherent: true + + interconnects: + maxItems: 2 + + interconnect-names: + items: + - const: cpu-cfg + - const: video-mem + + iommus: + maxItems: 4 + + iommu-map: + maxItems: 1 + + operating-points-v2: true + opp-table: + type: object + + power-domains: + maxItems: 5 + + power-domain-names: + items: + - const: venus + - const: vcodec0 + - const: mxc + - const: mmcx + - const: vcodec1 + + resets: + maxItems: 6 + + reset-names: + items: + - const: core_bus + - const: vcodec0_bus + - const: core + - const: vcodec0_core + - const: vcodec1_bus + - const: vcodec1_core + +required: + - clocks + - clock-names + - compatible + - dma-coherent + - interconnects + - interconnect-names + - iommus + - power-domains + - power-domain-names + - resets + - reset-names + +allOf: + - $ref: qcom,venus-common.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + + video-codec@aa00000 { + compatible =3D "qcom,glymur-iris"; + reg =3D <0x0aa00000 0xf0000>; + + clocks =3D <&gcc_video_axi0c_clk>, + <&videocc_mvs0c_clk>, + <&videocc_mvs0_clk>, + <&gcc_video_axi0_clk>, + <&videocc_mvs0c_freerun_clk>, + <&videocc_mvs0_freerun_clk>, + <&gcc_video_axi1_clk>, + <&videocc_mvs1_clk>, + <&videocc_mvs1_freerun_clk>; + clock-names =3D "core_iface", + "core", + "vcodec0_core", + "vcodec0_iface", + "core_freerun", + "vcodec0_core_freerun", + "vcodec1_iface", + "vcodec1_core", + "vcodec1_core_freerun"; + + dma-coherent; + + interconnects =3D <&hsc_noc_master_appss_proc &config_noc_slave_ve= nus_cfg>, + <&mmss_noc_master_video &mc_virt_slave_ebi1>; + interconnect-names =3D "cpu-cfg", + "video-mem"; + + interrupts =3D ; + + iommus =3D <&apps_smmu 0x1940 0x0>, + <&apps_smmu 0x1943 0x0>, + <&apps_smmu 0x1944 0x0>, + <&apps_smmu 0x19e0 0x0>; + + iommu-map =3D ; + + memory-region =3D <&video_mem>; + + operating-points-v2 =3D <&iris_opp_table>; + + power-domains =3D <&videocc_mvs0c_gdsc>, + <&videocc_mvs0_gdsc>, + <&rpmhpd RPMHPD_MXC>, + <&rpmhpd RPMHPD_MMCX>, + <&videocc_mvs1_gdsc>; + power-domain-names =3D "venus", + "vcodec0", + "mxc", + "mmcx", + "vcodec1"; + + resets =3D <&gcc_video_axi0c_clk_ares>, + <&gcc_video_axi0_clk_ares>, + <&videocc_mvs0c_freerun_clk_ares>, + <&videocc_mvs0_freerun_clk_ares>, + <&gcc_video_axi1_clk_ares>, + <&videocc_mvs1_freerun_clk_ares>; + reset-names =3D "core_bus", + "vcodec0_bus", + "core", + "vcodec0_core", + "vcodec1_bus", + "vcodec1_core"; + + iris_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-240000000 { + opp-hz =3D /bits/ 64 <240000000 240000000 360000000>; + required-opps =3D <&rpmhpd_opp_svs>, + <&rpmhpd_opp_low_svs>; + }; + + opp-338000000 { + opp-hz =3D /bits/ 64 <338000000 338000000 507000000>; + required-opps =3D <&rpmhpd_opp_svs>, + <&rpmhpd_opp_svs>; + }; + + opp-366000000 { + opp-hz =3D /bits/ 64 <366000000 366000000 549000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>, + <&rpmhpd_opp_svs_l1>; + }; + + opp-444000000 { + opp-hz =3D /bits/ 64 <444000000 444000000 666000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>, + <&rpmhpd_opp_nom>; + }; + + opp-533333334 { + opp-hz =3D /bits/ 64 <533333334 533333334 800000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>, + <&rpmhpd_opp_turbo>; + }; + + opp-655000000 { + opp-hz =3D /bits/ 64 <655000000 655000000 982000000>; + required-opps =3D <&rpmhpd_opp_nom>, + <&rpmhpd_opp_turbo_l1>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/media/qcom,venus-common.yaml= b/Documentation/devicetree/bindings/media/qcom,venus-common.yaml index 59a3fde846d2..10716a93dd35 100644 --- a/Documentation/devicetree/bindings/media/qcom,venus-common.yaml +++ b/Documentation/devicetree/bindings/media/qcom,venus-common.yaml @@ -20,11 +20,11 @@ properties: =20 clocks: minItems: 3 - maxItems: 7 + maxItems: 9 =20 clock-names: minItems: 3 - maxItems: 7 + maxItems: 9 =20 firmware-name: maxItems: 1 @@ -41,11 +41,11 @@ properties: =20 power-domains: minItems: 1 - maxItems: 4 + maxItems: 5 =20 power-domain-names: minItems: 1 - maxItems: 4 + maxItems: 5 =20 required: - reg diff --git a/include/dt-bindings/media/qcom,glymur-iris.h b/include/dt-bind= ings/media/qcom,glymur-iris.h new file mode 100644 index 000000000000..dcaa2bc21db5 --- /dev/null +++ b/include/dt-bindings/media/qcom,glymur-iris.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_MEDIA_QCOM_GLYMUR_IRIS_H_ +#define _DT_BINDINGS_MEDIA_QCOM_GLYMUR_IRIS_H_ + +#define IOMMU_FID_IRIS_FIRMWARE 0 + +#endif --=20 2.34.1 From nobody Fri Jun 12 11:18:18 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 21AEB376BC1 for ; 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Add init and deinit hooks in the vpu ops for context bank setup. These hooks allow platform specific code to initialize and tear down context banks. Reviewed-by: Vikash Garodia Signed-off-by: Vishnu Reddy --- drivers/media/platform/qcom/iris/iris_core.c | 9 ++++++++- drivers/media/platform/qcom/iris/iris_vpu_common.c | 14 ++++++++++++++ drivers/media/platform/qcom/iris/iris_vpu_common.h | 4 ++++ 3 files changed, 26 insertions(+), 1 deletion(-) diff --git a/drivers/media/platform/qcom/iris/iris_core.c b/drivers/media/p= latform/qcom/iris/iris_core.c index 52bf56e517f9..89dbe9bbf6b0 100644 --- a/drivers/media/platform/qcom/iris/iris_core.c +++ b/drivers/media/platform/qcom/iris/iris_core.c @@ -19,6 +19,7 @@ void iris_core_deinit(struct iris_core *core) iris_fw_unload(core); iris_vpu_power_off(core); iris_hfi_queues_deinit(core); + iris_deinit_cb_devs(core); core->state =3D IRIS_CORE_DEINIT; } mutex_unlock(&core->lock); @@ -58,10 +59,14 @@ int iris_core_init(struct iris_core *core) =20 core->state =3D IRIS_CORE_INIT; =20 - ret =3D iris_hfi_queues_init(core); + ret =3D iris_init_cb_devs(core); if (ret) goto error; =20 + ret =3D iris_hfi_queues_init(core); + if (ret) + goto error_deinit_cb_devs; + ret =3D iris_vpu_power_on(core); if (ret) goto error_queue_deinit; @@ -94,6 +99,8 @@ int iris_core_init(struct iris_core *core) iris_vpu_power_off(core); error_queue_deinit: iris_hfi_queues_deinit(core); +error_deinit_cb_devs: + iris_deinit_cb_devs(core); error: core->state =3D IRIS_CORE_DEINIT; exit: diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/m= edia/platform/qcom/iris/iris_vpu_common.c index ab41da1f47c8..8bdfee672954 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_common.c +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c @@ -319,6 +319,20 @@ int iris_vpu_switch_to_hwmode(struct iris_core *core) return core->iris_platform_data->vpu_ops->set_hwmode(core); } =20 +int iris_init_cb_devs(struct iris_core *core) +{ + if (core->iris_platform_data->vpu_ops->init_cb_devs) + return core->iris_platform_data->vpu_ops->init_cb_devs(core); + + return 0; +} + +void iris_deinit_cb_devs(struct iris_core *core) +{ + if (core->iris_platform_data->vpu_ops->deinit_cb_devs) + core->iris_platform_data->vpu_ops->deinit_cb_devs(core); +} + int iris_vpu35_vpu4x_power_off_controller(struct iris_core *core) { u32 clk_rst_tbl_size =3D core->iris_platform_data->clk_rst_tbl_size; diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.h b/drivers/m= edia/platform/qcom/iris/iris_vpu_common.h index 09799a375c14..e0dc109bbe6a 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_common.h +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.h @@ -22,6 +22,8 @@ struct vpu_ops { void (*program_bootup_registers)(struct iris_core *core); u64 (*calc_freq)(struct iris_inst *inst, size_t data_size); int (*set_hwmode)(struct iris_core *core); + int (*init_cb_devs)(struct iris_core *core); + void (*deinit_cb_devs)(struct iris_core *core); }; =20 int iris_vpu_boot_firmware(struct iris_core *core); @@ -33,6 +35,8 @@ int iris_vpu_power_on_controller(struct iris_core *core); int iris_vpu_power_on_hw(struct iris_core *core); int iris_vpu_set_hwmode(struct iris_core *core); int iris_vpu_switch_to_hwmode(struct iris_core *core); +int iris_init_cb_devs(struct iris_core *core); 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For qcom_scm_pas_auth_and_reset(), the hypervisor registers a Shared Memory (SHM) bridge over the Peripheral Image Loader (PIL) memory region so that TrustZone (TZ) can access it, forwards the authentication SMC to TZ, and upon return maps the PIL region and triggers the co-processor bring-up sequence: HLOS -> Hypervisor(SHM setup) -> TZ(auth) -> Hypervisor(map+reset) -> IRIS On platforms without a hypervisor, Linux drives these steps directly. The SHM bridge infrastructure required for this is already upstream [1]. To isolate firmware memory in its own Input-Output Memory Management Unit (IOMMU) context, a dedicated stream ID (SID) is required, tied to the firmware function ID. This SID is specified via the iommu-map property in the device tree using the firmware function ID as the lookup key. A firmware device is created and mapped to this SID. The presence of a SID mapped to the firmware device via iommu-map is used to detect whether a hypervisor is absent: when the firmware device has a SID mapped, Linux manages the IOMMU directly; when no SID is mapped, a hypervisor is assumed to be present and these steps are skipped. Extend the Iris driver to support Secure Peripheral Authentication Service (PAS) on platforms where Linux manages the IOMMU, by creating the firmware context device and performing the necessary IOMMU mapping when the firmware device SID is present. [1] https://lore.kernel.org/lkml/20260105-kvmrprocv10-v10-0-022e96815380 @oss.qualcomm.com/ Reviewed-by: Vishnu Reddy Co-developed-by: Vikash Garodia Signed-off-by: Vikash Garodia Signed-off-by: Mukesh Ojha Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/lkml/20260105-kvmrprocv10-v10-0-022e96815380@= oss.qualcomm.com/ Signed-off-by: Vishnu Reddy --- drivers/media/platform/qcom/iris/iris_core.h | 4 ++ drivers/media/platform/qcom/iris/iris_firmware.c | 69 ++++++++++++++++++++= ---- 2 files changed, 62 insertions(+), 11 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_core.h b/drivers/media/p= latform/qcom/iris/iris_core.h index 24da60448cf2..2edba569fa25 100644 --- a/drivers/media/platform/qcom/iris/iris_core.h +++ b/drivers/media/platform/qcom/iris/iris_core.h @@ -36,6 +36,8 @@ struct qcom_ubwc_cfg_data; * struct iris_core - holds core parameters valid for all instances * * @dev: reference to device structure + * @fw_dev: reference to the context bank device used for firmware load + * @pas_ctx: SCM PAS context for authenticated firmware load and shutdown * @reg_base: IO memory base address * @irq: iris irq * @v4l2_dev: a holder for v4l2 device structure @@ -81,6 +83,8 @@ struct qcom_ubwc_cfg_data; =20 struct iris_core { struct device *dev; + struct device *fw_dev; + struct qcom_scm_pas_context *pas_ctx; void __iomem *reg_base; int irq; struct v4l2_device v4l2_dev; diff --git a/drivers/media/platform/qcom/iris/iris_firmware.c b/drivers/med= ia/platform/qcom/iris/iris_firmware.c index 1a476146d758..07b3ade88777 100644 --- a/drivers/media/platform/qcom/iris/iris_firmware.c +++ b/drivers/media/platform/qcom/iris/iris_firmware.c @@ -5,6 +5,7 @@ =20 #include #include +#include #include #include #include @@ -15,11 +16,13 @@ #define IRIS_PAS_ID 9 =20 #define MAX_FIRMWARE_NAME_SIZE 128 +#define IRIS_FW_START_ADDR 0 =20 static int iris_load_fw_to_memory(struct iris_core *core, const char *fw_n= ame) { + struct device *fw_dev =3D core->fw_dev ? core->fw_dev : core->dev; const struct firmware *firmware =3D NULL; - struct device *dev =3D core->dev; + struct iommu_domain *domain; struct resource res; phys_addr_t mem_phys; size_t res_size; @@ -30,14 +33,21 @@ static int iris_load_fw_to_memory(struct iris_core *cor= e, const char *fw_name) if (strlen(fw_name) >=3D MAX_FIRMWARE_NAME_SIZE - 4) return -EINVAL; =20 - ret =3D of_reserved_mem_region_to_resource(dev->of_node, 0, &res); + ret =3D of_reserved_mem_region_to_resource(core->dev->of_node, 0, &res); if (ret) return ret; =20 mem_phys =3D res.start; res_size =3D resource_size(&res); =20 - ret =3D request_firmware(&firmware, fw_name, dev); + if (!core->pas_ctx) { + core->pas_ctx =3D devm_qcom_scm_pas_context_alloc(core->dev, IRIS_PAS_ID, + mem_phys, res_size); + if (IS_ERR(core->pas_ctx)) + return PTR_ERR(core->pas_ctx); + } + + ret =3D request_firmware(&firmware, fw_name, fw_dev); if (ret) return ret; =20 @@ -53,9 +63,23 @@ static int iris_load_fw_to_memory(struct iris_core *core= , const char *fw_name) goto err_release_fw; } =20 - ret =3D qcom_mdt_load(dev, firmware, fw_name, - IRIS_PAS_ID, mem_virt, mem_phys, res_size, NULL); + core->pas_ctx->use_tzmem =3D !!core->fw_dev; + ret =3D qcom_mdt_pas_load(core->pas_ctx, firmware, fw_name, mem_virt, NUL= L); + if (ret) + goto err_mem_unmap; + + if (core->pas_ctx->use_tzmem) { + domain =3D iommu_get_domain_for_dev(fw_dev); + if (!domain) { + ret =3D -ENODEV; + goto err_mem_unmap; + } + + ret =3D iommu_map(domain, IRIS_FW_START_ADDR, mem_phys, res_size, + IOMMU_READ | IOMMU_WRITE | IOMMU_PRIV, GFP_KERNEL); + } =20 +err_mem_unmap: memunmap(mem_virt); err_release_fw: release_firmware(firmware); @@ -63,6 +87,18 @@ static int iris_load_fw_to_memory(struct iris_core *core= , const char *fw_name) return ret; } =20 +static void iris_fw_iommu_unmap(struct iris_core *core) +{ + struct iommu_domain *domain; + + if (!core->pas_ctx->use_tzmem) + return; + + domain =3D iommu_get_domain_for_dev(core->fw_dev); + if (domain) + iommu_unmap(domain, IRIS_FW_START_ADDR, core->pas_ctx->mem_size); +} + int iris_fw_load(struct iris_core *core) { const struct tz_cp_config *cp_config; @@ -77,13 +113,13 @@ int iris_fw_load(struct iris_core *core) ret =3D iris_load_fw_to_memory(core, fwpath); if (ret) { dev_err(core->dev, "firmware download failed\n"); - return -ENOMEM; + return ret; } =20 - ret =3D qcom_scm_pas_auth_and_reset(IRIS_PAS_ID); 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Every new clock or power domain requires a new enum entry, and every enable/disable path has to loop through the clock table to find the right clock by enum value, adding overhead and boilerplate on each path. The enum index space is also shared across all hardware blocks. On the Glymur platform, the VPP0 index for VPU4x and the VCODEC1 index clash, making it error-prone to extend support without breaking existing platforms. Replace the flat tables and enum-based lookups with iris_power_domain, which bundles a power domain device and its associated clocks together per hardware block. Platform data describes each block via iris_power_domain_data, and the enable and disable helpers operate directly on an iris_power_domain instance, removing the need for any index lookup at runtime. Signed-off-by: Vishnu Reddy --- drivers/media/platform/qcom/iris/iris_core.h | 23 +++- .../platform/qcom/iris/iris_platform_common.h | 41 ++---- .../platform/qcom/iris/iris_platform_sc7280.h | 28 ++++- .../platform/qcom/iris/iris_platform_sm8250.h | 26 +++- .../platform/qcom/iris/iris_platform_sm8550.h | 26 +++- .../platform/qcom/iris/iris_platform_sm8750.h | 29 +++-- .../media/platform/qcom/iris/iris_platform_vpu2.c | 14 +-- .../media/platform/qcom/iris/iris_platform_vpu3x.c | 32 ++--- .../platform/qcom/iris/iris_platform_x1p42100.h | 27 +++- drivers/media/platform/qcom/iris/iris_probe.c | 134 +++++++++++++++++= +-- drivers/media/platform/qcom/iris/iris_resources.c | 82 +++++------- drivers/media/platform/qcom/iris/iris_resources.h | 8 +- drivers/media/platform/qcom/iris/iris_vpu3x.c | 37 +----- drivers/media/platform/qcom/iris/iris_vpu4x.c | 137 +++--------------= ---- drivers/media/platform/qcom/iris/iris_vpu_common.c | 98 ++------------- 15 files changed, 341 insertions(+), 401 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_core.h b/drivers/media/p= latform/qcom/iris/iris_core.h index 2edba569fa25..8c36b64153c7 100644 --- a/drivers/media/platform/qcom/iris/iris_core.h +++ b/drivers/media/platform/qcom/iris/iris_core.h @@ -16,6 +16,13 @@ #include "iris_resources.h" #include "iris_state.h" =20 +struct iris_power_domain { + struct device **dev; + unsigned int pd_cnt; + struct clk_bulk_data *clocks; + unsigned int clk_cnt; +}; + struct icc_info { const char *name; u32 bw_min_kbps; @@ -49,10 +56,12 @@ struct qcom_ubwc_cfg_data; * @iris_vb2_ops: iris vb2 ops * @icc_tbl: table of iris interconnects * @icc_count: count of iris interconnects - * @pmdomain_tbl: table of iris power domains + * @ctrl: power domain and clocks for the controller + * @vcodec: power domain and clocks for the vcodec + * @vcodec_vpp0: power domain and clocks for the vcodec VPP0 + * @vcodec_vpp1: power domain and clocks for the vcodec VPP1 + * @apv: power domain and clocks for the APV hardware block * @opp_pmdomain_tbl: table of opp power domains - * @clock_tbl: table of iris clocks - * @clk_count: count of iris clocks * @resets: table of iris reset clocks * @controller_resets: table of controller reset clocks * @iris_platform_data: a structure for platform data @@ -96,10 +105,12 @@ struct iris_core { const struct vb2_ops *iris_vb2_ops; struct icc_bulk_data *icc_tbl; u32 icc_count; - struct dev_pm_domain_list *pmdomain_tbl; + struct iris_power_domain *ctrl; + struct iris_power_domain *vcodec; + struct iris_power_domain *vcodec_vpp0; + struct iris_power_domain *vcodec_vpp1; + struct iris_power_domain *apv; struct dev_pm_domain_list *opp_pmdomain_tbl; - struct clk_bulk_data *clock_tbl; - u32 clk_count; struct reset_control_bulk_data *resets; struct reset_control_bulk_data *controller_resets; const struct iris_platform_data *iris_platform_data; diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/driv= ers/media/platform/qcom/iris/iris_platform_common.h index c9256f2323dc..99f59b64f853 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -61,26 +61,6 @@ extern const struct iris_platform_data sm8650_data; extern const struct iris_platform_data sm8750_data; extern const struct iris_platform_data x1p42100_data; =20 -enum platform_clk_type { - IRIS_AXI_CLK, /* AXI0 in case of platforms with multiple AXI clocks */ - IRIS_CTRL_CLK, - IRIS_AHB_CLK, - IRIS_HW_CLK, - IRIS_HW_AHB_CLK, - IRIS_AXI1_CLK, - IRIS_CTRL_FREERUN_CLK, - IRIS_HW_FREERUN_CLK, - IRIS_BSE_HW_CLK, - IRIS_VPP0_HW_CLK, - IRIS_VPP1_HW_CLK, - IRIS_APV_HW_CLK, -}; - -struct platform_clk_data { - enum platform_clk_type clk_type; - const char *clk_name; -}; - struct tz_cp_config { u32 cp_start; u32 cp_size; @@ -228,12 +208,11 @@ struct icc_vote_data { u32 fps; }; =20 -enum platform_pm_domain_type { - IRIS_CTRL_POWER_DOMAIN, - IRIS_HW_POWER_DOMAIN, - IRIS_VPP0_HW_POWER_DOMAIN, - IRIS_VPP1_HW_POWER_DOMAIN, - IRIS_APV_HW_POWER_DOMAIN, +struct iris_power_domain_data { + const char * const *pd_names; + unsigned int pd_cnt; + const char * const *clk_names; + unsigned int clk_cnt; }; =20 struct iris_firmware_data { @@ -300,13 +279,14 @@ struct iris_platform_data { unsigned int icc_tbl_size; const struct bw_info *bw_tbl_dec; unsigned int bw_tbl_dec_size; - const char * const *pmdomain_tbl; - unsigned int pmdomain_tbl_size; + const struct iris_power_domain_data *ctrl_data; + const struct iris_power_domain_data *vcodec_data; + const struct iris_power_domain_data *vcodec_vpp0_data; + const struct iris_power_domain_data *vcodec_vpp1_data; + const struct iris_power_domain_data *apv_data; const char * const *opp_pd_tbl; unsigned int opp_pd_tbl_size; - const struct platform_clk_data *clk_tbl; const char * const *opp_clk_tbl; - unsigned int clk_tbl_size; const char * const *clk_rst_tbl; unsigned int clk_rst_tbl_size; const char * const *controller_rst_tbl; @@ -320,6 +300,7 @@ struct iris_platform_data { u32 num_vpp_pipe; bool no_aon; u32 max_session_count; + u32 num_cores; /* max number of macroblocks per frame supported */ u32 max_core_mbpf; /* max number of macroblocks per second supported */ diff --git a/drivers/media/platform/qcom/iris/iris_platform_sc7280.h b/driv= ers/media/platform/qcom/iris/iris_platform_sc7280.h index 0ec8f334df67..f19547a8a51d 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_sc7280.h +++ b/drivers/media/platform/qcom/iris/iris_platform_sc7280.h @@ -15,12 +15,28 @@ static const struct bw_info sc7280_bw_table_dec[] =3D { =20 static const char * const sc7280_opp_pd_table[] =3D { "cx" }; =20 -static const struct platform_clk_data sc7280_clk_table[] =3D { - {IRIS_CTRL_CLK, "core" }, - {IRIS_AXI_CLK, "iface" }, - {IRIS_AHB_CLK, "bus" }, - {IRIS_HW_CLK, "vcodec_core" }, - {IRIS_HW_AHB_CLK, "vcodec_bus" }, +static const struct iris_power_domain_data sc7280_ctrl_data =3D { + .pd_names =3D (const char *[]) { + "venus", + }, + .pd_cnt =3D 1, + .clk_names =3D (const char *[]) { + "iface", "core", "bus", + }, + .clk_cnt =3D 3, +}; + +static const struct iris_power_domain_data sc7280_vcodec_data[] =3D { + { + .pd_names =3D (const char *[]) { + "vcodec0", + }, + .pd_cnt =3D 1, + .clk_names =3D (const char *[]) { + "vcodec_core", "vcodec_bus", + }, + .clk_cnt =3D 2, + }, }; =20 static const char * const sc7280_opp_clk_table[] =3D { diff --git a/drivers/media/platform/qcom/iris/iris_platform_sm8250.h b/driv= ers/media/platform/qcom/iris/iris_platform_sm8250.h index 50306043eb8e..7674cf9a330f 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_sm8250.h +++ b/drivers/media/platform/qcom/iris/iris_platform_sm8250.h @@ -15,10 +15,28 @@ static const struct bw_info sm8250_bw_table_dec[] =3D { =20 static const char * const sm8250_opp_pd_table[] =3D { "mx", "mmcx" }; =20 -static const struct platform_clk_data sm8250_clk_table[] =3D { - {IRIS_AXI_CLK, "iface" }, - {IRIS_CTRL_CLK, "core" }, - {IRIS_HW_CLK, "vcodec0_core" }, +static const struct iris_power_domain_data sm8250_ctrl_data =3D { + .pd_names =3D (const char *[]) { + "venus", + }, + .pd_cnt =3D 1, + .clk_names =3D (const char *[]) { + "iface", "core", + }, + .clk_cnt =3D 2, +}; + +static const struct iris_power_domain_data sm8250_vcodec_data[] =3D { + { + .pd_names =3D (const char *[]) { + "vcodec0", + }, + .pd_cnt =3D 1, + .clk_names =3D (const char *[]) { + "vcodec0_core", + }, + .clk_cnt =3D 1, + }, }; =20 static const char * const sm8250_opp_clk_table[] =3D { diff --git a/drivers/media/platform/qcom/iris/iris_platform_sm8550.h b/driv= ers/media/platform/qcom/iris/iris_platform_sm8550.h index 3c9dae995bb2..71de71a75e95 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_sm8550.h +++ b/drivers/media/platform/qcom/iris/iris_platform_sm8550.h @@ -8,10 +8,28 @@ =20 static const char * const sm8550_clk_reset_table[] =3D { "bus" }; =20 -static const struct platform_clk_data sm8550_clk_table[] =3D { - {IRIS_AXI_CLK, "iface" }, - {IRIS_CTRL_CLK, "core" }, - {IRIS_HW_CLK, "vcodec0_core" }, +static const struct iris_power_domain_data sm8550_ctrl_data =3D { + .pd_names =3D (const char *[]) { + "venus", + }, + .pd_cnt =3D 1, + .clk_names =3D (const char *[]) { + "iface", "core", + }, + .clk_cnt =3D 2, +}; + +static const struct iris_power_domain_data sm8550_vcodec_data[] =3D { + { + .pd_names =3D (const char *[]) { + "vcodec0", + }, + .pd_cnt =3D 1, + .clk_names =3D (const char *[]) { + "vcodec0_core", + }, + .clk_cnt =3D 1, + }, }; =20 static struct platform_inst_caps platform_inst_cap_sm8550 =3D { diff --git a/drivers/media/platform/qcom/iris/iris_platform_sm8750.h b/driv= ers/media/platform/qcom/iris/iris_platform_sm8750.h index 719056656a5b..45ab78781f4a 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_sm8750.h +++ b/drivers/media/platform/qcom/iris/iris_platform_sm8750.h @@ -10,13 +10,28 @@ static const char * const sm8750_clk_reset_table[] =3D { "bus0", "bus1", "core", "vcodec0_core" }; =20 -static const struct platform_clk_data sm8750_clk_table[] =3D { - {IRIS_AXI_CLK, "iface" }, - {IRIS_CTRL_CLK, "core" }, - {IRIS_HW_CLK, "vcodec0_core" }, - {IRIS_AXI1_CLK, "iface1" }, - {IRIS_CTRL_FREERUN_CLK, "core_freerun" }, - {IRIS_HW_FREERUN_CLK, "vcodec0_core_freerun" }, +static const struct iris_power_domain_data sm8750_ctrl_data =3D { + .pd_names =3D (const char *[]) { + "venus", + }, + .pd_cnt =3D 1, + .clk_names =3D (const char *[]) { + "iface1", "core_freerun", "core", + }, + .clk_cnt =3D 3, +}; + +static const struct iris_power_domain_data sm8750_vcodec_data[] =3D { + { + .pd_names =3D (const char *[]) { + "vcodec0", + }, + .pd_cnt =3D 1, + .clk_names =3D (const char *[]) { + "iface", "vcodec0_core_freerun", "vcodec0_core", + }, + .clk_cnt =3D 3, + }, }; =20 #endif diff --git a/drivers/media/platform/qcom/iris/iris_platform_vpu2.c b/driver= s/media/platform/qcom/iris/iris_platform_vpu2.c index 6e06a32822bb..c381a40da9ba 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_vpu2.c +++ b/drivers/media/platform/qcom/iris/iris_platform_vpu2.c @@ -53,8 +53,6 @@ static const struct icc_info iris_icc_info_vpu2[] =3D { =20 static const char * const iris_clk_reset_table_vpu2[] =3D { "bus", "core" = }; =20 -static const char * const iris_pmdomain_table_vpu2[] =3D { "venus", "vcode= c0" }; - static const struct tz_cp_config tz_cp_config_vpu2[] =3D { { .cp_start =3D 0, @@ -71,12 +69,10 @@ const struct iris_platform_data sc7280_data =3D { .icc_tbl_size =3D ARRAY_SIZE(iris_icc_info_vpu2), .bw_tbl_dec =3D sc7280_bw_table_dec, .bw_tbl_dec_size =3D ARRAY_SIZE(sc7280_bw_table_dec), - .pmdomain_tbl =3D iris_pmdomain_table_vpu2, - .pmdomain_tbl_size =3D ARRAY_SIZE(iris_pmdomain_table_vpu2), + .ctrl_data =3D &sc7280_ctrl_data, + .vcodec_data =3D sc7280_vcodec_data, .opp_pd_tbl =3D sc7280_opp_pd_table, .opp_pd_tbl_size =3D ARRAY_SIZE(sc7280_opp_pd_table), - .clk_tbl =3D sc7280_clk_table, - .clk_tbl_size =3D ARRAY_SIZE(sc7280_clk_table), .opp_clk_tbl =3D sc7280_opp_clk_table, /* Upper bound of DMA address range */ .dma_mask =3D 0xe0000000 - 1, @@ -102,12 +98,10 @@ const struct iris_platform_data sm8250_data =3D { .clk_rst_tbl_size =3D ARRAY_SIZE(iris_clk_reset_table_vpu2), .bw_tbl_dec =3D sm8250_bw_table_dec, .bw_tbl_dec_size =3D ARRAY_SIZE(sm8250_bw_table_dec), - .pmdomain_tbl =3D iris_pmdomain_table_vpu2, - .pmdomain_tbl_size =3D ARRAY_SIZE(iris_pmdomain_table_vpu2), + .ctrl_data =3D &sm8250_ctrl_data, + .vcodec_data =3D sm8250_vcodec_data, .opp_pd_tbl =3D sm8250_opp_pd_table, .opp_pd_tbl_size =3D ARRAY_SIZE(sm8250_opp_pd_table), - .clk_tbl =3D sm8250_clk_table, - .clk_tbl_size =3D ARRAY_SIZE(sm8250_clk_table), .opp_clk_tbl =3D sm8250_opp_clk_table, /* Upper bound of DMA address range */ .dma_mask =3D 0xe0000000 - 1, diff --git a/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c b/drive= rs/media/platform/qcom/iris/iris_platform_vpu3x.c index 2c63adbc5579..72dd23dbe02a 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c +++ b/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c @@ -67,8 +67,6 @@ static const struct bw_info iris_bw_table_dec_vpu3x[] =3D= { { ((1920 * 1080) / 256) * 30, 294000 }, }; =20 -static const char * const iris_pmdomain_table_vpu3x[] =3D { "venus", "vcod= ec0" }; - static const char * const iris_opp_pd_table_vpu3x[] =3D { "mxc", "mmcx" }; =20 static const char * const iris_opp_clk_table_vpu3x[] =3D { @@ -98,12 +96,10 @@ const struct iris_platform_data qcs8300_data =3D { .clk_rst_tbl_size =3D ARRAY_SIZE(sm8550_clk_reset_table), .bw_tbl_dec =3D iris_bw_table_dec_vpu3x, .bw_tbl_dec_size =3D ARRAY_SIZE(iris_bw_table_dec_vpu3x), - .pmdomain_tbl =3D iris_pmdomain_table_vpu3x, - .pmdomain_tbl_size =3D ARRAY_SIZE(iris_pmdomain_table_vpu3x), + .ctrl_data =3D &sm8550_ctrl_data, + .vcodec_data =3D sm8550_vcodec_data, .opp_pd_tbl =3D iris_opp_pd_table_vpu3x, .opp_pd_tbl_size =3D ARRAY_SIZE(iris_opp_pd_table_vpu3x), - .clk_tbl =3D sm8550_clk_table, - .clk_tbl_size =3D ARRAY_SIZE(sm8550_clk_table), .opp_clk_tbl =3D iris_opp_clk_table_vpu3x, /* Upper bound of DMA address range */ .dma_mask =3D 0xe0000000 - 1, @@ -127,12 +123,10 @@ const struct iris_platform_data sm8550_data =3D { .clk_rst_tbl_size =3D ARRAY_SIZE(sm8550_clk_reset_table), .bw_tbl_dec =3D iris_bw_table_dec_vpu3x, .bw_tbl_dec_size =3D ARRAY_SIZE(iris_bw_table_dec_vpu3x), - .pmdomain_tbl =3D iris_pmdomain_table_vpu3x, - .pmdomain_tbl_size =3D ARRAY_SIZE(iris_pmdomain_table_vpu3x), + .ctrl_data =3D &sm8550_ctrl_data, + .vcodec_data =3D sm8550_vcodec_data, .opp_pd_tbl =3D iris_opp_pd_table_vpu3x, .opp_pd_tbl_size =3D ARRAY_SIZE(iris_opp_pd_table_vpu3x), - .clk_tbl =3D sm8550_clk_table, - .clk_tbl_size =3D ARRAY_SIZE(sm8550_clk_table), .opp_clk_tbl =3D iris_opp_clk_table_vpu3x, /* Upper bound of DMA address range */ .dma_mask =3D 0xe0000000 - 1, @@ -164,12 +158,10 @@ const struct iris_platform_data sm8650_data =3D { .controller_rst_tbl_size =3D ARRAY_SIZE(sm8650_controller_reset_table), .bw_tbl_dec =3D iris_bw_table_dec_vpu3x, .bw_tbl_dec_size =3D ARRAY_SIZE(iris_bw_table_dec_vpu3x), - .pmdomain_tbl =3D iris_pmdomain_table_vpu3x, - .pmdomain_tbl_size =3D ARRAY_SIZE(iris_pmdomain_table_vpu3x), + .ctrl_data =3D &sm8550_ctrl_data, + .vcodec_data =3D sm8550_vcodec_data, .opp_pd_tbl =3D iris_opp_pd_table_vpu3x, .opp_pd_tbl_size =3D ARRAY_SIZE(iris_opp_pd_table_vpu3x), - .clk_tbl =3D sm8550_clk_table, - .clk_tbl_size =3D ARRAY_SIZE(sm8550_clk_table), .opp_clk_tbl =3D iris_opp_clk_table_vpu3x, /* Upper bound of DMA address range */ .dma_mask =3D 0xe0000000 - 1, @@ -193,12 +185,10 @@ const struct iris_platform_data sm8750_data =3D { .clk_rst_tbl_size =3D ARRAY_SIZE(sm8750_clk_reset_table), .bw_tbl_dec =3D iris_bw_table_dec_vpu3x, .bw_tbl_dec_size =3D ARRAY_SIZE(iris_bw_table_dec_vpu3x), - .pmdomain_tbl =3D iris_pmdomain_table_vpu3x, - .pmdomain_tbl_size =3D ARRAY_SIZE(iris_pmdomain_table_vpu3x), + .ctrl_data =3D &sm8750_ctrl_data, + .vcodec_data =3D sm8750_vcodec_data, .opp_pd_tbl =3D iris_opp_pd_table_vpu3x, .opp_pd_tbl_size =3D ARRAY_SIZE(iris_opp_pd_table_vpu3x), - .clk_tbl =3D sm8750_clk_table, - .clk_tbl_size =3D ARRAY_SIZE(sm8750_clk_table), .opp_clk_tbl =3D iris_opp_clk_table_vpu3x, /* Upper bound of DMA address range */ .dma_mask =3D 0xe0000000 - 1, @@ -228,12 +218,10 @@ const struct iris_platform_data x1p42100_data =3D { .clk_rst_tbl_size =3D ARRAY_SIZE(sm8550_clk_reset_table), .bw_tbl_dec =3D iris_bw_table_dec_vpu3x, .bw_tbl_dec_size =3D ARRAY_SIZE(iris_bw_table_dec_vpu3x), - .pmdomain_tbl =3D iris_pmdomain_table_vpu3x, - .pmdomain_tbl_size =3D ARRAY_SIZE(iris_pmdomain_table_vpu3x), + .ctrl_data =3D &x1p42100_ctrl_data, + .vcodec_data =3D x1p42100_vcodec_data, .opp_pd_tbl =3D iris_opp_pd_table_vpu3x, .opp_pd_tbl_size =3D ARRAY_SIZE(iris_opp_pd_table_vpu3x), - .clk_tbl =3D x1p42100_clk_table, - .clk_tbl_size =3D ARRAY_SIZE(x1p42100_clk_table), .opp_clk_tbl =3D x1p42100_opp_clk_table, /* Upper bound of DMA address range */ .dma_mask =3D 0xe0000000 - 1, diff --git a/drivers/media/platform/qcom/iris/iris_platform_x1p42100.h b/dr= ivers/media/platform/qcom/iris/iris_platform_x1p42100.h index d89acfbc1233..3444c1c3012b 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_x1p42100.h +++ b/drivers/media/platform/qcom/iris/iris_platform_x1p42100.h @@ -6,11 +6,28 @@ #ifndef __IRIS_PLATFORM_X1P42100_H__ #define __IRIS_PLATFORM_X1P42100_H__ =20 -static const struct platform_clk_data x1p42100_clk_table[] =3D { - {IRIS_AXI_CLK, "iface" }, - {IRIS_CTRL_CLK, "core" }, - {IRIS_HW_CLK, "vcodec0_core" }, - {IRIS_BSE_HW_CLK, "vcodec0_bse" }, +static const struct iris_power_domain_data x1p42100_ctrl_data =3D { + .pd_names =3D (const char *[]) { + "venus", + }, + .pd_cnt =3D 1, + .clk_names =3D (const char *[]) { + "iface", "core", + }, + .clk_cnt =3D 2, +}; + +static const struct iris_power_domain_data x1p42100_vcodec_data[] =3D { + { + .pd_names =3D (const char *[]) { + "vcodec0", + }, + .pd_cnt =3D 1, + .clk_names =3D (const char *[]) { + "vcodec0_core", "vcodec0_bse", + }, + .clk_cnt =3D 2, + }, }; =20 static const char *const x1p42100_opp_clk_table[] =3D { diff --git a/drivers/media/platform/qcom/iris/iris_probe.c b/drivers/media/= platform/qcom/iris/iris_probe.c index c2dcb50a2782..1e362570bb15 100644 --- a/drivers/media/platform/qcom/iris/iris_probe.c +++ b/drivers/media/platform/qcom/iris/iris_probe.c @@ -39,15 +39,42 @@ static int iris_init_icc(struct iris_core *core) return devm_of_icc_bulk_get(core->dev, core->icc_count, core->icc_tbl); } =20 -static int iris_init_power_domains(struct iris_core *core) +static int iris_init_power_domains_per_block(struct iris_core *core, + struct iris_power_domain *pd, + const struct iris_power_domain_data *pd_data) { - int ret; + struct dev_pm_domain_attach_data iris_pd_data =3D {}; + struct dev_pm_domain_list *pmdomain_tbl; + int ret, i; =20 - struct dev_pm_domain_attach_data iris_pd_data =3D { - .pd_names =3D core->iris_platform_data->pmdomain_tbl, - .num_pd_names =3D core->iris_platform_data->pmdomain_tbl_size, - .pd_flags =3D PD_FLAG_NO_DEV_LINK, - }; + if (!pd_data->pd_cnt) + return -EINVAL; + + iris_pd_data.pd_names =3D pd_data->pd_names; + iris_pd_data.num_pd_names =3D pd_data->pd_cnt; + iris_pd_data.pd_flags =3D PD_FLAG_NO_DEV_LINK; + + ret =3D devm_pm_domain_attach_list(core->dev, &iris_pd_data, &pmdomain_tb= l); + if (ret < 0) + return ret; + + pd->pd_cnt =3D ret; + + pd->dev =3D devm_kzalloc(core->dev, pd->pd_cnt * sizeof(*pd->dev), GFP_KE= RNEL); + if (!pd->dev) + return -ENOMEM; + + for (i =3D 0; i < pd->pd_cnt; i++) + pd->dev[i] =3D pmdomain_tbl->pd_devs[i]; + + return 0; +} + +static int iris_init_power_domains(struct iris_core *core) +{ + const struct iris_platform_data *plat =3D core->iris_platform_data; + u32 num_cores =3D max(plat->num_cores, 1); + int i, ret; =20 struct dev_pm_domain_attach_data iris_opp_pd_data =3D { .pd_names =3D core->iris_platform_data->opp_pd_tbl, @@ -60,10 +87,57 @@ static int iris_init_power_domains(struct iris_core *co= re) .config_clks =3D dev_pm_opp_config_clks_simple, }; =20 - ret =3D devm_pm_domain_attach_list(core->dev, &iris_pd_data, &core->pmdom= ain_tbl); - if (ret < 0) + core->ctrl =3D devm_kzalloc(core->dev, sizeof(*core->ctrl), GFP_KERNEL); + if (!core->ctrl) + return -ENOMEM; + + ret =3D iris_init_power_domains_per_block(core, core->ctrl, plat->ctrl_da= ta); + if (ret) return ret; =20 + core->vcodec =3D devm_kzalloc(core->dev, num_cores * sizeof(*core->vcodec= ), GFP_KERNEL); + if (!core->vcodec) + return -ENOMEM; + + for (i =3D 0; i < num_cores; i++) { + ret =3D iris_init_power_domains_per_block(core, &core->vcodec[i], + &plat->vcodec_data[i]); + if (ret) + return ret; + } + + if (plat->vcodec_vpp0_data) { + core->vcodec_vpp0 =3D devm_kzalloc(core->dev, sizeof(*core->vcodec_vpp0)= , GFP_KERNEL); + if (!core->vcodec_vpp0) + return -ENOMEM; + + ret =3D iris_init_power_domains_per_block(core, core->vcodec_vpp0, + plat->vcodec_vpp0_data); + if (ret) + return ret; + } + + if (plat->vcodec_vpp1_data) { + core->vcodec_vpp1 =3D devm_kzalloc(core->dev, sizeof(*core->vcodec_vpp1)= , GFP_KERNEL); + if (!core->vcodec_vpp1) + return -ENOMEM; + + ret =3D iris_init_power_domains_per_block(core, core->vcodec_vpp1, + plat->vcodec_vpp1_data); + if (ret) + return ret; + } + + if (plat->apv_data) { + core->apv =3D devm_kzalloc(core->dev, sizeof(*core->apv), GFP_KERNEL); + if (!core->apv) + return -ENOMEM; + + ret =3D iris_init_power_domains_per_block(core, core->apv, plat->apv_dat= a); + if (ret) + return ret; + } + ret =3D devm_pm_domain_attach_list(core->dev, &iris_opp_pd_data, &core->= opp_pmdomain_tbl); /* backwards compatibility for incomplete ABI SM8250 */ if (ret =3D=3D -ENODEV && @@ -82,17 +156,51 @@ static int iris_init_power_domains(struct iris_core *c= ore) return devm_pm_opp_of_add_table(core->dev); } =20 +static int iris_init_clocks_per_block(struct iris_core *core, struct iris_= power_domain *pd, + const struct iris_power_domain_data *pd_data) +{ + u32 i; + + if (!pd_data) + return 0; + + pd->clk_cnt =3D pd_data->clk_cnt; + pd->clocks =3D devm_kcalloc(core->dev, pd->clk_cnt, sizeof(*pd->clocks), = GFP_KERNEL); + if (!pd->clocks) + return -ENOMEM; + + for (i =3D 0; i < pd->clk_cnt; i++) + pd->clocks[i].id =3D pd_data->clk_names[i]; + + return devm_clk_bulk_get(core->dev, pd->clk_cnt, pd->clocks); +} + static int iris_init_clocks(struct iris_core *core) { + const struct iris_platform_data *plat =3D core->iris_platform_data; + u32 num_cores =3D max(plat->num_cores, 1); int ret; + u32 i; =20 - ret =3D devm_clk_bulk_get_all(core->dev, &core->clock_tbl); - if (ret < 0) + ret =3D iris_init_clocks_per_block(core, core->ctrl, plat->ctrl_data); + if (ret) return ret; =20 - core->clk_count =3D ret; + for (i =3D 0; i < num_cores; i++) { + ret =3D iris_init_clocks_per_block(core, &core->vcodec[i], &plat->vcodec= _data[i]); + if (ret) + return ret; + } =20 - return 0; + ret =3D iris_init_clocks_per_block(core, core->vcodec_vpp0, plat->vcodec_= vpp0_data); + if (ret) + return ret; + + ret =3D iris_init_clocks_per_block(core, core->vcodec_vpp1, plat->vcodec_= vpp1_data); + if (ret) + return ret; + + return iris_init_clocks_per_block(core, core->apv, plat->apv_data); } =20 static int iris_init_reset_table(struct iris_core *core, diff --git a/drivers/media/platform/qcom/iris/iris_resources.c b/drivers/me= dia/platform/qcom/iris/iris_resources.c index 773f6548370a..c7ab3a93b8a6 100644 --- a/drivers/media/platform/qcom/iris/iris_resources.c +++ b/drivers/media/platform/qcom/iris/iris_resources.c @@ -9,7 +9,6 @@ #include #include #include -#include =20 #include "iris_core.h" #include "iris_resources.h" @@ -70,74 +69,61 @@ int iris_opp_set_rate(struct device *dev, unsigned long= freq) return dev_pm_opp_set_opp(dev, opp); } =20 -int iris_enable_power_domains(struct iris_core *core, struct device *pd_de= v) +int iris_enable_power_domain_and_clocks(struct iris_core *core, struct iri= s_power_domain *pd) { - int ret; + int ret, i; =20 ret =3D iris_opp_set_rate(core->dev, ULONG_MAX); if (ret) return ret; =20 - ret =3D pm_runtime_get_sync(pd_dev); - if (ret < 0) - return ret; - - return ret; -} - -int iris_disable_power_domains(struct iris_core *core, struct device *pd_d= ev) -{ - int ret; + for (i =3D 0; i < pd->pd_cnt; i++) { + ret =3D pm_runtime_resume_and_get(pd->dev[i]); + if (ret < 0) + goto error; + } =20 - ret =3D iris_opp_set_rate(core->dev, 0); + ret =3D clk_bulk_prepare_enable(pd->clk_cnt, pd->clocks); if (ret) - return ret; - - pm_runtime_put_sync(pd_dev); + goto error; =20 return 0; -} =20 -static struct clk *iris_get_clk_by_type(struct iris_core *core, enum platf= orm_clk_type clk_type) -{ - const struct platform_clk_data *clk_tbl; - u32 clk_cnt, i, j; - - clk_tbl =3D core->iris_platform_data->clk_tbl; - clk_cnt =3D core->iris_platform_data->clk_tbl_size; - - for (i =3D 0; i < clk_cnt; i++) { - if (clk_tbl[i].clk_type =3D=3D clk_type) { - for (j =3D 0; core->clock_tbl && j < core->clk_count; j++) { - if (!strcmp(core->clock_tbl[j].id, clk_tbl[i].clk_name)) - return core->clock_tbl[j].clk; - } - } - } +error: + iris_opp_set_rate(core->dev, 0); =20 - return NULL; + while (--i >=3D 0) + pm_runtime_put_sync(pd->dev[i]); + + return ret; } =20 -int iris_prepare_enable_clock(struct iris_core *core, enum platform_clk_ty= pe clk_type) +void iris_disable_power_domain_and_clocks(struct iris_core *core, struct i= ris_power_domain *pd) { - struct clk *clock; + int i; =20 - clock =3D iris_get_clk_by_type(core, clk_type); - if (!clock) - return -ENOENT; + clk_bulk_disable_unprepare(pd->clk_cnt, pd->clocks); + iris_opp_set_rate(core->dev, 0); =20 - return clk_prepare_enable(clock); + for (i =3D 0; i < pd->pd_cnt; i++) + pm_runtime_put_sync(pd->dev[i]); } =20 -int iris_disable_unprepare_clock(struct iris_core *core, enum platform_clk= _type clk_type) +int iris_genpd_set_hwmode(struct iris_power_domain *pd, bool mode) { - struct clk *clock; + int i, ret; =20 - clock =3D iris_get_clk_by_type(core, clk_type); - if (!clock) - return -EINVAL; - - clk_disable_unprepare(clock); + for (i =3D 0; i < pd->pd_cnt; i++) { + ret =3D dev_pm_genpd_set_hwmode(pd->dev[i], mode); + if (ret) + goto error; + } =20 return 0; + +error: + while (--i >=3D 0) + dev_pm_genpd_set_hwmode(pd->dev[i], !mode); + + return ret; } diff --git a/drivers/media/platform/qcom/iris/iris_resources.h b/drivers/me= dia/platform/qcom/iris/iris_resources.h index 6bfbd2dc6db0..ec6ea408cb96 100644 --- a/drivers/media/platform/qcom/iris/iris_resources.h +++ b/drivers/media/platform/qcom/iris/iris_resources.h @@ -7,13 +7,13 @@ #define __IRIS_RESOURCES_H__ =20 struct iris_core; +struct iris_power_domain; =20 int iris_opp_set_rate(struct device *dev, unsigned long freq); -int iris_enable_power_domains(struct iris_core *core, struct device *pd_de= v); -int iris_disable_power_domains(struct iris_core *core, struct device *pd_d= ev); int iris_unset_icc_bw(struct iris_core *core); int iris_set_icc_bw(struct iris_core *core, unsigned long icc_bw); -int iris_disable_unprepare_clock(struct iris_core *core, enum platform_clk= _type clk_type); -int iris_prepare_enable_clock(struct iris_core *core, enum platform_clk_ty= pe clk_type); +int iris_enable_power_domain_and_clocks(struct iris_core *core, struct iri= s_power_domain *pd); +void iris_disable_power_domain_and_clocks(struct iris_core *core, struct i= ris_power_domain *pd); +int iris_genpd_set_hwmode(struct iris_power_domain *pd, bool mode); =20 #endif diff --git a/drivers/media/platform/qcom/iris/iris_vpu3x.c b/drivers/media/= platform/qcom/iris/iris_vpu3x.c index 3dad47be78b5..7cda94601555 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu3x.c +++ b/drivers/media/platform/qcom/iris/iris_vpu3x.c @@ -205,53 +205,20 @@ static int iris_vpu33_power_off_controller(struct iri= s_core *core) val &=3D ~NOC_HALT; writel(val, core->reg_base + AON_WRAPPER_MVP_NOC_CORE_CLK_CONTROL); =20 - iris_disable_unprepare_clock(core, IRIS_CTRL_CLK); - disable_power: - iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_PO= WER_DOMAIN]); - iris_disable_unprepare_clock(core, IRIS_AXI_CLK); + iris_disable_power_domain_and_clocks(core, core->ctrl); =20 return 0; } =20 static int iris_vpu35_power_on_hw(struct iris_core *core) { - int ret; - - ret =3D iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_= HW_POWER_DOMAIN]); - if (ret) - return ret; - - ret =3D iris_prepare_enable_clock(core, IRIS_AXI_CLK); - if (ret) - goto err_disable_power; - - ret =3D iris_prepare_enable_clock(core, IRIS_HW_FREERUN_CLK); - if (ret) - goto err_disable_axi_clk; - - ret =3D iris_prepare_enable_clock(core, IRIS_HW_CLK); - if (ret) - goto err_disable_hw_free_clk; - - return 0; - -err_disable_hw_free_clk: - iris_disable_unprepare_clock(core, IRIS_HW_FREERUN_CLK); -err_disable_axi_clk: - iris_disable_unprepare_clock(core, IRIS_AXI_CLK); -err_disable_power: - iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWE= R_DOMAIN]); - - return ret; + return iris_enable_power_domain_and_clocks(core, core->vcodec); } =20 static void iris_vpu35_power_off_hw(struct iris_core *core) { iris_vpu33_power_off_hardware(core); - - iris_disable_unprepare_clock(core, IRIS_HW_FREERUN_CLK); - iris_disable_unprepare_clock(core, IRIS_AXI_CLK); } =20 const struct vpu_ops iris_vpu3_ops =3D { diff --git a/drivers/media/platform/qcom/iris/iris_vpu4x.c b/drivers/media/= platform/qcom/iris/iris_vpu4x.c index 02e100a4045f..caee9e4351db 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu4x.c +++ b/drivers/media/platform/qcom/iris/iris_vpu4x.c @@ -27,27 +27,24 @@ static int iris_vpu4x_genpd_set_hwmode(struct iris_core= *core, bool hw_mode, u32 { int ret; =20 - ret =3D dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_HW_POWER= _DOMAIN], hw_mode); + ret =3D iris_genpd_set_hwmode(core->vcodec, hw_mode); if (ret) return ret; =20 if (!(efuse_value & DISABLE_VIDEO_VPP0_BIT)) { - ret =3D dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs - [IRIS_VPP0_HW_POWER_DOMAIN], hw_mode); + ret =3D iris_genpd_set_hwmode(core->vcodec_vpp0, hw_mode); if (ret) goto restore_hw_domain_mode; } =20 if (!(efuse_value & DISABLE_VIDEO_VPP1_BIT)) { - ret =3D dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs - [IRIS_VPP1_HW_POWER_DOMAIN], hw_mode); + ret =3D iris_genpd_set_hwmode(core->vcodec_vpp1, hw_mode); if (ret) goto restore_vpp0_domain_mode; } =20 if (!(efuse_value & DISABLE_VIDEO_APV_BIT)) { - ret =3D dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs - [IRIS_APV_HW_POWER_DOMAIN], hw_mode); + ret =3D iris_genpd_set_hwmode(core->apv, hw_mode); if (ret) goto restore_vpp1_domain_mode; } @@ -56,37 +53,19 @@ static int iris_vpu4x_genpd_set_hwmode(struct iris_core= *core, bool hw_mode, u32 =20 restore_vpp1_domain_mode: if (!(efuse_value & DISABLE_VIDEO_VPP1_BIT)) - dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_VPP1_HW_POWER_D= OMAIN], - !hw_mode); + iris_genpd_set_hwmode(core->vcodec_vpp1, !hw_mode); restore_vpp0_domain_mode: if (!(efuse_value & DISABLE_VIDEO_VPP0_BIT)) - dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_VPP0_HW_POWER_D= OMAIN], - !hw_mode); + iris_genpd_set_hwmode(core->vcodec_vpp0, !hw_mode); restore_hw_domain_mode: - dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]= , !hw_mode); + iris_genpd_set_hwmode(core->vcodec, !hw_mode); =20 return ret; } =20 static int iris_vpu4x_power_on_apv(struct iris_core *core) { - int ret; - - ret =3D iris_enable_power_domains(core, - core->pmdomain_tbl->pd_devs[IRIS_APV_HW_POWER_DOMAIN]); - if (ret) - return ret; - - ret =3D iris_prepare_enable_clock(core, IRIS_APV_HW_CLK); - if (ret) - goto disable_apv_hw_power_domain; - - return 0; - -disable_apv_hw_power_domain: - iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_APV_HW_= POWER_DOMAIN]); - - return ret; + return iris_enable_power_domain_and_clocks(core, core->apv); } =20 static void iris_vpu4x_power_off_apv(struct iris_core *core) @@ -138,8 +117,7 @@ static void iris_vpu4x_power_off_apv(struct iris_core *= core) writel(0x0, core->reg_base + CPU_CS_APV_BRIDGE_SYNC_RESET); =20 disable_clocks_and_power: - iris_disable_unprepare_clock(core, IRIS_APV_HW_CLK); - iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_APV_HW_= POWER_DOMAIN]); + iris_disable_power_domain_and_clocks(core, core->apv); } =20 static void iris_vpu4x_ahb_sync_reset_apv(struct iris_core *core) @@ -158,116 +136,43 @@ static void iris_vpu4x_ahb_sync_reset_hardware(struc= t iris_core *core) writel(0x0, core->reg_base + CPU_CS_AHB_BRIDGE_SYNC_RESET); } =20 -static int iris_vpu4x_enable_hardware_clocks(struct iris_core *core, u32 e= fuse_value) -{ - int ret; - - ret =3D iris_prepare_enable_clock(core, IRIS_AXI_CLK); - if (ret) - return ret; - - ret =3D iris_prepare_enable_clock(core, IRIS_HW_FREERUN_CLK); - if (ret) - goto disable_axi_clock; - - ret =3D iris_prepare_enable_clock(core, IRIS_HW_CLK); - if (ret) - goto disable_hw_free_run_clock; - - ret =3D iris_prepare_enable_clock(core, IRIS_BSE_HW_CLK); - if (ret) - goto disable_hw_clock; - - if (!(efuse_value & DISABLE_VIDEO_VPP0_BIT)) { - ret =3D iris_prepare_enable_clock(core, IRIS_VPP0_HW_CLK); - if (ret) - goto disable_bse_hw_clock; - } - - if (!(efuse_value & DISABLE_VIDEO_VPP1_BIT)) { - ret =3D iris_prepare_enable_clock(core, IRIS_VPP1_HW_CLK); - if (ret) - goto disable_vpp0_hw_clock; - } - - return 0; - -disable_vpp0_hw_clock: - if (!(efuse_value & DISABLE_VIDEO_VPP0_BIT)) - iris_disable_unprepare_clock(core, IRIS_VPP0_HW_CLK); -disable_bse_hw_clock: - iris_disable_unprepare_clock(core, IRIS_BSE_HW_CLK); -disable_hw_clock: - iris_disable_unprepare_clock(core, IRIS_HW_CLK); -disable_hw_free_run_clock: - iris_disable_unprepare_clock(core, IRIS_HW_FREERUN_CLK); -disable_axi_clock: - iris_disable_unprepare_clock(core, IRIS_AXI_CLK); - - return ret; -} - -static void iris_vpu4x_disable_hardware_clocks(struct iris_core *core, u32= efuse_value) -{ - if (!(efuse_value & DISABLE_VIDEO_VPP1_BIT)) - iris_disable_unprepare_clock(core, IRIS_VPP1_HW_CLK); - - if (!(efuse_value & DISABLE_VIDEO_VPP0_BIT)) - iris_disable_unprepare_clock(core, IRIS_VPP0_HW_CLK); - - iris_disable_unprepare_clock(core, IRIS_BSE_HW_CLK); - iris_disable_unprepare_clock(core, IRIS_HW_CLK); - iris_disable_unprepare_clock(core, IRIS_HW_FREERUN_CLK); - iris_disable_unprepare_clock(core, IRIS_AXI_CLK); -} - static int iris_vpu4x_power_on_hardware(struct iris_core *core) { u32 efuse_value =3D readl(core->reg_base + WRAPPER_EFUSE_MONITOR); int ret; =20 - ret =3D iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_= HW_POWER_DOMAIN]); + ret =3D iris_enable_power_domain_and_clocks(core, core->vcodec); if (ret) return ret; =20 if (!(efuse_value & DISABLE_VIDEO_VPP0_BIT)) { - ret =3D iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs - [IRIS_VPP0_HW_POWER_DOMAIN]); + ret =3D iris_enable_power_domain_and_clocks(core, core->vcodec_vpp0); if (ret) goto disable_hw_power_domain; } =20 if (!(efuse_value & DISABLE_VIDEO_VPP1_BIT)) { - ret =3D iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs - [IRIS_VPP1_HW_POWER_DOMAIN]); + ret =3D iris_enable_power_domain_and_clocks(core, core->vcodec_vpp1); if (ret) goto disable_vpp0_power_domain; } =20 - ret =3D iris_vpu4x_enable_hardware_clocks(core, efuse_value); - if (ret) - goto disable_vpp1_power_domain; - if (!(efuse_value & DISABLE_VIDEO_APV_BIT)) { ret =3D iris_vpu4x_power_on_apv(core); if (ret) - goto disable_hw_clocks; + goto disable_vpp1_power_domain; } =20 return 0; =20 -disable_hw_clocks: - iris_vpu4x_disable_hardware_clocks(core, efuse_value); disable_vpp1_power_domain: if (!(efuse_value & DISABLE_VIDEO_VPP1_BIT)) - iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs - [IRIS_VPP1_HW_POWER_DOMAIN]); + iris_disable_power_domain_and_clocks(core, core->vcodec_vpp1); disable_vpp0_power_domain: if (!(efuse_value & DISABLE_VIDEO_VPP0_BIT)) - iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs - [IRIS_VPP0_HW_POWER_DOMAIN]); + iris_disable_power_domain_and_clocks(core, core->vcodec_vpp0); disable_hw_power_domain: - iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWE= R_DOMAIN]); + iris_disable_power_domain_and_clocks(core, core->vcodec); =20 return ret; } @@ -335,17 +240,13 @@ static void iris_vpu4x_power_off_hardware(struct iris= _core *core) writel(0x0, core->reg_base + CPU_CS_AHB_BRIDGE_SYNC_RESET); =20 disable_clocks_and_power: - iris_vpu4x_disable_hardware_clocks(core, efuse_value); - if (!(efuse_value & DISABLE_VIDEO_VPP1_BIT)) - iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs - [IRIS_VPP1_HW_POWER_DOMAIN]); + iris_disable_power_domain_and_clocks(core, core->vcodec_vpp1); =20 if (!(efuse_value & DISABLE_VIDEO_VPP0_BIT)) - iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs - [IRIS_VPP0_HW_POWER_DOMAIN]); + iris_disable_power_domain_and_clocks(core, core->vcodec_vpp0); =20 - iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWE= R_DOMAIN]); + iris_disable_power_domain_and_clocks(core, core->vcodec); } =20 static int iris_vpu4x_set_hwmode(struct iris_core *core) diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/m= edia/platform/qcom/iris/iris_vpu_common.c index 8bdfee672954..330fc85d232b 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_common.c +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c @@ -212,21 +212,15 @@ int iris_vpu_power_off_controller(struct iris_core *c= ore) writel(0x0, core->reg_base + WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG); =20 disable_power: - iris_disable_unprepare_clock(core, IRIS_AHB_CLK); - iris_disable_unprepare_clock(core, IRIS_CTRL_CLK); - iris_disable_unprepare_clock(core, IRIS_AXI_CLK); - iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_PO= WER_DOMAIN]); + iris_disable_power_domain_and_clocks(core, core->ctrl); =20 return 0; } =20 void iris_vpu_power_off_hw(struct iris_core *core) { - dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]= , false); - iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWE= R_DOMAIN]); - iris_disable_unprepare_clock(core, IRIS_BSE_HW_CLK); - iris_disable_unprepare_clock(core, IRIS_HW_AHB_CLK); - iris_disable_unprepare_clock(core, IRIS_HW_CLK); + iris_genpd_set_hwmode(core->vcodec, false); + iris_disable_power_domain_and_clocks(core, core->vcodec); } =20 void iris_vpu_power_off(struct iris_core *core) @@ -245,7 +239,7 @@ int iris_vpu_power_on_controller(struct iris_core *core) u32 rst_tbl_size =3D core->iris_platform_data->clk_rst_tbl_size; int ret; =20 - ret =3D iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_= CTRL_POWER_DOMAIN]); + ret =3D iris_enable_power_domain_and_clocks(core, core->ctrl); if (ret) return ret; =20 @@ -253,65 +247,22 @@ int iris_vpu_power_on_controller(struct iris_core *co= re) if (ret) goto err_disable_power; =20 - ret =3D iris_prepare_enable_clock(core, IRIS_AXI_CLK); - if (ret) - goto err_disable_power; - - ret =3D iris_prepare_enable_clock(core, IRIS_CTRL_CLK); - if (ret) - goto err_disable_axi_clock; - - ret =3D iris_prepare_enable_clock(core, IRIS_AHB_CLK); - if (ret && ret !=3D -ENOENT) - goto err_disable_ctrl_clock; - return 0; =20 -err_disable_ctrl_clock: - iris_disable_unprepare_clock(core, IRIS_CTRL_CLK); -err_disable_axi_clock: - iris_disable_unprepare_clock(core, IRIS_AXI_CLK); err_disable_power: - iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_PO= WER_DOMAIN]); + iris_disable_power_domain_and_clocks(core, core->ctrl); =20 return ret; } =20 int iris_vpu_power_on_hw(struct iris_core *core) { - int ret; - - ret =3D iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_= HW_POWER_DOMAIN]); - if (ret) - return ret; - - ret =3D iris_prepare_enable_clock(core, IRIS_HW_CLK); - if (ret) - goto err_disable_power; - - ret =3D iris_prepare_enable_clock(core, IRIS_HW_AHB_CLK); - if (ret && ret !=3D -ENOENT) - goto err_disable_hw_clock; - - ret =3D iris_prepare_enable_clock(core, IRIS_BSE_HW_CLK); - if (ret && ret !=3D -ENOENT) - goto err_disable_hw_ahb_clock; - - return 0; - -err_disable_hw_ahb_clock: - iris_disable_unprepare_clock(core, IRIS_HW_AHB_CLK); -err_disable_hw_clock: - iris_disable_unprepare_clock(core, IRIS_HW_CLK); -err_disable_power: - iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWE= R_DOMAIN]); - - return ret; + return iris_enable_power_domain_and_clocks(core, core->vcodec); } =20 int iris_vpu_set_hwmode(struct iris_core *core) { - return dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_= DOMAIN], true); + return iris_genpd_set_hwmode(core->vcodec, true); } =20 int iris_vpu_switch_to_hwmode(struct iris_core *core) @@ -386,11 +337,7 @@ int iris_vpu35_vpu4x_power_off_controller(struct iris_= core *core) val, val =3D=3D 0, 200, 2000); =20 disable_power: - iris_disable_unprepare_clock(core, IRIS_CTRL_CLK); - iris_disable_unprepare_clock(core, IRIS_CTRL_FREERUN_CLK); - iris_disable_unprepare_clock(core, IRIS_AXI1_CLK); - - iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_PO= WER_DOMAIN]); + iris_disable_power_domain_and_clocks(core, core->ctrl); =20 reset_control_bulk_reset(clk_rst_tbl_size, core->resets); =20 @@ -399,34 +346,7 @@ int iris_vpu35_vpu4x_power_off_controller(struct iris_= core *core) =20 int iris_vpu35_vpu4x_power_on_controller(struct iris_core *core) { - int ret; - - ret =3D iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_= CTRL_POWER_DOMAIN]); - if (ret) - return ret; - - ret =3D iris_prepare_enable_clock(core, IRIS_AXI1_CLK); - if (ret) - goto err_disable_power; - - ret =3D iris_prepare_enable_clock(core, IRIS_CTRL_FREERUN_CLK); - if (ret) - goto err_disable_axi1_clk; - - ret =3D iris_prepare_enable_clock(core, IRIS_CTRL_CLK); - if (ret) - goto err_disable_ctrl_free_clk; - - return 0; - -err_disable_ctrl_free_clk: - iris_disable_unprepare_clock(core, IRIS_CTRL_FREERUN_CLK); -err_disable_axi1_clk: - iris_disable_unprepare_clock(core, IRIS_AXI1_CLK); -err_disable_power: - iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_PO= WER_DOMAIN]); - - return ret; + return iris_enable_power_domain_and_clocks(core, core->ctrl); } =20 void iris_vpu35_vpu4x_program_bootup_registers(struct iris_core *core) --=20 2.34.1 From nobody Fri Jun 12 11:18:18 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 228E237B3F9 for ; Wed, 10 Jun 2026 06:30:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; 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Both cores share a common clock source (video_cc_mvs0_clk_src) and the same power rails. The clock dividers between the source and the branch clocks are fixed. So when both cores are running, the source clock always runs at the highest frequency requested by either core. Since both cores share the same power rails, the power corner cannot be voted independently. Scaling one core's power corner up or down would directly affect the other, leading to under or over-voting. For these reasons, both cores should voted the clock and power rail must be based on the workload of both cores. Reviewed-by: Vikash Garodia Signed-off-by: Vishnu Reddy --- drivers/media/platform/qcom/iris/iris_vpu3x.c | 111 +++++++++++++++++= +++- drivers/media/platform/qcom/iris/iris_vpu_common.h | 1 + .../platform/qcom/iris/iris_vpu_register_defines.h | 10 ++ 3 files changed, 117 insertions(+), 5 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_vpu3x.c b/drivers/media/= platform/qcom/iris/iris_vpu3x.c index 7cda94601555..afd2a0e2a3a5 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu3x.c +++ b/drivers/media/platform/qcom/iris/iris_vpu3x.c @@ -17,14 +17,14 @@ #define NOC_HALT BIT(0) #define AON_WRAPPER_SPARE (AON_BASE_OFFS + 0x28) =20 -static bool iris_vpu3x_hw_power_collapsed(struct iris_core *core) +static bool iris_vpu3x_hw_power_collapsed(struct iris_core *core, u32 pwr_= status_bit) { u32 value, pwr_status; =20 value =3D readl(core->reg_base + WRAPPER_CORE_POWER_STATUS); - pwr_status =3D value & BIT(1); + pwr_status =3D value & pwr_status_bit; =20 - return pwr_status ? false : true; + return !pwr_status; } =20 static void iris_vpu3_power_off_hardware(struct iris_core *core) @@ -32,7 +32,7 @@ static void iris_vpu3_power_off_hardware(struct iris_core= *core) u32 reg_val =3D 0, value, i; int ret; =20 - if (iris_vpu3x_hw_power_collapsed(core)) + if (iris_vpu3x_hw_power_collapsed(core, VCODEC0_POWER_STATUS)) goto disable_power; =20 dev_err(core->dev, "video hw is power on\n"); @@ -78,7 +78,7 @@ static void iris_vpu33_power_off_hardware(struct iris_cor= e *core) u32 count =3D 0; int ret; =20 - if (iris_vpu3x_hw_power_collapsed(core)) + if (iris_vpu3x_hw_power_collapsed(core, VCODEC0_POWER_STATUS)) goto disable_power; =20 dev_err(core->dev, "video hw is power on\n"); @@ -221,6 +221,98 @@ static void iris_vpu35_power_off_hw(struct iris_core *= core) iris_vpu33_power_off_hardware(core); } =20 +static void iris_vpu36_power_off_vcodec(struct iris_core *core, u32 core_i= d) +{ + u32 bridge_hw_reset[] =3D {CORE_BRIDGE_HW_RESET_DISABLE, VCODEC1_BRIDGE_H= W_RESET_DISABLE}; + u32 power_down_prep[] =3D {REQ_POWER_DOWN_PREP, REQ_VCODEC1_POWER_DOWN_PR= EP}; + u32 bridge_sw_reset[] =3D {CORE_BRIDGE_SW_RESET, VCODEC1_BRIDGE_SW_RESET}; + u32 idle_status[] =3D {VCODEC_SS_IDLE_STATUSN, VCODEC1_SS_IDLE_STATUSN}; + u32 lpi_status[] =3D {NOC_LPI_STATUS_DONE, NOC_LPI_VCODEC1_STATUS_DONE}; + u32 power_status[] =3D {VCODEC0_POWER_STATUS, VCODEC1_POWER_STATUS}; + u32 value, i; + int ret; + + if (iris_vpu3x_hw_power_collapsed(core, power_status[core_id])) + goto disable_power; + + value =3D readl(core->reg_base + WRAPPER_CORE_CLOCK_CONFIG); + if (value) + writel(CORE_CLK_RUN, core->reg_base + WRAPPER_CORE_CLOCK_CONFIG); + + for (i =3D 0; i < core->iris_platform_data->num_vpp_pipe; i++) { + ret =3D readl_poll_timeout(core->reg_base + idle_status[core_id] + 4 * i, + value, value & DMA_NOC_IDLE, 2000, 20000); + if (ret) + goto disable_power; + } + + writel(power_down_prep[core_id], core->reg_base + AON_WRAPPER_MVP_NOC_LPI= _CONTROL); + ret =3D readl_poll_timeout(core->reg_base + AON_WRAPPER_MVP_NOC_LPI_STATU= S, value, + value & lpi_status[core_id], 2000, 20000); + if (ret) + goto disable_power; + + writel(0, core->reg_base + AON_WRAPPER_MVP_NOC_LPI_CONTROL); + + writel(bridge_sw_reset[core_id] | bridge_hw_reset[core_id], + core->reg_base + CPU_CS_AHB_BRIDGE_SYNC_RESET); + writel(bridge_hw_reset[core_id], core->reg_base + CPU_CS_AHB_BRIDGE_SYNC_= RESET); + writel(0x0, core->reg_base + CPU_CS_AHB_BRIDGE_SYNC_RESET); + +disable_power: + iris_genpd_set_hwmode(&core->vcodec[core_id], false); + iris_disable_power_domain_and_clocks(core, &core->vcodec[core_id]); +} + +static void iris_vpu36_power_off_hw(struct iris_core *core) +{ + u32 num_cores =3D core->iris_platform_data->num_cores; + int i; + + for (i =3D 0; i < num_cores; i++) + iris_vpu36_power_off_vcodec(core, i); +} + +static int iris_vpu36_power_on_hw(struct iris_core *core) +{ + u32 num_cores =3D core->iris_platform_data->num_cores; + int i, ret; + + for (i =3D 0; i < num_cores; i++) { + ret =3D iris_enable_power_domain_and_clocks(core, &core->vcodec[i]); + if (ret) + goto error; + } + + return 0; + +error: + while (--i >=3D 0) + iris_vpu36_power_off_vcodec(core, i); + + return ret; +} + +static int iris_vpu36_set_hwmode(struct iris_core *core) +{ + u32 num_cores =3D core->iris_platform_data->num_cores; + int i, ret; + + for (i =3D 0; i < num_cores; i++) { + ret =3D iris_genpd_set_hwmode(&core->vcodec[i], true); + if (ret) + goto error; + } + + return 0; + +error: + while (--i >=3D 0) + iris_genpd_set_hwmode(&core->vcodec[i], false); + + return ret; +} + const struct vpu_ops iris_vpu3_ops =3D { .power_off_hw =3D iris_vpu3_power_off_hardware, .power_on_hw =3D iris_vpu_power_on_hw, @@ -248,3 +340,12 @@ const struct vpu_ops iris_vpu35_ops =3D { .calc_freq =3D iris_vpu3x_vpu4x_calculate_frequency, .set_hwmode =3D iris_vpu_set_hwmode, }; + +const struct vpu_ops iris_vpu36_ops =3D { + .power_off_hw =3D iris_vpu36_power_off_hw, + .power_on_hw =3D iris_vpu36_power_on_hw, + .power_off_controller =3D iris_vpu35_vpu4x_power_off_controller, + .power_on_controller =3D iris_vpu35_vpu4x_power_on_controller, + .calc_freq =3D iris_vpu3x_vpu4x_calculate_frequency, + .set_hwmode =3D iris_vpu36_set_hwmode, +}; diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.h b/drivers/m= edia/platform/qcom/iris/iris_vpu_common.h index e0dc109bbe6a..e2e3e66574fa 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_common.h +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.h @@ -12,6 +12,7 @@ extern const struct vpu_ops iris_vpu2_ops; extern const struct vpu_ops iris_vpu3_ops; extern const struct vpu_ops iris_vpu33_ops; extern const struct vpu_ops iris_vpu35_ops; +extern const struct vpu_ops iris_vpu36_ops; extern const struct vpu_ops iris_vpu4x_ops; =20 struct vpu_ops { diff --git a/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h b= /drivers/media/platform/qcom/iris/iris_vpu_register_defines.h index 72168b9ffa73..e67d98b8c91e 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h +++ b/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h @@ -7,6 +7,7 @@ #define __IRIS_VPU_REGISTER_DEFINES_H__ =20 #define VCODEC_BASE_OFFS 0x00000000 +#define VCODEC1_BASE_OFFS 0x00040000 #define AON_MVP_NOC_RESET 0x0001F000 #define CPU_BASE_OFFS 0x000A0000 #define WRAPPER_BASE_OFFS 0x000B0000 @@ -14,6 +15,8 @@ #define AON_BASE_OFFS 0x000E0000 =20 #define VCODEC_SS_IDLE_STATUSN (VCODEC_BASE_OFFS + 0x70) +#define VCODEC1_SS_IDLE_STATUSN (VCODEC1_BASE_OFFS + 0x70) +#define DMA_NOC_IDLE BIT(22) =20 #define AON_WRAPPER_MVP_NOC_RESET_REQ (AON_MVP_NOC_RESET + 0x000) #define VIDEO_NOC_RESET_REQ (BIT(0) | BIT(1)) @@ -35,6 +38,8 @@ #define CPU_CS_AHB_BRIDGE_SYNC_RESET (CPU_CS_BASE_OFFS + 0x160) #define CORE_BRIDGE_SW_RESET BIT(0) #define CORE_BRIDGE_HW_RESET_DISABLE BIT(1) +#define VCODEC1_BRIDGE_SW_RESET BIT(2) +#define VCODEC1_BRIDGE_HW_RESET_DISABLE BIT(3) =20 #define CPU_CS_X2RPMH (CPU_CS_BASE_OFFS + 0x168) #define MSK_SIGNAL_FROM_TENSILICA BIT(0) @@ -52,14 +57,19 @@ #define WRAPPER_DEBUG_BRIDGE_LPI_STATUS (WRAPPER_BASE_OFFS + 0x58) #define WRAPPER_IRIS_CPU_NOC_LPI_CONTROL (WRAPPER_BASE_OFFS + 0x5C) #define REQ_POWER_DOWN_PREP BIT(0) +#define REQ_VCODEC1_POWER_DOWN_PREP BIT(1) =20 #define WRAPPER_IRIS_CPU_NOC_LPI_STATUS (WRAPPER_BASE_OFFS + 0x60) #define NOC_LPI_STATUS_DONE BIT(0) /* Indicates the NOC handshake is com= plete */ #define NOC_LPI_STATUS_DENY BIT(1) /* Indicates the NOC handshake is den= ied */ #define NOC_LPI_STATUS_ACTIVE BIT(2) /* Indicates the NOC is active */ +#define NOC_LPI_VCODEC1_STATUS_DONE BIT(8) =20 #define WRAPPER_IRIS_VCODEC_VPU_WRAPPER_SPARE_0 (WRAPPER_BASE_OFFS + 0x78) #define WRAPPER_CORE_POWER_STATUS (WRAPPER_BASE_OFFS + 0x80) +#define VCODEC0_POWER_STATUS BIT(1) +#define VCODEC1_POWER_STATUS BIT(4) + #define WRAPPER_CORE_CLOCK_CONFIG (WRAPPER_BASE_OFFS + 0x88) #define CORE_CLK_RUN 0x0 =20 --=20 2.34.1 From nobody Fri Jun 12 11:18:18 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2639A37DE99 for ; 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Writing the default 0x1 causes the firmware to treat the VM count as 2. To avoid that write 0x0 to CPU_CS_SCIACMDARG3 as a Glymur platform specific. Reviewed-by: Dmitry Baryshkov Signed-off-by: Vishnu Reddy --- drivers/media/platform/qcom/iris/iris_vpu3x.c | 6 ++++++ drivers/media/platform/qcom/iris/iris_vpu_common.c | 4 ++-- drivers/media/platform/qcom/iris/iris_vpu_register_defines.h | 1 + 3 files changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_vpu3x.c b/drivers/media/= platform/qcom/iris/iris_vpu3x.c index afd2a0e2a3a5..bafa2ab645b1 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu3x.c +++ b/drivers/media/platform/qcom/iris/iris_vpu3x.c @@ -313,6 +313,11 @@ static int iris_vpu36_set_hwmode(struct iris_core *cor= e) return ret; } =20 +static void iris_vpu36_program_bootup_registers(struct iris_core *core) +{ + writel(0x0, core->reg_base + CPU_CS_SCIACMDARG3); +} + const struct vpu_ops iris_vpu3_ops =3D { .power_off_hw =3D iris_vpu3_power_off_hardware, .power_on_hw =3D iris_vpu_power_on_hw, @@ -346,6 +351,7 @@ const struct vpu_ops iris_vpu36_ops =3D { .power_on_hw =3D iris_vpu36_power_on_hw, .power_off_controller =3D iris_vpu35_vpu4x_power_off_controller, .power_on_controller =3D iris_vpu35_vpu4x_power_on_controller, + .program_bootup_registers =3D iris_vpu36_program_bootup_registers, .calc_freq =3D iris_vpu3x_vpu4x_calculate_frequency, .set_hwmode =3D iris_vpu36_set_hwmode, }; diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/m= edia/platform/qcom/iris/iris_vpu_common.c index 330fc85d232b..a42554272964 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_common.c +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c @@ -26,7 +26,6 @@ #define QTBL_ENABLE BIT(0) =20 #define QTBL_ADDR (CPU_CS_BASE_OFFS + 0x54) -#define CPU_CS_SCIACMDARG3 (CPU_CS_BASE_OFFS + 0x58) #define SFR_ADDR (CPU_CS_BASE_OFFS + 0x5C) #define UC_REGION_ADDR (CPU_CS_BASE_OFFS + 0x64) #define UC_REGION_SIZE (CPU_CS_BASE_OFFS + 0x68) @@ -67,6 +66,8 @@ static void iris_vpu_setup_ucregion_memory_map(struct iri= s_core *core) writel(value, core->reg_base + SFR_ADDR); } =20 + writel(0x1, core->reg_base + CPU_CS_SCIACMDARG3); + if (vpu_ops->program_bootup_registers) vpu_ops->program_bootup_registers(core); } @@ -78,7 +79,6 @@ int iris_vpu_boot_firmware(struct iris_core *core) iris_vpu_setup_ucregion_memory_map(core); =20 writel(ctrl_init, core->reg_base + CTRL_INIT); - writel(0x1, core->reg_base + CPU_CS_SCIACMDARG3); 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The selected core is communicated to the firmware via the HFI_PROP_CORE_ID property at stream-on time. Since both cores share the same clock source, the required clock frequency is the maximum of the aggregated frequencies across both cores. The total session count limit is scaled by the number of cores, since each core independently supports sessions up to its own limit. Reviewed-by: Dmitry Baryshkov Signed-off-by: Vishnu Reddy --- drivers/media/platform/qcom/iris/iris_common.c | 10 ++++ drivers/media/platform/qcom/iris/iris_common.h | 1 + drivers/media/platform/qcom/iris/iris_core.h | 5 ++ drivers/media/platform/qcom/iris/iris_hfi_common.h | 1 + .../platform/qcom/iris/iris_hfi_gen2_command.c | 19 +++++++ .../platform/qcom/iris/iris_hfi_gen2_defines.h | 1 + drivers/media/platform/qcom/iris/iris_instance.h | 2 + drivers/media/platform/qcom/iris/iris_power.c | 20 +++++-- drivers/media/platform/qcom/iris/iris_utils.c | 58 +++++++++++++-----= -- drivers/media/platform/qcom/iris/iris_utils.h | 3 +- drivers/media/platform/qcom/iris/iris_vb2.c | 4 ++ drivers/media/platform/qcom/iris/iris_vidc.c | 6 ++- drivers/media/platform/qcom/iris/iris_vpu3x.c | 63 ++++++++++++++++++= ++++ drivers/media/platform/qcom/iris/iris_vpu_common.h | 2 + 14 files changed, 171 insertions(+), 24 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_common.c b/drivers/media= /platform/qcom/iris/iris_common.c index 25836561bcf3..abea6807a59e 100644 --- a/drivers/media/platform/qcom/iris/iris_common.c +++ b/drivers/media/platform/qcom/iris/iris_common.c @@ -46,6 +46,16 @@ void iris_set_ts_metadata(struct iris_inst *inst, struct= vb2_v4l2_buffer *vbuf) inst->metadata_idx++; } =20 +int iris_set_core_id(struct iris_inst *inst) +{ + const struct iris_hfi_session_ops *hfi_ops =3D inst->hfi_session_ops; + + if (!inst->core_id) + return 0; + + return hfi_ops->session_set_core_id(inst, inst->core_id); +} + int iris_process_streamon_input(struct iris_inst *inst) { const struct iris_hfi_session_ops *hfi_ops =3D inst->hfi_session_ops; diff --git a/drivers/media/platform/qcom/iris/iris_common.h b/drivers/media= /platform/qcom/iris/iris_common.h index b2a27b781c9a..34e32c60f768 100644 --- a/drivers/media/platform/qcom/iris/iris_common.h +++ b/drivers/media/platform/qcom/iris/iris_common.h @@ -11,6 +11,7 @@ struct iris_buffer; =20 int iris_vb2_buffer_to_driver(struct vb2_buffer *vb2, struct iris_buffer *= buf); void iris_set_ts_metadata(struct iris_inst *inst, struct vb2_v4l2_buffer *= vbuf); +int iris_set_core_id(struct iris_inst *inst); int iris_process_streamon_input(struct iris_inst *inst); int iris_process_streamon_output(struct iris_inst *inst); int iris_session_streamoff(struct iris_inst *inst, u32 plane); diff --git a/drivers/media/platform/qcom/iris/iris_core.h b/drivers/media/p= latform/qcom/iris/iris_core.h index 8c36b64153c7..84d4bc32e406 100644 --- a/drivers/media/platform/qcom/iris/iris_core.h +++ b/drivers/media/platform/qcom/iris/iris_core.h @@ -37,6 +37,11 @@ enum domain_type { DECODER =3D BIT(1), }; =20 +enum iris_vcodec_core_id { + IRIS_VCODEC0 =3D 1, + IRIS_VCODEC1, +}; + struct qcom_ubwc_cfg_data; =20 /** diff --git a/drivers/media/platform/qcom/iris/iris_hfi_common.h b/drivers/m= edia/platform/qcom/iris/iris_hfi_common.h index a27447eb2519..47786529998d 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_common.h +++ b/drivers/media/platform/qcom/iris/iris_hfi_common.h @@ -131,6 +131,7 @@ struct iris_hfi_session_ops { int (*session_drain)(struct iris_inst *inst, u32 plane); int (*session_resume_drain)(struct iris_inst *inst, u32 plane); int (*session_close)(struct iris_inst *inst); + int (*session_set_core_id)(struct iris_inst *inst, u32 core_id); }; =20 struct hfi_subscription_params { diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c b/dri= vers/media/platform/qcom/iris/iris_hfi_gen2_command.c index ca2954f8bd3a..e73743a391e0 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c @@ -1360,6 +1360,24 @@ static int iris_hfi_gen2_session_release_buffer(stru= ct iris_inst *inst, struct i inst_hfi_gen2->packet->size); } =20 +static int iris_hfi_gen2_set_core_id(struct iris_inst *inst, u32 core_id) +{ + struct iris_inst_hfi_gen2 *inst_hfi_gen2 =3D to_iris_inst_hfi_gen2(inst); + u32 payload =3D core_id; + + iris_hfi_gen2_packet_session_command(inst, + HFI_PROP_CORE_ID, + HFI_HOST_FLAGS_NONE, + HFI_PORT_NONE, + inst->session_id, + HFI_PAYLOAD_U32, + &payload, + sizeof(u32)); + + return iris_hfi_queue_cmd_write(inst->core, inst_hfi_gen2->packet, + inst_hfi_gen2->packet->size); +} + static const struct iris_hfi_session_ops iris_hfi_gen2_session_ops =3D { .session_open =3D iris_hfi_gen2_session_open, .session_set_config_params =3D iris_hfi_gen2_session_set_config_params, @@ -1373,6 +1391,7 @@ static const struct iris_hfi_session_ops iris_hfi_gen= 2_session_ops =3D { .session_drain =3D iris_hfi_gen2_session_drain, .session_resume_drain =3D iris_hfi_gen2_session_resume_drain, .session_close =3D iris_hfi_gen2_session_close, + .session_set_core_id =3D iris_hfi_gen2_set_core_id, }; =20 static struct iris_inst *iris_hfi_gen2_get_instance(void) diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen2_defines.h b/dri= vers/media/platform/qcom/iris/iris_hfi_gen2_defines.h index 776b21cd11b2..2e374c2005ef 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen2_defines.h +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen2_defines.h @@ -56,6 +56,7 @@ #define HFI_PROP_BUFFER_HOST_MAX_COUNT 0x03000123 #define HFI_PROP_BUFFER_FW_MIN_OUTPUT_COUNT 0x03000124 #define HFI_PROP_PIC_ORDER_CNT_TYPE 0x03000128 +#define HFI_PROP_CORE_ID 0x030001a9 =20 enum hfi_rate_control { HFI_RC_VBR_CFR =3D 0x00000000, diff --git a/drivers/media/platform/qcom/iris/iris_instance.h b/drivers/med= ia/platform/qcom/iris/iris_instance.h index a770331d1675..585aa7c51fb0 100644 --- a/drivers/media/platform/qcom/iris/iris_instance.h +++ b/drivers/media/platform/qcom/iris/iris_instance.h @@ -36,6 +36,7 @@ enum iris_fmt_type_cap { * * @list: used for attach an instance to the core * @core: pointer to core structure + * @core_id: specifies the hardware core on which the session runs * @session_id: id of current video session * @hfi_session_ops: iris HFI session ops * @ctx_q_lock: lock to serialize queues related ioctls @@ -83,6 +84,7 @@ enum iris_fmt_type_cap { struct iris_inst { struct list_head list; struct iris_core *core; + u32 core_id; u32 session_id; const struct iris_hfi_session_ops *hfi_session_ops; struct mutex ctx_q_lock;/* lock to serialize queues related ioctls */ diff --git a/drivers/media/platform/qcom/iris/iris_power.c b/drivers/media/= platform/qcom/iris/iris_power.c index 91aa21d4070e..a875647b3162 100644 --- a/drivers/media/platform/qcom/iris/iris_power.c +++ b/drivers/media/platform/qcom/iris/iris_power.c @@ -75,14 +75,12 @@ static int iris_vote_interconnects(struct iris_inst *in= st) return iris_set_interconnects(inst); } =20 -static int iris_set_clocks(struct iris_inst *inst) +static u64 iris_get_required_freq(struct iris_inst *inst) { struct iris_core *core =3D inst->core; struct iris_inst *instance; u64 freq =3D 0; - int ret; =20 - mutex_lock(&core->lock); list_for_each_entry(instance, &core->instances, list) { if (!instance->max_input_data_size) continue; @@ -90,6 +88,22 @@ static int iris_set_clocks(struct iris_inst *inst) freq +=3D instance->power.min_freq; } =20 + return freq; +} + +static int iris_set_clocks(struct iris_inst *inst) +{ + const struct vpu_ops *vpu_ops =3D inst->core->iris_platform_data->vpu_ops; + struct iris_core *core =3D inst->core; + u64 freq; + int ret; + + mutex_lock(&core->lock); + if (vpu_ops->get_required_freq) + freq =3D vpu_ops->get_required_freq(inst); + else + freq =3D iris_get_required_freq(inst); + core->power.clk_freq =3D freq; ret =3D iris_opp_set_rate(core->dev, freq); mutex_unlock(&core->lock); diff --git a/drivers/media/platform/qcom/iris/iris_utils.c b/drivers/media/= platform/qcom/iris/iris_utils.c index ba5c8dc1280c..4608e3f28832 100644 --- a/drivers/media/platform/qcom/iris/iris_utils.c +++ b/drivers/media/platform/qcom/iris/iris_utils.c @@ -7,6 +7,7 @@ #include =20 #include "iris_instance.h" +#include "iris_vpu_common.h" #include "iris_utils.h" =20 bool iris_res_is_less_than(u32 width, u32 height, @@ -23,7 +24,7 @@ bool iris_res_is_less_than(u32 width, u32 height, return false; } =20 -int iris_get_mbpf(struct iris_inst *inst) +u32 iris_get_mbpf(struct iris_inst *inst) { struct v4l2_format *inp_f =3D inst->fmt_src; u32 height =3D max(inp_f->fmt.pix_mp.height, inst->crop.height); @@ -32,6 +33,13 @@ int iris_get_mbpf(struct iris_inst *inst) return NUM_MBS_PER_FRAME(height, width); } =20 +u32 iris_get_mbps(struct iris_inst *inst) +{ + u32 fps =3D max(inst->frame_rate, inst->operating_rate); + + return iris_get_mbpf(inst) * fps; +} + bool iris_split_mode_enabled(struct iris_inst *inst) { return inst->fmt_dst->fmt.pix_mp.pixelformat =3D=3D V4L2_PIX_FMT_NV12 || @@ -101,40 +109,52 @@ struct iris_inst *iris_get_instance(struct iris_core = *core, u32 session_id) return NULL; } =20 -int iris_check_core_mbpf(struct iris_inst *inst) +static int iris_check_core_load(struct iris_inst *inst, bool mbpf) { - struct iris_core *core =3D inst->core; + const struct iris_platform_data *platform_data =3D inst->core->iris_platf= orm_data; + u32 max_load =3D mbpf ? platform_data->max_core_mbpf : platform_data->max= _core_mbps; struct iris_inst *instance; - u32 total_mbpf =3D 0; + u32 total_load =3D 0; =20 - mutex_lock(&core->lock); - list_for_each_entry(instance, &core->instances, list) - total_mbpf +=3D iris_get_mbpf(instance); - mutex_unlock(&core->lock); + list_for_each_entry(instance, &inst->core->instances, list) + total_load +=3D mbpf ? iris_get_mbpf(instance) : iris_get_mbps(instance); =20 - if (total_mbpf > core->iris_platform_data->max_core_mbpf) + if (total_load > max_load) return -ENOMEM; =20 return 0; } =20 -int iris_check_core_mbps(struct iris_inst *inst) +int iris_check_core_mbpf(struct iris_inst *inst) { + const struct vpu_ops *vpu_ops =3D inst->core->iris_platform_data->vpu_ops; struct iris_core *core =3D inst->core; - struct iris_inst *instance; - u32 total_mbps =3D 0, fps =3D 0; + int ret; =20 mutex_lock(&core->lock); - list_for_each_entry(instance, &core->instances, list) { - fps =3D max(instance->frame_rate, instance->operating_rate); - total_mbps +=3D iris_get_mbpf(instance) * fps; - } + if (vpu_ops->check_core_load) + ret =3D vpu_ops->check_core_load(inst, true); + else + ret =3D iris_check_core_load(inst, true); mutex_unlock(&core->lock); =20 - if (total_mbps > core->iris_platform_data->max_core_mbps) - return -ENOMEM; + return ret; +} =20 - return 0; +int iris_check_core_mbps(struct iris_inst *inst) +{ + const struct vpu_ops *vpu_ops =3D inst->core->iris_platform_data->vpu_ops; + struct iris_core *core =3D inst->core; + int ret; + + mutex_lock(&core->lock); + if (vpu_ops->check_core_load) + ret =3D vpu_ops->check_core_load(inst, false); + else + ret =3D iris_check_core_load(inst, false); + mutex_unlock(&core->lock); + + return ret; } =20 bool is_rotation_90_or_270(struct iris_inst *inst) diff --git a/drivers/media/platform/qcom/iris/iris_utils.h b/drivers/media/= platform/qcom/iris/iris_utils.h index 228a5f963812..c36ac494f461 100644 --- a/drivers/media/platform/qcom/iris/iris_utils.h +++ b/drivers/media/platform/qcom/iris/iris_utils.h @@ -43,7 +43,8 @@ static inline enum iris_buffer_type iris_v4l2_type_to_dri= ver(u32 type) =20 bool iris_res_is_less_than(u32 width, u32 height, u32 ref_width, u32 ref_height); -int iris_get_mbpf(struct iris_inst *inst); +u32 iris_get_mbpf(struct iris_inst *inst); +u32 iris_get_mbps(struct iris_inst *inst); bool iris_split_mode_enabled(struct iris_inst *inst); bool iris_fmt_is_8bit(u32 pixelformat); bool iris_fmt_is_10bit(u32 pixelformat); diff --git a/drivers/media/platform/qcom/iris/iris_vb2.c b/drivers/media/pl= atform/qcom/iris/iris_vb2.c index a2ea2d67f60d..dbb89396e651 100644 --- a/drivers/media/platform/qcom/iris/iris_vb2.c +++ b/drivers/media/platform/qcom/iris/iris_vb2.c @@ -176,6 +176,10 @@ int iris_vb2_start_streaming(struct vb2_queue *q, unsi= gned int count) if (ret) goto error; =20 + ret =3D iris_set_core_id(inst); + if (ret) + goto error; + if (V4L2_TYPE_IS_OUTPUT(q->type)) { if (inst->domain =3D=3D DECODER) ret =3D iris_vdec_streamon_input(inst); diff --git a/drivers/media/platform/qcom/iris/iris_vidc.c b/drivers/media/p= latform/qcom/iris/iris_vidc.c index 14d63dc76c9b..059d020f28c3 100644 --- a/drivers/media/platform/qcom/iris/iris_vidc.c +++ b/drivers/media/platform/qcom/iris/iris_vidc.c @@ -41,16 +41,20 @@ static void iris_v4l2_fh_deinit(struct iris_inst *inst,= struct file *filp) =20 static void iris_add_session(struct iris_inst *inst) { + const struct iris_platform_data *plat =3D inst->core->iris_platform_data; + u32 max_session_count =3D plat->max_session_count; struct iris_core *core =3D inst->core; struct iris_inst *iter; u32 count =3D 0; =20 + max_session_count *=3D max(plat->num_cores, 1); + mutex_lock(&core->lock); =20 list_for_each_entry(iter, &core->instances, list) count++; =20 - if (count < core->iris_platform_data->max_session_count) + if (count < max_session_count) list_add_tail(&inst->list, &core->instances); =20 mutex_unlock(&core->lock); diff --git a/drivers/media/platform/qcom/iris/iris_vpu3x.c b/drivers/media/= platform/qcom/iris/iris_vpu3x.c index bafa2ab645b1..dc491a5aecf5 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu3x.c +++ b/drivers/media/platform/qcom/iris/iris_vpu3x.c @@ -318,6 +318,67 @@ static void iris_vpu36_program_bootup_registers(struct= iris_core *core) writel(0x0, core->reg_base + CPU_CS_SCIACMDARG3); } =20 +static int iris_vpu36_check_core_load(struct iris_inst *inst, bool mbpf) +{ + const struct iris_platform_data *platform_data =3D inst->core->iris_platf= orm_data; + u32 max_load =3D mbpf ? platform_data->max_core_mbpf : platform_data->max= _core_mbps; + u32 max_session_cnt =3D platform_data->max_session_count; + u32 core0_session_cnt =3D 0, core1_session_cnt =3D 0; + u32 core0_load =3D 0, core1_load =3D 0; + bool select_core0, select_core1; + struct iris_inst *instance; + u32 load, new_load; + + inst->core_id =3D 0; + + list_for_each_entry(instance, &inst->core->instances, list) { + load =3D mbpf ? iris_get_mbpf(instance) : iris_get_mbps(instance); + + if (instance->core_id =3D=3D IRIS_VCODEC0) { + core0_load +=3D load; + core0_session_cnt++; + } else if (instance->core_id =3D=3D IRIS_VCODEC1) { + core1_load +=3D load; + core1_session_cnt++; + } + } + + new_load =3D mbpf ? iris_get_mbpf(inst) : iris_get_mbps(inst); + + select_core0 =3D core0_load + new_load <=3D max_load && core0_session_cnt= < max_session_cnt; + select_core1 =3D core1_load + new_load <=3D max_load && core1_session_cnt= < max_session_cnt; + + if (select_core0 && select_core1) + inst->core_id =3D (core0_load <=3D core1_load) ? IRIS_VCODEC0 : IRIS_VCO= DEC1; + else if (select_core0) + inst->core_id =3D IRIS_VCODEC0; + else if (select_core1) + inst->core_id =3D IRIS_VCODEC1; + else + return -ENOMEM; + + return 0; +} + +static u64 iris_vpu36_get_required_freq(struct iris_inst *inst) +{ + u64 vcodec0_freq =3D 0, vcodec1_freq =3D 0; + struct iris_core *core =3D inst->core; + struct iris_inst *instance; + + list_for_each_entry(instance, &core->instances, list) { + if (!instance->max_input_data_size) + continue; + + if (instance->core_id =3D=3D IRIS_VCODEC0) + vcodec0_freq +=3D instance->power.min_freq; + else + vcodec1_freq +=3D instance->power.min_freq; + } + + return max(vcodec0_freq, vcodec1_freq); +} + const struct vpu_ops iris_vpu3_ops =3D { .power_off_hw =3D iris_vpu3_power_off_hardware, .power_on_hw =3D iris_vpu_power_on_hw, @@ -354,4 +415,6 @@ const struct vpu_ops iris_vpu36_ops =3D { .program_bootup_registers =3D iris_vpu36_program_bootup_registers, .calc_freq =3D iris_vpu3x_vpu4x_calculate_frequency, .set_hwmode =3D iris_vpu36_set_hwmode, + .check_core_load =3D iris_vpu36_check_core_load, + .get_required_freq =3D iris_vpu36_get_required_freq, }; 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The major difference is that glymur integrates two codec cores (vcodec0 and vcodec1), while SM8550 has only one. Add glymur specific platform data, reusing SM8550 definitions wherever applicable. Reviewed-by: Vikash Garodia Reviewed-by: Dmitry Baryshkov Signed-off-by: Vishnu Reddy --- drivers/media/platform/qcom/iris/Makefile | 1 + .../platform/qcom/iris/iris_platform_common.h | 5 + .../platform/qcom/iris/iris_platform_glymur.c | 106 +++++++++++++++++= ++++ .../platform/qcom/iris/iris_platform_glymur.h | 17 ++++ .../media/platform/qcom/iris/iris_platform_vpu3x.c | 35 +++++++ drivers/media/platform/qcom/iris/iris_probe.c | 4 + drivers/media/platform/qcom/iris/iris_vpu3x.c | 3 + 7 files changed, 171 insertions(+) diff --git a/drivers/media/platform/qcom/iris/Makefile b/drivers/media/plat= form/qcom/iris/Makefile index 6deadd531c8e..6c45d4ad13a8 100644 --- a/drivers/media/platform/qcom/iris/Makefile +++ b/drivers/media/platform/qcom/iris/Makefile @@ -12,6 +12,7 @@ qcom-iris-objs +=3D iris_buffer.o \ iris_hfi_gen2_packet.o \ iris_hfi_gen2_response.o \ iris_hfi_queue.o \ + iris_platform_glymur.o \ iris_platform_vpu2.o \ iris_platform_vpu3x.o \ iris_power.o \ diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/driv= ers/media/platform/qcom/iris/iris_platform_common.h index 99f59b64f853..e182030bd537 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -39,6 +39,10 @@ struct iris_inst; #define MAX_HEVC_VBR_LAYER_HP_SLIDING_WINDOW 5 #define MAX_HIER_CODING_LAYER_GEN1 6 =20 +#define VIDEO_REGION_SECURE_FW_REGION_ID 0 +#define VIDEO_REGION_VM0_SECURE_NP_ID 1 +#define VIDEO_REGION_VM0_NONSECURE_NP_ID 5 + enum stage_type { STAGE_1 =3D 1, STAGE_2 =3D 2, @@ -53,6 +57,7 @@ enum pipe_type { extern const struct iris_firmware_data iris_hfi_gen1_data; extern const struct iris_firmware_data iris_hfi_gen2_data; =20 +extern const struct iris_platform_data glymur_data; extern const struct iris_platform_data qcs8300_data; extern const struct iris_platform_data sc7280_data; extern const struct iris_platform_data sm8250_data; diff --git a/drivers/media/platform/qcom/iris/iris_platform_glymur.c b/driv= ers/media/platform/qcom/iris/iris_platform_glymur.c new file mode 100644 index 000000000000..c42ac99870ed --- /dev/null +++ b/drivers/media/platform/qcom/iris/iris_platform_glymur.c @@ -0,0 +1,106 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include + +#include "iris_core.h" +#include "iris_platform_common.h" +#include "iris_platform_glymur.h" + +const struct iris_power_domain_data iris_glymur_ctrl_data =3D { + .pd_names =3D (const char *[]) { + "venus", + }, + .pd_cnt =3D 1, + .clk_names =3D (const char *[]) { + "core_iface", "core_freerun", "core", + }, + .clk_cnt =3D 3, +}; + +const struct iris_power_domain_data iris_glymur_vcodec_data[] =3D { + { + .pd_names =3D (const char *[]) { + "vcodec0", + }, + .pd_cnt =3D 1, + .clk_names =3D (const char *[]) { + "vcodec0_iface", "vcodec0_core_freerun", "vcodec0_core", + }, + .clk_cnt =3D 3, + }, + { + .pd_names =3D (const char *[]) { + "vcodec1", + }, + .pd_cnt =3D 1, + .clk_names =3D (const char *[]) { + "vcodec1_iface", "vcodec1_core_freerun", "vcodec1_core", + }, + .clk_cnt =3D 3, + }, +}; + +const char * const iris_glymur_clk_reset_table[] =3D { + "core_bus", + "vcodec0_bus", + "core", + "vcodec0_core", + "vcodec1_bus", + "vcodec1_core", +}; + +const char * const iris_glymur_opp_clk_table[] =3D { + "vcodec0_core", + "vcodec1_core", + "core", + NULL, +}; + +const struct tz_cp_config iris_glymur_tz_cp_config[] =3D { + { + .cp_start =3D VIDEO_REGION_SECURE_FW_REGION_ID, + .cp_size =3D 0, + .cp_nonpixel_start =3D 0, + .cp_nonpixel_size =3D 0x1000000, + }, + { + .cp_start =3D VIDEO_REGION_VM0_SECURE_NP_ID, + .cp_size =3D 0, + .cp_nonpixel_start =3D 0x1000000, + .cp_nonpixel_size =3D 0x24800000, + }, + { + .cp_start =3D VIDEO_REGION_VM0_NONSECURE_NP_ID, + .cp_size =3D 0, + .cp_nonpixel_start =3D 0x25800000, + .cp_nonpixel_size =3D 0xda600000, + }, +}; + +int iris_glymur_init_cb_devs(struct iris_core *core) +{ + u64 dma_mask =3D core->iris_platform_data->dma_mask; + const u32 fw_fid =3D IOMMU_FID_IRIS_FIRMWARE; + struct device *dev; + + dev =3D iris_vpu_bus_create_device(core->dev, "iris-firmware", dma_mask, = &fw_fid); + if (IS_ERR(dev)) + return PTR_ERR(dev); + + if (device_iommu_mapped(dev)) + core->fw_dev =3D dev; + else + device_unregister(dev); + + return 0; +} + +void iris_glymur_deinit_cb_devs(struct iris_core *core) +{ + if (core->fw_dev) + device_unregister(core->fw_dev); +} diff --git a/drivers/media/platform/qcom/iris/iris_platform_glymur.h b/driv= ers/media/platform/qcom/iris/iris_platform_glymur.h new file mode 100644 index 000000000000..1dae5764cb8c --- /dev/null +++ b/drivers/media/platform/qcom/iris/iris_platform_glymur.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef __IRIS_PLATFORM_GLYMUR_H__ +#define __IRIS_PLATFORM_GLYMUR_H__ + +extern const struct iris_power_domain_data iris_glymur_ctrl_data; +extern const struct iris_power_domain_data iris_glymur_vcodec_data[2]; +extern const char * const iris_glymur_clk_reset_table[6]; +extern const char * const iris_glymur_opp_clk_table[4]; +extern const struct tz_cp_config iris_glymur_tz_cp_config[3]; +int iris_glymur_init_cb_devs(struct iris_core *core); +void iris_glymur_deinit_cb_devs(struct iris_core *core); + +#endif /* __IRIS_PLATFORM_GLYMUR_H__ */ diff --git a/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c b/drive= rs/media/platform/qcom/iris/iris_platform_vpu3x.c index 72dd23dbe02a..4049e134c3f0 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c +++ b/drivers/media/platform/qcom/iris/iris_platform_vpu3x.c @@ -12,6 +12,7 @@ #include "iris_vpu_buffer.h" #include "iris_vpu_common.h" =20 +#include "iris_platform_glymur.h" #include "iris_platform_qcs8300.h" #include "iris_platform_sm8550.h" #include "iris_platform_sm8650.h" @@ -48,6 +49,12 @@ static const struct iris_firmware_desc iris_vpu35_p4_gen= 2_desc =3D { .fwname =3D "qcom/vpu/vpu35_p4.mbn", }; =20 +static const struct iris_firmware_desc iris_vpu36_p4_s7_gen2_desc =3D { + .firmware_data =3D &iris_hfi_gen2_data, + .get_vpu_buffer_size =3D iris_vpu_buf_size, + .fwname =3D "qcom/vpu/vpu36_p4_s7.mbn", +}; + static const u32 iris_fmts_vpu3x_dec[] =3D { [IRIS_FMT_H264] =3D V4L2_PIX_FMT_H264, [IRIS_FMT_HEVC] =3D V4L2_PIX_FMT_HEVC, @@ -83,6 +90,34 @@ static const struct tz_cp_config tz_cp_config_vpu3[] =3D= { }, }; =20 +const struct iris_platform_data glymur_data =3D { + .firmware_desc =3D &iris_vpu36_p4_s7_gen2_desc, + .vpu_ops =3D &iris_vpu36_ops, + .icc_tbl =3D iris_icc_info_vpu3x, + .icc_tbl_size =3D ARRAY_SIZE(iris_icc_info_vpu3x), + .clk_rst_tbl =3D iris_glymur_clk_reset_table, + .clk_rst_tbl_size =3D ARRAY_SIZE(iris_glymur_clk_reset_table), + .bw_tbl_dec =3D iris_bw_table_dec_vpu3x, + .bw_tbl_dec_size =3D ARRAY_SIZE(iris_bw_table_dec_vpu3x), + .ctrl_data =3D &iris_glymur_ctrl_data, + .vcodec_data =3D iris_glymur_vcodec_data, + .opp_pd_tbl =3D iris_opp_pd_table_vpu3x, + .opp_pd_tbl_size =3D ARRAY_SIZE(iris_opp_pd_table_vpu3x), + .opp_clk_tbl =3D iris_glymur_opp_clk_table, + /* Upper bound of DMA address range */ + .dma_mask =3D 0xffe00000 - 1, + .inst_iris_fmts =3D iris_fmts_vpu3x_dec, + .inst_iris_fmts_size =3D ARRAY_SIZE(iris_fmts_vpu3x_dec), + .inst_caps =3D &platform_inst_cap_sm8550, + .tz_cp_config_data =3D iris_glymur_tz_cp_config, + .tz_cp_config_data_size =3D ARRAY_SIZE(iris_glymur_tz_cp_config), + .num_vpp_pipe =3D 4, + .max_session_count =3D 16, + .num_cores =3D 2, + .max_core_mbpf =3D NUM_MBS_8K * 2, + .max_core_mbps =3D ((8192 * 4320) / 256) * 60, +}; + /* * Shares most of SM8550 data except: * - inst_caps to platform_inst_cap_qcs8300 diff --git a/drivers/media/platform/qcom/iris/iris_probe.c b/drivers/media/= platform/qcom/iris/iris_probe.c index 1e362570bb15..3537cf283f14 100644 --- a/drivers/media/platform/qcom/iris/iris_probe.c +++ b/drivers/media/platform/qcom/iris/iris_probe.c @@ -468,6 +468,10 @@ static const struct dev_pm_ops iris_pm_ops =3D { }; =20 static const struct of_device_id iris_dt_match[] =3D { + { + .compatible =3D "qcom,glymur-iris", + .data =3D &glymur_data, + }, { .compatible =3D "qcom,qcs8300-iris", .data =3D &qcs8300_data, diff --git a/drivers/media/platform/qcom/iris/iris_vpu3x.c b/drivers/media/= platform/qcom/iris/iris_vpu3x.c index dc491a5aecf5..87a0a2546284 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu3x.c +++ b/drivers/media/platform/qcom/iris/iris_vpu3x.c @@ -8,6 +8,7 @@ #include =20 #include "iris_instance.h" +#include "iris_platform_glymur.h" #include "iris_vpu_common.h" #include "iris_vpu_register_defines.h" =20 @@ -415,6 +416,8 @@ const struct vpu_ops iris_vpu36_ops =3D { .program_bootup_registers =3D iris_vpu36_program_bootup_registers, .calc_freq =3D iris_vpu3x_vpu4x_calculate_frequency, .set_hwmode =3D iris_vpu36_set_hwmode, + .init_cb_devs =3D iris_glymur_init_cb_devs, + .deinit_cb_devs =3D iris_glymur_deinit_cb_devs, .check_core_load =3D iris_vpu36_check_core_load, .get_required_freq =3D iris_vpu36_get_required_freq, }; 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Reviewed-by: Vikash Garodia Reviewed-by: Dmitry Baryshkov Signed-off-by: Vishnu Reddy --- arch/arm64/boot/dts/qcom/glymur.dtsi | 118 +++++++++++++++++++++++++++++++= ++++ 1 file changed, 118 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qco= m/glymur.dtsi index 20b49af7298e..42bcd03c4d3e 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -4788,6 +4789,123 @@ mdss_dp3_out: endpoint { }; }; =20 + iris: video-codec@aa00000 { + compatible =3D "qcom,glymur-iris"; + reg =3D <0x0 0xaa00000 0x0 0xf0000>; + + clocks =3D <&gcc GCC_VIDEO_AXI0C_CLK>, + <&videocc VIDEO_CC_MVS0C_CLK>, + <&videocc VIDEO_CC_MVS0_CLK>, + <&gcc GCC_VIDEO_AXI0_CLK>, + <&videocc VIDEO_CC_MVS0C_FREERUN_CLK>, + <&videocc VIDEO_CC_MVS0_FREERUN_CLK>, + <&gcc GCC_VIDEO_AXI1_CLK>, + <&videocc VIDEO_CC_MVS1_CLK>, + <&videocc VIDEO_CC_MVS1_FREERUN_CLK>; + clock-names =3D "core_iface", + "core", + "vcodec0_core", + "vcodec0_iface", + "core_freerun", + "vcodec0_core_freerun", + "vcodec1_iface", + "vcodec1_core", + "vcodec1_core_freerun"; + + dma-coherent; + + interconnects =3D <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mmss_noc MASTER_VIDEO QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "cpu-cfg", + "video-mem"; + + interrupts =3D ; + + iommus =3D <&apps_smmu 0x1940 0x0>, + <&apps_smmu 0x1943 0x0>, + <&apps_smmu 0x1944 0x0>, + <&apps_smmu 0x19e0 0x0>; + + iommu-map =3D ; + + memory-region =3D <&video_mem>; + + operating-points-v2 =3D <&iris_opp_table>; + + power-domains =3D <&videocc VIDEO_CC_MVS0C_GDSC>, + <&videocc VIDEO_CC_MVS0_GDSC>, + <&rpmhpd RPMHPD_MXC>, + <&rpmhpd RPMHPD_MMCX>, + <&videocc VIDEO_CC_MVS1_GDSC>; + power-domain-names =3D "venus", + "vcodec0", + "mxc", + "mmcx", + "vcodec1"; + + resets =3D <&gcc GCC_VIDEO_AXI0C_CLK_ARES>, + <&gcc GCC_VIDEO_AXI0_CLK_ARES>, + <&videocc VIDEO_CC_MVS0C_FREERUN_CLK_ARES>, + <&videocc VIDEO_CC_MVS0_FREERUN_CLK_ARES>, + <&gcc GCC_VIDEO_AXI1_CLK_ARES>, + <&videocc VIDEO_CC_MVS1_FREERUN_CLK_ARES>; + reset-names =3D "core_bus", + "vcodec0_bus", + "core", + "vcodec0_core", + "vcodec1_bus", + "vcodec1_core"; + + /* + * IRIS firmware is signed by vendors, only + * enable on boards where the proper signed firmware + * is available. + */ + status =3D "disabled"; + + iris_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-240000000 { + opp-hz =3D /bits/ 64 <240000000 240000000 360000000>; + required-opps =3D <&rpmhpd_opp_svs>, + <&rpmhpd_opp_low_svs>; + }; + + opp-338000000 { + opp-hz =3D /bits/ 64 <338000000 338000000 507000000>; + required-opps =3D <&rpmhpd_opp_svs>, + <&rpmhpd_opp_svs>; + }; + + opp-366000000 { + opp-hz =3D /bits/ 64 <366000000 366000000 549000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>, + <&rpmhpd_opp_svs_l1>; + }; + + opp-444000000 { + opp-hz =3D /bits/ 64 <444000000 444000000 666000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>, + <&rpmhpd_opp_nom>; + }; + + opp-533333334 { + opp-hz =3D /bits/ 64 <533333334 533333334 800000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>, + <&rpmhpd_opp_turbo>; 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Reviewed-by: Vikash Garodia Reviewed-by: Dmitry Baryshkov Signed-off-by: Vishnu Reddy --- arch/arm64/boot/dts/qcom/glymur-crd.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dts b/arch/arm64/boot/dts/= qcom/glymur-crd.dts index c98dfb3941fa..9445badeb18b 100644 --- a/arch/arm64/boot/dts/qcom/glymur-crd.dts +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dts @@ -198,6 +198,12 @@ ptn3222_1: redriver@47 { }; }; =20 +&iris { + firmware-name =3D "qcom/vpu/vpu36_p4_s7.mbn"; + + status =3D "okay"; +}; + &mdss { status =3D "okay"; }; --=20 2.34.1