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AFNElJ/TFN4ljvYzoHeidcJvNUF47CFpsm8WdBwnvLaynXP5UYwzd0n4Ls0/zbAIpfM+K6Eti9mp6E9CW3HRhjY=@vger.kernel.org X-Gm-Message-State: AOJu0YyeQfU8yjguC0Ac2dMOHoLszH7lk8/vd7s8zlbaW4FP5nyuqC1s zXZ1EITRZwn2z+TYXCCw3VEPhQkJrHXA/b8mc4cMLCuSBSLURhD05topnfWaPw384+cP4kt0akE JUgxDMg== X-Received: from pfbfk4.prod.google.com ([2002:a05:6a00:3a84:b0:842:4def:be29]) (user=ctshao job=prod-delivery.src-stubby-dispatcher) by 2002:a05:6a00:b806:b0:842:6a97:52f3 with SMTP id d2e1a72fcca58-842b0e1c969mr23556939b3a.7.1781041849699; Tue, 09 Jun 2026 14:50:49 -0700 (PDT) Date: Tue, 9 Jun 2026 14:50:40 -0700 In-Reply-To: <20260609215046.2391903-1-ctshao@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20260609215046.2391903-1-ctshao@google.com> X-Mailer: git-send-email 2.54.0.1099.g489fc7bff1-goog Message-ID: <20260609215046.2391903-2-ctshao@google.com> Subject: [PATCH v1 1/6] perf vendor events intel: Update arrowlake events from 1.17 to 1.19 From: Chun-Tse Shao To: peterz@infradead.org, mingo@redhat.com, acme@kernel.org, namhyung@kernel.org Cc: alexander.shishkin@linux.intel.com, jolsa@kernel.org, irogers@google.com, adrian.hunter@intel.com, james.clark@linaro.org, afaerber@suse.de, mani@kernel.org, dapeng1.mi@linux.intel.com, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-actions@lists.infradead.org, Chun-Tse Shao Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The updated events were published in: https://github.com/intel/perfmon/commit/b84e75626ae78558b8f526a276e4597c5ca= 6c429 Signed-off-by: Chun-Tse Shao --- .../pmu-events/arch/x86/arrowlake/cache.json | 30 +++- .../arch/x86/arrowlake/floating-point.json | 45 ++++++ .../pmu-events/arch/x86/arrowlake/memory.json | 18 +++ .../arch/x86/arrowlake/pipeline.json | 129 +++++++++++++++++- tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +- 5 files changed, 217 insertions(+), 7 deletions(-) diff --git a/tools/perf/pmu-events/arch/x86/arrowlake/cache.json b/tools/pe= rf/pmu-events/arch/x86/arrowlake/cache.json index fe6b9ad68f87..142f62c59531 100644 --- a/tools/perf/pmu-events/arch/x86/arrowlake/cache.json +++ b/tools/perf/pmu-events/arch/x86/arrowlake/cache.json @@ -1,6 +1,6 @@ [ { - "BriefDescription": "Counts the number of request that were not ac= cepted into the L2Q because the L2Q is FULL.", + "BriefDescription": "Counts the number of requests that were not a= ccepted into the L2Q because the L2Q is FULL.", "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x31", "EventName": "CORE_REJECT_L2Q.ANY", @@ -8,6 +8,15 @@ "SampleAfterValue": "1000003", "Unit": "cpu_atom" }, + { + "BriefDescription": "Counts the number of requests that were not a= ccepted into the L2Q because the L2Q is FULL.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0x31", + "EventName": "CORE_REJECT_L2Q.ANY", + "PublicDescription": "Counts the number of (demand and L1 prefetch= ers) core requests rejected by the L2Q due to a full or nearly full w condi= tion which likely indicates back pressure from L2Q. It also counts request= s that would have gone directly to the XQ, but are rejected due to a full o= r nearly full condition, indicating back pressure from the IDI link. The L= 2Q may also reject transactions from a core to insure fairness between cor= es, or to delay a cores dirty eviction when the address conflicts incoming = external snoops. (Note that L2 prefetcher requests that are dropped are no= t counted by this event.) Counts on a per core basis.", + "SampleAfterValue": "200003", + "Unit": "cpu_lowpower" + }, { "BriefDescription": "Counts the number of L1D cacheline (dirty) ev= ictions caused by load misses, stores, and prefetches.", "Counter": "0,1,2,3,4,5,6,7", @@ -310,6 +319,15 @@ "SampleAfterValue": "1000003", "Unit": "cpu_atom" }, + { + "BriefDescription": "Counts the number of demand and prefetch tran= sactions that the External Queue (XQ) rejects due to a full or near full co= ndition.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0x30", + "EventName": "L2_REJECT_XQ.ANY", + "PublicDescription": "Counts the number of demand and prefetch tra= nsactions that the External Queue (XQ) rejects due to a full or near full c= ondition which likely indicates back pressure from the IDI link. The XQ ma= y reject transactions from the L2Q (non-cacheable requests), BBL (L2 misses= ) and WOB (L2 write-back victims).", + "SampleAfterValue": "200003", + "Unit": "cpu_lowpower" + }, { "BriefDescription": "Counts the number of L2 Cache Accesses Counts= the total number of L2 Cache Accesses - sum of hits, misses, rejects fron= t door requests for CRd/DRd/RFO/ItoM/L2 Prefetches only, per core event", "Counter": "0,1,2,3,4,5,6,7", @@ -1382,6 +1400,16 @@ "UMask": "0x83", "Unit": "cpu_atom" }, + { + "BriefDescription": "Counts the number of memory uops retired. A = single uop that performs both a load AND a store will be counted as 1, not = 2 (e.g. ADD [mem], CONST)", + "Counter": "0,1,2,3,4,5,6,7", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_UOPS_RETIRED.ALL", + "SampleAfterValue": "200003", + "UMask": "0x83", + "Unit": "cpu_lowpower" + }, { "BriefDescription": "Counts the number of load uops retired.", "Counter": "0,1,2,3,4,5,6,7", diff --git a/tools/perf/pmu-events/arch/x86/arrowlake/floating-point.json b= /tools/perf/pmu-events/arch/x86/arrowlake/floating-point.json index c54fc201a6ca..8dc3a11350c5 100644 --- a/tools/perf/pmu-events/arch/x86/arrowlake/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/arrowlake/floating-point.json @@ -510,6 +510,15 @@ "UMask": "0x1f", "Unit": "cpu_atom" }, + { + "BriefDescription": "Counts the number of uops executed on all flo= ating point ports.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xb2", + "EventName": "FP_VINT_UOPS_EXECUTED.ALL", + "SampleAfterValue": "1000003", + "UMask": "0xf", + "Unit": "cpu_lowpower" + }, { "BriefDescription": "Counts the number of uops executed on floatin= g point and vector integer port 0.", "Counter": "0,1,2,3,4,5,6,7", @@ -519,6 +528,15 @@ "UMask": "0x2", "Unit": "cpu_atom" }, + { + "BriefDescription": "Counts the number of uops executed on floatin= g point and vector integer port 0.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xb2", + "EventName": "FP_VINT_UOPS_EXECUTED.P0", + "SampleAfterValue": "1000003", + "UMask": "0x2", + "Unit": "cpu_lowpower" + }, { "BriefDescription": "Counts the number of uops executed on floatin= g point and vector integer port 1.", "Counter": "0,1,2,3,4,5,6,7", @@ -528,6 +546,15 @@ "UMask": "0x4", "Unit": "cpu_atom" }, + { + "BriefDescription": "Counts the number of uops executed on floatin= g point and vector integer port 1.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xb2", + "EventName": "FP_VINT_UOPS_EXECUTED.P1", + "SampleAfterValue": "1000003", + "UMask": "0x4", + "Unit": "cpu_lowpower" + }, { "BriefDescription": "Counts the number of uops executed on floatin= g point and vector integer port 2.", "Counter": "0,1,2,3,4,5,6,7", @@ -537,6 +564,15 @@ "UMask": "0x8", "Unit": "cpu_atom" }, + { + "BriefDescription": "Counts the number of uops executed on floatin= g point and vector integer port 2.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xb2", + "EventName": "FP_VINT_UOPS_EXECUTED.P2", + "SampleAfterValue": "1000003", + "UMask": "0x8", + "Unit": "cpu_lowpower" + }, { "BriefDescription": "Counts the number of uops executed on floatin= g point and vector integer port 3.", "Counter": "0,1,2,3,4,5,6,7", @@ -555,6 +591,15 @@ "UMask": "0x1e", "Unit": "cpu_atom" }, + { + "BriefDescription": "Counts the number of uops executed on floatin= g point and vector integer port 0, 1, 2.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xb2", + "EventName": "FP_VINT_UOPS_EXECUTED.PRIMARY", + "SampleAfterValue": "1000003", + "UMask": "0xe", + "Unit": "cpu_lowpower" + }, { "BriefDescription": "Counts the number of uops executed on floatin= g point and vector integer store data port.", "Counter": "0,1,2,3,4,5,6,7", diff --git a/tools/perf/pmu-events/arch/x86/arrowlake/memory.json b/tools/p= erf/pmu-events/arch/x86/arrowlake/memory.json index 05cc46518232..44922186c2b0 100644 --- a/tools/perf/pmu-events/arch/x86/arrowlake/memory.json +++ b/tools/perf/pmu-events/arch/x86/arrowlake/memory.json @@ -173,6 +173,15 @@ "UMask": "0x2", "Unit": "cpu_atom" }, + { + "BriefDescription": "Counts the number of cycles that the head (ol= dest load) of the load buffer is stalled due to request buffers full or loc= k in progress.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0x05", + "EventName": "LD_HEAD.WCB_FULL", + "SampleAfterValue": "1000003", + "UMask": "0x2", + "Unit": "cpu_lowpower" + }, { "BriefDescription": "Counts the number of cycles that the head (ol= dest load) of the load buffer and retirement are both stalled due to reques= t buffers full or lock in progress.", "Counter": "0,1,2,3,4,5,6,7", @@ -182,6 +191,15 @@ "UMask": "0x82", "Unit": "cpu_atom" }, + { + "BriefDescription": "Counts the number of cycles that the head (ol= dest load) of the load buffer and retirement are both stalled due to reques= t buffers full or lock in progress.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0x05", + "EventName": "LD_HEAD.WCB_FULL_AT_RET", + "SampleAfterValue": "1000003", + "UMask": "0x82", + "Unit": "cpu_lowpower" + }, { "BriefDescription": "Counts the number of memory ordering machine = clears triggered due to a snoop from an external agent. Does not count inte= rnally generated machine clears such as those due to disambiguations.", "Counter": "0,1,2,3,4,5,6,7", diff --git a/tools/perf/pmu-events/arch/x86/arrowlake/pipeline.json b/tools= /perf/pmu-events/arch/x86/arrowlake/pipeline.json index a0fd63cace22..bdfee0347cc5 100644 --- a/tools/perf/pmu-events/arch/x86/arrowlake/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/arrowlake/pipeline.json @@ -209,7 +209,6 @@ "EventName": "BR_INST_RETIRED.COND_TAKEN_FWD", "PublicDescription": "Counts taken forward conditional branch inst= ructions retired. Available PDIST counters: 0,1", "SampleAfterValue": "400009", - "UMask": "0x102", "Unit": "cpu_core" }, { @@ -608,7 +607,7 @@ "EventName": "BR_MISP_RETIRED.COND_TAKEN_BWD_COST", "PublicDescription": "number of branch instructions retired that w= ere mispredicted and taken backward. This precise event may be used to get = the misprediction cost via the Retire_Latency field of PEBS. It fires on th= e instruction that immediately follows the mispredicted branch. Available P= DIST counters: 0,1", "SampleAfterValue": "400009", - "UMask": "0x8001", + "UMask": "0x41", "Unit": "cpu_core" }, { @@ -637,7 +636,7 @@ "EventName": "BR_MISP_RETIRED.COND_TAKEN_FWD_COST", "PublicDescription": "number of branch instructions retired that w= ere mispredicted and taken forward. This precise event may be used to get t= he misprediction cost via the Retire_Latency field of PEBS. It fires on the= instruction that immediately follows the mispredicted branch. Available PD= IST counters: 0,1", "SampleAfterValue": "400009", - "UMask": "0x8002", + "UMask": "0x140", "Unit": "cpu_core" }, { @@ -773,11 +772,11 @@ "Unit": "cpu_core" }, { - "BriefDescription": "This event counts the number of mispredicted = ret instructions retired. Non PEBS", + "BriefDescription": "This event counts the number of mispredicted = ret instructions retired.", "Counter": "0,1,2,3,4,5,6,7,8,9", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.RET", - "PublicDescription": "This is a non-precise version (that is, does= not use PEBS) of the event that counts mispredicted return instructions re= tired. Available PDIST counters: 0,1", + "PublicDescription": "This event counts the number of mispredicted= ret instructions retired. Available PDIST counters: 0,1", "SampleAfterValue": "100007", "UMask": "0x8", "Unit": "cpu_core" @@ -1326,6 +1325,15 @@ "UMask": "0xff", "Unit": "cpu_atom" }, + { + "BriefDescription": "Counts the number of uops executed on all Int= eger ports.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xb3", + "EventName": "INT_UOPS_EXECUTED.ALL", + "SampleAfterValue": "1000003", + "UMask": "0xff", + "Unit": "cpu_lowpower" + }, { "BriefDescription": "Counts the number of uops executed on a load = port.", "Counter": "0,1,2,3,4,5,6,7", @@ -1336,6 +1344,16 @@ "UMask": "0x1", "Unit": "cpu_atom" }, + { + "BriefDescription": "Counts the number of uops executed on a load = port.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xb3", + "EventName": "INT_UOPS_EXECUTED.LD", + "PublicDescription": "Counts the number of uops executed on a load= port. This event counts for integer uops even if the destination is FP/ve= ctor", + "SampleAfterValue": "1000003", + "UMask": "0x1", + "Unit": "cpu_lowpower" + }, { "BriefDescription": "Counts the number of uops executed on integer= port 0.", "Counter": "0,1,2,3,4,5,6,7", @@ -1345,6 +1363,15 @@ "UMask": "0x8", "Unit": "cpu_atom" }, + { + "BriefDescription": "Counts the number of uops executed on integer= port 0.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xb3", + "EventName": "INT_UOPS_EXECUTED.P0", + "SampleAfterValue": "1000003", + "UMask": "0x8", + "Unit": "cpu_lowpower" + }, { "BriefDescription": "Counts the number of uops executed on integer= port 1.", "Counter": "0,1,2,3,4,5,6,7", @@ -1354,6 +1381,15 @@ "UMask": "0x10", "Unit": "cpu_atom" }, + { + "BriefDescription": "Counts the number of uops executed on integer= port 1.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xb3", + "EventName": "INT_UOPS_EXECUTED.P1", + "SampleAfterValue": "1000003", + "UMask": "0x10", + "Unit": "cpu_lowpower" + }, { "BriefDescription": "Counts the number of uops executed on integer= port 2.", "Counter": "0,1,2,3,4,5,6,7", @@ -1363,6 +1399,15 @@ "UMask": "0x20", "Unit": "cpu_atom" }, + { + "BriefDescription": "Counts the number of uops executed on integer= port 2.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xb3", + "EventName": "INT_UOPS_EXECUTED.P2", + "SampleAfterValue": "1000003", + "UMask": "0x20", + "Unit": "cpu_lowpower" + }, { "BriefDescription": "Counts the number of uops executed on integer= port 3.", "Counter": "0,1,2,3,4,5,6,7", @@ -1372,6 +1417,15 @@ "UMask": "0x40", "Unit": "cpu_atom" }, + { + "BriefDescription": "Counts the number of uops executed on integer= port 3.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xb3", + "EventName": "INT_UOPS_EXECUTED.P3", + "SampleAfterValue": "1000003", + "UMask": "0x40", + "Unit": "cpu_lowpower" + }, { "BriefDescription": "Counts the number of uops executed on integer= port 0,1, 2, 3.", "Counter": "0,1,2,3,4,5,6,7", @@ -1381,6 +1435,15 @@ "UMask": "0x78", "Unit": "cpu_atom" }, + { + "BriefDescription": "Counts the number of uops executed on integer= port 0,1, 2, 3.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xb3", + "EventName": "INT_UOPS_EXECUTED.PRIMARY", + "SampleAfterValue": "1000003", + "UMask": "0x78", + "Unit": "cpu_lowpower" + }, { "BriefDescription": "Counts the number of uops executed on a Store= address port.", "Counter": "0,1,2,3,4,5,6,7", @@ -1391,6 +1454,16 @@ "UMask": "0x2", "Unit": "cpu_atom" }, + { + "BriefDescription": "Counts the number of uops executed on a Store= address port.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xb3", + "EventName": "INT_UOPS_EXECUTED.STA", + "PublicDescription": "Counts the number of uops executed on a Stor= e address port. This event counts integer uops even if the data source is F= P/vector", + "SampleAfterValue": "1000003", + "UMask": "0x2", + "Unit": "cpu_lowpower" + }, { "BriefDescription": "Counts the number of uops executed on an inte= ger store data and jump port.", "Counter": "0,1,2,3,4,5,6,7", @@ -1400,6 +1473,15 @@ "UMask": "0x4", "Unit": "cpu_atom" }, + { + "BriefDescription": "Counts the number of uops executed on an inte= ger store data and jump port.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xb3", + "EventName": "INT_UOPS_EXECUTED.STD_JMP", + "SampleAfterValue": "1000003", + "UMask": "0x4", + "Unit": "cpu_lowpower" + }, { "BriefDescription": "Number of vector integer instructions retired= of 128-bit vector-width.", "Counter": "0,1,2,3,4,5,6,7,8,9", @@ -1691,6 +1773,15 @@ "UMask": "0x88", "Unit": "cpu_atom" }, + { + "BriefDescription": "Counts the number of machine clears that flus= h the pipeline and restart the machine without the use of microcode.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc3", + "EventName": "MACHINE_CLEARS.FAST", + "SampleAfterValue": "20003", + "UMask": "0x10", + "Unit": "cpu_lowpower" + }, { "BriefDescription": "Counts number of virtual trap actually taken = (e.g. highest priority event during retirement). It can count virtual trap = from FPC port 0 or port 1 (x87/SSE) equally in a single counter.", "Counter": "0,1,2,3,4,5,6,7", @@ -1700,6 +1791,15 @@ "UMask": "0x40", "Unit": "cpu_atom" }, + { + "BriefDescription": "Counts the number of virtual traps taken.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc3", + "EventName": "MACHINE_CLEARS.FPC_VIRTUAL_TRAP", + "SampleAfterValue": "20003", + "UMask": "0x40", + "Unit": "cpu_lowpower" + }, { "BriefDescription": "Counts the number of nukes due to memory rena= ming", "Counter": "0,1,2,3,4,5,6,7", @@ -2015,6 +2115,15 @@ "UMask": "0x8", "Unit": "cpu_atom" }, + { + "BriefDescription": "Counts the number of issue slots not consumed= due to a color request for an FCW or MXCSR control register when all 4 col= ors (copies) are already in use.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0x75", + "EventName": "SERIALIZATION.COLOR_STALLS", + "SampleAfterValue": "200003", + "UMask": "0x8", + "Unit": "cpu_lowpower" + }, { "BriefDescription": "Counts the number of issue slots where no uop= could issue due to an IQ scoreboard that stalls allocation until a specifi= ed older uop retires or (in the case of jump scoreboard) executes. Commonly= executed instructions with IQ scoreboards include LFENCE and MFENCE.", "Counter": "0,1,2,3,4,5,6,7", @@ -2034,6 +2143,16 @@ "UMask": "0x2", "Unit": "cpu_atom" }, + { + "BriefDescription": "Counts the number of issue slots not consumed= by the backend due to a micro-sequencer (MS) scoreboard, which stalls the = front-end from issuing from the UROM until a specified older uop retires.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0x75", + "EventName": "SERIALIZATION.NON_C01_MS_SCB", + "PublicDescription": "Counts the number of issue slots not consume= d by the backend due to a micro-sequencer (MS) scoreboard, which stalls the= front-end from issuing from the UROM until a specified older uop retires. = The most commonly executed instruction with an MS scoreboard is PAUSE.", + "SampleAfterValue": "200003", + "UMask": "0x2", + "Unit": "cpu_lowpower" + }, { "BriefDescription": "This event counts a subset of the Topdown Slo= ts event that were not consumed by the back-end pipeline due to lack of bac= k-end resources, as a result of memory subsystem delays, execution units li= mitations, or other conditions.", "Counter": "0,1,2,3,4,5,6,7,8,9", diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-ev= ents/arch/x86/mapfile.csv index 50a403b429b1..613881d04a9a 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -1,7 +1,7 @@ Family-model,Version,Filename,EventType GenuineIntel-6-(97|9A|B7|BA|BF),v1.39,alderlake,core GenuineIntel-6-BE,v1.39,alderlaken,core -GenuineIntel-6-C[56],v1.17,arrowlake,core +GenuineIntel-6-C[56],v1.19,arrowlake,core GenuineIntel-6-(1C|26|27|35|36),v5,bonnell,core GenuineIntel-6-(3D|47),v30,broadwell,core GenuineIntel-6-56,v12,broadwellde,core --=20 2.54.0.1099.g489fc7bff1-goog From nobody Wed Jun 10 18:41:25 2026 Received: from mail-pl1-f202.google.com (mail-pl1-f202.google.com [209.85.214.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A53534071F2 for ; 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Tue, 09 Jun 2026 14:50:50 -0700 (PDT) Date: Tue, 9 Jun 2026 14:50:41 -0700 In-Reply-To: <20260609215046.2391903-1-ctshao@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20260609215046.2391903-1-ctshao@google.com> X-Mailer: git-send-email 2.54.0.1099.g489fc7bff1-goog Message-ID: <20260609215046.2391903-3-ctshao@google.com> Subject: [PATCH v1 2/6] perf vendor events intel: Update emeraldrapids events from 1.23 to 1.24 From: Chun-Tse Shao To: peterz@infradead.org, mingo@redhat.com, acme@kernel.org, namhyung@kernel.org Cc: alexander.shishkin@linux.intel.com, jolsa@kernel.org, irogers@google.com, adrian.hunter@intel.com, james.clark@linaro.org, afaerber@suse.de, mani@kernel.org, dapeng1.mi@linux.intel.com, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-actions@lists.infradead.org, Chun-Tse Shao Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The updated events were published in: https://github.com/intel/perfmon/commit/3f1d40d1953193e75c6b5a559638cf1f67b= acaed Signed-off-by: Chun-Tse Shao --- tools/perf/pmu-events/arch/x86/emeraldrapids/cache.json | 9 +++++++++ tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +- 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/tools/perf/pmu-events/arch/x86/emeraldrapids/cache.json b/tool= s/perf/pmu-events/arch/x86/emeraldrapids/cache.json index ff6071d7728e..a44e1f027c1d 100644 --- a/tools/perf/pmu-events/arch/x86/emeraldrapids/cache.json +++ b/tools/perf/pmu-events/arch/x86/emeraldrapids/cache.json @@ -368,6 +368,15 @@ "SampleAfterValue": "200003", "UMask": "0x40" }, + { + "BriefDescription": "Cycles when L1D is locked", + "Counter": "0,1,2,3", + "EventCode": "0x42", + "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION", + "PublicDescription": "This event counts the number of cycles when = the L1D is locked. It is a superset of the 0x1 mask (BUS_LOCK_CLOCKS.BUS_LO= CK_DURATION).", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, { "BriefDescription": "Core-originated cacheable requests that misse= d L3 (Except hardware prefetches to the L3)", "Counter": "0,1,2,3,4,5,6,7", diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-ev= ents/arch/x86/mapfile.csv index 613881d04a9a..0f39073805ba 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -9,7 +9,7 @@ GenuineIntel-6-4F,v23,broadwellx,core GenuineIntel-6-55-[56789ABCDEF],v1.25,cascadelakex,core GenuineIntel-6-DD,v1.02,clearwaterforest,core GenuineIntel-6-9[6C],v1.05,elkhartlake,core -GenuineIntel-6-CF,v1.23,emeraldrapids,core +GenuineIntel-6-CF,v1.24,emeraldrapids,core GenuineIntel-6-5[CF],v13,goldmont,core GenuineIntel-6-7A,v1.01,goldmontplus,core GenuineIntel-6-B6,v1.12,grandridge,core --=20 2.54.0.1099.g489fc7bff1-goog From nobody Wed Jun 10 18:41:25 2026 Received: from mail-pg1-f201.google.com (mail-pg1-f201.google.com [209.85.215.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BEEDB4ADD91 for ; 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Tue, 09 Jun 2026 14:50:51 -0700 (PDT) Date: Tue, 9 Jun 2026 14:50:42 -0700 In-Reply-To: <20260609215046.2391903-1-ctshao@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20260609215046.2391903-1-ctshao@google.com> X-Mailer: git-send-email 2.54.0.1099.g489fc7bff1-goog Message-ID: <20260609215046.2391903-4-ctshao@google.com> Subject: [PATCH v1 3/6] perf vendor events intel: Update graniterapids events from 1.18 to 1.19 From: Chun-Tse Shao To: peterz@infradead.org, mingo@redhat.com, acme@kernel.org, namhyung@kernel.org Cc: alexander.shishkin@linux.intel.com, jolsa@kernel.org, irogers@google.com, adrian.hunter@intel.com, james.clark@linaro.org, afaerber@suse.de, mani@kernel.org, dapeng1.mi@linux.intel.com, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-actions@lists.infradead.org, Chun-Tse Shao Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The updated events were published in: https://github.com/intel/perfmon/commit/875354c88686ef50387d9601f52354a6da8= f24cc Signed-off-by: Chun-Tse Shao --- .../arch/x86/graniterapids/uncore-interconnect.json | 10 ++++++++++ .../arch/x86/graniterapids/uncore-memory.json | 2 +- tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +- 3 files changed, 12 insertions(+), 2 deletions(-) diff --git a/tools/perf/pmu-events/arch/x86/graniterapids/uncore-interconne= ct.json b/tools/perf/pmu-events/arch/x86/graniterapids/uncore-interconnect.= json index 5eb1145f204f..9f0c4c7198b0 100644 --- a/tools/perf/pmu-events/arch/x86/graniterapids/uncore-interconnect.json +++ b/tools/perf/pmu-events/arch/x86/graniterapids/uncore-interconnect.json @@ -808,6 +808,16 @@ "PerPkg": "1", "Unit": "IRP" }, + { + "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Wr= ite Transactions as Secondary", + "Counter": "0,1,2,3", + "EventCode": "0x1E", + "EventName": "UNC_I_MISC0.2ND_WR_INSERT", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "IRP" + }, { "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Rejects", "Counter": "0,1,2,3", diff --git a/tools/perf/pmu-events/arch/x86/graniterapids/uncore-memory.jso= n b/tools/perf/pmu-events/arch/x86/graniterapids/uncore-memory.json index f559e27e2815..9cd2905726fd 100644 --- a/tools/perf/pmu-events/arch/x86/graniterapids/uncore-memory.json +++ b/tools/perf/pmu-events/arch/x86/graniterapids/uncore-memory.json @@ -539,7 +539,7 @@ "Unit": "IMC" }, { - "BriefDescription": "DRAM Precharge commands. : Precharge due to (= ?) : Counts the number of DRAM Precharge commands sent on this channel.", + "BriefDescription": "DRAM Precharge commands. : Precharge due to p= age table : Counts the number of DRAM Precharge commands sent on this chann= el.", "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_M_PRE_COUNT.PGT", diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-ev= ents/arch/x86/mapfile.csv index 0f39073805ba..b8ea72b99c52 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -13,7 +13,7 @@ GenuineIntel-6-CF,v1.24,emeraldrapids,core GenuineIntel-6-5[CF],v13,goldmont,core GenuineIntel-6-7A,v1.01,goldmontplus,core GenuineIntel-6-B6,v1.12,grandridge,core -GenuineIntel-6-A[DE],v1.18,graniterapids,core +GenuineIntel-6-A[DE],v1.19,graniterapids,core GenuineIntel-6-(3C|45|46),v36,haswell,core GenuineIntel-6-3F,v29,haswellx,core GenuineIntel-6-7[DE],v1.24,icelake,core --=20 2.54.0.1099.g489fc7bff1-goog From nobody Wed Jun 10 18:41:25 2026 Received: from mail-pf1-f201.google.com (mail-pf1-f201.google.com [209.85.210.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 54D1247F2D2 for ; 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Tue, 09 Jun 2026 14:50:53 -0700 (PDT) Date: Tue, 9 Jun 2026 14:50:43 -0700 In-Reply-To: <20260609215046.2391903-1-ctshao@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20260609215046.2391903-1-ctshao@google.com> X-Mailer: git-send-email 2.54.0.1099.g489fc7bff1-goog Message-ID: <20260609215046.2391903-5-ctshao@google.com> Subject: [PATCH v1 4/6] perf vendor events intel: Update lunarlake events from 1.22 to 1.25 From: Chun-Tse Shao To: peterz@infradead.org, mingo@redhat.com, acme@kernel.org, namhyung@kernel.org Cc: alexander.shishkin@linux.intel.com, jolsa@kernel.org, irogers@google.com, adrian.hunter@intel.com, james.clark@linaro.org, afaerber@suse.de, mani@kernel.org, dapeng1.mi@linux.intel.com, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-actions@lists.infradead.org, Chun-Tse Shao Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The updated events were published in: https://github.com/intel/perfmon/commit/5535a3e8cc14ae8ef58013cf3d8e9480018= b911a Signed-off-by: Chun-Tse Shao --- .../pmu-events/arch/x86/lunarlake/cache.json | 2 +- .../arch/x86/lunarlake/pipeline.json | 27 ++- .../arch/x86/lunarlake/uncore-memory.json | 208 +++++++++++++++++- tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +- 4 files changed, 228 insertions(+), 11 deletions(-) diff --git a/tools/perf/pmu-events/arch/x86/lunarlake/cache.json b/tools/pe= rf/pmu-events/arch/x86/lunarlake/cache.json index 92a3667b4520..5b350233a5e1 100644 --- a/tools/perf/pmu-events/arch/x86/lunarlake/cache.json +++ b/tools/perf/pmu-events/arch/x86/lunarlake/cache.json @@ -1,6 +1,6 @@ [ { - "BriefDescription": "Counts the number of request that were not ac= cepted into the L2Q because the L2Q is FULL.", + "BriefDescription": "Counts the number of requests that were not a= ccepted into the L2Q because the L2Q is FULL.", "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x31", "EventName": "CORE_REJECT_L2Q.ANY", diff --git a/tools/perf/pmu-events/arch/x86/lunarlake/pipeline.json b/tools= /perf/pmu-events/arch/x86/lunarlake/pipeline.json index d66eafccebbb..a7467b2f291d 100644 --- a/tools/perf/pmu-events/arch/x86/lunarlake/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/lunarlake/pipeline.json @@ -190,7 +190,6 @@ "EventName": "BR_INST_RETIRED.COND_TAKEN_FWD", "PublicDescription": "Counts taken forward conditional branch inst= ructions retired. Available PDIST counters: 0,1", "SampleAfterValue": "400009", - "UMask": "0x102", "Unit": "cpu_core" }, { @@ -324,6 +323,15 @@ "UMask": "0xdf", "Unit": "cpu_atom" }, + { + "BriefDescription": "Counts the number of taken branch instruction= s retired", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.TAKEN", + "SampleAfterValue": "200003", + "UMask": "0x80", + "Unit": "cpu_atom" + }, { "BriefDescription": "Counts the total number of mispredicted branc= h instructions retired for all branch types.", "Counter": "0,1,2,3,4,5,6,7", @@ -446,7 +454,7 @@ "EventName": "BR_MISP_RETIRED.COND_TAKEN_BWD_COST", "PublicDescription": "number of branch instructions retired that w= ere mispredicted and taken backward. This precise event may be used to get = the misprediction cost via the Retire_Latency field of PEBS. It fires on th= e instruction that immediately follows the mispredicted branch. Available P= DIST counters: 0,1", "SampleAfterValue": "400009", - "UMask": "0x8001", + "UMask": "0x41", "Unit": "cpu_core" }, { @@ -475,7 +483,7 @@ "EventName": "BR_MISP_RETIRED.COND_TAKEN_FWD_COST", "PublicDescription": "number of branch instructions retired that w= ere mispredicted and taken forward. This precise event may be used to get t= he misprediction cost via the Retire_Latency field of PEBS. It fires on the= instruction that immediately follows the mispredicted branch. Available PD= IST counters: 0,1", "SampleAfterValue": "400009", - "UMask": "0x8002", + "UMask": "0x140", "Unit": "cpu_core" }, { @@ -575,11 +583,11 @@ "Unit": "cpu_core" }, { - "BriefDescription": "This event counts the number of mispredicted = ret instructions retired. Non PEBS", + "BriefDescription": "This event counts the number of mispredicted = ret instructions retired.", "Counter": "0,1,2,3,4,5,6,7,8,9", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.RET", - "PublicDescription": "This is a non-precise version (that is, does= not use PEBS) of the event that counts mispredicted return instructions re= tired. Available PDIST counters: 0,1", + "PublicDescription": "This event counts the number of mispredicted= ret instructions retired. Available PDIST counters: 0,1", "SampleAfterValue": "100007", "UMask": "0x8", "Unit": "cpu_core" @@ -1373,6 +1381,15 @@ "UMask": "0x88", "Unit": "cpu_atom" }, + { + "BriefDescription": "Counts number of virtual trap actually taken = (e.g. highest priority event during retirement). It can count virtual trap = from FPC port 0 or port 1 (x87/SSE) equally in a single counter.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc3", + "EventName": "MACHINE_CLEARS.FPC_VIRTUAL_TRAP", + "SampleAfterValue": "20003", + "UMask": "0x40", + "Unit": "cpu_atom" + }, { "BriefDescription": "Counts the number of nukes due to memory rena= ming", "Counter": "0,1,2,3,4,5,6,7", diff --git a/tools/perf/pmu-events/arch/x86/lunarlake/uncore-memory.json b/= tools/perf/pmu-events/arch/x86/lunarlake/uncore-memory.json index 63c4aa2791e4..a1e79f06645a 100644 --- a/tools/perf/pmu-events/arch/x86/lunarlake/uncore-memory.json +++ b/tools/perf/pmu-events/arch/x86/lunarlake/uncore-memory.json @@ -1,6 +1,30 @@ [ { - "BriefDescription": "Read CAS command sent to DRAM", + "BriefDescription": "ACT command for a read request sent to DRAM.", + "Counter": "0,1,2,3,4", + "EventCode": "0x24", + "EventName": "UNC_M_ACT_COUNT_RD", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "ACT command sent to DRAM.", + "Counter": "0,1,2,3,4", + "EventCode": "0x26", + "EventName": "UNC_M_ACT_COUNT_TOTAL", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "ACT command for a write request sent to DRAM.= ", + "Counter": "0,1,2,3,4", + "EventCode": "0x25", + "EventName": "UNC_M_ACT_COUNT_WR", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "Read CAS command sent to DRAM.", "Counter": "0,1,2,3,4", "EventCode": "0x22", "EventName": "UNC_M_CAS_COUNT_RD", @@ -8,7 +32,7 @@ "Unit": "iMC" }, { - "BriefDescription": "Write CAS command sent to DRAM", + "BriefDescription": "Write CAS command sent to DRAM.", "Counter": "0,1,2,3,4", "EventCode": "0x23", "EventName": "UNC_M_CAS_COUNT_WR", @@ -16,7 +40,94 @@ "Unit": "iMC" }, { - "BriefDescription": "Any Rank at Hot state", + "BriefDescription": "Counting the number of clocks.", + "Counter": "0,1,2,3,4", + "EventCode": "0x01", + "EventName": "UNC_M_CLOCKTICKS", + "Experimental": "1", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "CKE in DRAM is low.", + "Counter": "0,1,2,3,4", + "EventCode": "0x29", + "EventName": "UNC_M_DRAM_CKE_OFF_CYCLES", + "Experimental": "1", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "Incoming read request page status is Page Emp= ty.", + "Counter": "0,1,2,3,4", + "EventCode": "0x1D", + "EventName": "UNC_M_DRAM_PAGE_EMPTY_RD", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "incoming read request page status is Page Em= pty", + "Unit": "iMC" + }, + { + "BriefDescription": "Incoming write request page status is Page Em= pty.", + "Counter": "0,1,2,3,4", + "EventCode": "0x20", + "EventName": "UNC_M_DRAM_PAGE_EMPTY_WR", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "incoming write request page status is Page E= mpty", + "Unit": "iMC" + }, + { + "BriefDescription": "Incoming read request page status is Page Hit= .", + "Counter": "0,1,2,3,4", + "EventCode": "0x1C", + "EventName": "UNC_M_DRAM_PAGE_HIT_RD", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "incoming read request page status is Page Hi= t", + "Unit": "iMC" + }, + { + "BriefDescription": "Incoming write request page status is Page Hi= t.", + "Counter": "0,1,2,3,4", + "EventCode": "0x1F", + "EventName": "UNC_M_DRAM_PAGE_HIT_WR", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "incoming write request page status is Page H= it", + "Unit": "iMC" + }, + { + "BriefDescription": "Incoming read request page status is Page Mis= s.", + "Counter": "0,1,2,3,4", + "EventCode": "0x1E", + "EventName": "UNC_M_DRAM_PAGE_MISS_RD", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "incoming read request page status is Page Mi= ss", + "Unit": "iMC" + }, + { + "BriefDescription": "Incoming write request page status is Page Mi= ss.", + "Counter": "0,1,2,3,4", + "EventCode": "0x21", + "EventName": "UNC_M_DRAM_PAGE_MISS_WR", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "incoming write request page status is Page M= iss", + "Unit": "iMC" + }, + { + "BriefDescription": "DRAM in Self-refresh (all channels).", + "Counter": "0,1,2,3,4", + "EventCode": "0x12", + "EventName": "UNC_M_DRAM_SELF_REFRESH", + "Experimental": "1", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "Any Rank at Hot state.", "Counter": "0,1,2,3,4", "EventCode": "0x19", "EventName": "UNC_M_DRAM_THERMAL_HOT", @@ -25,7 +136,7 @@ "Unit": "iMC" }, { - "BriefDescription": "Any Rank at Warm state", + "BriefDescription": "Any Rank at Warm state.", "Counter": "0,1,2,3,4", "EventCode": "0x1A", "EventName": "UNC_M_DRAM_THERMAL_WARM", @@ -33,6 +144,42 @@ "PerPkg": "1", "Unit": "iMC" }, + { + "BriefDescription": "PRE command sent to DRAM for a read/write req= uest.", + "Counter": "0,1,2,3,4", + "EventCode": "0x27", + "EventName": "UNC_M_PRE_COUNT_PAGE_MISS", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "Counts number of bytes read, in 32B chunk, pe= r DDR channel. Counter increments by 1 after receiving 32B chunk data.", + "Counter": "0,1,2,3,4", + "EventCode": "0x3A", + "EventName": "UNC_M_RD_DATA", + "PerPkg": "1", + "PublicDescription": "This counter counts number of bytes read, in= 32B chunk, per DDR channel. Counter increments by 1 after receiving 32B ch= unk data.", + "Unit": "iMC" + }, + { + "BriefDescription": "Number of VC0 read in channel0 - this event = can increment by more than 1 (per channel/sub-ch).", + "Counter": "0,1,2,3,4", + "EventCode": "0x13", + "EventName": "UNC_M_RD_OCCUPANCY_CH0", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "Number of VC0 read in channel0 - this event= can increment by more than 1 (per channel/sub-ch)", + "Unit": "iMC" + }, + { + "BriefDescription": "Number of VC0 read in channel1 - this event c= an increment by more than 1 (per channel/sub-ch).", + "Counter": "0,1,2,3,4", + "EventCode": "0x14", + "EventName": "UNC_M_RD_OCCUPANCY_CH1", + "Experimental": "1", + "PerPkg": "1", + "Unit": "iMC" + }, { "BriefDescription": "Total number of read and write byte transfers= to/from DRAM, in 32B chunk, per DDR channel. Counter increments by 1 after= sending or receiving 32B chunk data.", "Counter": "0,1,2,3,4", @@ -40,5 +187,58 @@ "EventName": "UNC_M_TOTAL_DATA", "PerPkg": "1", "Unit": "iMC" + }, + { + "BriefDescription": "Total number of requests entering MC, this is= the sum of all RD + WR requests for all VCs.", + "Counter": "0,1,2,3,4", + "EventCode": "0x39", + "EventName": "UNC_M_TOTAL_REQUESTS", + "Experimental": "1", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "Incoming VC0 read request.", + "Counter": "0,1,2,3,4", + "EventCode": "0x02", + "EventName": "UNC_M_VC0_REQUESTS_RD", + "Experimental": "1", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "Incoming VC0 write request.", + "Counter": "0,1,2,3,4", + "EventCode": "0x03", + "EventName": "UNC_M_VC0_REQUESTS_WR", + "Experimental": "1", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "Incoming VC1 read request.", + "Counter": "0,1,2,3,4", + "EventCode": "0x04", + "EventName": "UNC_M_VC1_REQUESTS_RD", + "Experimental": "1", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "Incoming VC1 write request.", + "Counter": "0,1,2,3,4", + "EventCode": "0x05", + "EventName": "UNC_M_VC1_REQUESTS_WR", + "Experimental": "1", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "Counts number of bytes written, in 32B chunk,= per DDR channel. Counter increments by 1 after sending 32B chunk data.", + "Counter": "0,1,2,3,4", + "EventCode": "0x3B", + "EventName": "UNC_M_WR_DATA", + "PerPkg": "1", + "Unit": "iMC" } ] diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-ev= ents/arch/x86/mapfile.csv index b8ea72b99c52..7d19f8fa335a 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -22,7 +22,7 @@ GenuineIntel-6-3A,v24,ivybridge,core GenuineIntel-6-3E,v24,ivytown,core GenuineIntel-6-2D,v24,jaketown,core GenuineIntel-6-(57|85),v16,knightslanding,core -GenuineIntel-6-BD,v1.22,lunarlake,core +GenuineIntel-6-BD,v1.25,lunarlake,core GenuineIntel-6-(AA|AC|B5),v1.21,meteorlake,core GenuineIntel-6-1[AEF],v4,nehalemep,core GenuineIntel-6-2E,v4,nehalemex,core --=20 2.54.0.1099.g489fc7bff1-goog From nobody Wed Jun 10 18:41:25 2026 Received: from mail-pg1-f202.google.com (mail-pg1-f202.google.com [209.85.215.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 51D74411663 for ; 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Tue, 09 Jun 2026 14:50:55 -0700 (PDT) Date: Tue, 9 Jun 2026 14:50:44 -0700 In-Reply-To: <20260609215046.2391903-1-ctshao@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20260609215046.2391903-1-ctshao@google.com> X-Mailer: git-send-email 2.54.0.1099.g489fc7bff1-goog Message-ID: <20260609215046.2391903-6-ctshao@google.com> Subject: [PATCH v1 5/6] perf vendor events intel: Update pantherlake events from 1.05 to 1.06 From: Chun-Tse Shao To: peterz@infradead.org, mingo@redhat.com, acme@kernel.org, namhyung@kernel.org Cc: alexander.shishkin@linux.intel.com, jolsa@kernel.org, irogers@google.com, adrian.hunter@intel.com, james.clark@linaro.org, afaerber@suse.de, mani@kernel.org, dapeng1.mi@linux.intel.com, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-actions@lists.infradead.org, Chun-Tse Shao Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The updated events were published in: https://github.com/intel/perfmon/commit/ffc03fc3b414127c5a36bbb648e500c4afe= ff134 Signed-off-by: Chun-Tse Shao --- tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +- .../arch/x86/pantherlake/counter.json | 5 + .../arch/x86/pantherlake/pipeline.json | 29 ++- .../x86/pantherlake/uncore-interconnect.json | 10 + .../arch/x86/pantherlake/uncore-memory.json | 221 +++++++++++++++++- 5 files changed, 260 insertions(+), 7 deletions(-) create mode 100644 tools/perf/pmu-events/arch/x86/pantherlake/uncore-inter= connect.json diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-ev= ents/arch/x86/mapfile.csv index 7d19f8fa335a..6af3cee12c8a 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -26,7 +26,7 @@ GenuineIntel-6-BD,v1.25,lunarlake,core GenuineIntel-6-(AA|AC|B5),v1.21,meteorlake,core GenuineIntel-6-1[AEF],v4,nehalemep,core GenuineIntel-6-2E,v4,nehalemex,core -GenuineIntel-6-(CC|D5),v1.05,pantherlake,core +GenuineIntel-6-(CC|D5),v1.06,pantherlake,core GenuineIntel-6-A7,v1.04,rocketlake,core GenuineIntel-6-2A,v19,sandybridge,core GenuineIntel-6-8F,v1.39,sapphirerapids,core diff --git a/tools/perf/pmu-events/arch/x86/pantherlake/counter.json b/tool= s/perf/pmu-events/arch/x86/pantherlake/counter.json index 432b6946ccbc..9794b435f650 100644 --- a/tools/perf/pmu-events/arch/x86/pantherlake/counter.json +++ b/tools/perf/pmu-events/arch/x86/pantherlake/counter.json @@ -13,5 +13,10 @@ "Unit": "iMC", "CountersNumFixed": "0", "CountersNumGeneric": "5" + }, + { + "Unit": "SANTA", + "CountersNumFixed": 1, + "CountersNumGeneric": "0" } ] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/pantherlake/pipeline.json b/too= ls/perf/pmu-events/arch/x86/pantherlake/pipeline.json index d476bad5e2a7..5d5303c02954 100644 --- a/tools/perf/pmu-events/arch/x86/pantherlake/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/pantherlake/pipeline.json @@ -887,11 +887,32 @@ "Unit": "cpu_core" }, { - "BriefDescription": "This event counts the number of mispredicted = ret instructions retired. Non PEBS [This event is alias to BR_MISP_RETIRED.= RET]", + "BriefDescription": "This event is deprecated. [This event is alia= s to BR_MISP_RETIRED.NEAR_RETURN]", + "Counter": "0,1,2,3,4,5,6,7", + "Deprecated": "1", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.NEAR_RET", + "PublicDescription": "This event is deprecated. [This event is ali= as to BR_MISP_RETIRED.NEAR_RETURN] Available PDIST counters: 0,1", + "SampleAfterValue": "1000003", + "UMask": "0x8", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of mispredicted near RET br= anch instructions retired. [This event is alias to BR_MISP_RETIRED.NEAR_RET= ]", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.NEAR_RETURN", + "PublicDescription": "Counts the number of mispredicted near RET b= ranch instructions retired. [This event is alias to BR_MISP_RETIRED.NEAR_RE= T] Available PDIST counters: 0,1", + "SampleAfterValue": "1000003", + "UMask": "0x8", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "This event counts the number of mispredicted = ret instructions retired [This event is alias to BR_MISP_RETIRED.RET]", "Counter": "0,1,2,3,4,5,6,7,8,9", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.NEAR_RETURN", - "PublicDescription": "This is a non-precise version (that is, does= not use PEBS) of the event that counts mispredicted return instructions re= tired. [This event is alias to BR_MISP_RETIRED.RET] Available PDIST counter= s: 0,1", + "PublicDescription": "This event counts the number of mispredicted= ret instructions retired [This event is alias to BR_MISP_RETIRED.RET] Avai= lable PDIST counters: 0,1", "SampleAfterValue": "100007", "UMask": "0x8", "Unit": "cpu_core" @@ -1726,7 +1747,7 @@ "Unit": "cpu_atom" }, { - "BriefDescription": "Counts the number of machines clears due to m= emory renaming.", + "BriefDescription": "Counts the number of machine clears due to me= mory renaming.", "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc3", "EventName": "MACHINE_CLEARS.MRN_NUKE", @@ -1930,7 +1951,7 @@ "Unit": "cpu_atom" }, { - "BriefDescription": "Counts the number issue slots not consumed d= ue to a color request for an FCW or MXCSR control register when all 4 colo= rs (copies) are already in use.", + "BriefDescription": "Counts the number of issue slots not consumed= due to a color request for an FCW or MXCSR control register when all 4 col= ors (copies) are already in use.", "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x75", "EventName": "SERIALIZATION.COLOR_STALLS", diff --git a/tools/perf/pmu-events/arch/x86/pantherlake/uncore-interconnect= .json b/tools/perf/pmu-events/arch/x86/pantherlake/uncore-interconnect.json new file mode 100644 index 000000000000..69ef928d57f6 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/pantherlake/uncore-interconnect.json @@ -0,0 +1,10 @@ +[ + { + "BriefDescription": "This 48-bit fixed counter counts the UCLK cyc= les.", + "Counter": "FIXED", + "EventCode": "0xff", + "EventName": "UNC_CLOCK.SOCKET", + "PerPkg": "1", + "Unit": "SANTA" + } +] diff --git a/tools/perf/pmu-events/arch/x86/pantherlake/uncore-memory.json = b/tools/perf/pmu-events/arch/x86/pantherlake/uncore-memory.json index a881b99be5f3..8faa03e1c6d0 100644 --- a/tools/perf/pmu-events/arch/x86/pantherlake/uncore-memory.json +++ b/tools/perf/pmu-events/arch/x86/pantherlake/uncore-memory.json @@ -1,6 +1,30 @@ [ { - "BriefDescription": "Read CAS command sent to DRAM", + "BriefDescription": "ACT command for a read request sent to DRAM.", + "Counter": "0,1,2,3,4", + "EventCode": "0x24", + "EventName": "UNC_M_ACT_COUNT_RD", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "ACT command sent to DRAM.", + "Counter": "0,1,2,3,4", + "EventCode": "0x26", + "EventName": "UNC_M_ACT_COUNT_TOTAL", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "ACT command for a write request sent to DRAM.= ", + "Counter": "0,1,2,3,4", + "EventCode": "0x25", + "EventName": "UNC_M_ACT_COUNT_WR", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "Read CAS command sent to DRAM.", "Counter": "0,1,2,3,4", "EventCode": "0x22", "EventName": "UNC_M_CAS_COUNT_RD", @@ -8,13 +32,153 @@ "Unit": "iMC" }, { - "BriefDescription": "Write CAS command sent to DRAM", + "BriefDescription": "Write CAS command sent to DRAM.", "Counter": "0,1,2,3,4", "EventCode": "0x23", "EventName": "UNC_M_CAS_COUNT_WR", "PerPkg": "1", "Unit": "iMC" }, + { + "BriefDescription": "Counting the number of clocks.", + "Counter": "0,1,2,3,4", + "EventCode": "0x01", + "EventName": "UNC_M_CLOCKTICKS", + "Experimental": "1", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "CKE in DRAM is low.", + "Counter": "0,1,2,3,4", + "EventCode": "0x29", + "EventName": "UNC_M_DRAM_CKE_OFF_CYCLES", + "Experimental": "1", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "Incoming read request page status is Page Emp= ty.", + "Counter": "0,1,2,3,4", + "EventCode": "0x1D", + "EventName": "UNC_M_DRAM_PAGE_EMPTY_RD", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "incoming read request page status is Page Em= pty", + "Unit": "iMC" + }, + { + "BriefDescription": "Incoming write request page status is Page Em= pty.", + "Counter": "0,1,2,3,4", + "EventCode": "0x20", + "EventName": "UNC_M_DRAM_PAGE_EMPTY_WR", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "incoming write request page status is Page E= mpty", + "Unit": "iMC" + }, + { + "BriefDescription": "Incoming read request page status is Page Hit= .", + "Counter": "0,1,2,3,4", + "EventCode": "0x1C", + "EventName": "UNC_M_DRAM_PAGE_HIT_RD", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "incoming read request page status is Page Hi= t", + "Unit": "iMC" + }, + { + "BriefDescription": "Incoming write request page status is Page Hi= t.", + "Counter": "0,1,2,3,4", + "EventCode": "0x1F", + "EventName": "UNC_M_DRAM_PAGE_HIT_WR", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "incoming write request page status is Page H= it", + "Unit": "iMC" + }, + { + "BriefDescription": "Incoming read request page status is Page Mis= s.", + "Counter": "0,1,2,3,4", + "EventCode": "0x1E", + "EventName": "UNC_M_DRAM_PAGE_MISS_RD", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "incoming read request page status is Page Mi= ss", + "Unit": "iMC" + }, + { + "BriefDescription": "Incoming write request page status is Page Mi= ss.", + "Counter": "0,1,2,3,4", + "EventCode": "0x21", + "EventName": "UNC_M_DRAM_PAGE_MISS_WR", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "incoming write request page status is Page M= iss", + "Unit": "iMC" + }, + { + "BriefDescription": "DRAM in Self-refresh (all channels).", + "Counter": "0,1,2,3,4", + "EventCode": "0x12", + "EventName": "UNC_M_DRAM_SELF_REFRESH", + "Experimental": "1", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "Any Rank at Hot state.", + "Counter": "0,1,2,3,4", + "EventCode": "0x19", + "EventName": "UNC_M_DRAM_THERMAL_HOT", + "Experimental": "1", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "Any Rank at Warm state.", + "Counter": "0,1,2,3,4", + "EventCode": "0x1A", + "EventName": "UNC_M_DRAM_THERMAL_WARM", + "Experimental": "1", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "PRE command sent to DRAM for a read/write req= uest.", + "Counter": "0,1,2,3,4", + "EventCode": "0x27", + "EventName": "UNC_M_PRE_COUNT_PAGE_MISS", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "Counts number of bytes read, in 32B chunk, pe= r DDR channel. Counter increments by 1 after receiving 32B chunk data.", + "Counter": "0,1,2,3,4", + "EventCode": "0x3A", + "EventName": "UNC_M_RD_DATA", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "Number of VC0 read in channel0 - this event = can increment by more than 1 (per channel/sub-ch).", + "Counter": "0,1,2,3,4", + "EventCode": "0x13", + "EventName": "UNC_M_RD_OCCUPANCY_CH0", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "Number of VC0 read in channel0 - this event= can increment by more than 1 (per channel/sub-ch)", + "Unit": "iMC" + }, + { + "BriefDescription": "Number of VC0 read in channel1 - this event c= an increment by more than 1 (per channel/sub-ch).", + "Counter": "0,1,2,3,4", + "EventCode": "0x14", + "EventName": "UNC_M_RD_OCCUPANCY_CH1", + "Experimental": "1", + "PerPkg": "1", + "Unit": "iMC" + }, { "BriefDescription": "Total number of read and write byte transfers= to/from DRAM, in 32B chunk, per DDR channel. Counter increments by 1 after= sending or receiving 32B chunk data.", "Counter": "0,1,2,3,4", @@ -22,5 +186,58 @@ "EventName": "UNC_M_TOTAL_DATA", "PerPkg": "1", "Unit": "iMC" + }, + { + "BriefDescription": "Total number of requests entering MC, this is= the sum of all RD + WR requests for all VCs.", + "Counter": "0,1,2,3,4", + "EventCode": "0x39", + "EventName": "UNC_M_TOTAL_REQUESTS", + "Experimental": "1", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "Incoming VC0 read request.", + "Counter": "0,1,2,3,4", + "EventCode": "0x02", + "EventName": "UNC_M_VC0_REQUESTS_RD", + "Experimental": "1", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "Incoming VC0 write request.", + "Counter": "0,1,2,3,4", + "EventCode": "0x03", + "EventName": "UNC_M_VC0_REQUESTS_WR", + "Experimental": "1", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "Incoming VC1 read request.", + "Counter": "0,1,2,3,4", + "EventCode": "0x04", + "EventName": "UNC_M_VC1_REQUESTS_RD", + "Experimental": "1", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "Incoming VC1 write request.", + "Counter": "0,1,2,3,4", + "EventCode": "0x05", + "EventName": "UNC_M_VC1_REQUESTS_WR", + "Experimental": "1", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "Counts number of bytes written, in 32B chunk,= per DDR channel. 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AFNElJ9RgJsowJDVeogZUx1mh24hI2ocV74duOyaj8QzxpVIvxGMSdqMYwfiG1PnyyXNma+/tB0vfWBUuXG8J/k=@vger.kernel.org X-Gm-Message-State: AOJu0Yxz7M8NrWM+7e2Dn6LMgkyRTBxf0VBrk6rhLBhbD/CCYQVKoUZd lfBnmd9AyWQbsjdqaZpLxop9DAunDl1Mgggcp4bZEi55yPNAhRUafP08KT1q/IVNWG8KL2PJ1qs q425fWA== X-Received: from pjbfu17.prod.google.com ([2002:a17:90a:d191:b0:369:1a1a:82d6]) (user=ctshao job=prod-delivery.src-stubby-dispatcher) by 2002:a17:90b:1642:b0:369:7421:75cf with SMTP id 98e67ed59e1d1-370f0284a7bmr20878362a91.16.1781041856338; Tue, 09 Jun 2026 14:50:56 -0700 (PDT) Date: Tue, 9 Jun 2026 14:50:45 -0700 In-Reply-To: <20260609215046.2391903-1-ctshao@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20260609215046.2391903-1-ctshao@google.com> X-Mailer: git-send-email 2.54.0.1099.g489fc7bff1-goog Message-ID: <20260609215046.2391903-7-ctshao@google.com> Subject: [PATCH v1 6/6] perf vendor events intel: Update tigerlake events from 1.18 to 1.19 From: Chun-Tse Shao To: peterz@infradead.org, mingo@redhat.com, acme@kernel.org, namhyung@kernel.org Cc: alexander.shishkin@linux.intel.com, jolsa@kernel.org, irogers@google.com, adrian.hunter@intel.com, james.clark@linaro.org, afaerber@suse.de, mani@kernel.org, dapeng1.mi@linux.intel.com, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-actions@lists.infradead.org, Chun-Tse Shao Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The updated events were published in: https://github.com/intel/perfmon/commit/8353ffb63efcad6b6fac1a8c05d76e2d631= 7ae23 Signed-off-by: Chun-Tse Shao --- tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-ev= ents/arch/x86/mapfile.csv index 6af3cee12c8a..a7f870669827 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -35,7 +35,7 @@ GenuineIntel-6-(37|4A|4C|4D|5A),v15,silvermont,core GenuineIntel-6-(4E|5E|8E|9E|A5|A6),v59,skylake,core GenuineIntel-6-55-[01234],v1.37,skylakex,core GenuineIntel-6-86,v1.23,snowridgex,core -GenuineIntel-6-8[CD],v1.18,tigerlake,core +GenuineIntel-6-8[CD],v1.19,tigerlake,core GenuineIntel-6-2C,v5,westmereep-dp,core GenuineIntel-6-25,v4,westmereep-sp,core GenuineIntel-6-2F,v4,westmereex,core --=20 2.54.0.1099.g489fc7bff1-goog