From nobody Thu Jun 11 14:14:42 2026 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0745A4968EC for ; Tue, 9 Jun 2026 16:37:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=170.10.133.124 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781023038; cv=none; b=MbeDMVyhYzJBXgN58j6519aYVaMqHxinCjNnqN4c8u4LlgroWeZLwxtYKLpbhaacLFHupNR7mh7MpvC7lrSkRzffFLQLEuDMKpD5T8+rJ78pWTQ+pxsGTkru19L8W0WI0vjVKfSX9ovFwQ2u/DIIhhTWl87tWABRgYjTuPWxOEc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781023038; c=relaxed/simple; bh=RB51zGeQICHGKMGUIcNIovONUOJ0k7n8f9vI3EMMXVk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=UgabFiFEJ7oryT65zzFx99EbNKy+bDy7qL7ZX6IwGR2ZQjDXlx5dA1O6fx73FymdF2BQXdlP28bBwyPLZdBVJkwTEyLFX+8znp1rW0uoRTj/UbJkYOQXzIQKZ87V7y7x3KW0y98Kp597DeTQIiETre1xgfSlAfr8X8aXNuykDgI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=redhat.com; spf=pass smtp.mailfrom=redhat.com; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b=PMxtRIcb; arc=none smtp.client-ip=170.10.133.124 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=redhat.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=redhat.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="PMxtRIcb" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1781023034; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=BlJUbNpU0pTX5NWiNJbaiX2FROLLctIsfkxEzOcvkg8=; b=PMxtRIcb8mvqnIBy7DezkDnsgidn7tedKCLZ+P6A6cA2h9jE8pNPYo5o2QwQ9UZfuAmFDV H8RxDsUJtxZxLDMx/Q44G78t3PLNP+Z6WhSWiHUd8lZg+tOQDTOjC6XsNFio0Ut1eIwcbE 2qehymgRuhqav9a2wqc4mzOojK7M0s0= Received: from mx-prod-mc-01.mail-002.prod.us-west-2.aws.redhat.com (ec2-54-186-198-63.us-west-2.compute.amazonaws.com [54.186.198.63]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-424-FuDVg-dlNkCYHEmFdXSS1w-1; Tue, 09 Jun 2026 12:37:09 -0400 X-MC-Unique: FuDVg-dlNkCYHEmFdXSS1w-1 X-Mimecast-MFC-AGG-ID: FuDVg-dlNkCYHEmFdXSS1w_1781023027 Received: from mx-prod-int-08.mail-002.prod.us-west-2.aws.redhat.com (mx-prod-int-08.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.111]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx-prod-mc-01.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id D076219560BC; Tue, 9 Jun 2026 16:37:05 +0000 (UTC) Received: from fedora.redhat.com (unknown [10.44.32.77]) by mx-prod-int-08.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 8502C1800662; Tue, 9 Jun 2026 16:37:01 +0000 (UTC) From: Jose Ignacio Tornos Martinez To: bhelgaas@google.com, alex@shazbot.org Cc: jjohnson@kernel.org, mani@kernel.org, linux-pci@vger.kernel.org, linux-wireless@vger.kernel.org, ath11k@lists.infradead.org, ath12k@lists.infradead.org, mhi@lists.linux.dev, linux-kernel@vger.kernel.org, Jose Ignacio Tornos Martinez Subject: [PATCH v8 1/3] PCI: Add d3cold as general reset method Date: Tue, 9 Jun 2026 18:36:47 +0200 Message-ID: <20260609163649.319755-2-jtornosm@redhat.com> In-Reply-To: <20260609163649.319755-1-jtornosm@redhat.com> References: <20260609163649.319755-1-jtornosm@redhat.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.111 Content-Type: text/plain; charset="utf-8" Add D3cold power cycle as a general PCI reset method for single-function devices on platforms with ACPI _PR3 power resources. This provides true power cycle reset capability when the platform can physically cut power to the device. The implementation strictly requires _PR3 to be present - the platform must be able to control device power. This ensures d3cold only attempts true power cycling, not falling back to D3hot transitions. D3cold reset is placed at the end of the reset hierarchy since it requires specific platform support and should be tried after standard methods. Reset hierarchy with this change: 1. device_specific 2. acpi 3. flr 4. af_flr 5. pm (D3hot via config space, checks NoSoftRst) 6. bus (SBR) 7. cxl_bus 8. d3cold (NEW - true power cycle, requires _PR3) This benefits: - Platforms with _PR3 support - Single-function devices needing true power cycle - VFIO passthrough scenarios where FLR/PM unavailable Signed-off-by: Jose Ignacio Tornos Martinez --- v8: code unchanged from v7 v7: https://lore.kernel.org/all/20260603105853.326290-2-jtornosm@redhat.com= /=20 drivers/pci/pci.c | 50 +++++++++++++++++++++++++++++++++++++++++++++ include/linux/pci.h | 2 +- 2 files changed, 51 insertions(+), 1 deletion(-) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 8f7cfcc00090..096868f80cd4 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -4491,6 +4491,55 @@ static int pci_pm_reset(struct pci_dev *dev, bool pr= obe) return ret; } =20 +/** + * pci_d3cold_reset - Put device into D3cold and back to D0 for reset + * @dev: PCI device to reset + * @probe: if true, check if D3cold reset is supported; if false, perform = reset + * + * Reset the device by transitioning through D3cold (actual power removal = via + * platform power control) and back to D0. This requires ACPI _PR3 power + * resources to be present - the platform must be able to physically cut p= ower + * to the device. + * + * Only available for single-function devices to avoid affecting other + * functions in multi-function devices. + * + * Returns 0 if device can be/was reset this way, -ENOTTY if not supported, + * or other negative error code on failure. + */ +static int pci_d3cold_reset(struct pci_dev *dev, bool probe) +{ + int ret; + + if (dev->multifunction) + return -ENOTTY; + + if (!pci_pr3_present(dev)) + return -ENOTTY; + + if (probe) + return 0; + + if (dev->current_state !=3D PCI_D0) + return -EINVAL; + + ret =3D pci_dev_reset_iommu_prepare(dev); + if (ret) { + pci_err(dev, "failed to stop IOMMU for a PCI reset: %d\n", ret); + return ret; + } + + ret =3D pci_set_power_state(dev, PCI_D3cold); + if (ret) + goto done; + + ret =3D pci_set_power_state(dev, PCI_D0); + +done: + pci_dev_reset_iommu_done(dev); + return ret; +} + /** * pcie_wait_for_link_status - Wait for link status change * @pdev: Device whose link to wait for. @@ -5065,6 +5114,7 @@ const struct pci_reset_fn_method pci_reset_fn_methods= [] =3D { { pci_pm_reset, .name =3D "pm" }, { pci_reset_bus_function, .name =3D "bus" }, { cxl_reset_bus_function, .name =3D "cxl_bus" }, + { pci_d3cold_reset, .name =3D "d3cold" }, }; =20 /** diff --git a/include/linux/pci.h b/include/linux/pci.h index 2c4454583c11..1ca7b880ead7 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -51,7 +51,7 @@ PCI_STATUS_PARITY) =20 /* Number of reset methods used in pci_reset_fn_methods array in pci.c */ -#define PCI_NUM_RESET_METHODS 8 +#define PCI_NUM_RESET_METHODS 9 =20 #define PCI_RESET_PROBE true #define PCI_RESET_DO_RESET false --=20 2.54.0 From nobody Thu Jun 11 14:14:42 2026 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.129.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 59E6E3F65EB for ; Tue, 9 Jun 2026 16:37:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=170.10.129.124 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781023044; cv=none; b=lLiUxV7U8aZjZdu9IYVzzfy1uIk59w+KB0M+KZq2JMmqgMTC5kbkN0R10kTKzJzYsmIynaT1vqHHvB/MoBrRd7ptWdv4XG4jhx4YPSEgpZPVi7Zs+R2jT8sXz+QOTlHWkPjY5tXc5UpeeDYEwmaIQkbO0yyLIj50f2pQGx/LpP8= ARC-Message-Signature: i=1; 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Tue, 9 Jun 2026 16:37:10 +0000 (UTC) Received: from fedora.redhat.com (unknown [10.44.32.77]) by mx-prod-int-08.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 843D31800662; Tue, 9 Jun 2026 16:37:07 +0000 (UTC) From: Jose Ignacio Tornos Martinez To: bhelgaas@google.com, alex@shazbot.org Cc: jjohnson@kernel.org, mani@kernel.org, linux-pci@vger.kernel.org, linux-wireless@vger.kernel.org, ath11k@lists.infradead.org, ath12k@lists.infradead.org, mhi@lists.linux.dev, linux-kernel@vger.kernel.org, Jose Ignacio Tornos Martinez Subject: [PATCH v8 2/3] PCI: Add device-specific reset for Qualcomm devices Date: Tue, 9 Jun 2026 18:36:48 +0200 Message-ID: <20260609163649.319755-3-jtornosm@redhat.com> In-Reply-To: <20260609163649.319755-1-jtornosm@redhat.com> References: <20260609163649.319755-1-jtornosm@redhat.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.111 Content-Type: text/plain; charset="utf-8" Some Qualcomm PCIe devices (WCN6855/WCN7850 WiFi cards, SDX62/SDX65 modems) lack working reset methods for VFIO passthrough scenarios. These devices have no FLR capability, advertise NoSoftRst+ (blocking PM reset), and have broken bus reset. The problem manifests in VFIO passthrough scenarios: - WCN6855 WiFi card (17cb:1103): Normal VM operation works fine, including clean shutdown/reboot. However, when the VM terminates uncleanly (crash, force-off), VFIO attempts to reset the device before it can be assigned to another VM. Without a working reset method, the device remains in an undefined state, preventing reuse. - WCN7850 WiFi card (17cb:1107): Same behavior as WCN6855. - SDX62/SDX65 5G modems (17cb:0308): Never successfully initialize even on first VM assignment without proper reset capability. Add device-specific reset entries for these Qualcomm devices using D3cold power cycling with automatic D3hot fallback. The implementation uses pci_set_power_state(D3cold) which automatically falls back to D3hot on platforms without ACPI _PR3 power resources. While not a complete reset (BARs preserved), testing shows D3hot transition provides sufficient reset for VFIO reuse. Extract a shared pci_dev_d3cold_d0_cycle() helper function to avoid code duplication between pci_d3cold_reset() (strict _PR3 requirement) and the new reset_d3cold_d3hot() device-specific reset (automatic fallback). The helper performs only the power cycle; IOMMU handling is done by the caller (pci_d3cold_reset() for general method, __pci_dev_specific_reset() wrapper for device-specific methods). Device-specific reset is position #1 in the reset hierarchy, so these Qualcomm devices will use power cycling as their primary reset method, with the general d3cold method (position #8) available as a fallback on _PR3-capable platforms if users override via sysfs. Signed-off-by: Jose Ignacio Tornos Martinez --- v8: Fix commit message: correct IOMMU handling description. The helper performs only the power cycle; IOMMU is handled by callers (this was v6 fix) v7: https://lore.kernel.org/all/20260603105853.326290-3-jtornosm@redhat.com/ drivers/pci/pci.c | 37 +++++++++++++++++++++++++++---------- drivers/pci/pci.h | 1 + drivers/pci/quirks.c | 19 +++++++++++++++++++ 3 files changed, 47 insertions(+), 10 deletions(-) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 096868f80cd4..f7a7443287fd 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -4491,6 +4491,32 @@ static int pci_pm_reset(struct pci_dev *dev, bool pr= obe) return ret; } =20 +/** + * pci_dev_d3cold_d0_cycle - Perform D3cold->D0 power cycle + * @dev: Device to power cycle + * + * Common helper to perform D3cold->D0 power cycle for reset methods. + * Attempts D3cold transition with automatic fallback to D3hot on platforms + * without ACPI _PR3 power resources. + * + * Caller must handle IOMMU preparation/cleanup if needed. + * + * Returns 0 on success, negative error code on failure. + */ +int pci_dev_d3cold_d0_cycle(struct pci_dev *dev) +{ + int ret; + + if (dev->current_state !=3D PCI_D0) + return -EINVAL; + + ret =3D pci_set_power_state(dev, PCI_D3cold); + if (ret) + return ret; + + return pci_set_power_state(dev, PCI_D0); +} + /** * pci_d3cold_reset - Put device into D3cold and back to D0 for reset * @dev: PCI device to reset @@ -4520,22 +4546,13 @@ static int pci_d3cold_reset(struct pci_dev *dev, bo= ol probe) if (probe) return 0; =20 - if (dev->current_state !=3D PCI_D0) - return -EINVAL; - ret =3D pci_dev_reset_iommu_prepare(dev); if (ret) { pci_err(dev, "failed to stop IOMMU for a PCI reset: %d\n", ret); return ret; } =20 - ret =3D pci_set_power_state(dev, PCI_D3cold); - if (ret) - goto done; - - ret =3D pci_set_power_state(dev, PCI_D0); - -done: + ret =3D pci_dev_d3cold_d0_cycle(dev); pci_dev_reset_iommu_done(dev); return ret; } diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 4a14f88e543a..a9942787de9e 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -234,6 +234,7 @@ void pci_init_reset_methods(struct pci_dev *dev); int pci_bridge_secondary_bus_reset(struct pci_dev *dev); int pci_bus_error_reset(struct pci_dev *dev); int pci_try_reset_bridge(struct pci_dev *bridge); +int pci_dev_d3cold_d0_cycle(struct pci_dev *dev); =20 struct pci_cap_saved_data { u16 cap_nr; diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index e49136ac5dbf..70f3b0f26799 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -4237,6 +4237,22 @@ static int reset_hinic_vf_dev(struct pci_dev *pdev, = bool probe) return 0; } =20 +/* + * Device-specific reset method via D3cold/D3hot power cycle. + * + * Some devices lack working FLR, advertise NoSoftRst+ (blocking PM reset), + * and have broken bus reset. This function provides device-specific reset= via + * power cycling, attempting D3cold with automatic fallback to D3hot on pl= atforms + * without ACPI _PR3 power resources. + */ +static int reset_d3cold_d3hot(struct pci_dev *dev, bool probe) +{ + if (probe) + return 0; + + return pci_dev_d3cold_d0_cycle(dev); +} + static const struct pci_dev_reset_methods pci_dev_reset_methods[] =3D { { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF, reset_intel_82599_sfp_virtfn }, @@ -4252,6 +4268,9 @@ static const struct pci_dev_reset_methods pci_dev_res= et_methods[] =3D { reset_chelsio_generic_dev }, { PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_HINIC_VF, reset_hinic_vf_dev }, + { PCI_VENDOR_ID_QCOM, 0x1103, reset_d3cold_d3hot }, /* WCN6855 */ + { PCI_VENDOR_ID_QCOM, 0x1107, reset_d3cold_d3hot }, /* WCN7850 */ + { PCI_VENDOR_ID_QCOM, 0x0308, reset_d3cold_d3hot }, /* SDX62/SDX65 */ { 0 } }; =20 --=20 2.54.0 From nobody Thu Jun 11 14:14:42 2026 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8983B48A2CA for ; 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Tue, 09 Jun 2026 12:37:26 -0400 X-MC-Unique: fWQzA6GMOYCOx6xgw1VLcw-1 X-Mimecast-MFC-AGG-ID: fWQzA6GMOYCOx6xgw1VLcw_1781023044 Received: from mx-prod-int-08.mail-002.prod.us-west-2.aws.redhat.com (mx-prod-int-08.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.111]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx-prod-mc-01.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id A13B21955F08; Tue, 9 Jun 2026 16:37:24 +0000 (UTC) Received: from fedora.redhat.com (unknown [10.44.32.77]) by mx-prod-int-08.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 471741800662; Tue, 9 Jun 2026 16:37:21 +0000 (UTC) From: Jose Ignacio Tornos Martinez To: bhelgaas@google.com, alex@shazbot.org Cc: jjohnson@kernel.org, mani@kernel.org, linux-pci@vger.kernel.org, linux-wireless@vger.kernel.org, ath11k@lists.infradead.org, ath12k@lists.infradead.org, mhi@lists.linux.dev, linux-kernel@vger.kernel.org, Jose Ignacio Tornos Martinez Subject: [PATCH v8 3/3] PCI: Disable broken bus reset on Qualcomm devices Date: Tue, 9 Jun 2026 18:36:49 +0200 Message-ID: <20260609163649.319755-4-jtornosm@redhat.com> In-Reply-To: <20260609163649.319755-1-jtornosm@redhat.com> References: <20260609163649.319755-1-jtornosm@redhat.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.111 Content-Type: text/plain; charset="utf-8" Some Qualcomm PCIe devices (WCN6855/WCN7850 WiFi cards, SDX62/SDX65 modems) do not properly support Secondary Bus Reset (SBR). Testing confirms this is device-specific, not deployment-specific: MediaTek MT7925e successfully uses bus reset through the same passive M.2-to-PCIe adapters where Qualcomm devices fail, proving PERST# is properly wired through the adapters. This quirk acts as a safety net, preventing the broken bus reset from being attempted if users override reset methods (device_specific or d3cold when available) via sysfs. Signed-off-by: Jose Ignacio Tornos Martinez --- v8: code unchanged from v7 v7: https://lore.kernel.org/all/20260603105853.326290-4-jtornosm@redhat.com/ drivers/pci/quirks.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index 000000000000..111111111111 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -3789,6 +3789,9 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003= 0, quirk_no_bus_reset); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0032, quirk_no_bus_reset= ); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003c, quirk_no_bus_reset= ); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0033, quirk_no_bus_reset= ); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0034, quirk_no_bus_reset= ); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003e, quirk_no_bus_reset= ); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_QCOM, 0x1103, quirk_no_bus_reset); = /* WCN6855 */ +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_QCOM, 0x1107, quirk_no_bus_reset); = /* WCN7850 */ +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_QCOM, 0x0308, quirk_no_bus_reset); = /* SDX62/SDX65 */ /* * Root port on some Cavium CN8xxx chips do not successfully complete a bus -- 2.53.0