From nobody Sat Jun 13 16:18:26 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1FECE32B126; Tue, 9 Jun 2026 14:25:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781015144; cv=none; b=YUw0BFyyJuOkt3ndhUEGeleDLyd6Wj8JXX0MeCp+xEsY6K0n92YrH9J0HonfU0/71az3Lrl0H7v3+2719XWfbLN8IZw7DbUzfjzwxsTWBcmwA/Jyofj4Yviy0t8cLcT2eLuBXpEyTAg1u/jCkMw2mm4tWoja4BUvhik7Y11Oz6w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781015144; c=relaxed/simple; bh=rffY4CyethuWreEaV3IdcILtZUUY+OP61QIlf5gygF4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=tVD6S51i5YV4M6ql9Ofnyg1L7IqHV2chzjqMed9v0mrWDBBcweiCK9imOm4w2nZpXDFiihqQf+FB+1SVCgL57sOCuBh4Zb+tlC1u0iqSCn5dEcKYrZc+enu5wFRF/jn3+d6hu3c4Z4peKQeCFhVTq3PY79c6dn9gP6+KtXVoJWk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 Received: by smtp.kernel.org (Postfix) with ESMTPSA id 40C141F00893; Tue, 9 Jun 2026 14:25:38 +0000 (UTC) From: Greg Ungerer To: linux-m68k@lists.linux-m68k.org Cc: linux-kernel@vger.kernel.org, arnd@kernel.org, wei.fang@nxp.com, frank.li@nxp.com, shenwei.wang@nxp.com, imx@lists.linux.dev, netdev@vger.kernel.org, nico@fluxnic.net, adureghello@baylibre.com, ulfh@kernel.org, linux-mmc@vger.kernel.org, linux-can@vger.kernel.org, linux-spi@vger.kernel.org, olteanv@gmail.com, Greg Ungerer Subject: [PATCHv2 1/4] net: fec: do not use readl()/writel() for ColdFire Date: Wed, 10 Jun 2026 00:12:58 +1000 Message-ID: <20260609142139.1563360-3-gerg@linux-m68k.org> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260609142139.1563360-1-gerg@linux-m68k.org> References: <20260609142139.1563360-1-gerg@linux-m68k.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Modify the FEC driver to not directly use readl() and writel() to access hardware registers but instead local fec_readl() and fec_writel() methods. This allows for different architecture users of this driver to have different underlying access functions - to support both little and big endian hardware. The FEC hardware block in ColdFire SoC parts is accessed big-endian. The usual kernel readl()/writel() IO memory access methods are defined to access little endian data. Change access for ColdFire to use __raw_readl() and __raw_writel() access methods - which do not modify or swap bytes on access. The FEC driver works today because the m68k architecture io.h has a kludge in the definitions of the readl() and writel() functions for ColdFire that allow big-endian access if the address of the register to access is within the SoC's internal peripheral registers. This is being fixed in the near future to define readl() and writel() correctly - with no byte swapping. Thus the motivation for this fix here. __raw_readl()/__raw_writel() access methods are used instead of the more commonly used ioread32be()/iowrite32be() here because those are broken too, because of the current readl()/writel() kludge. They are implemented in asm-generic/io.h in terms of readl()/writel(). Note that even when readl() and writel() are fixed on ColdFire they will not be the right thing to use within the FEC driver on ColdFire hardware. Signed-off-by: Greg Ungerer Reviewed-by: Andrew Lunn --- v2: changed from RFC to PATCH minor reordering of local variables for preferred layout drivers/net/ethernet/freescale/fec.h | 15 ++ drivers/net/ethernet/freescale/fec_main.c | 257 +++++++++++----------- drivers/net/ethernet/freescale/fec_ptp.c | 78 +++---- 3 files changed, 183 insertions(+), 167 deletions(-) diff --git a/drivers/net/ethernet/freescale/fec.h b/drivers/net/ethernet/fr= eescale/fec.h index 7176803146f3..af31d946a638 100644 --- a/drivers/net/ethernet/freescale/fec.h +++ b/drivers/net/ethernet/freescale/fec.h @@ -701,5 +701,20 @@ int fec_ptp_set(struct net_device *ndev, struct kernel= _hwtstamp_config *config, struct netlink_ext_ack *extack); void fec_ptp_get(struct net_device *ndev, struct kernel_hwtstamp_config *c= onfig); =20 +/* + * ColdFire SoC peripheral blocks are big-endian, so use the raw IO access + * functions for them. + */ +#ifdef CONFIG_COLDFIRE +#define fec_readl __raw_readl +#define fec_writel __raw_writel +#define fec_readl_poll_timeout_atomic(addr, val, cond, delay_us, timeout_u= s) \ + readx_poll_timeout_atomic(__raw_readl, addr, val, cond, delay_us, timeout= _us) +#else +#define fec_readl readl +#define fec_writel writel +#define fec_readl_poll_timeout_atomic readl_poll_timeout_atomic +#endif + /*************************************************************************= ***/ #endif /* FEC_H */ diff --git a/drivers/net/ethernet/freescale/fec_main.c b/drivers/net/ethern= et/freescale/fec_main.c index 6ebde65d7f1b..023fde9cfa3b 100644 --- a/drivers/net/ethernet/freescale/fec_main.c +++ b/drivers/net/ethernet/freescale/fec_main.c @@ -497,11 +497,11 @@ static void fec_txq_trigger_xmit(struct fec_enet_priv= ate *fep, struct fec_enet_priv_tx_q *txq) { if (!(fep->quirks & FEC_QUIRK_ERR007885) || - !readl(txq->bd.reg_desc_active) || - !readl(txq->bd.reg_desc_active) || - !readl(txq->bd.reg_desc_active) || - !readl(txq->bd.reg_desc_active)) - writel(0, txq->bd.reg_desc_active); + !fec_readl(txq->bd.reg_desc_active) || + !fec_readl(txq->bd.reg_desc_active) || + !fec_readl(txq->bd.reg_desc_active) || + !fec_readl(txq->bd.reg_desc_active)) + fec_writel(0, txq->bd.reg_desc_active); } =20 static struct bufdesc * @@ -1069,7 +1069,7 @@ static void fec_enet_active_rxring(struct net_device = *ndev) int i; =20 for (i =3D 0; i < fep->num_rx_queues; i++) - writel(0, fep->rx_queue[i]->bd.reg_desc_active); + fec_writel(0, fep->rx_queue[i]->bd.reg_desc_active); } =20 static void fec_enet_enable_ring(struct net_device *ndev) @@ -1081,23 +1081,23 @@ static void fec_enet_enable_ring(struct net_device = *ndev) =20 for (i =3D 0; i < fep->num_rx_queues; i++) { rxq =3D fep->rx_queue[i]; - writel(rxq->bd.dma, fep->hwp + FEC_R_DES_START(i)); - writel(fep->max_buf_size, fep->hwp + FEC_R_BUFF_SIZE(i)); + fec_writel(rxq->bd.dma, fep->hwp + FEC_R_DES_START(i)); + fec_writel(fep->max_buf_size, fep->hwp + FEC_R_BUFF_SIZE(i)); =20 /* enable DMA1/2 */ if (i) - writel(RCMR_MATCHEN | RCMR_CMP(i), - fep->hwp + FEC_RCMR(i)); + fec_writel(RCMR_MATCHEN | RCMR_CMP(i), + fep->hwp + FEC_RCMR(i)); } =20 for (i =3D 0; i < fep->num_tx_queues; i++) { txq =3D fep->tx_queue[i]; - writel(txq->bd.dma, fep->hwp + FEC_X_DES_START(i)); + fec_writel(txq->bd.dma, fep->hwp + FEC_X_DES_START(i)); =20 /* enable DMA1/2 */ if (i) - writel(DMA_CLASS_EN | IDLE_SLOPE(i), - fep->hwp + FEC_DMA_CFG(i)); + fec_writel(DMA_CLASS_EN | IDLE_SLOPE(i), + fep->hwp + FEC_DMA_CFG(i)); } } =20 @@ -1112,15 +1112,15 @@ static void fec_ctrl_reset(struct fec_enet_private = *fep, bool allow_wol) if (!allow_wol || !(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) { if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES || ((fep->quirks & FEC_QUIRK_NO_HARD_RESET) && fep->link)) { - writel(0, fep->hwp + FEC_ECNTRL); + fec_writel(0, fep->hwp + FEC_ECNTRL); } else { - writel(FEC_ECR_RESET, fep->hwp + FEC_ECNTRL); + fec_writel(FEC_ECR_RESET, fep->hwp + FEC_ECNTRL); udelay(10); } } else { - val =3D readl(fep->hwp + FEC_ECNTRL); + val =3D fec_readl(fep->hwp + FEC_ECNTRL); val |=3D (FEC_ECR_MAGICEN | FEC_ECR_SLEEP); - writel(val, fep->hwp + FEC_ECNTRL); + fec_writel(val, fep->hwp + FEC_ECNTRL); } } =20 @@ -1128,11 +1128,11 @@ static void fec_set_hw_mac_addr(struct net_device *= ndev) { struct fec_enet_private *fep =3D netdev_priv(ndev); =20 - writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) | - (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24), - fep->hwp + FEC_ADDR_LOW); - writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24), - fep->hwp + FEC_ADDR_HIGH); + fec_writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) | + (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24), + fep->hwp + FEC_ADDR_LOW); + fec_writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24), + fep->hwp + FEC_ADDR_HIGH); } =20 /* @@ -1162,7 +1162,7 @@ fec_restart(struct net_device *ndev) fec_set_hw_mac_addr(ndev); =20 /* Clear any outstanding interrupt, except MDIO. */ - writel((0xffffffff & ~FEC_ENET_MII), fep->hwp + FEC_IEVENT); + fec_writel((0xffffffff & ~FEC_ENET_MII), fep->hwp + FEC_IEVENT); =20 fec_enet_bd_init(ndev); =20 @@ -1171,19 +1171,19 @@ fec_restart(struct net_device *ndev) /* Enable MII mode */ if (fep->full_duplex =3D=3D DUPLEX_FULL) { /* FD enable */ - writel(0x04, fep->hwp + FEC_X_CNTRL); + fec_writel(0x04, fep->hwp + FEC_X_CNTRL); } else { /* No Rcv on Xmit */ rcntl |=3D FEC_RCR_DRT; - writel(0x0, fep->hwp + FEC_X_CNTRL); + fec_writel(0x0, fep->hwp + FEC_X_CNTRL); } =20 /* Set MII speed */ - writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); + fec_writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); =20 #if !defined(CONFIG_M5272) if (fep->quirks & FEC_QUIRK_HAS_RACC) { - u32 val =3D readl(fep->hwp + FEC_RACC); + u32 val =3D fec_readl(fep->hwp + FEC_RACC); =20 /* align IP header */ val |=3D FEC_RACC_SHIFT16; @@ -1192,8 +1192,8 @@ fec_restart(struct net_device *ndev) val |=3D FEC_RACC_OPTIONS; else val &=3D ~FEC_RACC_OPTIONS; - writel(val, fep->hwp + FEC_RACC); - writel(min(fep->rx_frame_size, fep->max_buf_size), fep->hwp + FEC_FTRL); + fec_writel(val, fep->hwp + FEC_RACC); + fec_writel(min(fep->rx_frame_size, fep->max_buf_size), fep->hwp + FEC_FT= RL); } #endif =20 @@ -1227,8 +1227,8 @@ fec_restart(struct net_device *ndev) if (fep->quirks & FEC_QUIRK_USE_GASKET) { u32 cfgr; /* disable the gasket and wait */ - writel(0, fep->hwp + FEC_MIIGSK_ENR); - while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4) + fec_writel(0, fep->hwp + FEC_MIIGSK_ENR); + while (fec_readl(fep->hwp + FEC_MIIGSK_ENR) & 4) udelay(1); =20 /* @@ -1240,10 +1240,10 @@ fec_restart(struct net_device *ndev) ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII; if (ndev->phydev && ndev->phydev->speed =3D=3D SPEED_10) cfgr |=3D BM_MIIGSK_CFGR_FRCONT_10M; - writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR); + fec_writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR); =20 /* re-enable the gasket */ - writel(2, fep->hwp + FEC_MIIGSK_ENR); + fec_writel(2, fep->hwp + FEC_MIIGSK_ENR); } #endif } @@ -1256,25 +1256,25 @@ fec_restart(struct net_device *ndev) rcntl |=3D FEC_RCR_FLOWCTL; =20 /* set FIFO threshold parameter to reduce overrun */ - writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM); - writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL); - writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM); - writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL); + fec_writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM); + fec_writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL); + fec_writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM); + fec_writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL); =20 /* OPD */ - writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD); + fec_writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD); } else { rcntl &=3D ~FEC_RCR_FLOWCTL; } #endif /* !defined(CONFIG_M5272) */ =20 - writel(rcntl, fep->hwp + FEC_R_CNTRL); + fec_writel(rcntl, fep->hwp + FEC_R_CNTRL); =20 /* Setup multicast filter. */ set_multicast_list(ndev); #ifndef CONFIG_M5272 - writel(0, fep->hwp + FEC_HASH_TABLE_HIGH); - writel(0, fep->hwp + FEC_HASH_TABLE_LOW); + fec_writel(0, fep->hwp + FEC_HASH_TABLE_HIGH); + fec_writel(0, fep->hwp + FEC_HASH_TABLE_LOW); #endif =20 if (fep->quirks & FEC_QUIRK_ENET_MAC) { @@ -1290,9 +1290,9 @@ fec_restart(struct net_device *ndev) */ if ((fep->quirks & FEC_QUIRK_JUMBO_FRAME) && (ndev->mtu > (PKT_MAXBUF_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN))) - writel(0xF, fep->hwp + FEC_X_WMRK); + fec_writel(0xF, fep->hwp + FEC_X_WMRK); else - writel(FEC_TXWMRK_STRFWD, fep->hwp + FEC_X_WMRK); + fec_writel(FEC_TXWMRK_STRFWD, fep->hwp + FEC_X_WMRK); } =20 if (fep->bufdesc_ex) @@ -1307,11 +1307,11 @@ fec_restart(struct net_device *ndev) =20 #ifndef CONFIG_M5272 /* Enable the MIB statistic event counters */ - writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT); + fec_writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT); #endif =20 /* And last, enable the transmit and receive processing */ - writel(ecntl, fep->hwp + FEC_ECNTRL); + fec_writel(ecntl, fep->hwp + FEC_ECNTRL); fec_enet_active_rxring(ndev); =20 if (fep->bufdesc_ex) { @@ -1321,9 +1321,9 @@ fec_restart(struct net_device *ndev) =20 /* Enable interrupts we wish to service */ if (fep->link) - writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); + fec_writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); else - writel(0, fep->hwp + FEC_IMASK); + fec_writel(0, fep->hwp + FEC_IMASK); =20 /* Init the interrupt coalescing */ if (fep->quirks & FEC_QUIRK_HAS_COALESCE) @@ -1384,29 +1384,30 @@ static void fec_irqs_disable(struct net_device *nde= v) { struct fec_enet_private *fep =3D netdev_priv(ndev); =20 - writel(0, fep->hwp + FEC_IMASK); + fec_writel(0, fep->hwp + FEC_IMASK); } =20 static void fec_irqs_disable_except_wakeup(struct net_device *ndev) { struct fec_enet_private *fep =3D netdev_priv(ndev); =20 - writel(0, fep->hwp + FEC_IMASK); - writel(FEC_ENET_WAKEUP, fep->hwp + FEC_IMASK); + fec_writel(0, fep->hwp + FEC_IMASK); + fec_writel(FEC_ENET_WAKEUP, fep->hwp + FEC_IMASK); } =20 static void fec_stop(struct net_device *ndev) { struct fec_enet_private *fep =3D netdev_priv(ndev); - u32 rmii_mode =3D readl(fep->hwp + FEC_R_CNTRL) & FEC_RCR_RMII; - u32 val; + u32 rmii_mode, val; + + rmii_mode =3D fec_readl(fep->hwp + FEC_R_CNTRL) & FEC_RCR_RMII; =20 /* We cannot expect a graceful transmit stop without link !!! */ if (fep->link) { - writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */ + fec_writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */ udelay(10); - if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA)) + if (!(fec_readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA)) netdev_err(ndev, "Graceful transmit stop did not complete!\n"); } =20 @@ -1414,20 +1415,20 @@ fec_stop(struct net_device *ndev) fec_ptp_save_state(fep); =20 fec_ctrl_reset(fep, true); - writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); - writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); + fec_writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); + fec_writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); =20 /* We have to keep ENET enabled to have MII interrupt stay working */ if (fep->quirks & FEC_QUIRK_ENET_MAC && !(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) { - writel(FEC_ECR_ETHEREN, fep->hwp + FEC_ECNTRL); - writel(rmii_mode, fep->hwp + FEC_R_CNTRL); + fec_writel(FEC_ECR_ETHEREN, fep->hwp + FEC_ECNTRL); + fec_writel(rmii_mode, fep->hwp + FEC_R_CNTRL); } =20 if (fep->bufdesc_ex) { - val =3D readl(fep->hwp + FEC_ECNTRL); + val =3D fec_readl(fep->hwp + FEC_ECNTRL); val |=3D FEC_ECR_EN1588; - writel(val, fep->hwp + FEC_ECNTRL); + fec_writel(val, fep->hwp + FEC_ECNTRL); =20 fec_ptp_start_cyclecounter(ndev); fec_ptp_restore_state(fep); @@ -1713,8 +1714,8 @@ static int fec_enet_tx_queue(struct fec_enet_private = *fep, =20 /* ERR006358: Keep the transmitter going */ if (bdp !=3D txq->bd.cur && - readl(txq->bd.reg_desc_active) =3D=3D 0) - writel(0, txq->bd.reg_desc_active); + fec_readl(txq->bd.reg_desc_active) =3D=3D 0) + fec_writel(0, txq->bd.reg_desc_active); =20 if (txq->xsk_pool) { struct xsk_buff_pool *pool =3D txq->xsk_pool; @@ -1923,7 +1924,7 @@ static int fec_enet_rx_queue(struct fec_enet_private = *fep, break; pkt_received++; =20 - writel(FEC_ENET_RXF_GET(queue), fep->hwp + FEC_IEVENT); + fec_writel(FEC_ENET_RXF_GET(queue), fep->hwp + FEC_IEVENT); =20 /* Check for errors. */ status ^=3D BD_ENET_RX_LAST; @@ -1991,7 +1992,7 @@ static int fec_enet_rx_queue(struct fec_enet_private = *fep, * incoming frames. On a heavily loaded network, we should be * able to keep up at the expense of system resources. */ - writel(0, rxq->bd.reg_desc_active); + fec_writel(0, rxq->bd.reg_desc_active); } rxq->bd.cur =3D bdp; =20 @@ -2053,7 +2054,7 @@ static int fec_enet_rx_queue_xdp(struct fec_enet_priv= ate *fep, int queue, break; pkt_received++; =20 - writel(FEC_ENET_RXF_GET(queue), fep->hwp + FEC_IEVENT); + fec_writel(FEC_ENET_RXF_GET(queue), fep->hwp + FEC_IEVENT); =20 /* Check for errors. */ status ^=3D BD_ENET_RX_LAST; @@ -2166,7 +2167,7 @@ static int fec_enet_rx_queue_xdp(struct fec_enet_priv= ate *fep, int queue, * incoming frames. On a heavily loaded network, we should be * able to keep up at the expense of system resources. */ - writel(0, rxq->bd.reg_desc_active); + fec_writel(0, rxq->bd.reg_desc_active); } =20 rxq->bd.cur =3D bdp; @@ -2296,7 +2297,7 @@ static int fec_enet_rx_queue_xsk(struct fec_enet_priv= ate *fep, int queue, if (unlikely(pkt_received >=3D budget)) break; =20 - writel(FEC_ENET_RXF_GET(queue), fep->hwp + FEC_IEVENT); + fec_writel(FEC_ENET_RXF_GET(queue), fep->hwp + FEC_IEVENT); =20 index =3D fec_enet_get_bd_index(bdp, &rxq->bd); xsk =3D rxq->rx_buf[index].xdp; @@ -2428,7 +2429,7 @@ static int fec_enet_rx_queue_xsk(struct fec_enet_priv= ate *fep, int queue, * incoming frames. On a heavily loaded network, we should be * able to keep up at the expense of system resources. */ - writel(0, rxq->bd.reg_desc_active); + fec_writel(0, rxq->bd.reg_desc_active); } =20 rxq->bd.cur =3D bdp; @@ -2475,12 +2476,12 @@ static bool fec_enet_collect_events(struct fec_enet= _private *fep) { uint int_events; =20 - int_events =3D readl(fep->hwp + FEC_IEVENT); + int_events =3D fec_readl(fep->hwp + FEC_IEVENT); =20 /* Don't clear MDIO events, we poll for those */ int_events &=3D ~FEC_ENET_MII; =20 - writel(int_events, fep->hwp + FEC_IEVENT); + fec_writel(int_events, fep->hwp + FEC_IEVENT); =20 return int_events !=3D 0; } @@ -2497,7 +2498,7 @@ fec_enet_interrupt(int irq, void *dev_id) =20 if (napi_schedule_prep(&fep->napi)) { /* Disable interrupts */ - writel(0, fep->hwp + FEC_IMASK); + fec_writel(0, fep->hwp + FEC_IMASK); __napi_schedule(&fep->napi); } } @@ -2520,7 +2521,7 @@ static int fec_enet_rx_napi(struct napi_struct *napi,= int budget) =20 if (max_done < budget) { napi_complete_done(napi, max_done); - writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); + fec_writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); return max_done; } =20 @@ -2576,9 +2577,9 @@ static int fec_get_mac(struct net_device *ndev) */ if (!is_valid_ether_addr(iap)) { *((__be32 *) &tmpaddr[0]) =3D - cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW)); + cpu_to_be32(fec_readl(fep->hwp + FEC_ADDR_LOW)); *((__be16 *) &tmpaddr[4]) =3D - cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16); + cpu_to_be16(fec_readl(fep->hwp + FEC_ADDR_HIGH) >> 16); iap =3D &tmpaddr[0]; } =20 @@ -2630,8 +2631,8 @@ static int fec_enet_eee_mode_set(struct net_device *n= dev, u32 lpi_timer, wake_cycle =3D 0; } =20 - writel(sleep_cycle, fep->hwp + FEC_LPI_SLEEP); - writel(wake_cycle, fep->hwp + FEC_LPI_WAKE); + fec_writel(sleep_cycle, fep->hwp + FEC_LPI_SLEEP); + fec_writel(wake_cycle, fep->hwp + FEC_LPI_WAKE); =20 return 0; } @@ -2701,11 +2702,11 @@ static int fec_enet_mdio_wait(struct fec_enet_priva= te *fep) uint ievent; int ret; =20 - ret =3D readl_poll_timeout_atomic(fep->hwp + FEC_IEVENT, ievent, - ievent & FEC_ENET_MII, 2, 30000); + ret =3D fec_readl_poll_timeout_atomic(fep->hwp + FEC_IEVENT, ievent, + ievent & FEC_ENET_MII, 2, 30000); =20 if (!ret) - writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT); + fec_writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT); =20 return ret; } @@ -2726,9 +2727,9 @@ static int fec_enet_mdio_read_c22(struct mii_bus *bus= , int mii_id, int regnum) frame_addr =3D regnum; =20 /* start a read op */ - writel(frame_start | frame_op | - FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) | - FEC_MMFR_TA, fep->hwp + FEC_MII_DATA); + fec_writel(frame_start | frame_op | + FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) | + FEC_MMFR_TA, fep->hwp + FEC_MII_DATA); =20 /* wait for end of transfer */ ret =3D fec_enet_mdio_wait(fep); @@ -2737,7 +2738,7 @@ static int fec_enet_mdio_read_c22(struct mii_bus *bus= , int mii_id, int regnum) goto out; } =20 - ret =3D FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA)); + ret =3D FEC_MMFR_DATA(fec_readl(fep->hwp + FEC_MII_DATA)); =20 out: pm_runtime_put_autosuspend(dev); @@ -2759,10 +2760,10 @@ static int fec_enet_mdio_read_c45(struct mii_bus *b= us, int mii_id, frame_start =3D FEC_MMFR_ST_C45; =20 /* write address */ - writel(frame_start | FEC_MMFR_OP_ADDR_WRITE | - FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(devad) | - FEC_MMFR_TA | (regnum & 0xFFFF), - fep->hwp + FEC_MII_DATA); + fec_writel(frame_start | FEC_MMFR_OP_ADDR_WRITE | + FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(devad) | + FEC_MMFR_TA | (regnum & 0xFFFF), + fep->hwp + FEC_MII_DATA); =20 /* wait for end of transfer */ ret =3D fec_enet_mdio_wait(fep); @@ -2774,9 +2775,9 @@ static int fec_enet_mdio_read_c45(struct mii_bus *bus= , int mii_id, frame_op =3D FEC_MMFR_OP_READ_C45; =20 /* start a read op */ - writel(frame_start | frame_op | - FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(devad) | - FEC_MMFR_TA, fep->hwp + FEC_MII_DATA); + fec_writel(frame_start | frame_op | + FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(devad) | + FEC_MMFR_TA, fep->hwp + FEC_MII_DATA); =20 /* wait for end of transfer */ ret =3D fec_enet_mdio_wait(fep); @@ -2785,7 +2786,7 @@ static int fec_enet_mdio_read_c45(struct mii_bus *bus= , int mii_id, goto out; } =20 - ret =3D FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA)); + ret =3D FEC_MMFR_DATA(fec_readl(fep->hwp + FEC_MII_DATA)); =20 out: pm_runtime_put_autosuspend(dev); @@ -2809,10 +2810,10 @@ static int fec_enet_mdio_write_c22(struct mii_bus *= bus, int mii_id, int regnum, frame_addr =3D regnum; =20 /* start a write op */ - writel(frame_start | FEC_MMFR_OP_WRITE | - FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) | - FEC_MMFR_TA | FEC_MMFR_DATA(value), - fep->hwp + FEC_MII_DATA); + fec_writel(frame_start | FEC_MMFR_OP_WRITE | + FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) | + FEC_MMFR_TA | FEC_MMFR_DATA(value), + fep->hwp + FEC_MII_DATA); =20 /* wait for end of transfer */ ret =3D fec_enet_mdio_wait(fep); @@ -2838,10 +2839,10 @@ static int fec_enet_mdio_write_c45(struct mii_bus *= bus, int mii_id, frame_start =3D FEC_MMFR_ST_C45; =20 /* write address */ - writel(frame_start | FEC_MMFR_OP_ADDR_WRITE | - FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(devad) | - FEC_MMFR_TA | (regnum & 0xFFFF), - fep->hwp + FEC_MII_DATA); + fec_writel(frame_start | FEC_MMFR_OP_ADDR_WRITE | + FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(devad) | + FEC_MMFR_TA | (regnum & 0xFFFF), + fep->hwp + FEC_MII_DATA); =20 /* wait for end of transfer */ ret =3D fec_enet_mdio_wait(fep); @@ -2851,10 +2852,10 @@ static int fec_enet_mdio_write_c45(struct mii_bus *= bus, int mii_id, } =20 /* start a write op */ - writel(frame_start | FEC_MMFR_OP_WRITE | - FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(devad) | - FEC_MMFR_TA | FEC_MMFR_DATA(value), - fep->hwp + FEC_MII_DATA); + fec_writel(frame_start | FEC_MMFR_OP_WRITE | + FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(devad) | + FEC_MMFR_TA | FEC_MMFR_DATA(value), + fep->hwp + FEC_MII_DATA); =20 /* wait for end of transfer */ ret =3D fec_enet_mdio_wait(fep); @@ -3132,13 +3133,13 @@ static int fec_enet_mii_init(struct platform_device= *pdev) * - writing MMFR: * - mscr[7:0]_not_zero */ - writel(0, fep->hwp + FEC_MII_DATA); + fec_writel(0, fep->hwp + FEC_MII_DATA); } =20 - writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); + fec_writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); =20 /* Clear any pending transaction complete indication */ - writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT); + fec_writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT); =20 fep->mii_bus =3D mdiobus_alloc(); if (fep->mii_bus =3D=3D NULL) { @@ -3320,7 +3321,7 @@ static void fec_enet_get_regs(struct net_device *ndev, continue; =20 off >>=3D 2; - buf[off] =3D readl(&theregs[off]); + buf[off] =3D fec_readl(&theregs[off]); } =20 pm_runtime_put_autosuspend(dev); @@ -3487,7 +3488,7 @@ static void fec_enet_update_ethtool_stats(struct net_= device *dev) int i; =20 for (i =3D 0; i < ARRAY_SIZE(fec_stats); i++) - fep->ethtool_stats[i] =3D readl(fep->hwp + fec_stats[i].offset); + fep->ethtool_stats[i] =3D fec_readl(fep->hwp + fec_stats[i].offset); } =20 static void fec_enet_get_xdp_stats(struct fec_enet_private *fep, u64 *data) @@ -3588,10 +3589,10 @@ static void fec_enet_clear_ethtool_stats(struct net= _device *dev) int i, j; =20 /* Disable MIB statistics counters */ - writel(FEC_MIB_CTRLSTAT_DISABLE, fep->hwp + FEC_MIB_CTRLSTAT); + fec_writel(FEC_MIB_CTRLSTAT_DISABLE, fep->hwp + FEC_MIB_CTRLSTAT); =20 for (i =3D 0; i < ARRAY_SIZE(fec_stats); i++) - writel(0, fep->hwp + fec_stats[i].offset); + fec_writel(0, fep->hwp + fec_stats[i].offset); =20 for (i =3D fep->num_rx_queues - 1; i >=3D 0; i--) { rxq =3D fep->rx_queue[i]; @@ -3600,7 +3601,7 @@ static void fec_enet_clear_ethtool_stats(struct net_d= evice *dev) } =20 /* Don't disable MIB statistics counters */ - writel(0, fep->hwp + FEC_MIB_CTRLSTAT); + fec_writel(0, fep->hwp + FEC_MIB_CTRLSTAT); } =20 #else /* !defined(CONFIG_M5272) */ @@ -3649,13 +3650,13 @@ static void fec_enet_itr_coal_set(struct net_device= *ndev) tx_itr |=3D FEC_ITR_ICTT(tx_ictt); } =20 - writel(tx_itr, fep->hwp + FEC_TXIC0); - writel(rx_itr, fep->hwp + FEC_RXIC0); + fec_writel(tx_itr, fep->hwp + FEC_TXIC0); + fec_writel(rx_itr, fep->hwp + FEC_RXIC0); if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES) { - writel(tx_itr, fep->hwp + FEC_TXIC1); - writel(rx_itr, fep->hwp + FEC_RXIC1); - writel(tx_itr, fep->hwp + FEC_TXIC2); - writel(rx_itr, fep->hwp + FEC_RXIC2); + fec_writel(tx_itr, fep->hwp + FEC_TXIC1); + fec_writel(rx_itr, fep->hwp + FEC_RXIC1); + fec_writel(tx_itr, fep->hwp + FEC_TXIC2); + fec_writel(rx_itr, fep->hwp + FEC_RXIC2); } } =20 @@ -4281,22 +4282,22 @@ static void set_multicast_list(struct net_device *n= dev) unsigned int hash_high =3D 0, hash_low =3D 0; =20 if (ndev->flags & IFF_PROMISC) { - tmp =3D readl(fep->hwp + FEC_R_CNTRL); + tmp =3D fec_readl(fep->hwp + FEC_R_CNTRL); tmp |=3D 0x8; - writel(tmp, fep->hwp + FEC_R_CNTRL); + fec_writel(tmp, fep->hwp + FEC_R_CNTRL); return; } =20 - tmp =3D readl(fep->hwp + FEC_R_CNTRL); + tmp =3D fec_readl(fep->hwp + FEC_R_CNTRL); tmp &=3D ~0x8; - writel(tmp, fep->hwp + FEC_R_CNTRL); + fec_writel(tmp, fep->hwp + FEC_R_CNTRL); =20 if (ndev->flags & IFF_ALLMULTI) { /* Catch all multicast addresses, so set the * filter to all 1's */ - writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); - writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW); + fec_writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); + fec_writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW); =20 return; } @@ -4317,8 +4318,8 @@ static void set_multicast_list(struct net_device *nde= v) hash_low |=3D 1 << hash; } =20 - writel(hash_high, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); - writel(hash_low, fep->hwp + FEC_GRP_HASH_TABLE_LOW); + fec_writel(hash_high, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); + fec_writel(hash_low, fep->hwp + FEC_GRP_HASH_TABLE_LOW); } =20 /* Set a MAC change in hardware. */ @@ -5003,7 +5004,7 @@ static int fec_enet_init(struct net_device *ndev) ndev->netdev_ops =3D &fec_netdev_ops; ndev->ethtool_ops =3D &fec_enet_ethtool_ops; =20 - writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK); + fec_writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK); netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi); =20 if (fep->quirks & FEC_QUIRK_HAS_VLAN) @@ -5607,9 +5608,9 @@ static int fec_resume(struct device *dev) enable_irq(fep->wake_irq); } =20 - val =3D readl(fep->hwp + FEC_ECNTRL); + val =3D fec_readl(fep->hwp + FEC_ECNTRL); val &=3D ~(FEC_ECR_MAGICEN | FEC_ECR_SLEEP); - writel(val, fep->hwp + FEC_ECNTRL); + fec_writel(val, fep->hwp + FEC_ECNTRL); fep->wol_flag &=3D ~FEC_WOL_FLAG_SLEEP_ON; } fec_restart(ndev); diff --git a/drivers/net/ethernet/freescale/fec_ptp.c b/drivers/net/etherne= t/freescale/fec_ptp.c index 56801c2009d5..07062599b522 100644 --- a/drivers/net/ethernet/freescale/fec_ptp.c +++ b/drivers/net/ethernet/freescale/fec_ptp.c @@ -102,14 +102,14 @@ static u64 fec_ptp_read(struct cyclecounter *cc) container_of(cc, struct fec_enet_private, cc); u32 tempval; =20 - tempval =3D readl(fep->hwp + FEC_ATIME_CTRL); + tempval =3D fec_readl(fep->hwp + FEC_ATIME_CTRL); tempval |=3D FEC_T_CTRL_CAPTURE; - writel(tempval, fep->hwp + FEC_ATIME_CTRL); + fec_writel(tempval, fep->hwp + FEC_ATIME_CTRL); =20 if (fep->quirks & FEC_QUIRK_BUG_CAPTURE) udelay(1); =20 - return readl(fep->hwp + FEC_ATIME); + return fec_readl(fep->hwp + FEC_ATIME); } =20 /** @@ -142,17 +142,17 @@ static int fec_ptp_enable_pps(struct fec_enet_private= *fep, uint enable) if (enable) { /* clear capture or output compare interrupt status if have. */ - writel(FEC_T_TF_MASK, fep->hwp + FEC_TCSR(fep->pps_channel)); + fec_writel(FEC_T_TF_MASK, fep->hwp + FEC_TCSR(fep->pps_channel)); =20 /* It is recommended to double check the TMODE field in the * TCSR register to be cleared before the first compare counter * is written into TCCR register. Just add a double check. */ - val =3D readl(fep->hwp + FEC_TCSR(fep->pps_channel)); + val =3D fec_readl(fep->hwp + FEC_TCSR(fep->pps_channel)); do { val &=3D ~(FEC_T_TMODE_MASK); - writel(val, fep->hwp + FEC_TCSR(fep->pps_channel)); - val =3D readl(fep->hwp + FEC_TCSR(fep->pps_channel)); + fec_writel(val, fep->hwp + FEC_TCSR(fep->pps_channel)); + val =3D fec_readl(fep->hwp + FEC_TCSR(fep->pps_channel)); } while (val & FEC_T_TMODE_MASK); =20 /* Dummy read counter to update the counter */ @@ -194,31 +194,31 @@ static int fec_ptp_enable_pps(struct fec_enet_private= *fep, uint enable) * is bigger than fep->cc.mask would be a error. */ val &=3D fep->cc.mask; - writel(val, fep->hwp + FEC_TCCR(fep->pps_channel)); + fec_writel(val, fep->hwp + FEC_TCCR(fep->pps_channel)); =20 /* Calculate the second the compare event timestamp */ fep->next_counter =3D (val + fep->reload_period) & fep->cc.mask; =20 /* * Enable compare event when overflow */ - val =3D readl(fep->hwp + FEC_ATIME_CTRL); + val =3D fec_readl(fep->hwp + FEC_ATIME_CTRL); val |=3D FEC_T_CTRL_PINPER; - writel(val, fep->hwp + FEC_ATIME_CTRL); + fec_writel(val, fep->hwp + FEC_ATIME_CTRL); =20 /* Compare channel setting. */ - val =3D readl(fep->hwp + FEC_TCSR(fep->pps_channel)); + val =3D fec_readl(fep->hwp + FEC_TCSR(fep->pps_channel)); val |=3D (1 << FEC_T_TF_OFFSET | 1 << FEC_T_TIE_OFFSET); val &=3D ~(1 << FEC_T_TDRE_OFFSET); val &=3D ~(FEC_T_TMODE_MASK); val |=3D (FEC_HIGH_PULSE << FEC_T_TMODE_OFFSET); - writel(val, fep->hwp + FEC_TCSR(fep->pps_channel)); + fec_writel(val, fep->hwp + FEC_TCSR(fep->pps_channel)); =20 /* Write the second compare event timestamp and calculate * the third timestamp. Refer the TCCR register detail in the spec. */ - writel(fep->next_counter, fep->hwp + FEC_TCCR(fep->pps_channel)); + fec_writel(fep->next_counter, fep->hwp + FEC_TCCR(fep->pps_channel)); fep->next_counter =3D (fep->next_counter + fep->reload_period) & fep->cc= .mask; } else { - writel(0, fep->hwp + FEC_TCSR(fep->pps_channel)); + fec_writel(0, fep->hwp + FEC_TCSR(fep->pps_channel)); } =20 fep->pps_enable =3D enable; @@ -258,26 +258,26 @@ static int fec_ptp_pps_perout(struct fec_enet_private= *fep) compare_val =3D fep->perout_stime - curr_time + ptp_hc; compare_val &=3D fep->cc.mask; =20 - writel(compare_val, fep->hwp + FEC_TCCR(fep->pps_channel)); + fec_writel(compare_val, fep->hwp + FEC_TCCR(fep->pps_channel)); fep->next_counter =3D (compare_val + fep->reload_period) & fep->cc.mask; =20 /* Enable compare event when overflow */ - temp_val =3D readl(fep->hwp + FEC_ATIME_CTRL); + temp_val =3D fec_readl(fep->hwp + FEC_ATIME_CTRL); temp_val |=3D FEC_T_CTRL_PINPER; - writel(temp_val, fep->hwp + FEC_ATIME_CTRL); + fec_writel(temp_val, fep->hwp + FEC_ATIME_CTRL); =20 /* Compare channel setting. */ - temp_val =3D readl(fep->hwp + FEC_TCSR(fep->pps_channel)); + temp_val =3D fec_readl(fep->hwp + FEC_TCSR(fep->pps_channel)); temp_val |=3D (1 << FEC_T_TF_OFFSET | 1 << FEC_T_TIE_OFFSET); temp_val &=3D ~(1 << FEC_T_TDRE_OFFSET); temp_val &=3D ~(FEC_T_TMODE_MASK); temp_val |=3D (FEC_TMODE_TOGGLE << FEC_T_TMODE_OFFSET); - writel(temp_val, fep->hwp + FEC_TCSR(fep->pps_channel)); + fec_writel(temp_val, fep->hwp + FEC_TCSR(fep->pps_channel)); =20 /* Write the second compare event timestamp and calculate * the third timestamp. Refer the TCCR register detail in the spec. */ - writel(fep->next_counter, fep->hwp + FEC_TCCR(fep->pps_channel)); + fec_writel(fep->next_counter, fep->hwp + FEC_TCCR(fep->pps_channel)); fep->next_counter =3D (fep->next_counter + fep->reload_period) & fep->cc.= mask; spin_unlock_irqrestore(&fep->tmreg_lock, flags); =20 @@ -314,13 +314,13 @@ void fec_ptp_start_cyclecounter(struct net_device *nd= ev) spin_lock_irqsave(&fep->tmreg_lock, flags); =20 /* 1ns counter */ - writel(inc << FEC_T_INC_OFFSET, fep->hwp + FEC_ATIME_INC); + fec_writel(inc << FEC_T_INC_OFFSET, fep->hwp + FEC_ATIME_INC); =20 /* use 31-bit timer counter */ - writel(FEC_COUNTER_PERIOD, fep->hwp + FEC_ATIME_EVT_PERIOD); + fec_writel(FEC_COUNTER_PERIOD, fep->hwp + FEC_ATIME_EVT_PERIOD); =20 - writel(FEC_T_CTRL_ENABLE | FEC_T_CTRL_PERIOD_RST, - fep->hwp + FEC_ATIME_CTRL); + fec_writel(FEC_T_CTRL_ENABLE | FEC_T_CTRL_PERIOD_RST, + fep->hwp + FEC_ATIME_CTRL); =20 memset(&fep->cc, 0, sizeof(fep->cc)); fep->cc.read =3D fec_ptp_read; @@ -397,11 +397,11 @@ static int fec_ptp_adjfine(struct ptp_clock_info *ptp= , long scaled_ppm) =20 spin_lock_irqsave(&fep->tmreg_lock, flags); =20 - tmp =3D readl(fep->hwp + FEC_ATIME_INC) & FEC_T_INC_MASK; + tmp =3D fec_readl(fep->hwp + FEC_ATIME_INC) & FEC_T_INC_MASK; tmp |=3D corr_ns << FEC_T_INC_CORR_OFFSET; - writel(tmp, fep->hwp + FEC_ATIME_INC); + fec_writel(tmp, fep->hwp + FEC_ATIME_INC); corr_period =3D corr_period > 1 ? corr_period - 1 : corr_period; - writel(corr_period, fep->hwp + FEC_ATIME_CORR); + fec_writel(corr_period, fep->hwp + FEC_ATIME_CORR); /* dummy read to update the timer. */ timecounter_read(&fep->tc); =20 @@ -493,7 +493,7 @@ static int fec_ptp_settime(struct ptp_clock_info *ptp, counter =3D ns & fep->cc.mask; =20 spin_lock_irqsave(&fep->tmreg_lock, flags); - writel(counter, fep->hwp + FEC_ATIME); + fec_writel(counter, fep->hwp + FEC_ATIME); timecounter_init(&fep->tc, &fep->cc, ns); spin_unlock_irqrestore(&fep->tmreg_lock, flags); mutex_unlock(&fep->ptp_clk_mutex); @@ -508,7 +508,7 @@ static int fec_ptp_pps_disable(struct fec_enet_private = *fep, uint channel) =20 spin_lock_irqsave(&fep->tmreg_lock, flags); fep->perout_enable =3D false; - writel(0, fep->hwp + FEC_TCSR(channel)); + fec_writel(0, fep->hwp + FEC_TCSR(channel)); spin_unlock_irqrestore(&fep->tmreg_lock, flags); =20 return 0; @@ -701,15 +701,15 @@ static irqreturn_t fec_pps_interrupt(int irq, void *d= ev_id) u8 channel =3D fep->pps_channel; struct ptp_clock_event event; =20 - val =3D readl(fep->hwp + FEC_TCSR(channel)); + val =3D fec_readl(fep->hwp + FEC_TCSR(channel)); if (val & FEC_T_TF_MASK) { /* Write the next next compare(not the next according the spec) * value to the register */ - writel(fep->next_counter, fep->hwp + FEC_TCCR(channel)); + fec_writel(fep->next_counter, fep->hwp + FEC_TCCR(channel)); do { - writel(val, fep->hwp + FEC_TCSR(channel)); - } while (readl(fep->hwp + FEC_TCSR(channel)) & FEC_T_TF_MASK); + fec_writel(val, fep->hwp + FEC_TCSR(channel)); + } while (fec_readl(fep->hwp + FEC_TCSR(channel)) & FEC_T_TF_MASK); =20 /* Update the counter; */ fep->next_counter =3D (fep->next_counter + fep->reload_period) & @@ -813,8 +813,8 @@ void fec_ptp_save_state(struct fec_enet_private *fep) fep->ptp_saved_state.ns_phc =3D timecounter_read(&fep->tc); fep->ptp_saved_state.ns_sys =3D ktime_get_ns(); =20 - fep->ptp_saved_state.at_corr =3D readl(fep->hwp + FEC_ATIME_CORR); - atime_inc_corr =3D readl(fep->hwp + FEC_ATIME_INC) & FEC_T_INC_CORR_MASK; + fep->ptp_saved_state.at_corr =3D fec_readl(fep->hwp + FEC_ATIME_CORR); + atime_inc_corr =3D fec_readl(fep->hwp + FEC_ATIME_INC) & FEC_T_INC_CORR_M= ASK; fep->ptp_saved_state.at_inc_corr =3D (u8)(atime_inc_corr >> FEC_T_INC_COR= R_OFFSET); =20 spin_unlock_irqrestore(&fep->tmreg_lock, flags); @@ -823,7 +823,7 @@ void fec_ptp_save_state(struct fec_enet_private *fep) /* Restore PTP functionality after a reset */ void fec_ptp_restore_state(struct fec_enet_private *fep) { - u32 atime_inc =3D readl(fep->hwp + FEC_ATIME_INC) & FEC_T_INC_MASK; + u32 atime_inc =3D fec_readl(fep->hwp + FEC_ATIME_INC) & FEC_T_INC_MASK; unsigned long flags; u32 counter; u64 ns; @@ -833,13 +833,13 @@ void fec_ptp_restore_state(struct fec_enet_private *f= ep) /* Reset turned it off, so adjust our status flag */ fep->pps_enable =3D 0; =20 - writel(fep->ptp_saved_state.at_corr, fep->hwp + FEC_ATIME_CORR); + fec_writel(fep->ptp_saved_state.at_corr, fep->hwp + FEC_ATIME_CORR); atime_inc |=3D ((u32)fep->ptp_saved_state.at_inc_corr) << FEC_T_INC_CORR_= OFFSET; - writel(atime_inc, fep->hwp + FEC_ATIME_INC); + fec_writel(atime_inc, fep->hwp + FEC_ATIME_INC); =20 ns =3D ktime_get_ns() - fep->ptp_saved_state.ns_sys + fep->ptp_saved_stat= e.ns_phc; counter =3D ns & fep->cc.mask; - writel(counter, fep->hwp + FEC_ATIME); + fec_writel(counter, fep->hwp + FEC_ATIME); timecounter_init(&fep->tc, &fep->cc, ns); =20 spin_unlock_irqrestore(&fep->tmreg_lock, flags); --=20 2.54.0 From nobody Sat Jun 13 16:18:26 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E56F233E377; Tue, 9 Jun 2026 14:26:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781015219; cv=none; b=DLkX8zGGINlSSMXrA+zdmvm5I6SDqRCpRx9vWGCSXmNeevpWbMFgVpTmcTJf3PQAUtE0YY42cQ4c5hC352TMxLM6VmVWPsuO61Gewq+4b3Q9nZn+bqrBJJGM3o5zN2MA3ToISRBCHJQ2onu4/EKtLeCdUelBKD4Y7OGgv2ES2D4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781015219; c=relaxed/simple; bh=7hp/UOb4cP9+2Ta+q1UxShiAHGLDd0VAZhe5AMhowmA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=HUxqY4P+fxgQYBRZQfhJbwIxS+RwfkBDzXktpJktOv6jeTPsHrAy/A8YKID/nu8rvWxhz0/QAM414Bg6OTukZWPhKkr67EwE4JYe6jSue9vTzF93KNda0Z9i4k5CSpZ2RrHAYnl5U9AInNjjDuNnUSD/JXzgMLijfwrIzOWgpy8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0C0121F00893; Tue, 9 Jun 2026 14:26:54 +0000 (UTC) From: Greg Ungerer To: linux-m68k@lists.linux-m68k.org Cc: linux-kernel@vger.kernel.org, arnd@kernel.org, wei.fang@nxp.com, frank.li@nxp.com, shenwei.wang@nxp.com, imx@lists.linux.dev, netdev@vger.kernel.org, nico@fluxnic.net, adureghello@baylibre.com, ulfh@kernel.org, linux-mmc@vger.kernel.org, linux-can@vger.kernel.org, linux-spi@vger.kernel.org, olteanv@gmail.com, Greg Ungerer Subject: [PATCHv2 2/4] net: smc91x: do not use readw()/writew() on ColdFire platforms Date: Wed, 10 Jun 2026 00:12:59 +1000 Message-ID: <20260609142139.1563360-4-gerg@linux-m68k.org> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260609142139.1563360-1-gerg@linux-m68k.org> References: <20260609142139.1563360-1-gerg@linux-m68k.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Modify the access macros and functions used to access the smsc hardware registers when used on ColdFire SoC platforms so they do not use readw() or writew(), or derived functions like ioread16be() and iowrite16be(). The current set of readX()/writeX() access methods for ColdFire have historically been non-standard, in that they mostly access memory big-endian instead of the expected little-endian. Before fixing the ColdFire readX() and writeX() supporting code to properly work with little-endian data existing driver uses need to be fixed. Convert the smsc driver ColdFire uses of these to use the raw access macros - which are well defined to be (native) big-endian on ColdFire. This change requires some byte swapping at time of access to retain existing correct behavior. Signed-off-by: Greg Ungerer --- v2: changed from RFC to PATCH drivers/net/ethernet/smsc/smc91x.h | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/net/ethernet/smsc/smc91x.h b/drivers/net/ethernet/smsc= /smc91x.h index 38aa4374e813..1290335629c1 100644 --- a/drivers/net/ethernet/smsc/smc91x.h +++ b/drivers/net/ethernet/smsc/smc91x.h @@ -142,22 +142,26 @@ static inline void _SMC_outw_align4(u16 val, void __i= omem *ioaddr, int reg, #define SMC_CAN_USE_32BIT 0 #define SMC_NOWAIT 1 =20 +/* + * Access SMSC device registers using raw IO access primitives. Byte + * swap as required for device registers, but not data. + */ static inline void mcf_insw(void __iomem *a, unsigned char *p, int l) { u16 *wp =3D (u16 *) p; while (l-- > 0) - *wp++ =3D readw(a); + *wp++ =3D __raw_readw(a); } =20 static inline void mcf_outsw(void __iomem *a, unsigned char *p, int l) { u16 *wp =3D (u16 *) p; while (l-- > 0) - writew(*wp++, a); + __raw_writew(*wp++, a); } =20 -#define SMC_inw(a, r) ioread16be((a) + (r)) -#define SMC_outw(lp, v, a, r) iowrite16be(v, (a) + (r)) +#define SMC_inw(a, r) swab16(__raw_readw((a) + (r))) +#define SMC_outw(lp, v, a, r) __raw_writew(swab16(v), (a) + (r)) #define SMC_insw(a, r, p, l) mcf_insw(a + r, p, l) #define SMC_outsw(a, r, p, l) mcf_outsw(a + r, p, l) =20 --=20 2.54.0 From nobody Sat Jun 13 16:18:26 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DB652340405; Tue, 9 Jun 2026 14:27:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781015232; cv=none; b=IB0wNxhkHX0ZnWuQo+pgeSjBJ97x1j6n8UBqG+1FLB69h9fu/A2nhzf4fPSlkP4zLuwE/KJ+JXITir/Vh7gTahtOGzeJLjeo19BjsY3y6J9zcSXzv8eirWRZWAEX+1yq5veursNOjybA0UDKcn0s+Ex6cJ/1JGPoBY67Hy33NRg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781015232; c=relaxed/simple; bh=rzc75Une4XksouE+EJDTAmNaO9mGZSpp85vUi5ihuoM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=HUIhR2+/Ex+S/s4fyf8uglk+vHp3RwX8bQ29iHs4cEAN6a+Wxlwzl8Y41dxHmbGN4zyHcmNiNHTN8nHcE3B8hXxnXTa1zVHcvLGwfUd+s79xIUYElJEnA3lnhOerosgRlQCk6PDSJYOUfFdDSN79p6ordh3XptyuWaSjbyPLiao= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 Received: by smtp.kernel.org (Postfix) with ESMTPSA id 3B1F71F00898; Tue, 9 Jun 2026 14:27:07 +0000 (UTC) From: Greg Ungerer To: linux-m68k@lists.linux-m68k.org Cc: linux-kernel@vger.kernel.org, arnd@kernel.org, wei.fang@nxp.com, frank.li@nxp.com, shenwei.wang@nxp.com, imx@lists.linux.dev, netdev@vger.kernel.org, nico@fluxnic.net, adureghello@baylibre.com, ulfh@kernel.org, linux-mmc@vger.kernel.org, linux-can@vger.kernel.org, linux-spi@vger.kernel.org, olteanv@gmail.com, Greg Ungerer Subject: [PATCHv2 3/4] mmc: sdhci-esdhc-mcf: do not use readl()/writel() on ColdFire Date: Wed, 10 Jun 2026 00:13:00 +1000 Message-ID: <20260609142139.1563360-5-gerg@linux-m68k.org> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260609142139.1563360-1-gerg@linux-m68k.org> References: <20260609142139.1563360-1-gerg@linux-m68k.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The implementation of the readX() and writeX() family of IO access functions is non-standard on ColdFire platforms. They check the supplied IO address and will return either big or little endian results based on that check. This is non-standard, they are expected to always return little-endian byte ordered data. Unfortunately this behavior also means that ioreadX()/iowroteX() and their big-endian counter parts ioreadXbe()/iowriteXbe() are wrong. This is now in the process of being cleaned up and fixed. Change the use of the readX() and writeX() access functions in this driver to use the recently defined specific ColdFire internal SoC hardware IO access functions mcf_read8()/mcf_read16()/mcf_read32() and mcf_write8()/mcf_write16()/mcf_write32(). There is no functional change to the driver. Though it does have the effect of making the IO access slightly more efficient, since there is no longer a need to do the address check at every register access. Acked-by: Angelo Dureghello Tested-by: Angelo Dureghello Signed-off-by: Greg Ungerer --- v2: moved from RFC to PATCH drivers/mmc/host/sdhci-esdhc-mcf.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/mmc/host/sdhci-esdhc-mcf.c b/drivers/mmc/host/sdhci-es= dhc-mcf.c index 375fce5639d7..6853521e8b2c 100644 --- a/drivers/mmc/host/sdhci-esdhc-mcf.c +++ b/drivers/mmc/host/sdhci-esdhc-mcf.c @@ -55,7 +55,7 @@ static inline void esdhc_clrset_be(struct sdhci_host *hos= t, if (reg =3D=3D SDHCI_HOST_CONTROL) val |=3D ESDHC_PROCTL_D3CD; =20 - writel((readl(base) & ~mask) | val, base); + mcf_write32((mcf_read32(base) & ~mask) | val, base); } =20 /* @@ -71,7 +71,7 @@ static void esdhc_mcf_writeb_be(struct sdhci_host *host, = u8 val, int reg) if (reg =3D=3D SDHCI_HOST_CONTROL) { u32 host_ctrl =3D ESDHC_DEFAULT_HOST_CONTROL; u8 dma_bits =3D (val & SDHCI_CTRL_DMA_MASK) >> 3; - u8 tmp =3D readb(host->ioaddr + SDHCI_HOST_CONTROL + 1); + u8 tmp =3D mcf_read8(host->ioaddr + SDHCI_HOST_CONTROL + 1); =20 tmp &=3D ~0x03; tmp |=3D dma_bits; @@ -82,12 +82,12 @@ static void esdhc_mcf_writeb_be(struct sdhci_host *host= , u8 val, int reg) */ host_ctrl |=3D val; host_ctrl |=3D (dma_bits << 8); - writel(host_ctrl, host->ioaddr + SDHCI_HOST_CONTROL); + mcf_write32(host_ctrl, host->ioaddr + SDHCI_HOST_CONTROL); =20 return; } =20 - writel((readl(base) & mask) | (val << shift), base); + mcf_write32((mcf_read32(base) & mask) | (val << shift), base); } =20 static void esdhc_mcf_writew_be(struct sdhci_host *host, u16 val, int reg) @@ -110,24 +110,24 @@ static void esdhc_mcf_writew_be(struct sdhci_host *ho= st, u16 val, int reg) * As for the fsl driver, * we have to set the mode in a single write here. */ - writel(val << 16 | mcf_data->aside, + mcf_write32(val << 16 | mcf_data->aside, host->ioaddr + SDHCI_TRANSFER_MODE); return; } =20 - writel((readl(base) & mask) | (val << shift), base); + mcf_write32((mcf_read32(base) & mask) | (val << shift), base); } =20 static void esdhc_mcf_writel_be(struct sdhci_host *host, u32 val, int reg) { - writel(val, host->ioaddr + reg); + mcf_write32(val, host->ioaddr + reg); } =20 static u8 esdhc_mcf_readb_be(struct sdhci_host *host, int reg) { if (reg =3D=3D SDHCI_HOST_CONTROL) { u8 __iomem *base =3D host->ioaddr + (reg & ~3); - u16 val =3D readw(base + 2); + u16 val =3D mcf_read16(base + 2); u8 dma_bits =3D (val >> 5) & SDHCI_CTRL_DMA_MASK; u8 host_ctrl =3D val & 0xff; =20 @@ -137,7 +137,7 @@ static u8 esdhc_mcf_readb_be(struct sdhci_host *host, i= nt reg) return host_ctrl; } =20 - return readb(host->ioaddr + (reg ^ 0x3)); + return mcf_read8(host->ioaddr + (reg ^ 0x3)); } =20 static u16 esdhc_mcf_readw_be(struct sdhci_host *host, int reg) @@ -149,14 +149,14 @@ static u16 esdhc_mcf_readw_be(struct sdhci_host *host= , int reg) if (reg =3D=3D SDHCI_HOST_VERSION) reg -=3D 2; =20 - return readw(host->ioaddr + (reg ^ 0x2)); + return mcf_read16(host->ioaddr + (reg ^ 0x2)); } =20 static u32 esdhc_mcf_readl_be(struct sdhci_host *host, int reg) { u32 val; =20 - val =3D readl(host->ioaddr + reg); + val =3D mcf_read32(host->ioaddr + reg); =20 /* * RM (25.3.9) sd pin clock must never exceed 25Mhz. @@ -245,7 +245,7 @@ static void esdhc_mcf_pltfm_set_clock(struct sdhci_host= *host, * fvco =3D fsys * outdvi1 + 1 * fshdc =3D fvco / outdiv3 + 1 */ - temp =3D readl(pll_dr); + temp =3D mcf_read32(pll_dr); fsys =3D pltfm_host->clock; fvco =3D fsys * ((temp & 0x1f) + 1); fesdhc =3D fvco / (((temp >> 10) & 0x1f) + 1); --=20 2.54.0 From nobody Sat Jun 13 16:18:26 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B352434D3B5; Tue, 9 Jun 2026 14:27:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781015238; cv=none; b=JVyz4dI3tb+TOFyFlYHuVntsPAaqx/QSKm+soKrSc9lPgtnfiVqSUdKFOmXBgxlqm5B20IWk0XRqrtzBqEqHHcLbhZyjOVZmSjo9FRAzAR774xLBO+EjRfbLG/NQREK1gJliBHoab1Jz4sCnkk4IhT5OU37sapxCFr6viAIhbn0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781015238; c=relaxed/simple; bh=nB6yR+5lHkcKXtcSPQmcAn47ObOmCovFrFplIEFItSw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=OEdAVKjwEd9qtAqWmLoOyGzZJzqxenerF5zhhu2ijVk7IVPeXhFBwCMUK3zN+LQLtZIkm3Hu+TtY0l4S+syceub+nAlSUy8DN0FA5tWn+wtT/7VfPGE5dVoNbhE32AAqCj3U7x4TVdD7rxr6WOphQtYHsm8hWZCB2D12x1ahN0o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 Received: by smtp.kernel.org (Postfix) with ESMTPSA id 91A421F00893; Tue, 9 Jun 2026 14:27:12 +0000 (UTC) From: Greg Ungerer To: linux-m68k@lists.linux-m68k.org Cc: linux-kernel@vger.kernel.org, arnd@kernel.org, wei.fang@nxp.com, frank.li@nxp.com, shenwei.wang@nxp.com, imx@lists.linux.dev, netdev@vger.kernel.org, nico@fluxnic.net, adureghello@baylibre.com, ulfh@kernel.org, linux-mmc@vger.kernel.org, linux-can@vger.kernel.org, linux-spi@vger.kernel.org, olteanv@gmail.com, Greg Ungerer , Marc Kleine-Budde Subject: [PATCHv2 4/4] m68k: coldfire: fix non-standard readX()/writeX() functions Date: Wed, 10 Jun 2026 00:13:01 +1000 Message-ID: <20260609142139.1563360-6-gerg@linux-m68k.org> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260609142139.1563360-1-gerg@linux-m68k.org> References: <20260609142139.1563360-1-gerg@linux-m68k.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Remove the local ColdFire definitions of readb()/readw()/readl() and writeb()/writew()/writel() and use the asm-generic versions of them. The implementation of the readX()/writeX() family of IO access functions is non-standard on ColdFire platforms. They either return big-endian (that is native endian) data, or on platforms with PCI bus support check the supplied address and return either big or little endian data based on that check. This is non-standard, they are expected to always return little-endian byte ordered data. Unfortunately this behavior also means that ioreadX()/iowroteX() and their big-endian counter parts ioreadXbe()/iowriteXbe() are currently broken because they are implemented using the readX()/writeX() functions. The change to use the asm-generic versions of readX()/writeX() itself is quite strait forward, just remove the ColdFire local versions of them. But this of course has implications for any remaining drivers that use any of these IO access functions. A number of drivers can be independently fixed, before this final fix to readX()/writeX() for ColdFire. A small number of drivers cannot easily be independently fixed and remain in a working state. Those drivers are fixed here as well: drivers/dma/mcf-edma-main.c Supports big-endian access by setting the big-endian flag of the drivers struct fsl_edma_engine. But locally should be using ioread32be() and iowrite32be() instead of ioread32() and iowrite32(). drivers/net/can/flexcan/flexcan-core.c Setting the driver quirks flag for big-endian access will force driver to use correct access functions. drivers/spi/spi-fsl-dspi.c Setting the regmap format_endian flags to use native endian will force driver to use appropriate big or little endian access on whatever platform it is built for. These drivers have only been compile tested. Acked-by: Marc Kleine-Budde # for drivers/net/can/flex= can Signed-off-by: Greg Ungerer Reviewed-by: Frank Li --- v2: changed from RFC to PATCH use separate regmap config for mcf5441x (spi-fsl-dspi.c) reorder quirks for mcf5441x (flexcan-core.c) arch/m68k/include/asm/io_no.h | 68 +++----------------------- drivers/dma/mcf-edma-main.c | 14 +++--- drivers/net/can/flexcan/flexcan-core.c | 1 + drivers/spi/spi-fsl-dspi.c | 14 +++++- 4 files changed, 27 insertions(+), 70 deletions(-) diff --git a/arch/m68k/include/asm/io_no.h b/arch/m68k/include/asm/io_no.h index 4f0f34b06e37..2f12f4ed0da5 100644 --- a/arch/m68k/include/asm/io_no.h +++ b/arch/m68k/include/asm/io_no.h @@ -3,15 +3,10 @@ #define _M68KNOMMU_IO_H =20 /* - * Convert a physical memory address into a IO memory address. - * For us this is trivially a type cast. - */ -#define iomem(a) ((void __iomem *) (a)) - -/* - * The non-MMU m68k and ColdFire IO and memory mapped hardware access - * functions have always worked in CPU native endian. We need to define - * that behavior here first before we include asm-generic/io.h. + * Historically the raw native endian IO access macros for non-MMU m68k and + * ColdFire have accepted any integral value as the address argument. + * The asm-generic versions of these expect "void __iomem *" for the addre= ss, + * so define local permissive versions here. */ #define __raw_readb(addr) \ ({ u8 __v =3D (*(__force volatile u8 *) (addr)); __v; }) @@ -45,66 +40,15 @@ * applies just the same of there is no MMU but something like a PCI bus * is present. */ -static int __cf_internalio(unsigned long addr) +static inline int __cf_internalio(unsigned long addr) { return (addr >=3D IOMEMBASE) && (addr <=3D IOMEMBASE + IOMEMSIZE - 1); } =20 -static int cf_internalio(const volatile void __iomem *addr) +static inline int cf_internalio(const volatile void __iomem *addr) { return __cf_internalio((unsigned long) addr); } - -/* - * We need to treat built-in peripherals and bus based address ranges - * differently. Local built-in peripherals (and the ColdFire SoC parts - * have quite a lot of them) are always native endian - which is big - * endian on m68k/ColdFire. Bus based address ranges, like the PCI bus, - * are accessed little endian - so we need to byte swap those. - */ -#define readw readw -static inline u16 readw(const volatile void __iomem *addr) -{ - if (cf_internalio(addr)) - return __raw_readw(addr); - return swab16(__raw_readw(addr)); -} - -#define readl readl -static inline u32 readl(const volatile void __iomem *addr) -{ - if (cf_internalio(addr)) - return __raw_readl(addr); - return swab32(__raw_readl(addr)); -} - -#define writew writew -static inline void writew(u16 value, volatile void __iomem *addr) -{ - if (cf_internalio(addr)) - __raw_writew(value, addr); - else - __raw_writew(swab16(value), addr); -} - -#define writel writel -static inline void writel(u32 value, volatile void __iomem *addr) -{ - if (cf_internalio(addr)) - __raw_writel(value, addr); - else - __raw_writel(swab32(value), addr); -} - -#else - -#define readb __raw_readb -#define readw __raw_readw -#define readl __raw_readl -#define writeb __raw_writeb -#define writew __raw_writew -#define writel __raw_writel - #endif /* IOMEMBASE */ =20 #if defined(CONFIG_COLDFIRE) diff --git a/drivers/dma/mcf-edma-main.c b/drivers/dma/mcf-edma-main.c index 9e1c6400c77b..4ed0ce644e37 100644 --- a/drivers/dma/mcf-edma-main.c +++ b/drivers/dma/mcf-edma-main.c @@ -21,9 +21,9 @@ static irqreturn_t mcf_edma_tx_handler(int irq, void *dev= _id) unsigned int ch; u64 intmap; =20 - intmap =3D ioread32(regs->inth); + intmap =3D ioread32be(regs->inth); intmap <<=3D 32; - intmap |=3D ioread32(regs->intl); + intmap |=3D ioread32be(regs->intl); if (!intmap) return IRQ_NONE; =20 @@ -43,7 +43,7 @@ static irqreturn_t mcf_edma_err_handler(int irq, void *de= v_id) struct edma_regs *regs =3D &mcf_edma->regs; unsigned int err, ch; =20 - err =3D ioread32(regs->errl); + err =3D ioread32be(regs->errl); if (!err) return IRQ_NONE; =20 @@ -55,7 +55,7 @@ static irqreturn_t mcf_edma_err_handler(int irq, void *de= v_id) } } =20 - err =3D ioread32(regs->errh); + err =3D ioread32be(regs->errh); if (!err) return IRQ_NONE; =20 @@ -203,8 +203,8 @@ static int mcf_edma_probe(struct platform_device *pdev) edma_write_tcdreg(mcf_chan, cpu_to_le32(0), csr); } =20 - iowrite32(~0, regs->inth); - iowrite32(~0, regs->intl); + iowrite32be(~0, regs->inth); + iowrite32be(~0, regs->intl); =20 ret =3D mcf_edma->drvdata->setup_irq(pdev, mcf_edma); if (ret) @@ -248,7 +248,7 @@ static int mcf_edma_probe(struct platform_device *pdev) } =20 /* Enable round robin arbitration */ - iowrite32(EDMA_CR_ERGA | EDMA_CR_ERCA, regs->cr); + iowrite32be(EDMA_CR_ERGA | EDMA_CR_ERCA, regs->cr); =20 return 0; } diff --git a/drivers/net/can/flexcan/flexcan-core.c b/drivers/net/can/flexc= an/flexcan-core.c index f5d22c61503f..f0571b97817b 100644 --- a/drivers/net/can/flexcan/flexcan-core.c +++ b/drivers/net/can/flexcan/flexcan-core.c @@ -295,6 +295,7 @@ static_assert(sizeof(struct flexcan_regs) =3D=3D 0x4 *= 18 + 0xfb8); =20 static const struct flexcan_devtype_data fsl_mcf5441x_devtype_data =3D { .quirks =3D FLEXCAN_QUIRK_BROKEN_PERR_STATE | + FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN | FLEXCAN_QUIRK_NR_IRQ_3 | FLEXCAN_QUIRK_NR_MB_16 | FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX | FLEXCAN_QUIRK_SUPPORT_RX_FIFO, diff --git a/drivers/spi/spi-fsl-dspi.c b/drivers/spi/spi-fsl-dspi.c index 9f2a7b8163b1..abd3b20c2f17 100644 --- a/drivers/spi/spi-fsl-dspi.c +++ b/drivers/spi/spi-fsl-dspi.c @@ -192,6 +192,7 @@ enum { DSPI_XSPI_REGMAP, S32G_DSPI_XSPI_REGMAP, DSPI_PUSHR, + MCF5441X_DSPI_REGMAP, }; =20 static const struct regmap_config dspi_regmap_config[] =3D { @@ -238,6 +239,17 @@ static const struct regmap_config dspi_regmap_config[]= =3D { .reg_stride =3D 2, .max_register =3D 0x2, }, + [MCF5441X_DSPI_REGMAP] =3D { + .reg_bits =3D 32, + .val_bits =3D 32, + .reg_stride =3D 4, + .max_register =3D SPI_RXFR3, + .volatile_table =3D &dspi_volatile_table, + .rd_table =3D &dspi_access_table, + .wr_table =3D &dspi_access_table, + .reg_format_endian =3D REGMAP_ENDIAN_BIG, + .val_format_endian =3D REGMAP_ENDIAN_BIG, + }, }; =20 static const struct fsl_dspi_devtype_data devtype_data[] =3D { @@ -303,7 +315,7 @@ static const struct fsl_dspi_devtype_data devtype_data[= ] =3D { .trans_mode =3D DSPI_DMA_MODE, .max_clock_factor =3D 8, .fifo_size =3D 16, - .regmap =3D &dspi_regmap_config[DSPI_REGMAP], + .regmap =3D &dspi_regmap_config[MCF5441X_DSPI_REGMAP], }, [S32G] =3D { .trans_mode =3D DSPI_XSPI_MODE, --=20 2.54.0