From nobody Wed Jun 10 10:54:38 2026 Received: from CH5PR02CU005.outbound.protection.outlook.com (mail-northcentralusazon11012069.outbound.protection.outlook.com [40.107.200.69]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 36D2A3DD520; Tue, 9 Jun 2026 07:32:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.200.69 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780990352; cv=fail; b=tXD2tFhG5xmeAAvjUm3uORGBQdJryMacQiDbs0KzXXOZqBOdvzHo2zC6tj7XfH+0pbFeo/ssX9xTYHWNeYHGz5X+e/2w9COi4DiTJTShb/rFjuullwLE0RZNiBJlgSj8G5yJIMxqjAHbniNac3mcIVOBqIZ3n0hdVyPm3EHTJpg= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780990352; c=relaxed/simple; bh=P57JaIwr2rey1zM8IhJtDwke61H0X1LW7taNqpoLcb8=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=lqtR2sWyfsLLIPD/2cuDCXOQTy+84cYhm68yMyKloO736xyLo8ZTI9Jybwt0oLo8oG/HHQ3RXm5V/p+HZmYR9ZwrPAcf5ncVd/MriomLSp68mcaewbvziXfsRFwYA0tiN07Y/IoIe36WQXeXjcCtQiVKJaAjhsSSd20qNg9+Lfk= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=GRAfGLrc; arc=fail smtp.client-ip=40.107.200.69 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="GRAfGLrc" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=tKqEVhJeOrQZ+5cr7VB/Qex4NSzF8g6ZHGTGw9sazPcjDwwKjaWvcnlutHxOOOct8pbKuQG+kUiTfrcBWuhL50Lg0hc/mvf3yXRYvxeDHA2KUdPTOULjFfEDQf3oK+vj4SDdm4jRNu6zNi5NJvTB5u7H/c4zxM6t844+zZKWsay1k9gJ0cYvLvqm+ODnBf1CLr1sQ6fTzRKz1ppo3TFRcBXd7KA2huB8RPNM5wNQ0+Xu6k3HjoG8HuJWKmlioCAoGsT4UyTZvnt/NIbd1AYnAvakilLbDNS+tQ9nx0Sg7x6wrwy4h0wlfLhy38oCrZq4y+n4C3Kq38Pu17CcBHkwIA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=1jaMPIM6KX+UST2o1FwG6tW3QIGROy+dkeeNMng5ZTg=; b=sAv8qz8vu2hwtq6mc0CqBiYSs4lIHMXkJmj/TevaRGbuUV3dGjDoMFf8a5l7xzFwDvqT7Wd8/VrCLh4G4z53/VM9JK1jIkwZWl0YjMVhQZPDJDbgIXCOeQJT/kb8fjNXQdQ8f3n+9UPVzLY69hu2eYxIy3gLoXhXP8mfGcA0iSuhuz3rv3xYiY/l48UDnuBJgTQX44mQcJHZYaqcSS/NjDVLY1PZ6BVFW5R8I81kVtr5UVxi+yU30xfbl56dxKBqW/kOXpFDHeCMxEhQArbbRqn4BBtRH7lUBUZMAmFYjZq9T6kV0HeJsKdUsceWULyAdzwfZaSOcSAFkG/1ehM+NA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=1jaMPIM6KX+UST2o1FwG6tW3QIGROy+dkeeNMng5ZTg=; b=GRAfGLrcHuYRveSRpsTkoYdtySkdBXhf1Hd0Xm/aMi7JKQkRKuCYv8P301hVeJV+/RajFaWlwR/HRHQH4b76Pw/P8Tk5rMh/hqtFa6qERiX2Awwn09NWo3X7hMEsIRMI2TzLI2Dfp8Dun2q590M/kVYkiEOJSZJpz3lE9Zw3wsP+v9XXNxqcRiAwszOCQ3KR/uG9/crgtE6I6kP6UZpnepJVKCKpSg1EinjbxFMuGvY8b/LL04EIcVQu4WbfY2jSaS+Jp0uXPLchYQVf388OjvrV+ttO5WyEHfpV/CtVFAdlkOw8Ynck1gGmLmFA9ej6YKGLz/V19u1f8PFgJIonHA== Received: from SJ0PR03CA0342.namprd03.prod.outlook.com (2603:10b6:a03:39c::17) by PH0PR12MB7816.namprd12.prod.outlook.com (2603:10b6:510:28c::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.92.12; Tue, 9 Jun 2026 07:32:26 +0000 Received: from CO1PEPF000066ED.namprd05.prod.outlook.com (2603:10b6:a03:39c:cafe::64) by SJ0PR03CA0342.outlook.office365.com (2603:10b6:a03:39c::17) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.92.14 via Frontend Transport; Tue, 9 Jun 2026 07:32:26 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by CO1PEPF000066ED.mail.protection.outlook.com (10.167.249.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.113.7 via Frontend Transport; Tue, 9 Jun 2026 07:32:25 +0000 Received: from rnnvmail205.nvidia.com (10.129.68.10) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 9 Jun 2026 00:32:08 -0700 Received: from rnnvmail201.nvidia.com (10.129.68.8) by rnnvmail205.nvidia.com (10.129.68.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 9 Jun 2026 00:32:07 -0700 Received: from build-amhetre-focal-20250829.internal (10.127.8.12) by mail.nvidia.com (10.129.68.8) with Microsoft SMTP Server id 15.2.2562.20 via Frontend Transport; Tue, 9 Jun 2026 00:32:07 -0700 From: Ashish Mhetre To: , , , , CC: , , , , Ashish Mhetre Subject: [PATCH v4 1/3] iommu/arm-smmu-v3: Factor out CMDQ batch force-sync conditions Date: Tue, 9 Jun 2026 07:32:02 +0000 Message-ID: <20260609073204.1760077-2-amhetre@nvidia.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260609073204.1760077-1-amhetre@nvidia.com> References: <20260609073204.1760077-1-amhetre@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000066ED:EE_|PH0PR12MB7816:EE_ X-MS-Office365-Filtering-Correlation-Id: 40360114-49cb-4c6e-6334-08dec5f940f9 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|1800799024|82310400026|376014|18002099003|22082099003|56012099006|11063799006; X-Microsoft-Antispam-Message-Info: Dd3g0kLTBXy476Q9C+TnkhYrps6CEAKZkO0taHIcaQBIrGoPcbjV0SYzok7f+UyLGu+fWE4TtWh4Q0RQyviPMuSf4ye6aHxLZzo63CvIUd+A8ft5hd3IjE1pdRf1eMuga7BLmaJqEJ+l8njyRDjhn9yMpamjnuwVHJiH80yOtoaJ1QX/tLflZDt2mo1pb3XmmkNJunyugT+4USd/r4sc+fKD1JHcnJmI795ofSaSzB75mb/AluXB7DNPnW4sMc7rqSDAPDb0pOqcSEpe5yBaZQFlKvo+QUP2uW0luAWrXdvHyVFsMfnoG0Y1qPDdL2gNb7nlfGBgm8blESI4KO2s6tlxQ5YUWPhDYUhszfwkKlpTHcrbGb8LGYM7ouKqYgk8gMrOLqGlYtrQvwsyQ1qJX/Gy6AmKT9cnY602sHr4GqDsCOiK3y/5PSwS3y20D2aFs2wAIEa49vTsIudcZpqrEf1FR5/RD1MRnW7wUOfI0ygePwgxbHNsG9C4CDxuMDB0/PQ09PBJhrDXSlExlDHxJGSlOT5iT7IHefhA3jT33LuVSWVqN7EzhhrGGmhqQuohodBBaeU7IE4/G1Fxi8NCiKyrtqK5nxAgj6hYPDgcjy5wC6YIyAMzph8o54cEWAVMRQalihiOlNLZzjXOEIUQgMNqhPop8THJKyTPHTfABS/vOn2e+oG0q17wXGl2z2TJT/mEiWzZHFT/1ge1YUVo4Prjq8hAp6+cdIuZqQEyjaE= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700016)(1800799024)(82310400026)(376014)(18002099003)(22082099003)(56012099006)(11063799006);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 8+Eu2dZ//Jz3OHYYzLYbdt0ADHDhoAUqX2LBC/4OLAYE3M7Ly3aNreX/02DHSYiFLXl65CekPj22y4d2yfkoasHPgMZ9a9DTjGXzIl+5Ovm62FxHM5rvSUBUUlvqQBjeUWnFDgh6QNuI8Ia/nTSWuZ9WEwsG5wh8BwRrxGz3PP82sU+V+xOZcjUJwoSm+WH4V90l4nJ+hEeRTeNT0WqOvAu+dHPZ+rtBxvwd5tfhevrRthW6qW5luiQj62XbR78CrdfF4AIsSP8XhlV4maZGkU2159AsfuCl8jWvNZpe/muoqq23W5B97AnnFxC6slLJzlnHFL/jYpZtApNeP7KJUXXBer0HhiFqdWYvWibC+sDM9DMX9VAmEQUNEcM5G5BQJvBTYsNBhdTiuNTu1gf/GmuqW/beLWYJTYwIaIvf9XYaYklAmdH7j9FdWT5V4/qS X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Jun 2026 07:32:25.9798 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 40360114-49cb-4c6e-6334-08dec5f940f9 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000066ED.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB7816 Content-Type: text/plain; charset="utf-8" From: Nicolin Chen arm_smmu_cmdq_batch_add_cmd_p() carries two distinct reasons for flushing the current batch with a CMD_SYNC before appending the new command: - The batch's pre-assigned cmdq does not support the new command. - The Arm erratum 2812531 workaround (ARM_SMMU_OPT_CMDQ_FORCE_SYNC) forces a SYNC at one entry before the batch is full. Lift those checks into a new arm_smmu_cmdq_batch_force_sync() helper so that adding another force-sync condition becomes a one-line addition. No functional change. Signed-off-by: Nicolin Chen Signed-off-by: Ashish Mhetre --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 23 +++++++++++++++------ 1 file changed, 17 insertions(+), 6 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index a10affb483a4..76efe479e80f 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -847,16 +847,27 @@ static void arm_smmu_cmdq_batch_init_cmd(struct arm_s= mmu_device *smmu, cmds->cmdq =3D arm_smmu_get_cmdq(smmu, cmd); } =20 +static bool arm_smmu_cmdq_batch_force_sync(struct arm_smmu_device *smmu, + struct arm_smmu_cmdq_batch *cmds, + struct arm_smmu_cmd *cmd) +{ + /* The batch's pre-assigned cmdq doesn't support the new command */ + if (!arm_smmu_cmdq_supports_cmd(cmds->cmdq, cmd)) + return true; + + /* Arm erratum 2812531 */ + if (cmds->num =3D=3D CMDQ_BATCH_ENTRIES - 1 && + (smmu->options & ARM_SMMU_OPT_CMDQ_FORCE_SYNC)) + return true; + + return false; +} + static void arm_smmu_cmdq_batch_add_cmd_p(struct arm_smmu_device *smmu, struct arm_smmu_cmdq_batch *cmds, struct arm_smmu_cmd *cmd) { - bool force_sync =3D (cmds->num =3D=3D CMDQ_BATCH_ENTRIES - 1) && - (smmu->options & ARM_SMMU_OPT_CMDQ_FORCE_SYNC); - bool unsupported_cmd; - - unsupported_cmd =3D !arm_smmu_cmdq_supports_cmd(cmds->cmdq, cmd); - if (force_sync || unsupported_cmd) { + if (arm_smmu_cmdq_batch_force_sync(smmu, cmds, cmd)) { arm_smmu_cmdq_issue_cmdlist(smmu, cmds->cmdq, cmds->cmds, cmds->num, true); arm_smmu_cmdq_batch_init_cmd(smmu, cmds, cmd); --=20 2.50.1 From nobody Wed Jun 10 10:54:38 2026 Received: from SN4PR2101CU001.outbound.protection.outlook.com (mail-southcentralusazon11012047.outbound.protection.outlook.com [40.93.195.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 57A9D3164B7; Tue, 9 Jun 2026 07:32:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.93.195.47 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780990351; cv=fail; b=Z6xnAfYUdt1XsuZfsbWPcNJHQx8sb8qaDAs6PseXvwyNZKgJ4z2rEBZjZWxjLc1mg9u/p77MIp3tey6E8Q5+QjezYPkNnhmdbOY0j5tJnDGrvH8fSp2K+IitgPuW0Rvxh0vZLdLdEPVAc42B0uik/xsLRouDorgtKA/ULXUeFNA= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780990351; c=relaxed/simple; bh=2Vm/ml7bd1QW/nP8sYXRG6TbXY0yArCHnk/Ka1gaJ9E=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Oi8LsNBNj1Cy+T4ZKylng6rQUlX9Y5stzlyb3R4/28HAzp4ED7GOrMetLlZlwwhtpzS80AcFDXp8iMO5XDYyFP2ZMKysAiYrtRw9ADdGIBeOss8DQCAFz8Vr/r8LEP7qMc3wBBYXjQFrMKgdGg1uSWB8uDyY9BpOGrGLCIENxps= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=tZxXRCvx; arc=fail smtp.client-ip=40.93.195.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="tZxXRCvx" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=cIfs3wenOKaF8jUGJ9+KWQw07FIwkJQxiThES9gCo1aHnrYrD3uRSybpj/CSyRT1mDWZkvsWQM2rGRx+L3fvGSH/STiu/imxqvD8pDoyjQFBozp7DtUiZ1pp23Ysv33FcJXKfEPYvPj3WTJHubtBh8vne7rhiPyLe61E8QLCiTsTvwxnILvrn5Oo45rLUY08qJavXfMqpIud+3Kupws4YyWFKYs64ITlW2qd833mG8yJLs2g9mw2P9YL3kmSfJkAFvvndgTRt54r3aozLR2eSI5eqJfv46+CGgXqYhJi1TMuq+n1YwGvBuuHaTzHcKdm2+Xi3dZoW1gEDwedWFv0sw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=19+vKjac78PiQVFTITr8mXZO4eaZtGjK32u1Hpqwbf0=; b=Po1tZSNQRjLskVNBFLbrdVG7lJd4RVSgnPfMOGOSCQjzOuahTTHycGnUvaNyRNm08iFQ0sunBnaHymCMPEeMV3taHEJn2EYO8LMKU+cQ0VkkADQgO2gzcsxGCTnY1ewIDmix/mXN4SzmST6pgok83/wC+JNTv9/OVm7ChZucmQr0z/VUb+NP6jWPRZcBLPc/TZHVBtySN6k97IaoJzrs3viyLv5srKWMyLWvnxN28QNvpRzaKtR4lLmo6EurbUMSbZgaBLvLVmzcXMpR89a3WLzXxs0XfoxptRkX12kN2tizomiicJrv8VuXyWymdO6V3rpLtFWzQCX1Tz08ImP4Xw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=19+vKjac78PiQVFTITr8mXZO4eaZtGjK32u1Hpqwbf0=; b=tZxXRCvxA0WxofF43Qy/bJxWo/9XaCLDnxvGCH6+sSqmBdTTw3KQNEIQmRAPm9PpzBVTbmhE+2P3EcqGV07gsJGEwXeoePt/FMaQ/t+Cuh15Cu8ke7KNNNLaXkYxGo5vZ948ToYNQ3J5cMY/oI1yRC0zsYmGSHA39txAxiJOj1VgpWG3fEbQq90X4YYreLKc5Z9PC6JCefPacX/pSEcmI1OO5VUP9d2XJVS3dP3yBiIVINHBRJKQmrsnBw9WW4mv2oseDb4V+3rdEqy3SaVV0kdM5SnH/i4mj4cAERH+IL9mz6xeP/UhYo9MmF194LQ3lmMwbAJJMgRUycW1EMN7+w== Received: from MW4PR03CA0350.namprd03.prod.outlook.com (2603:10b6:303:dc::25) by SA1PR12MB6896.namprd12.prod.outlook.com (2603:10b6:806:24f::5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.92.13; Tue, 9 Jun 2026 07:32:25 +0000 Received: from CO1PEPF00012E62.namprd05.prod.outlook.com (2603:10b6:303:dc:cafe::a2) by MW4PR03CA0350.outlook.office365.com (2603:10b6:303:dc::25) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.113.10 via Frontend Transport; Tue, 9 Jun 2026 07:32:25 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by CO1PEPF00012E62.mail.protection.outlook.com (10.167.249.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.113.7 via Frontend Transport; Tue, 9 Jun 2026 07:32:25 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 9 Jun 2026 00:32:09 -0700 Received: from rnnvmail201.nvidia.com (10.129.68.8) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 9 Jun 2026 00:32:08 -0700 Received: from build-amhetre-focal-20250829.internal (10.127.8.12) by mail.nvidia.com (10.129.68.8) with Microsoft SMTP Server id 15.2.2562.20 via Frontend Transport; Tue, 9 Jun 2026 00:32:08 -0700 From: Ashish Mhetre To: , , , , CC: , , , , Ashish Mhetre Subject: [PATCH v4 2/3] iommu/arm-smmu-v3: Detect Tegra264 erratum Date: Tue, 9 Jun 2026 07:32:03 +0000 Message-ID: <20260609073204.1760077-3-amhetre@nvidia.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260609073204.1760077-1-amhetre@nvidia.com> References: <20260609073204.1760077-1-amhetre@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF00012E62:EE_|SA1PR12MB6896:EE_ X-MS-Office365-Filtering-Correlation-Id: 93fa9eed-09dd-49d8-9ddd-08dec5f940ae X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|376014|36860700016|6133799003|18002099003|22082099003|11063799006|56012099006; X-Microsoft-Antispam-Message-Info: fe2RQpATzvRKuIfKw4zYjZHoKrv9U3hjZX69TT7Rm2m5hCsy3Sxn1Lq0OEEn1K3qZ/5foTZVBfoB5eZ+DJtdMjSV/JBIq79TA4VfnnrMGGur8V5VUmzKxc7Nk0wjlHoqq05Tva3ljxnIgZvoWjBhQyuJDgWzv3mRUvviNtF9T5fKTIAUbaRTECAXLq0+SUC6Lr4H2pC6YDbRHcpw6APkIUtt9ZiGJEQuqxLLXF49pqOXTzgc2vDooUsPBcBJebJzeOncNuCyQzLLgf3aLQi2qHyB3LVIiCIx2kiZV5SLOUtgvFC4E0KyS6BVJgQdw7FgoCKhjTqnE82aGGvMtwJJbtVfkNOnQPxTJjxr1BVwW3Bbz0fSE5SCyot73GLHARlr6uJMFPxt3bxDo2L5HdmADNFdMY0o9GY/AUyXGjaNxwmyHk+62si840yyCMa++abW8fzbi+6FeNUu/N8+NOqPjHl4vR4VezbLCPGSbL6RIVBzZsgSdt4Z30cDqJUMuht9FVMZOL1MM1NlDTjPLouZGZoAg7UBikWD3GEB4MGwDyGl6bvOf7XEhLqxd228n5V6NqlJtkqEeq/zLFbsiu05Drc1pdlThbEl9gV+VXYtapQi7r7lixsHbxO5doiZ+a8OFqR7luia3uUC+PQJgK9a2mAMsb3lktzm3zW8uuk7bWJiDQ4W7ZxrfEF2D+9I8esiy8THkjgpko8znBon/72bX+pXNGXl46wJSP7LKiK+sPs= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(376014)(36860700016)(6133799003)(18002099003)(22082099003)(11063799006)(56012099006);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: T5ZH+cSho6hqwHcHAGw9TUGyEsXs73J+XnQb9iPj/J8145pi+fbUoigcQDxnO/AwPNwjQGe/waOXv095R2gHTZ6Eh3mHAqgTPmrPnVqAFRtjgSYKk6IQ/G5Gnl1aC12vFgFMx3fGKjO/HF8fF4wKG9ubNhGl4z3+Sj0ukEcws5cjDJrbWNFaojwH2oyBIfkkWR0znGxre9k8XD5aZ62EUqH+PpsNnJsKxDppXyUlajbKpU9qnhmb42Fxwj3F6sWDRclr5xu0qqY+3S+37vHTXfErLfIHk2mgO6JOW4B2WBK9h6pSdg6FePt4bAb5TJpXC65IQdX5DGUS9P02lRuyzv8rtKca2JMNzV7w1nlIsW1Hpio5nADvbQNe46Wetma7sJD+RUL6L3sycvRZa84acB1utWuLrv4ie5DSwbUh3LJwcGmayF/buf3PPQ4eG9Wu X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Jun 2026 07:32:25.4992 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 93fa9eed-09dd-49d8-9ddd-08dec5f940ae X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF00012E62.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB6896 Content-Type: text/plain; charset="utf-8" Tegra264 SMMU is affected by an erratum where a TLB entry can survive an invalidation that races with concurrent traffic targeting the same entry. The hardware-recommended software workaround is to issue every CFGI/TLBI command (each followed by CMD_SYNC) twice. The second issue is guaranteed to evict the entry. ATC_INV is not affected and must not be doubled. The erratum is not flagged by any SMMUv3 IDR/IIDR register, so it cannot be detected from hardware registers. Tegra264 boots from device tree only and has no ACPI/IORT support, so detection is through device tree only. Add the ARM_SMMU_OPT_REPEAT_TLBI_CFGI option and set it on instances matching the existing "nvidia,tegra264-smmu" compatible. Also add a matching arm_smmu_erratum_repeat_tlbi_cfgi_key static key that DT probe enables, so the inline classifier compiles down to a single test+branch on unaffected kernels. Add an arm_smmu_erratum_cmd_needs_repeating() helper in arm-smmu-v3.h that gates on the static key first and then range-checks the opcode (CFGI_STE .. ATC_INV), so subsequent changes wiring the workaround into the CMDQ submission and iommufd batching paths can share a single predicate. No callers consume the option yet. A subsequent change wires the workaround into the CMDQ issue paths. Signed-off-by: Ashish Mhetre --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 7 +++++- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 24 +++++++++++++++++++++ 2 files changed, 30 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 76efe479e80f..599c835c50d8 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -42,6 +42,8 @@ MODULE_PARM_DESC(disable_msipolling, static const struct iommu_ops arm_smmu_ops; static struct iommu_dirty_ops arm_smmu_dirty_ops; =20 +DEFINE_STATIC_KEY_FALSE(arm_smmu_erratum_repeat_tlbi_cfgi_key); + enum arm_smmu_msi_index { EVTQ_MSI_INDEX, GERROR_MSI_INDEX, @@ -5303,8 +5305,11 @@ static int arm_smmu_device_dt_probe(struct platform_= device *pdev, if (of_dma_is_coherent(dev->of_node)) smmu->features |=3D ARM_SMMU_FEAT_COHERENCY; =20 - if (of_device_is_compatible(dev->of_node, "nvidia,tegra264-smmu")) + if (of_device_is_compatible(dev->of_node, "nvidia,tegra264-smmu")) { tegra_cmdqv_dt_probe(dev->of_node, smmu); + smmu->options |=3D ARM_SMMU_OPT_REPEAT_TLBI_CFGI; + static_branch_enable(&arm_smmu_erratum_repeat_tlbi_cfgi_key); + } =20 return ret; } diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index c909c9a88538..c6ea3b8dc761 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -928,6 +929,12 @@ struct arm_smmu_device { #define ARM_SMMU_OPT_MSIPOLL (1 << 2) #define ARM_SMMU_OPT_CMDQ_FORCE_SYNC (1 << 3) #define ARM_SMMU_OPT_TEGRA241_CMDQV (1 << 4) +/* + * Repeat every {CFGI,TLBI};CMD_SYNC command sequence so that the second + * issue executes only after the first issue's CMD_SYNC has completed. + * Does not apply to ATC_INV. + */ +#define ARM_SMMU_OPT_REPEAT_TLBI_CFGI (1 << 5) u32 options; =20 struct arm_smmu_cmdq cmdq; @@ -1212,6 +1219,23 @@ int arm_smmu_cmdq_issue_cmdlist(struct arm_smmu_devi= ce *smmu, struct arm_smmu_cmd *cmds, int n, bool sync); =20 +DECLARE_STATIC_KEY_FALSE(arm_smmu_erratum_repeat_tlbi_cfgi_key); + +static inline bool +arm_smmu_erratum_cmd_needs_repeating(struct arm_smmu_device *smmu, + struct arm_smmu_cmd *cmd) +{ + u8 opcode; + + if (!static_branch_unlikely(&arm_smmu_erratum_repeat_tlbi_cfgi_key)) + return false; + if (!(smmu->options & ARM_SMMU_OPT_REPEAT_TLBI_CFGI)) + return false; + + opcode =3D FIELD_GET(CMDQ_0_OP, cmd->data[0]); + return opcode >=3D CMDQ_OP_CFGI_STE && opcode < CMDQ_OP_ATC_INV; +} + #ifdef CONFIG_ARM_SMMU_V3_SVA bool arm_smmu_sva_supported(struct arm_smmu_device *smmu); void arm_smmu_sva_notifier_synchronize(void); --=20 2.50.1 From nobody Wed Jun 10 10:54:38 2026 Received: from MW6PR02CU001.outbound.protection.outlook.com (mail-westus2azon11012048.outbound.protection.outlook.com [52.101.48.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4ECFF3DD512; Tue, 9 Jun 2026 07:32:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.48.48 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780990353; cv=fail; b=PvyQosoezO4PyCqqWE8aXIOr/wpymavMxg2iW1lhCvkeWpdxCj1t2Do4QVnH04XIzt8lCGPa8FMOlRwf5TNbdCiMu5xKMI6XoZbxhSqSVMrQA7S38rFSr1mzBXzGRxihgDxryWl997wIEMiWNHUSBCpR2LDRKtiswH1iE+SeCN0= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780990353; c=relaxed/simple; bh=nstEDKDJeZpY50n8TBgy3fAtviCOXofp7+s3EqlLgw4=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=PJYgnj91aSUjgsYozz0FadKqP7xMwQ3m5PWrtWwFxDiWwWWHT0Wc5oSvFMv9smNIhlVdIKL6wf1CDNO9jaYtb5SvfkjWy+asimYIqeA703mxQNn4VJ9jfjs2dEwi1btJplLqn9f/rOJEUbyIz74AuWU3Tdcer9Ng7bt04a9uYak= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=jD/S5Fiu; arc=fail smtp.client-ip=52.101.48.48 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="jD/S5Fiu" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=MA69uYuBQJf25VLf22dMMvXgPPrK0DS/QOeGXeuNCv8f5HakjXZhiXzizdwqV5khEeVq8D9cVSzCrBqdLk2sQgAXjvK8/twDbW9XgLgkL1d7U/4v7tID7TSGLp4EzrYF/jsH9a3M1tJ0pN69GBuTGFfnzKplcocTS8kaJUfE91z6BRQmyazKjCEwn/s3JAR0ABFG7EXTCXwBW6w2/98xtyM2eju/pxR4c0xIhw2IyCV82MM1JLa2gWPgC39eYMKuhBw92bG+FagJpu9VTM8r1qYYW+UjDtWBaY/a481zXuperG9T0XKJA+vDEVLwIQZzCSX8zs6o/Wi2t44f7n6TQw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=/RMEKfOOXWABl/OB7w9sMWEc09wb3jg+KsxGPyobtO0=; b=fVBuZb75SwW/3sbmwCXqpgSP3x6raac4Vm3Ed7XWcPpzQlQ369DeyBwY/bYWDvxJ3012UDnQ9UYxVJGDouXUMMYJ66nOghArK/lSA92Wneyw515wA7kN+IPREITszikySU1yydk37Bl3e4HJc8XwQz8nz3zFEDoPKf9aDv2Iyi7s09yslQfp8ViGyZc2VYIzu2TVVYMgFXVe21srRsBbozwBWe8FEpaDa34nLf1a5owbC3PHg4Jr6hPiFnO8U1a3KjAUdIZak6q+jqIglf9gdRvLwwK/XaI3fHtRUvEjyUWXLSaEOBry8haJT7w9nffXkifqFRbDU5CG3RA7pKQbWA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=kernel.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=/RMEKfOOXWABl/OB7w9sMWEc09wb3jg+KsxGPyobtO0=; b=jD/S5FiuC2s8ys4UeQuc7Zon8DqJQES98i/zWDW9jE8IIKoDdc5t8zd6eXFdGH7+q9h3eHNOI9PsUC6ZFl6u4ztswty2ZPqx+K/IekCJ/LpoHnCC774RGSEyfFYNxubLwQYcDrNt+gST8Hcv2KhxZJJCT7I2EdTrHXnoL9O9CZdB7osVcjRGSRhD986BSWf6Sc4icSg71CFaK98lzVIOuhjbyFqRPWnN8Dm2HShxgcIn0+VgB1NbktEObZ88iUuUAUaWSxq0IQ3jvRt9G7Ukrc6FlATVg2UuQv/TOfOPc3mcQxVtvSrxZfCnfOd+7LUZ+Px9yEfUrXDKl9YRY22qOw== Received: from MW4PR03CA0340.namprd03.prod.outlook.com (2603:10b6:303:dc::15) by MN0PR12MB6126.namprd12.prod.outlook.com (2603:10b6:208:3c6::5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.92.14; Tue, 9 Jun 2026 07:32:27 +0000 Received: from CO1PEPF00012E62.namprd05.prod.outlook.com (2603:10b6:303:dc:cafe::5d) by MW4PR03CA0340.outlook.office365.com (2603:10b6:303:dc::15) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.113.10 via Frontend Transport; Tue, 9 Jun 2026 07:32:26 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by CO1PEPF00012E62.mail.protection.outlook.com (10.167.249.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.113.7 via Frontend Transport; Tue, 9 Jun 2026 07:32:26 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 9 Jun 2026 00:32:11 -0700 Received: from rnnvmail201.nvidia.com (10.129.68.8) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Tue, 9 Jun 2026 00:32:10 -0700 Received: from build-amhetre-focal-20250829.internal (10.127.8.12) by mail.nvidia.com (10.129.68.8) with Microsoft SMTP Server id 15.2.2562.20 via Frontend Transport; Tue, 9 Jun 2026 00:32:10 -0700 From: Ashish Mhetre To: , , , , CC: , , , , Ashish Mhetre Subject: [PATCH v4 3/3] iommu/arm-smmu-v3: Issue CFGI/TLBI twice on Tegra264 Date: Tue, 9 Jun 2026 07:32:04 +0000 Message-ID: <20260609073204.1760077-4-amhetre@nvidia.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260609073204.1760077-1-amhetre@nvidia.com> References: <20260609073204.1760077-1-amhetre@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF00012E62:EE_|MN0PR12MB6126:EE_ X-MS-Office365-Filtering-Correlation-Id: 0d300576-e725-48ef-2c26-08dec5f9412a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700016|376014|1800799024|56012099006|3023799007|11063799006|18002099003|22082099003; X-Microsoft-Antispam-Message-Info: KIfxrWO0oNPthpQ3QmzVVNa1XWfiZsxv9+8LglFPyDRmZY0X3WeAOXe5YjX78U9ZCiyhPemUEuY6XxzZntHT9yi3X2X6vH9PwXImA4ccTS0/jYZgBCkFLWeI2Dza4uJRtM3vPyJu5wnwxKx7JjtYE2+hlCUBkay++3m81dHvVkzITb839NnVDeyPtYXg9ynuNVdnZ0Xd8OLch2iwGRG/3G2APyT6YjUAYxYDuhhzdXs0TpQj9Y1pzj1FSyHigLw3Cw5fwU11DvcljL92dGrPJ1YDHT0qcZykPDMUI68C2SwV7i8HysiEH0HAbhfCBQjLJslRAx0WD7Dxkm9ocDp6J5M5Z3r4U7gYDnTDzNKmg9JpZgNfYqX9aUBt4DmEbm8y/8NUqeMMMfZ7ccl0xeJNoPBtcO3jt+3ZnsGQUe93fRr0bD4eS56ujRFq81p/AHiZFqYKgQw+2ZR2Mptz696A7ROHyy7Zv/h3PnpUzB8jw0iM/z3Yut1eNLPYtWXZ2AdjAl33zMs7vvDAa0CWyGRrR/3hqQA6yucJvRx72IKwZilrX4m5ZlnY4myyEi4dzgSoJ8JlqsauEv88ANoe6GzpbL4fSRBNUAr2ESDR3VVUGQuQVu1ERd56u0zUny+YXEskSl73JYxDgVCKsWskGUB24hCUAmF2ZDn/2FQFhrBdA9YJ5O2xAMGm//I51CPsHa2tely+uaKUoNKQNsYhiQK+n015RDGcgSjWk1gfqP9cFNQ= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(36860700016)(376014)(1800799024)(56012099006)(3023799007)(11063799006)(18002099003)(22082099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: v83q4IXRw0MRbfqWBGMdPKCHHyE2Dc3KlufYeWeGEBfRkZq5xRGYOmMVUe6Dzz2+MChqI0YvOvCyBghGE5JA/Ymx2FGOW8T2Xte0AOmCh8gpF2kgB3vOx7qFLE12YiA4c54SVJSp9AnFwUhQ/Y8uoma/rpA+s4jlqubFCOveq2dMWzAkry/yBjDmmiZK+ShI2og1Fyp+uno5q5Hs6dFd+NZwBEir6GPyFX5CQRE2DRb6lC2zBqBV6P1XdGvMLVgPMOyLPIluTE382bPFOoCSx7lrV2Vmbt10WdJBeajVNSTOtTv6eGqYOaLFKQQt4rskWM11R7QeIgGwGEu0wmeaqKowOxhRGJq17UWCObt7GLd30j9qa+VcmV43lEdtyYiN3keBRue6I8LFpuXE7E+/spJdLrahxiCv4ytCEJEakhyxuCfcQ/QgC8ovCUZWtaen X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Jun 2026 07:32:26.3084 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0d300576-e725-48ef-2c26-08dec5f9412a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF00012E62.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB6126 Content-Type: text/plain; charset="utf-8" Apply the workaround for Tegra264 erratum ARM_SMMU_OPT_REPEAT_TLBI_CFGI by issuing every CFGI/TLBI cmdlist twice on affected SMMU instances, with CMD_SYNC after each. The erratum requires this exact sequencing: TLBI/CFGI ... CMD_SYNC TLBI/CFGI ... CMD_SYNC Rename the existing arm_smmu_cmdq_issue_cmdlist() to __arm_smmu_cmdq_issue_cmdlist() and add a thin wrapper that, on affected SMMUs and when @sync is true with @n > 0, re-issues the same cmdlist a second time when arm_smmu_erratum_cmd_needs_repeating() is true. The @n > 0 gate is needed because arm_smmu_cmdq_batch_add_cmd_p() can call arm_smmu_cmdq_issue_cmdlist() with @n =3D=3D 0 and @sync =3D=3D tr= ue to flush a bare CMD_SYNC when the next command is not supported by the batch's pre-selected cmdq; the repeat path must not inspect cmds[0] in that case. The static-key gate inside the predicate means the wrapper compiles to a single tested branch on unaffected kernels. For the in-tree batching path, register the new condition with arm_smmu_cmdq_batch_force_sync() so that a full batch carrying CFGI/TLBI commands flushes with sync=3Dtrue. For the iommufd VSMMU path add an arm_vsmmu_can_batch_cmd() predicate that splits the iommufd batch at every "needs repeating" transition, so the wrapper's per-batch decision based on the first command stays correct even when userspace mixes opcode classes. Also document the erratum in Documentation/arch/arm64/silicon-errata.rst. Suggested-by: Nicolin Chen Signed-off-by: Ashish Mhetre --- Documentation/arch/arm64/silicon-errata.rst | 2 ++ .../arm/arm-smmu-v3/arm-smmu-v3-iommufd.c | 15 +++++++- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 35 ++++++++++++++++--- 3 files changed, 47 insertions(+), 5 deletions(-) diff --git a/Documentation/arch/arm64/silicon-errata.rst b/Documentation/ar= ch/arm64/silicon-errata.rst index 046a7fa47063..96050886a7d6 100644 --- a/Documentation/arch/arm64/silicon-errata.rst +++ b/Documentation/arch/arm64/silicon-errata.rst @@ -268,6 +268,8 @@ stable kernels. | | | T241-MPAM-4, | = | | | | T241-MPAM-6 | = | +----------------+-----------------+-----------------+--------------------= ---------+ +| NVIDIA | T264 SMMU | T264-SMMU-3 | N/A = | ++----------------+-----------------+-----------------+--------------------= ---------+ +----------------+-----------------+-----------------+--------------------= ---------+ | Freescale/NXP | LS2080A/LS1043A | A-008585 | FSL_ERRATUM_A008585= | +----------------+-----------------+-----------------+--------------------= ---------+ diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c b/drivers/= iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c index 1e9f7d2de344..11d22acae613 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c @@ -350,6 +350,18 @@ static int arm_vsmmu_convert_user_cmd(struct arm_vsmmu= *vsmmu, return 0; } =20 +static bool arm_vsmmu_can_batch_cmd(struct arm_smmu_device *smmu, + struct arm_vsmmu_invalidation_cmd *last, + struct arm_vsmmu_invalidation_cmd *next) +{ + struct arm_smmu_cmd next_cmd =3D { + .data[0] =3D le64_to_cpu(next->ucmd.cmd[0]), + }; + + return arm_smmu_erratum_cmd_needs_repeating(smmu, &last->cmd) =3D=3D + arm_smmu_erratum_cmd_needs_repeating(smmu, &next_cmd); +} + int arm_vsmmu_cache_invalidate(struct iommufd_viommu *viommu, struct iommu_user_data_array *array) { @@ -382,7 +394,8 @@ int arm_vsmmu_cache_invalidate(struct iommufd_viommu *v= iommu, =20 /* FIXME work in blocks of CMDQ_BATCH_ENTRIES and copy each block? */ cur++; - if (cur !=3D end && (cur - last) !=3D CMDQ_BATCH_ENTRIES - 1) + if (cur !=3D end && (cur - last) !=3D CMDQ_BATCH_ENTRIES - 1 && + arm_vsmmu_can_batch_cmd(smmu, last, cur)) continue; =20 /* FIXME always uses the main cmdq rather than trying to group by type */ diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 599c835c50d8..041e188b3b30 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -700,10 +700,10 @@ static void arm_smmu_cmdq_write_entries(struct arm_sm= mu_cmdq *cmdq, * insert their own list of commands then all of the commands from one * CPU will appear before any of the commands from the other CPU. */ -int arm_smmu_cmdq_issue_cmdlist(struct arm_smmu_device *smmu, - struct arm_smmu_cmdq *cmdq, - struct arm_smmu_cmd *cmds, int n, - bool sync) +static int __arm_smmu_cmdq_issue_cmdlist(struct arm_smmu_device *smmu, + struct arm_smmu_cmdq *cmdq, + struct arm_smmu_cmd *cmds, int n, + bool sync) { struct arm_smmu_cmd cmd_sync; u32 prod; @@ -822,6 +822,28 @@ int arm_smmu_cmdq_issue_cmdlist(struct arm_smmu_device= *smmu, return ret; } =20 +int arm_smmu_cmdq_issue_cmdlist(struct arm_smmu_device *smmu, + struct arm_smmu_cmdq *cmdq, + struct arm_smmu_cmd *cmds, int n, + bool sync) +{ + int ret =3D __arm_smmu_cmdq_issue_cmdlist(smmu, cmdq, cmds, n, sync); + + /* + * arm_smmu_cmdq_batch_add_cmd_p() can flush its current batch with + * sync=3Dtrue and n=3D0 (bare SYNC) when the next command is not + * supported by the batch's pre-selected cmdq, so the repeat path + * must not inspect cmds[0]. + */ + if (!n || ret || !sync) + return ret; + + if (arm_smmu_erratum_cmd_needs_repeating(smmu, &cmds[0])) + ret =3D __arm_smmu_cmdq_issue_cmdlist(smmu, cmdq, cmds, n, sync); + + return ret; +} + static int arm_smmu_cmdq_issue_cmd_p(struct arm_smmu_device *smmu, struct arm_smmu_cmd *cmd, bool sync) { @@ -862,6 +884,11 @@ static bool arm_smmu_cmdq_batch_force_sync(struct arm_= smmu_device *smmu, (smmu->options & ARM_SMMU_OPT_CMDQ_FORCE_SYNC)) return true; =20 + /* See ARM_SMMU_OPT_REPEAT_TLBI_CFGI */ + if (cmds->num =3D=3D CMDQ_BATCH_ENTRIES && + arm_smmu_erratum_cmd_needs_repeating(smmu, &cmds->cmds[0])) + return true; + return false; } =20 --=20 2.50.1