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Tue, 09 Jun 2026 10:39:31 -0700 (PDT) From: Alexey Klimov Date: Tue, 09 Jun 2026 18:39:23 +0100 Subject: [PATCH v5 1/6] dt-bindings: soc: move,rename google,gs101-pmu-intr-gen and add exynos850 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260609-exynos850-cpuhotplug-v5-1-8422cf80d43b@linaro.org> References: <20260609-exynos850-cpuhotplug-v5-0-8422cf80d43b@linaro.org> In-Reply-To: <20260609-exynos850-cpuhotplug-v5-0-8422cf80d43b@linaro.org> To: Sam Protsenko , linux-samsung-soc@vger.kernel.org, Krzysztof Kozlowski , Peter Griffin Cc: linux-samsung-soc@vger.kernel.org, =?utf-8?q?Andr=C3=A9_Draszik?= , Tudor Ambarus , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar , Henrik Grimler , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.3 The PMU interrupt generation block introduced for the Google GS101 is actually a standard Samsung Exynos IP block found in older SoCs, such as the Exynos850, and is not exclusive to Google SoCs. To accurately reflect its origin, move the schema file to under soc/samsung/ directory and rename it. Concurrently, add the new "samsung,exynos850-pmu-intr-gen" compatible string to the bindings. Support for this block is required to enable power management features like CPU hotplug and idle states on Exynos850 platforms. Also, move this file under Exynos850 SoC in MAINTAINERS entry. Reviewed-by: Rob Herring (Arm) Signed-off-by: Alexey Klimov --- .../samsung,exynos850-pmu-intr-gen.yaml} | 8 ++++= +--- MAINTAINERS | 2 +- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/soc/google/google,gs101-pmu-= intr-gen.yaml b/Documentation/devicetree/bindings/soc/samsung/samsung,exyno= s850-pmu-intr-gen.yaml similarity index 70% rename from Documentation/devicetree/bindings/soc/google/google,gs101-pmu-i= ntr-gen.yaml rename to Documentation/devicetree/bindings/soc/samsung/samsung,exynos850-p= mu-intr-gen.yaml index 2be022ca6a7d..df23467d0e0e 100644 --- a/Documentation/devicetree/bindings/soc/google/google,gs101-pmu-intr-ge= n.yaml +++ b/Documentation/devicetree/bindings/soc/samsung/samsung,exynos850-pmu-i= ntr-gen.yaml @@ -1,10 +1,10 @@ # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- -$id: http://devicetree.org/schemas/soc/google/google,gs101-pmu-intr-gen.ya= ml# +$id: http://devicetree.org/schemas/soc/samsung/samsung,exynos850-pmu-intr-= gen.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# =20 -title: Google Power Management Unit (PMU) Interrupt Generation +title: Samsung Power Management Unit (PMU) Interrupt Generation =20 description: | PMU interrupt generator for handshaking between PMU through interrupts. @@ -15,7 +15,9 @@ maintainers: properties: compatible: items: - - const: google,gs101-pmu-intr-gen + - enum: + - google,gs101-pmu-intr-gen + - samsung,exynos850-pmu-intr-gen - const: syscon =20 reg: diff --git a/MAINTAINERS b/MAINTAINERS index 86ca9297edab..498ca30a00c5 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -10952,7 +10952,6 @@ P: Documentation/process/maintainer-soc-clean-dts.r= st C: irc://irc.oftc.net/pixel6-kernel-dev F: Documentation/devicetree/bindings/clock/google,gs101-clock.yaml F: Documentation/devicetree/bindings/phy/google,lga-usb-phy.yaml -F: Documentation/devicetree/bindings/soc/google/google,gs101-pmu-intr-gen.= yaml F: Documentation/devicetree/bindings/usb/google,lga-dwc3.yaml F: arch/arm64/boot/dts/exynos/google/ F: drivers/clk/samsung/clk-gs101.c @@ -23652,6 +23651,7 @@ L: linux-arm-kernel@lists.infradead.org (moderated = for non-subscribers) L: linux-samsung-soc@vger.kernel.org S: Maintained F: Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml +F: Documentation/devicetree/bindings/soc/samsung/samsung,exynos850-pmu-int= r-gen.yaml F: arch/arm64/boot/dts/exynos/exynos850* F: drivers/clk/samsung/clk-exynos850.c F: include/dt-bindings/clock/exynos850.h --=20 2.51.0 From nobody Fri Jun 12 17:36:39 2026 Received: from mail-wm1-f51.google.com (mail-wm1-f51.google.com [209.85.128.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8A7154D2ED4 for ; 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Tue, 09 Jun 2026 10:39:33 -0700 (PDT) Received: from [127.0.1.1] ([94.4.195.193]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-490bc3fcf5bsm593605215e9.9.2026.06.09.10.39.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Jun 2026 10:39:32 -0700 (PDT) From: Alexey Klimov Date: Tue, 09 Jun 2026 18:39:24 +0100 Subject: [PATCH v5 2/6] dt-bindings: soc: samsung: exynos-pmu: Require pmu-intr-gen-syscon for Exynos850 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260609-exynos850-cpuhotplug-v5-2-8422cf80d43b@linaro.org> References: <20260609-exynos850-cpuhotplug-v5-0-8422cf80d43b@linaro.org> In-Reply-To: <20260609-exynos850-cpuhotplug-v5-0-8422cf80d43b@linaro.org> To: Sam Protsenko , linux-samsung-soc@vger.kernel.org, Krzysztof Kozlowski , Peter Griffin Cc: linux-samsung-soc@vger.kernel.org, =?utf-8?q?Andr=C3=A9_Draszik?= , Tudor Ambarus , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar , Henrik Grimler , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.3 Update the Exynos PMU schema to mandate the 'google,pmu-intr-gen-syscon' property for the 'samsung,exynos850-pmu' compatible so the driver can obtain the necessary syscon regmap. The Exynos850 PMU relies on a separate system controller block to handle interrupts generation, similar to the hardware design of the GS101 SoC. To ensure the hardware is correctly described, this syscon phandle must be explicitly provided. Reviewed-by: Peter Griffin Acked-by: Rob Herring (Arm) Signed-off-by: Alexey Klimov --- Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml = b/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml index 76ce7e98c10f..6550c3736a3b 100644 --- a/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml +++ b/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml @@ -182,6 +182,7 @@ allOf: contains: enum: - google,gs101-pmu + - samsung,exynos850-pmu then: required: - google,pmu-intr-gen-syscon --=20 2.51.0 From nobody Fri Jun 12 17:36:39 2026 Received: from mail-wm1-f54.google.com (mail-wm1-f54.google.com [209.85.128.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D5E134D2EF8 for ; Tue, 9 Jun 2026 17:39:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Tue, 09 Jun 2026 10:39:34 -0700 (PDT) Received: from [127.0.1.1] ([94.4.195.193]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-490bc3fcf5bsm593605215e9.9.2026.06.09.10.39.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Jun 2026 10:39:33 -0700 (PDT) From: Alexey Klimov Date: Tue, 09 Jun 2026 18:39:25 +0100 Subject: [PATCH v5 3/6] soc: samsung: exynos-pmu: generalise gs101-specific cpu{idle,hotplug} for Exynos SoCs Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260609-exynos850-cpuhotplug-v5-3-8422cf80d43b@linaro.org> References: <20260609-exynos850-cpuhotplug-v5-0-8422cf80d43b@linaro.org> In-Reply-To: <20260609-exynos850-cpuhotplug-v5-0-8422cf80d43b@linaro.org> To: Sam Protsenko , linux-samsung-soc@vger.kernel.org, Krzysztof Kozlowski , Peter Griffin Cc: linux-samsung-soc@vger.kernel.org, =?utf-8?q?Andr=C3=A9_Draszik?= , Tudor Ambarus , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar , Henrik Grimler , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.3 The cpuhotplug and cpuidle support for GS101-based SoCs which utilizes GS101 PMU interrupts generation block can be generalised to be (re)used for other Exynos-based SoCs. Also, the GS101 PMU interrupts generation block is not exclusive to Google GS101 SoCs and should be made more Exynos-generic. Specifically, apply the following changes: - rename gs101-specific calls, structs, names to be exynos-prefixed; - move exynos_pmu_context and CPU_INFORM_* defines into exynos-pmu.h; - introduce cpu_pmu_{offline,online} callbacks in driver-specific exynos_pmu_data which can be used to hold PMU and PMU intr gen update routines for different platforms and update cpuidle and cpuhotplug support to use them; - add checks for the presense of cpu_pmu_{offline,online} callbacks; - move and rename gs101-specific cpu{offline,online} PMU updates routines into gs101-pmu.c file, also removing underscore prefix; - update gs101_pmu_data to use newly introduced callbacks; - rename PMU interrupts generation GS101_INTR_* regs to EXYNOS_INTR_*. This allows other platforms to add cpuhotplug and cpuidle support in a similar manner, using their own platform-specific PMU and PMU intr gen update routines. Reviewed-by: Peter Griffin Tested-by: Peter Griffin Signed-off-by: Alexey Klimov --- drivers/soc/samsung/exynos-pmu.c | 122 ++++++------------------= ---- drivers/soc/samsung/exynos-pmu.h | 33 ++++++++ drivers/soc/samsung/gs101-pmu.c | 49 +++++++++++ include/linux/soc/samsung/exynos-regs-pmu.h | 10 +-- 4 files changed, 112 insertions(+), 102 deletions(-) diff --git a/drivers/soc/samsung/exynos-pmu.c b/drivers/soc/samsung/exynos-= pmu.c index 846313a28e9a..f170abe08ef1 100644 --- a/drivers/soc/samsung/exynos-pmu.c +++ b/drivers/soc/samsung/exynos-pmu.c @@ -24,24 +24,6 @@ =20 #include "exynos-pmu.h" =20 -struct exynos_pmu_context { - struct device *dev; - const struct exynos_pmu_data *pmu_data; - struct regmap *pmureg; - struct regmap *pmuintrgen; - /* - * Serialization lock for CPU hot plug and cpuidle ACPM hint - * programming. Also protects in_cpuhp, sys_insuspend & sys_inreboot - * flags. - */ - raw_spinlock_t cpupm_lock; - unsigned long *in_cpuhp; - bool sys_insuspend; - bool sys_inreboot; - int cpuhp_prepare_state; - int cpuhp_online_state; -}; - void __iomem *pmu_base_addr; static struct exynos_pmu_context *pmu_context; /* forward declaration */ @@ -221,43 +203,8 @@ struct regmap *exynos_get_pmu_regmap_by_phandle(struct= device_node *np, } EXPORT_SYMBOL_GPL(exynos_get_pmu_regmap_by_phandle); =20 -/* - * CPU_INFORM register "hint" values are required to be programmed in addi= tion to - * the standard PSCI calls to have functional CPU hotplug and CPU idle sta= tes. - * This is required to workaround limitations in the el3mon/ACPM firmware. - */ -#define CPU_INFORM_CLEAR 0 -#define CPU_INFORM_C2 1 - -/* - * __gs101_cpu_pmu_ prefix functions are common code shared by CPU PM noti= fiers - * (CPUIdle) and CPU hotplug callbacks. Functions should be called with IR= Qs - * disabled and cpupm_lock held. - */ -static int __gs101_cpu_pmu_online(unsigned int cpu) - __must_hold(&pmu_context->cpupm_lock) -{ - u32 reg, mask; - - /* clear cpu inform hint */ - regmap_write(pmu_context->pmureg, GS101_CPU_INFORM(cpu), - CPU_INFORM_CLEAR); - - mask =3D BIT(cpu); - - regmap_update_bits(pmu_context->pmuintrgen, GS101_GRP2_INTR_BID_ENABLE, - mask, (0 << cpu)); - - regmap_read(pmu_context->pmuintrgen, GS101_GRP2_INTR_BID_UPEND, ®); - - regmap_write(pmu_context->pmuintrgen, GS101_GRP2_INTR_BID_CLEAR, - reg & mask); - - return 0; -} - /* Called from CPU PM notifier (CPUIdle code path) with IRQs disabled */ -static int gs101_cpu_pmu_online(void) +static int exynos_cpu_pmu_online(void) { int cpu; =20 @@ -269,20 +216,20 @@ static int gs101_cpu_pmu_online(void) } =20 cpu =3D smp_processor_id(); - __gs101_cpu_pmu_online(cpu); + pmu_context->pmu_data->cpu_pmu_online(pmu_context, cpu); raw_spin_unlock(&pmu_context->cpupm_lock); =20 return NOTIFY_OK; } =20 /* Called from CPU hot plug callback with IRQs enabled */ -static int gs101_cpuhp_pmu_online(unsigned int cpu) +static int exynos_cpuhp_pmu_online(unsigned int cpu) { unsigned long flags; =20 raw_spin_lock_irqsave(&pmu_context->cpupm_lock, flags); =20 - __gs101_cpu_pmu_online(cpu); + pmu_context->pmu_data->cpu_pmu_online(pmu_context, cpu); /* * Mark this CPU as having finished the hotplug. * This means this CPU can now enter C2 idle state. @@ -293,33 +240,8 @@ static int gs101_cpuhp_pmu_online(unsigned int cpu) return 0; } =20 -/* Common function shared by both CPU hot plug and CPUIdle */ -static int __gs101_cpu_pmu_offline(unsigned int cpu) - __must_hold(&pmu_context->cpupm_lock) -{ - u32 reg, mask; - - /* set cpu inform hint */ - regmap_write(pmu_context->pmureg, GS101_CPU_INFORM(cpu), CPU_INFORM_C2); - - mask =3D BIT(cpu); - regmap_update_bits(pmu_context->pmuintrgen, GS101_GRP2_INTR_BID_ENABLE, - mask, BIT(cpu)); - - regmap_read(pmu_context->pmuintrgen, GS101_GRP1_INTR_BID_UPEND, ®); - regmap_write(pmu_context->pmuintrgen, GS101_GRP1_INTR_BID_CLEAR, - reg & mask); - - mask =3D (BIT(cpu + 8)); - regmap_read(pmu_context->pmuintrgen, GS101_GRP1_INTR_BID_UPEND, ®); - regmap_write(pmu_context->pmuintrgen, GS101_GRP1_INTR_BID_CLEAR, - reg & mask); - - return 0; -} - /* Called from CPU PM notifier (CPUIdle code path) with IRQs disabled */ -static int gs101_cpu_pmu_offline(void) +static int exynos_cpu_pmu_offline(void) { int cpu; =20 @@ -337,14 +259,14 @@ static int gs101_cpu_pmu_offline(void) return NOTIFY_OK; } =20 - __gs101_cpu_pmu_offline(cpu); + pmu_context->pmu_data->cpu_pmu_offline(pmu_context, cpu); raw_spin_unlock(&pmu_context->cpupm_lock); =20 return NOTIFY_OK; } =20 /* Called from CPU hot plug callback with IRQs enabled */ -static int gs101_cpuhp_pmu_offline(unsigned int cpu) +static int exynos_cpuhp_pmu_offline(unsigned int cpu) { unsigned long flags; =20 @@ -354,29 +276,29 @@ static int gs101_cpuhp_pmu_offline(unsigned int cpu) * ACPM the CPU entering hotplug should not enter C2 idle state. */ set_bit(cpu, pmu_context->in_cpuhp); - __gs101_cpu_pmu_offline(cpu); + pmu_context->pmu_data->cpu_pmu_offline(pmu_context, cpu); =20 raw_spin_unlock_irqrestore(&pmu_context->cpupm_lock, flags); =20 return 0; } =20 -static int gs101_cpu_pm_notify_callback(struct notifier_block *self, +static int exynos_cpu_pm_notify_callback(struct notifier_block *self, unsigned long action, void *v) { switch (action) { case CPU_PM_ENTER: - return gs101_cpu_pmu_offline(); + return exynos_cpu_pmu_offline(); =20 case CPU_PM_EXIT: - return gs101_cpu_pmu_online(); + return exynos_cpu_pmu_online(); } =20 return NOTIFY_OK; } =20 -static struct notifier_block gs101_cpu_pm_notifier =3D { - .notifier_call =3D gs101_cpu_pm_notify_callback, +static struct notifier_block exynos_cpu_pm_notifier =3D { + .notifier_call =3D exynos_cpu_pm_notify_callback, /* * We want to be called first, as the ACPM hint and handshake is what * puts the CPU into C2. @@ -408,7 +330,7 @@ static struct notifier_block exynos_cpupm_reboot_nb =3D= { =20 static void destroy_cpuhp_and_cpuidle(void) { - cpu_pm_unregister_notifier(&gs101_cpu_pm_notifier); + cpu_pm_unregister_notifier(&exynos_cpu_pm_notifier); unregister_reboot_notifier(&exynos_cpupm_reboot_nb); =20 if (pmu_context->cpuhp_prepare_state !=3D CPUHP_INVALID) @@ -424,6 +346,12 @@ static int setup_cpuhp_and_cpuidle(struct device *dev) void __iomem *virt_addr; int ret, cpu; =20 + if (!pmu_context->pmu_data->cpu_pmu_offline || !pmu_context->pmu_data->cp= u_pmu_online) { + dev_err(dev, + "PMU write/update sequence is not present for cpuhotplug and cpuidle\n"= ); + return -ENODEV; + } + intr_gen_node =3D of_parse_phandle(dev->of_node, "google,pmu-intr-gen-syscon", 0); if (!intr_gen_node) { @@ -475,28 +403,28 @@ static int setup_cpuhp_and_cpuidle(struct device *dev) =20 /* set PMU to power on */ for_each_online_cpu(cpu) - gs101_cpuhp_pmu_online(cpu); + exynos_cpuhp_pmu_online(cpu); =20 /* register CPU hotplug callbacks */ pmu_context->cpuhp_prepare_state =3D CPUHP_INVALID; pmu_context->cpuhp_online_state =3D CPUHP_INVALID; =20 ret =3D cpuhp_setup_state(CPUHP_BP_PREPARE_DYN, "soc/exynos-pmu:prepare", - gs101_cpuhp_pmu_online, NULL); + exynos_cpuhp_pmu_online, NULL); if (ret < 0) return ret; =20 pmu_context->cpuhp_prepare_state =3D ret; =20 ret =3D cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "soc/exynos-pmu:online", - NULL, gs101_cpuhp_pmu_offline); + NULL, exynos_cpuhp_pmu_offline); if (ret < 0) goto clean_cpuhp_states; =20 pmu_context->cpuhp_online_state =3D ret; =20 /* register CPU PM notifiers for cpuidle */ - ret =3D cpu_pm_register_notifier(&gs101_cpu_pm_notifier); + ret =3D cpu_pm_register_notifier(&exynos_cpu_pm_notifier); if (ret) goto clean_cpuhp_states; =20 @@ -505,7 +433,7 @@ static int setup_cpuhp_and_cpuidle(struct device *dev) /* Success */ return ret; =20 - cpu_pm_unregister_notifier(&gs101_cpu_pm_notifier); + cpu_pm_unregister_notifier(&exynos_cpu_pm_notifier); =20 clean_cpuhp_states: if (pmu_context->cpuhp_prepare_state !=3D CPUHP_INVALID) diff --git a/drivers/soc/samsung/exynos-pmu.h b/drivers/soc/samsung/exynos-= pmu.h index fbe381e2a2e1..733e188fa2b1 100644 --- a/drivers/soc/samsung/exynos-pmu.h +++ b/drivers/soc/samsung/exynos-pmu.h @@ -13,6 +13,14 @@ =20 #define PMU_TABLE_END (-1U) =20 +/* + * CPU_INFORM register "hint" values are required to be programmed in addi= tion to + * the standard PSCI calls to have functional CPU hotplug and CPU idle sta= tes. + * This is required to workaround limitations in the el3mon/ACPM firmware. + */ +#define CPU_INFORM_CLEAR 0 +#define CPU_INFORM_C2 1 + struct regmap_access_table; =20 struct exynos_pmu_conf { @@ -20,6 +28,24 @@ struct exynos_pmu_conf { u8 val[NUM_SYS_POWERDOWN]; }; =20 +struct exynos_pmu_context { + struct device *dev; + const struct exynos_pmu_data *pmu_data; + struct regmap *pmureg; + struct regmap *pmuintrgen; + /* + * Serialization lock for CPU hot plug and cpuidle ACPM hint + * programming. Also protects in_cpuhp, sys_insuspend & sys_inreboot + * flags. + */ + raw_spinlock_t cpupm_lock; + unsigned long *in_cpuhp; + bool sys_insuspend; + bool sys_inreboot; + int cpuhp_prepare_state; + int cpuhp_online_state; +}; + /** * struct exynos_pmu_data - of_device_id (match) data * @@ -44,6 +70,10 @@ struct exynos_pmu_conf { * used (i.e. when @pmu_secure is @true). * @wr_table: A table of writable register ranges in case a custom regmap = is * used (i.e. when @pmu_secure is @true). + * @cpu_pmu_offline: Optional callback to be called before entering CPU of= fline + * or idle state. Only valid when pmu_cpuhp set to true. + * @cpu_pmu_online: Optional callback to be called after CPU onlined or af= ter + * exiting idle state. Only valid when pmu_cpuhp set to t= rue. */ struct exynos_pmu_data { const struct exynos_pmu_conf *pmu_config; @@ -57,6 +87,9 @@ struct exynos_pmu_data { =20 const struct regmap_access_table *rd_table; const struct regmap_access_table *wr_table; + + int (*cpu_pmu_offline)(struct exynos_pmu_context *pmu_context, unsigned i= nt cpu); + int (*cpu_pmu_online)(struct exynos_pmu_context *pmu_context, unsigned in= t cpu); }; =20 extern void __iomem *pmu_base_addr; diff --git a/drivers/soc/samsung/gs101-pmu.c b/drivers/soc/samsung/gs101-pm= u.c index 17dadc1b9c6e..ec75ff062ce0 100644 --- a/drivers/soc/samsung/gs101-pmu.c +++ b/drivers/soc/samsung/gs101-pmu.c @@ -322,11 +322,60 @@ static const struct regmap_access_table gs101_pmu_wr_= table =3D { .n_no_ranges =3D ARRAY_SIZE(gs101_pmu_ro_registers), }; =20 +/* + * gs101_cpu_pmu_ prefix functions are common code shared by CPU PM notifi= ers + * (CPUIdle) and CPU hotplug callbacks. Functions should be called with IR= Qs + * disabled and cpupm_lock held. + */ +static int gs101_cpu_pmu_online(struct exynos_pmu_context *pmu_context, un= signed int cpu) + __must_hold(&pmu_context->cpupm_lock) +{ + u32 reg, mask; + + /* clear cpu inform hint */ + regmap_write(pmu_context->pmureg, GS101_CPU_INFORM(cpu), CPU_INFORM_CLEAR= ); + + mask =3D BIT(cpu); + regmap_update_bits(pmu_context->pmuintrgen, EXYNOS_GRP2_INTR_BID_ENABLE, + mask, (0 << cpu)); + + regmap_read(pmu_context->pmuintrgen, EXYNOS_GRP2_INTR_BID_UPEND, ®); + + regmap_write(pmu_context->pmuintrgen, EXYNOS_GRP2_INTR_BID_CLEAR, reg & m= ask); + + return 0; +} + +/* Common function shared by both CPU hot plug and CPUIdle */ +static int gs101_cpu_pmu_offline(struct exynos_pmu_context *pmu_context, u= nsigned int cpu) + __must_hold(&pmu_context->cpupm_lock) +{ + u32 reg, mask; + + /* set cpu inform hint */ + regmap_write(pmu_context->pmureg, GS101_CPU_INFORM(cpu), CPU_INFORM_C2); + + mask =3D BIT(cpu); + regmap_update_bits(pmu_context->pmuintrgen, EXYNOS_GRP2_INTR_BID_ENABLE, + mask, BIT(cpu)); + + regmap_read(pmu_context->pmuintrgen, EXYNOS_GRP1_INTR_BID_UPEND, ®); + regmap_write(pmu_context->pmuintrgen, EXYNOS_GRP1_INTR_BID_CLEAR, reg & m= ask); + + mask =3D (BIT(cpu + 8)); + regmap_read(pmu_context->pmuintrgen, EXYNOS_GRP1_INTR_BID_UPEND, ®); + regmap_write(pmu_context->pmuintrgen, EXYNOS_GRP1_INTR_BID_CLEAR, reg & m= ask); + + return 0; +} + const struct exynos_pmu_data gs101_pmu_data =3D { .pmu_secure =3D true, .pmu_cpuhp =3D true, .rd_table =3D &gs101_pmu_rd_table, .wr_table =3D &gs101_pmu_wr_table, + .cpu_pmu_offline =3D gs101_cpu_pmu_offline, + .cpu_pmu_online =3D gs101_cpu_pmu_online, }; =20 /* diff --git a/include/linux/soc/samsung/exynos-regs-pmu.h b/include/linux/so= c/samsung/exynos-regs-pmu.h index db8a7ca81080..9c4d3da41dbf 100644 --- a/include/linux/soc/samsung/exynos-regs-pmu.h +++ b/include/linux/soc/samsung/exynos-regs-pmu.h @@ -1009,11 +1009,11 @@ #define GS101_PHY_CTRL_UFS 0x3ec8 =20 /* PMU INTR GEN */ -#define GS101_GRP1_INTR_BID_UPEND (0x0108) -#define GS101_GRP1_INTR_BID_CLEAR (0x010c) -#define GS101_GRP2_INTR_BID_ENABLE (0x0200) -#define GS101_GRP2_INTR_BID_UPEND (0x0208) -#define GS101_GRP2_INTR_BID_CLEAR (0x020c) +#define EXYNOS_GRP1_INTR_BID_UPEND (0x0108) +#define EXYNOS_GRP1_INTR_BID_CLEAR (0x010c) +#define EXYNOS_GRP2_INTR_BID_ENABLE (0x0200) +#define EXYNOS_GRP2_INTR_BID_UPEND (0x0208) +#define EXYNOS_GRP2_INTR_BID_CLEAR (0x020c) =20 /* exynosautov920 */ #define EXYNOSAUTOV920_PHY_CTRL_USB20 (0x0710) --=20 2.51.0 From nobody Fri Jun 12 17:36:39 2026 Received: from mail-wr1-f48.google.com (mail-wr1-f48.google.com [209.85.221.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0C8284D2ED0 for ; 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Tue, 09 Jun 2026 10:39:36 -0700 (PDT) Received: from [127.0.1.1] ([94.4.195.193]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-490bc3fcf5bsm593605215e9.9.2026.06.09.10.39.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Jun 2026 10:39:35 -0700 (PDT) From: Alexey Klimov Date: Tue, 09 Jun 2026 18:39:26 +0100 Subject: [PATCH v5 4/6] soc: samsung: exynos-pmu: add Exynos850 CPU hotplug support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260609-exynos850-cpuhotplug-v5-4-8422cf80d43b@linaro.org> References: <20260609-exynos850-cpuhotplug-v5-0-8422cf80d43b@linaro.org> In-Reply-To: <20260609-exynos850-cpuhotplug-v5-0-8422cf80d43b@linaro.org> To: Sam Protsenko , linux-samsung-soc@vger.kernel.org, Krzysztof Kozlowski , Peter Griffin Cc: linux-samsung-soc@vger.kernel.org, =?utf-8?q?Andr=C3=A9_Draszik?= , Tudor Ambarus , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar , Henrik Grimler , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.3 Add cpuhotplug support for Exynos850 platforms. This SoC requires its own specific set of writes/updates to PMU and PMU interrupts generation block in order to put a CPU or a group of CPUs into a different sleep states or prepare these entities for a CPU_OFF or wake-up out of idle state or after CPU online. Without these writes/updates the CPU(s) wake-up or online fails. This also requires syscon regmap with raw spinlocks, so add its initialisation to main exynos pmu probe() routine. Signed-off-by: Alexey Klimov --- drivers/soc/samsung/Makefile | 2 +- drivers/soc/samsung/exynos-pmu.c | 24 ++++++++ drivers/soc/samsung/exynos-pmu.h | 1 + drivers/soc/samsung/exynos850-pmu.c | 95 +++++++++++++++++++++++++= ++++ include/linux/soc/samsung/exynos-regs-pmu.h | 5 ++ 5 files changed, 126 insertions(+), 1 deletion(-) diff --git a/drivers/soc/samsung/Makefile b/drivers/soc/samsung/Makefile index 636a762608c9..7f544e3c1fcc 100644 --- a/drivers/soc/samsung/Makefile +++ b/drivers/soc/samsung/Makefile @@ -7,7 +7,7 @@ exynos_chipid-y +=3D exynos-chipid.o exynos-asv.o obj-$(CONFIG_EXYNOS_USI) +=3D exynos-usi.o =20 obj-$(CONFIG_EXYNOS_PMU) +=3D exynos_pmu.o -exynos_pmu-y +=3D exynos-pmu.o gs101-pmu.o +exynos_pmu-y +=3D exynos-pmu.o gs101-pmu.o exynos850-pmu.o =20 obj-$(CONFIG_EXYNOS_PMU_ARM_DRIVERS) +=3D exynos3250-pmu.o exynos4-pmu.o \ exynos5250-pmu.o exynos5420-pmu.o diff --git a/drivers/soc/samsung/exynos-pmu.c b/drivers/soc/samsung/exynos-= pmu.c index f170abe08ef1..cec0a7211c93 100644 --- a/drivers/soc/samsung/exynos-pmu.c +++ b/drivers/soc/samsung/exynos-pmu.c @@ -92,6 +92,14 @@ static const struct regmap_config regmap_smccfg =3D { .use_raw_spinlock =3D true, }; =20 +static const struct regmap_config regmap_pmu =3D { + .name =3D "pmu_regs", + .reg_bits =3D 32, + .val_bits =3D 32, + .reg_stride =3D 4, + .use_raw_spinlock =3D true, +}; + static const struct regmap_config regmap_pmu_intr =3D { .name =3D "pmu_intr_gen", .reg_bits =3D 32, @@ -133,6 +141,7 @@ static const struct of_device_id exynos_pmu_of_device_i= ds[] =3D { .compatible =3D "samsung,exynos7-pmu", }, { .compatible =3D "samsung,exynos850-pmu", + .data =3D &exynos850_pmu_data, }, { /*sentinel*/ }, }; @@ -488,6 +497,21 @@ static int exynos_pmu_probe(struct platform_device *pd= ev) ret =3D of_syscon_register_regmap(dev->of_node, regmap); if (ret) return ret; + /* + * For SoCs that support cpuhotplug/cpuidle via PMU updates callbacks. + * Such callbacks are executed under raw_spinlock so we need a custom + * regmap too. + */ + } else if (pmu_context->pmu_data && pmu_context->pmu_data->pmu_cpuhp) { + regmap =3D devm_regmap_init_mmio(dev, pmu_base_addr, ®map_pmu); + if (IS_ERR(regmap)) + return dev_err_probe(dev, PTR_ERR(regmap), + "hotplug regmap init failed\n"); + + ret =3D of_syscon_register_regmap(dev->of_node, regmap); + if (ret) + return dev_err_probe(dev, ret, + "failed to register hotplug regmap with syscon\n"); } else { /* let syscon create mmio regmap */ regmap =3D syscon_node_to_regmap(dev->of_node); diff --git a/drivers/soc/samsung/exynos-pmu.h b/drivers/soc/samsung/exynos-= pmu.h index 733e188fa2b1..4ecbf53cd4f7 100644 --- a/drivers/soc/samsung/exynos-pmu.h +++ b/drivers/soc/samsung/exynos-pmu.h @@ -104,6 +104,7 @@ extern const struct exynos_pmu_data exynos5250_pmu_data; extern const struct exynos_pmu_data exynos5420_pmu_data; #endif extern const struct exynos_pmu_data gs101_pmu_data; +extern const struct exynos_pmu_data exynos850_pmu_data; =20 extern void pmu_raw_writel(u32 val, u32 offset); extern u32 pmu_raw_readl(u32 offset); diff --git a/drivers/soc/samsung/exynos850-pmu.c b/drivers/soc/samsung/exyn= os850-pmu.c new file mode 100644 index 000000000000..0503c54d6363 --- /dev/null +++ b/drivers/soc/samsung/exynos850-pmu.c @@ -0,0 +1,95 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2026 Linaro Ltd. + * + * Exynos850 PMU support + */ + +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt + +#include +#include +#include +#include +#include +#include +#include + +#include "exynos-pmu.h" + +static int exynos850_cpu_pmu_offline(struct exynos_pmu_context *pmu_contex= t, unsigned int cpu) + __must_hold(&pmu_context->cpupm_lock) +{ + int cluster_id, core_id; + u32 reg, mask; + + cluster_id =3D topology_cluster_id(cpu); + if (cluster_id < 0) { + pr_err_ratelimited("invalid cluster ID for cpu: %u\n", cpu); + return -EINVAL; + } + + core_id =3D topology_core_id(cpu); + if (core_id < 0) { + pr_err_ratelimited("invalid core ID for cpu: %u\n", cpu); + return -EINVAL; + } + + /* set cpu inform hint */ + regmap_write(pmu_context->pmureg, EXYNOS850_CPU_INFORM(cpu), CPU_INFORM_C= 2); + + mask =3D BIT(cpu); + regmap_update_bits(pmu_context->pmuintrgen, EXYNOS_GRP2_INTR_BID_ENABLE, + mask, BIT(cpu)); + + regmap_read(pmu_context->pmuintrgen, EXYNOS_GRP1_INTR_BID_UPEND, ®); + regmap_write(pmu_context->pmuintrgen, EXYNOS_GRP1_INTR_BID_CLEAR, reg & m= ask); + + mask =3D (BIT(cpu + 8)); + regmap_read(pmu_context->pmuintrgen, EXYNOS_GRP1_INTR_BID_UPEND, ®); + regmap_write(pmu_context->pmuintrgen, EXYNOS_GRP1_INTR_BID_CLEAR, reg & m= ask); + + regmap_update_bits(pmu_context->pmureg, + EXYNOS850_CLUSTER_CPU_INT_EN(cluster_id, core_id), 1 << 3, 1 << 3); + return 0; +} + +static int exynos850_cpu_pmu_online(struct exynos_pmu_context *pmu_context= , unsigned int cpu) + __must_hold(&pmu_context->cpupm_lock) +{ + int cluster_id, core_id; + u32 reg, mask; + + cluster_id =3D topology_cluster_id(cpu); + if (cluster_id < 0) { + pr_err_ratelimited("invalid cluster ID for cpu: %u\n", cpu); + return -EINVAL; + } + + core_id =3D topology_core_id(cpu); + if (core_id < 0) { + pr_err_ratelimited("invalid core ID for cpu: %u\n", cpu); + return -EINVAL; + } + + /* clear cpu inform hint */ + regmap_write(pmu_context->pmureg, EXYNOS850_CPU_INFORM(cpu), CPU_INFORM_C= LEAR); + + mask =3D BIT(cpu); + regmap_update_bits(pmu_context->pmuintrgen, EXYNOS_GRP2_INTR_BID_ENABLE, + mask, (0 << cpu)); + + regmap_read(pmu_context->pmuintrgen, EXYNOS_GRP2_INTR_BID_UPEND, ®); + + regmap_write(pmu_context->pmuintrgen, EXYNOS_GRP2_INTR_BID_CLEAR, reg & m= ask); + + regmap_update_bits(pmu_context->pmureg, + EXYNOS850_CLUSTER_CPU_INT_EN(cluster_id, core_id), 1 << 3, 0 << 3); + return 0; +} + +const struct exynos_pmu_data exynos850_pmu_data =3D { + .pmu_cpuhp =3D true, + .cpu_pmu_offline =3D exynos850_cpu_pmu_offline, + .cpu_pmu_online =3D exynos850_cpu_pmu_online, +}; diff --git a/include/linux/soc/samsung/exynos-regs-pmu.h b/include/linux/so= c/samsung/exynos-regs-pmu.h index 9c4d3da41dbf..c7a82635fc36 100644 --- a/include/linux/soc/samsung/exynos-regs-pmu.h +++ b/include/linux/soc/samsung/exynos-regs-pmu.h @@ -1015,6 +1015,11 @@ #define EXYNOS_GRP2_INTR_BID_UPEND (0x0208) #define EXYNOS_GRP2_INTR_BID_CLEAR (0x020c) =20 +/* Exynos850 PMU Alive */ +#define EXYNOS850_CPU_INFORM(cpu) (0x0860 + ((cpu) & 7) * 4) +#define EXYNOS850_CLUSTER_CPU_OFFSET(cl, cpu) (0x1000 + (((cl) * 0x400) + = ((cpu) * 0x80))) +#define EXYNOS850_CLUSTER_CPU_INT_EN(cl, cpu) (EXYNOS850_CLUSTER_CPU_OFFSE= T(cl, cpu) + 0x44) + /* exynosautov920 */ #define EXYNOSAUTOV920_PHY_CTRL_USB20 (0x0710) #define EXYNOSAUTOV920_PHY_CTRL_USB31 (0x0714) --=20 2.51.0 From nobody Fri Jun 12 17:36:39 2026 Received: from mail-wm1-f42.google.com (mail-wm1-f42.google.com [209.85.128.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 17B524D90B6 for ; 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Tue, 09 Jun 2026 10:39:37 -0700 (PDT) Received: from [127.0.1.1] ([94.4.195.193]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-490bc3fcf5bsm593605215e9.9.2026.06.09.10.39.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Jun 2026 10:39:37 -0700 (PDT) From: Alexey Klimov Date: Tue, 09 Jun 2026 18:39:27 +0100 Subject: [PATCH v5 5/6] MAINTAINERS: add Exynos850 PMU entry Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260609-exynos850-cpuhotplug-v5-5-8422cf80d43b@linaro.org> References: <20260609-exynos850-cpuhotplug-v5-0-8422cf80d43b@linaro.org> In-Reply-To: <20260609-exynos850-cpuhotplug-v5-0-8422cf80d43b@linaro.org> To: Sam Protsenko , linux-samsung-soc@vger.kernel.org, Krzysztof Kozlowski , Peter Griffin Cc: linux-samsung-soc@vger.kernel.org, =?utf-8?q?Andr=C3=A9_Draszik?= , Tudor Ambarus , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar , Henrik Grimler , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.3 Add Exynos850 PMU entry describing new file drivers/soc/samsung/exynos850-pmu.c. Add myself as M there since I contributed Exynos850 PMU support and intend to maintain that. Signed-off-by: Alexey Klimov --- MAINTAINERS | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 498ca30a00c5..60c25fed8ffa 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -23645,6 +23645,13 @@ F: arch/arm64/boot/dts/exynos/exynos2200* F: drivers/clk/samsung/clk-exynos2200.c F: include/dt-bindings/clock/samsung,exynos2200-cmu.h =20 +SAMSUNG EXYNOS850 PMU SUPPORT +M: Alexey Klimov +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) +L: linux-samsung-soc@vger.kernel.org +S: Maintained +F: drivers/soc/samsung/exynos850-pmu.c + SAMSUNG EXYNOS850 SoC SUPPORT M: Sam Protsenko L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) --=20 2.51.0 From nobody Fri Jun 12 17:36:39 2026 Received: from mail-wm1-f47.google.com (mail-wm1-f47.google.com [209.85.128.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 420F64D90DF for ; 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Tue, 09 Jun 2026 10:39:38 -0700 (PDT) Received: from [127.0.1.1] ([94.4.195.193]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-490bc3fcf5bsm593605215e9.9.2026.06.09.10.39.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Jun 2026 10:39:38 -0700 (PDT) From: Alexey Klimov Date: Tue, 09 Jun 2026 18:39:28 +0100 Subject: [PATCH v5 6/6] arm64: dts: exynos850: add PMU interrupt generation node Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260609-exynos850-cpuhotplug-v5-6-8422cf80d43b@linaro.org> References: <20260609-exynos850-cpuhotplug-v5-0-8422cf80d43b@linaro.org> In-Reply-To: <20260609-exynos850-cpuhotplug-v5-0-8422cf80d43b@linaro.org> To: Sam Protsenko , linux-samsung-soc@vger.kernel.org, Krzysztof Kozlowski , Peter Griffin Cc: linux-samsung-soc@vger.kernel.org, =?utf-8?q?Andr=C3=A9_Draszik?= , Tudor Ambarus , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar , Henrik Grimler , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.3 Add pmu_intr_gen node for Exynos850. This hw block is required for different power management routines like CPU hotplug and different sleep and idle states. Also reference this node from main PMU node. Reviewed-by: Peter Griffin Signed-off-by: Alexey Klimov --- arch/arm64/boot/dts/exynos/exynos850.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos850.dtsi b/arch/arm64/boot/dt= s/exynos/exynos850.dtsi index 3881f573ec08..04662b1c5458 100644 --- a/arch/arm64/boot/dts/exynos/exynos850.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos850.dtsi @@ -214,6 +214,7 @@ gic: interrupt-controller@12a01000 { pmu_system_controller: system-controller@11860000 { compatible =3D "samsung,exynos850-pmu", "syscon"; reg =3D <0x11860000 0x10000>; + google,pmu-intr-gen-syscon =3D <&pmu_intr_gen>; =20 poweroff: syscon-poweroff { compatible =3D "syscon-poweroff"; @@ -231,6 +232,11 @@ reboot: syscon-reboot { }; }; =20 + pmu_intr_gen: syscon@11870000 { + compatible =3D "samsung,exynos850-pmu-intr-gen", "syscon"; + reg =3D <0x11870000 0x10000>; + }; + watchdog_cl0: watchdog@10050000 { compatible =3D "samsung,exynos850-wdt"; reg =3D <0x10050000 0x100>; --=20 2.51.0