From nobody Thu Jun 25 00:33:53 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C4EDF3D890E for ; Mon, 8 Jun 2026 17:20:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780939254; cv=none; b=rS1gsNewjhShSbbDrBrvIEwgaHcjj1R8xit7VjclmH5iCaTIlj8mCLBY+mpw1sdRGVa7SNXaARxxBK6QgQUQmtXt3BCjdBxwve9TorREnW4sERMsmGA48qZhpvmCzz/exmmahSslgBJFgmljl+W6i+j5ZHauwjpDyzFnSiF8V5E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780939254; c=relaxed/simple; bh=OMLP+uCENoAFecLoBJilbqGTAnWIIlg7uB7y+iEierI=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=ZZd8Xf16p/pKIja61slYfmAKKrkfYI9CCvHXI0aM7kGa4aeR5CzN70i2M5yaYg9oI30skICWKN3oDnsYcguF47cwKliF3MhynSm17y7faKTZXgz12mPuH1aZA6XeUHXHhO6LuwFhIe32cT9skzF8vMHBmrPB3QgeOObuztcLmJs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=QAVg628P; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=FgXBfl/a; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="QAVg628P"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="FgXBfl/a" Received: from pps.filterd (m0279863.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 658FFh3d3593094 for ; Mon, 8 Jun 2026 17:20:53 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=V2sa5Dvnjol aVGPuM8QeMt0IAdF0OTIT4oFME/COs60=; b=QAVg628POzrG7zt3KSIKtKL68OW rmtBx9jdbZPm45NozJZchs4HyY5qVubhnxqig+ij24v01h2VhDSqdfgigr6Nfhc8 XJ+jB1BiGR0heUXYg5t+RSShM1Aa98W4MP2ukrSqUPSomGln+y2fsDu3Q3C4OVQR r+cEVWg2kqESTTGC/BMn1plMBLGz9llIAaNUj7rYlnh74+xOk2MtOP8tx6n5j45B zhi55bNx50PyXIpGVH5pf48Vd9EF5PABXXc4zr8EUC2hRRMVNs+nd+N4J6NDg03N M/z43iZQuCRtWhz9acvCnsCUIU9+DTN2J4gXCOvscFMgazswZ5qCLl25qIw== Received: from mail-pf1-f200.google.com (mail-pf1-f200.google.com [209.85.210.200]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4enw5m1m77-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Mon, 08 Jun 2026 17:20:53 +0000 (GMT) Received: by mail-pf1-f200.google.com with SMTP id d2e1a72fcca58-8423f6247c6so5241384b3a.3 for ; Mon, 08 Jun 2026 10:20:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1780939252; x=1781544052; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=V2sa5DvnjolaVGPuM8QeMt0IAdF0OTIT4oFME/COs60=; b=FgXBfl/aY2qtQ7YIOG8CjayIVkwOeWwYfM1nvOCzZXgqu0rEbdoKSXB2KRbreChids MeTwbs68j+1s016fIXXwtCmSmD6qjGe/FLAfyb43HJsVklqsNRSpm/UY5epsgGiGZohS 5UJEyf7VtFQAQ6dqjpEw6OhO+0uTSmgBKaudJQEata2cjNLPyMX/2keppRiAlkPowSTh TAaZfCR0btcCMKEwXqLeKUs+eRztdfxzLzkp4dp0CpdNlXthWnz28nxM9SwDh4Bml/r0 +M6FxVtO7jcX82w8zSZLOt/J9nAoak80QoxoeTqh1ghW8abOgyrkU6ei37Szf8+CT7i6 FlUw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1780939252; x=1781544052; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=V2sa5DvnjolaVGPuM8QeMt0IAdF0OTIT4oFME/COs60=; b=Fy5zW/OljiZmjb4pUCgyqCxgA32nkPMK1T107apHbs0I/JV8sucAK9qhIl0K9rrFH2 zLbEC0muXIX2/PL23rLK6zay+MMs7QVXyNI9kLIMFAJ09FvHXQ+cPvEJPFQ24ayp/17L MVQqVYuKy3HW3J6dFmJL2CmELPHG8p5Hr/ewSowJImowuJ1vu2qANbZ3ZFpIFtME44rP q5ODSkTVNIqyJctVCrwfqNNc67kJ2k6dkNKk/KrLt0X/R6IB9yz5z+RuoNWwoOFqE4nS jiO4aLon7dx2t0b1eOqG3IMdPJ0GabwMpFV1fJe9Mw+m8UMsyC7DafcWhmVA021LK/T4 /cng== X-Forwarded-Encrypted: i=1; AFNElJ/CvJE2I65TOgC9h97BYJwc6qT7QjoJOXH9C+fLy5XNT84PREnRZLZK2B9MWikf0ZAD1uKp+bzfnxdcQxQ=@vger.kernel.org X-Gm-Message-State: AOJu0YyOSNR4NG9WzpDOeneWfLesM1oehfivEYNBAmc2nqUJFosJ9Dd1 6/vOvnNInhpMzcV4Ok/5x5oGpLOIyCVEChudMbEqSjko/7hMvTbcGLonI/HRGJUBHrQ/nDZwOic 2QThHibEl8vOBOqDp0gPUkfgT5MCIjK8uf/CB2p/wP9kr7Ke2M+CrWixnKlX2E4QXsr8= X-Gm-Gg: Acq92OHYISFuI2XrvmRqxg9K0JFCN0nMJ0uqPBrWBxdltD7ssoFI8gplXw2Mze8841H Puqb8Xcovtr9LOWDNPE4aAL0ukNFRztD+ufhv+xxQL5Oo+IfR43rvU4AZj4TnY1cjzkurP2RT80 qBgClOOX4pBowXoiw3CgXBOrvLH2Y6bpelHZ/vwya/QlDSx1iGNwKhZY9iYz3NXocNlXQ0Kda/g T4m3f0DCyanPFL2EIsF6gmKUlRWvhU9+s5ktv5LkYNUce2LMIz0QxFt2FMW95LVMKFCwayuYlwO 0BnftGdp4HnbUwiXsVbn3Ums5o3HqignuAd8AWL6dW94oeD5ii4xgfo5iBA4EO9KiBYwzrWHNUw LeNf+cMf/wJnW4lk94neGYZoGde1JUugltFp5ySZHQfmadz3GOG5N4DxT6dC95u1SKZy0 X-Received: by 2002:a05:6a00:114f:b0:842:7e7f:2914 with SMTP id d2e1a72fcca58-842b0d837famr15464843b3a.4.1780939252522; Mon, 08 Jun 2026 10:20:52 -0700 (PDT) X-Received: by 2002:a05:6a00:114f:b0:842:7e7f:2914 with SMTP id d2e1a72fcca58-842b0d837famr15464822b3a.4.1780939252106; Mon, 08 Jun 2026 10:20:52 -0700 (PDT) Received: from hu-mohs-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-84282221059sm17590409b3a.7.2026.06.08.10.20.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Jun 2026 10:20:51 -0700 (PDT) From: Mohammad Rafi Shaik To: Srinivas Kandagatla , Liam Girdwood , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jaroslav Kysela , Takashi Iwai Cc: linux-arm-msm@vger.kernel.org, linux-sound@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 1/3] ASoC: dt-bindings: qcom: Add Shikra rx and va macro codecs Date: Mon, 8 Jun 2026 22:50:21 +0530 Message-Id: <20260608172023.2965292-2-mohammad.rafi.shaik@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260608172023.2965292-1-mohammad.rafi.shaik@oss.qualcomm.com> References: <20260608172023.2965292-1-mohammad.rafi.shaik@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjA4MDE2NCBTYWx0ZWRfXwbVndfMM6euZ 3h0KAQroKHCHJIoNHcm/asUte1i0iEna5PDg3yVU6Cd6NWNA08F/VlA9yOx7T7lU4S4r9MiKz6z lGgBVs918wgtBAzVvf7h0I9FpqTeZUM2n6ps2i8ffYKpBoSU/U6+/C9G1glcAgN4fKg2ht1zg87 iMO2qYaWj598MFSJeQeVtxqxKUnLQ+tGXEWyDP2N4I1mJGI/xvW7/oV4CRZMO0in3Ww7ZcKK1kS 8rPQXF3Sy1LOwO7BF2d2xnSRRnKhOBK7955ANOf4kDnGWgxKjzZkEhhhWy81lCm/jnXmShw7fmL 9PjT5tdeJe2Xwq3jq9TphypNQHQtsyjPmA78wGSFTsX6SI+8cJlpuHvI71An3uCE2oFS4OXegxR qEHSkkKUA0JbGiHTC0jgT4xmcs98g5y3GFxoKn2Kwo1z/9R6A2KtipFOL2aYmJHxnWy3BQxmWGV JLApXPChd3GYou1yCOQ== X-Proofpoint-ORIG-GUID: Md5N1vNlY-sDee22w6dHZsrwPBAjtNUs X-Authority-Analysis: v=2.4 cv=UptT8ewB c=1 sm=1 tr=0 ts=6a26f9f5 cx=c_pps a=mDZGXZTwRPZaeRUbqKGCBw==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=EUspDBNiAAAA:8 a=oREbJnUDou8kn3UKV8gA:9 a=zc0IvFSfCIW2DFIPzwfm:22 X-Proofpoint-GUID: Md5N1vNlY-sDee22w6dHZsrwPBAjtNUs X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-08_04,2026-06-05_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 spamscore=0 lowpriorityscore=0 bulkscore=0 adultscore=0 clxscore=1015 malwarescore=0 impostorscore=0 suspectscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605210000 definitions=main-2606080164 Content-Type: text/plain; charset="utf-8" Add bindings for Qualcomm shikra rx and va macro codec. Signed-off-by: Mohammad Rafi Shaik --- Documentation/devicetree/bindings/sound/qcom,lpass-rx-macro.yaml | 1 + Documentation/devicetree/bindings/sound/qcom,lpass-va-macro.yaml | 1 + 2 files changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/sound/qcom,lpass-rx-macro.ya= ml b/Documentation/devicetree/bindings/sound/qcom,lpass-rx-macro.yaml index 2eed2277511f..07fe0dc51801 100644 --- a/Documentation/devicetree/bindings/sound/qcom,lpass-rx-macro.yaml +++ b/Documentation/devicetree/bindings/sound/qcom,lpass-rx-macro.yaml @@ -19,6 +19,7 @@ properties: - qcom,sm8450-lpass-rx-macro - qcom,sm8550-lpass-rx-macro - qcom,sc8280xp-lpass-rx-macro + - qcom,shikra-lpass-rx-macro - items: - enum: - qcom,kaanapali-lpass-rx-macro diff --git a/Documentation/devicetree/bindings/sound/qcom,lpass-va-macro.ya= ml b/Documentation/devicetree/bindings/sound/qcom,lpass-va-macro.yaml index 5c42b2b323ee..d43adaa2fbff 100644 --- a/Documentation/devicetree/bindings/sound/qcom,lpass-va-macro.yaml +++ b/Documentation/devicetree/bindings/sound/qcom,lpass-va-macro.yaml @@ -19,6 +19,7 @@ properties: - qcom,sm8450-lpass-va-macro - qcom,sm8550-lpass-va-macro - qcom,sc8280xp-lpass-va-macro + - qcom,shikra-lpass-va-macro - items: - enum: - qcom,glymur-lpass-va-macro --=20 2.34.1 From nobody Thu Jun 25 00:33:53 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EBBD93DB64D for ; Mon, 8 Jun 2026 17:20:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780939260; cv=none; b=RQqQGpP0DrZF0zU12nedkHc2kVjVP7E0cPy2dhxX4rljHTVLU8e8/LdvsufSEHTdksNrpuyBcYX71kwICXesPXjpJJoQFnsf+/Cok15kOqRkFRVIG1OBD1Vkw2MRqXXw8Fr0UDEkruz24aSTb1DXnKnga+CQXnoqzKZwD/fZSxg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780939260; c=relaxed/simple; bh=0jd7mihh8ACWVh4EcTW6xSrf8XmCjGByX2d8FT3LxWY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=eeZMPwaVPE2PyIMk9LeVLN/x+dPvMc2Z6MyjS8OAN9zXLUYMGZfBanj4RykcVvHP5Fbr7YCO7Kz0ioxRU9sfY0Bxvg9rlFQ9Lb73eFTizLTEFRU+YcVt7zjvElZ1Qo6pM/N9Y58pYg1prYiScbQ9Fb/hLezbsM95jSzmoDj9gaA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=Y9DjpZgf; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=XnTCjZJg; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="Y9DjpZgf"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="XnTCjZJg" Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 658FFeLT3971480 for ; Mon, 8 Jun 2026 17:20:58 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=gbxt1HAh8ZL N92HDEFPV+qV+PKjudLTq4Va2vv6Rdg0=; b=Y9DjpZgf4Dc960FTPhvH+A7uB0F 14Rxv/MCkwLly0CRGU7KPTWlI5kF6Dvaovna7kNi0vRwSJNGRlJr6Wcjgvg7A4xT EyvLdxG4UX0FrAyh59WoRuvxvt3vGU1SmSnJq/3gSRg3wq1AkG0DJlhz/diabl0r EENyJ367HE8NsfwcaXQEa8x6Yu3qHdzGCgpDzlrWhZdj1uHPd70elEDnkJiq1vk5 K39MGqBamazt+AkSDexBjxsh9SXxwizkLcnTvM24y5csDrKApv+j47AUykyuNSR9 prY5DM7r1iftllLuI5m34rSkFVgV37fA9ghGdzywLOrAtl2blYtgiNPA66Q== Received: from mail-pf1-f199.google.com (mail-pf1-f199.google.com [209.85.210.199]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4enuptj268-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Mon, 08 Jun 2026 17:20:57 +0000 (GMT) Received: by mail-pf1-f199.google.com with SMTP id d2e1a72fcca58-8422ca754d8so3028091b3a.1 for ; Mon, 08 Jun 2026 10:20:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1780939257; x=1781544057; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=gbxt1HAh8ZLN92HDEFPV+qV+PKjudLTq4Va2vv6Rdg0=; b=XnTCjZJgH6qWgcXCv9y0SITTaz55BpdfMT2nUt+1uNONKgAjGRDT1piUxD1PKmS++8 aYDHbsO+KgdydNHocnlBheCELnTpGL5XgEzZTe/QuLqh94y6+iN2vIL5qS/EvE2gH4xg qzYP2XoNtPpMAE66XKMKy3/JVy4t6G87R2CvM4iVS/3HgV+midBx2VlBAoMM0+XH9G8r QtjkCA6A6MVGVttggwRBQGLx1nP2IsfGEsAMN3bM0RCQeyt/SPTPdUjjSeP+HIk28ydW C9e9FlaQDitUG5PooKVzbKzRABNAsWcVdc9zHJbywaeBJXw5AAJ/E+DsfPxjRI+tHGaV yJPg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1780939257; x=1781544057; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=gbxt1HAh8ZLN92HDEFPV+qV+PKjudLTq4Va2vv6Rdg0=; b=Tz8+/eflr+qTneS/Jnq7Kr7jOyJSeQtKBxsUip8Lfl219QK9T8wk+KJgPZmg2r4djU EcRLSAqVTtHIuqHZf+U9cFcaGENDD0PSZrPi/G8J6q3/lrQEcSw7HKFK8j011A9ct2ti 3VVPEGLdT8b2HpjKwjL4BGlGrDCgxNHRvodxKdMXdeqPAEAOQqzyo8f7gYTFdWrBchFq MVke3tCQwVH5hVqRvZCVqGoJBK1e1lGTia3xZhWu/IQk7eRYEpO4848AqEPcRtS+61yR jLGJpd7Y3pL6kQqQAvN7b5q3H+r/oPUqheMeCmFMfJV7ZZeCBy/3YLUTytSVz5+N000/ 1X0Q== X-Forwarded-Encrypted: i=1; AFNElJ/OlXFh3cKQhzgEMxfAZp+a+ZJHoQIoVNBeMbvH4JDdR5+tEo/Uv24huz9y9jB0IGIQ2VcX4wbzyNuV6e4=@vger.kernel.org X-Gm-Message-State: AOJu0YxT0reqDrT2SHaUHU0p6lmczG57jcbcEupXAw4o+3y8VN2ze8wr uPPIBLn5GtZ72ijQBr4/YIg/x7YLJWUa6kSCPBYbi1oDX0Sy7QW4dKXjqFh3abD4YQ/AXrxxOFW gZrVyn+QsGJJ8ylLedYi9k+sQEBVv8KpN45B+GzvVqCaSbjjePOHF181I3pXgSl+IA1E= X-Gm-Gg: Acq92OFzrr+MRZTPS8CoBdG1Fpm5ot48Cs5iCPrDJmkQ20+W3kMzCfe21FSUK/oEq5k F3DKSoajHwGsGq8B0RD2P24dAHetde2Qc5XrMEh6T2ByNdLZKj1NzgMLr44AGo/StxUeMbRWG9r qbT1bvNDUOb5bY5XC7owmXUceZhYtnlMSmrxsAoCBCo0vkBbN1u68Snvn6TaeF2Zdb8yZFFs2Rn uc4wqZrDHiDyXSln6ecyRq+lErbNiD6ewWzNnKpL+Z1kOReg9SOF6qIUrViYK7qNYBCkJnlQbse VvTo0tMTeTjQSPj16qAAEX91SWDyP0sSyLiFvu9Q5eLOT9fO0u2uHNj+lQNZqQkI1rOx8ZiR1C4 pDlky2LlPAHzs01LLkNi9OPv6ZBCtKP5Of7WejJUPIp69E6ncKxAfSU7E1fuzTXmbSZIa X-Received: by 2002:a05:6a00:2993:b0:836:3f6a:3e7a with SMTP id d2e1a72fcca58-842b1007c0amr16327395b3a.26.1780939256794; Mon, 08 Jun 2026 10:20:56 -0700 (PDT) X-Received: by 2002:a05:6a00:2993:b0:836:3f6a:3e7a with SMTP id d2e1a72fcca58-842b1007c0amr16327366b3a.26.1780939256294; Mon, 08 Jun 2026 10:20:56 -0700 (PDT) Received: from hu-mohs-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-84282221059sm17590409b3a.7.2026.06.08.10.20.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Jun 2026 10:20:55 -0700 (PDT) From: Mohammad Rafi Shaik To: Srinivas Kandagatla , Liam Girdwood , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jaroslav Kysela , Takashi Iwai Cc: linux-arm-msm@vger.kernel.org, linux-sound@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 2/3] ASoC: qcom: lpass-rx-macro: Add shikra compatible Date: Mon, 8 Jun 2026 22:50:22 +0530 Message-Id: <20260608172023.2965292-3-mohammad.rafi.shaik@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260608172023.2965292-1-mohammad.rafi.shaik@oss.qualcomm.com> References: <20260608172023.2965292-1-mohammad.rafi.shaik@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: BNlGeRjk9M2Qqn5LTZqTYsEy8aY2mfkQ X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjA4MDE2NCBTYWx0ZWRfXxhOYix31iL1H VGRXd9c3FqIBg1kJE6subabHoP0E4S5rVVbtj7AGYpHd4nrAk9ZkO/k1vVPP7DMMDGC0IKbcROs +Iz8oLmbKkBUnl14ItT17aSnqX5X0t1d3w7r/kS6l3MYx8tUQohSH7ST6m3gXFlCVDjbmTHUjl7 E4xB4Do9I60XAP2qbH2xKGNN0D8h93oQTLYL9CcdU/6CV4zdYHdcK85rHt1OH7mumye6lh8P73H yUKyL/X8LsmHKCkoWI0VhSZ7jJ7rfessWv3V3sdXDvWHuXF6ocoeNtY4EGm3Ed73OOBz0fOxws8 nJe8foT+wsQ6O+SxBdccHKWUiVXLg9Sd6CrbUs+DebQdpTYeMK4FF18sEnpI3FqlIV18MnUmQfU g1BRiJzqDutQ0pyA9Cfwib7cIB9QJqR+JMcYKDM8uXp3jTVMZ2MmFLbq4x+LXyJw8bD9RCHv+Ph UXICa1OPHK0R3gbBxYQ== X-Authority-Analysis: v=2.4 cv=XKAAjwhE c=1 sm=1 tr=0 ts=6a26f9f9 cx=c_pps a=WW5sKcV1LcKqjgzy2JUPuA==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=EUspDBNiAAAA:8 a=8B9EPOnZN0DhMybeGFQA:9 a=OpyuDcXvxspvyRM73sMx:22 X-Proofpoint-GUID: BNlGeRjk9M2Qqn5LTZqTYsEy8aY2mfkQ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-08_04,2026-06-05_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 phishscore=0 lowpriorityscore=0 bulkscore=0 adultscore=0 suspectscore=0 malwarescore=0 spamscore=0 clxscore=1015 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605210000 definitions=main-2606080164 Content-Type: text/plain; charset="utf-8" Add shikra RX macro compatible data and hook it into the existing LPASS codec v4.0 flow. Map codec v4.0 to the 2.5+ RX register handling paths, and enable the FS counter bypass bit during MCLK enable when the platform requests LPASS_MACRO_FLAG_BYPASS_FS_CONTROL. Signed-off-by: Mohammad Rafi Shaik --- sound/soc/codecs/lpass-macro-common.h | 5 +++++ sound/soc/codecs/lpass-rx-macro.c | 14 ++++++++++++++ 2 files changed, 19 insertions(+) diff --git a/sound/soc/codecs/lpass-macro-common.h b/sound/soc/codecs/lpass= -macro-common.h index 10ad682019fa..86adad190a10 100644 --- a/sound/soc/codecs/lpass-macro-common.h +++ b/sound/soc/codecs/lpass-macro-common.h @@ -10,6 +10,8 @@ #define LPASS_MACRO_FLAG_HAS_NPL_CLOCK BIT(0) /* The soundwire block should be internally reset at probe */ #define LPASS_MACRO_FLAG_RESET_SWR BIT(1) +/* FS counter control bit[7] must be toggled (v4.0) */ +#define LPASS_MACRO_FLAG_BYPASS_FS_CONTROL BIT(2) =20 enum lpass_version { LPASS_VER_9_0_0, @@ -30,6 +32,7 @@ enum lpass_codec_version { LPASS_CODEC_VERSION_2_7, LPASS_CODEC_VERSION_2_8, LPASS_CODEC_VERSION_2_9, + LPASS_CODEC_VERSION_4_0, }; =20 struct lpass_macro { @@ -68,6 +71,8 @@ static inline const char *lpass_macro_get_codec_version_s= tring(int version) return "v2.7"; case LPASS_CODEC_VERSION_2_8: return "v2.8"; + case LPASS_CODEC_VERSION_4_0: + return "v4.0"; default: break; } diff --git a/sound/soc/codecs/lpass-rx-macro.c b/sound/soc/codecs/lpass-rx-= macro.c index 6233aa9f5bc6..3a3dec6b14cd 100644 --- a/sound/soc/codecs/lpass-rx-macro.c +++ b/sound/soc/codecs/lpass-rx-macro.c @@ -646,6 +646,7 @@ struct rx_macro { int clsh_users; int rx_mclk_cnt; enum lpass_codec_version codec_version; + bool bypass_fs_control; int rxn_reg_stride; int rxn_reg_stride2; bool is_ear_mode_on; @@ -1612,6 +1613,7 @@ static bool rx_is_rw_register(struct device *dev, uns= igned int reg) case LPASS_CODEC_VERSION_2_6: case LPASS_CODEC_VERSION_2_7: case LPASS_CODEC_VERSION_2_8: + case LPASS_CODEC_VERSION_4_0: return rx_2_5_is_rw_register(dev, reg); default: break; @@ -2043,6 +2045,11 @@ static void rx_macro_mclk_enable(struct rx_macro *rx= , bool mclk_enable) CDC_RX_CLK_MCLK2_ENABLE); regmap_update_bits(regmap, CDC_RX_CLK_RST_CTRL_FS_CNT_CONTROL, CDC_RX_FS_MCLK_CNT_CLR_MASK, 0x00); + + if (rx->bypass_fs_control) + regmap_update_bits(regmap, + CDC_RX_CLK_RST_CTRL_FS_CNT_CONTROL, + 0x80, 0x80); regmap_update_bits(regmap, CDC_RX_CLK_RST_CTRL_FS_CNT_CONTROL, CDC_RX_FS_MCLK_CNT_EN_MASK, CDC_RX_FS_MCLK_CNT_ENABLE); @@ -3648,6 +3655,7 @@ static int rx_macro_component_probe(struct snd_soc_co= mponent *component) case LPASS_CODEC_VERSION_2_6: case LPASS_CODEC_VERSION_2_7: case LPASS_CODEC_VERSION_2_8: + case LPASS_CODEC_VERSION_4_0: controls =3D rx_macro_2_5_snd_controls; num_controls =3D ARRAY_SIZE(rx_macro_2_5_snd_controls); widgets =3D rx_macro_2_5_dapm_widgets; @@ -3809,6 +3817,7 @@ static int rx_macro_probe(struct platform_device *pde= v) return PTR_ERR(base); =20 rx->codec_version =3D lpass_macro_get_codec_version(); + rx->bypass_fs_control =3D !!(flags & LPASS_MACRO_FLAG_BYPASS_FS_CONTROL); struct reg_default *reg_defaults __free(kfree) =3D NULL; =20 switch (rx->codec_version) { @@ -3831,6 +3840,7 @@ static int rx_macro_probe(struct platform_device *pde= v) case LPASS_CODEC_VERSION_2_6: case LPASS_CODEC_VERSION_2_7: case LPASS_CODEC_VERSION_2_8: + case LPASS_CODEC_VERSION_4_0: rx->rxn_reg_stride =3D 0xc0; rx->rxn_reg_stride2 =3D 0x0; def_count =3D ARRAY_SIZE(rx_defaults) + ARRAY_SIZE(rx_2_5_defaults); @@ -3961,6 +3971,10 @@ static const struct of_device_id rx_macro_dt_match[]= =3D { }, { .compatible =3D "qcom,sc8280xp-lpass-rx-macro", .data =3D (void *)LPASS_MACRO_FLAG_HAS_NPL_CLOCK, + }, { + .compatible =3D "qcom,shikra-lpass-rx-macro", + .data =3D (void *)(LPASS_MACRO_FLAG_HAS_NPL_CLOCK | + LPASS_MACRO_FLAG_BYPASS_FS_CONTROL), }, { } }; --=20 2.34.1 From nobody Thu Jun 25 00:33:53 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6063A3DCDB7 for ; Mon, 8 Jun 2026 17:21:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780939265; cv=none; b=ZXQK94GBgbMWSnZAXfhZzuEX9aNFhNLpq+aTIuGhmOca4Lk31KB8JLC3WX4ael11jf1IU5cBQt50z/6VXq2LxLUfxQJbi9g5Ilp7GaQYWm7x7qKQZxYLINyV0msKTgf7X4G1R+zm6VTw71N1xkdmk8uBsZoVHKRbmh5svzzbjt8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780939265; c=relaxed/simple; bh=LsbtL8WxOuTyNIvCVL4eiU1HaJF6qCdGwZtZffvzC7g=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=elczOas/OTIaIxsrG7RS6fJOCMimH3zjoGWfiSVUH7H4xAeLcgSZCPrDodKDlh2Mbt5K8F9otggu4XvEZ80gen2jNde0CmK1a6SC2RvYL3smnmbkIqnK23bo/4ti0t2hbJHSZziJP3mo7i6Q6oNhnByinP/uTjM+jcZPro331AM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=VQWVd2kj; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=f4FWeCO1; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="VQWVd2kj"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="f4FWeCO1" Received: from pps.filterd (m0279863.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 658FFRKR3592882 for ; Mon, 8 Jun 2026 17:21:01 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=8JXEaP0we+p 3cefk1Csn6U/OyR2c7qgAlxITwtCdLPc=; b=VQWVd2kji7QNLyiyL+t5EqVNS8j YJYEnLXjNd1WDPzpzKdTa1m9QdCynNzknpB/RUsSIWT/WHAJ+1EMPOGZtfOX/C1x j0VPrSEC/okSD1SuKzhd+4VzyR5/vIXODkZobNONt7lMEanJfXHglImcUv2axpoX Gk4dl6tQSs7LbTfzxwFXoYNuvIQZbX3CtHef6FRbyvIKpJmwGOGz0Gxm3rKIeM9I ibp4j9mzD097YhzmJQYKA2DyJJwU3LP7oPvzppue5BhMKP0vqNwUEOe1rnanrfKy hpJ+cjdUDH1lOj3xB89kt3Jskp6Y19TXoFEq/Ny3ZOnTCJKtq4aEkukHnjQ== Received: from mail-pf1-f198.google.com (mail-pf1-f198.google.com [209.85.210.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4enw5m1m7w-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Mon, 08 Jun 2026 17:21:01 +0000 (GMT) Received: by mail-pf1-f198.google.com with SMTP id d2e1a72fcca58-8423f1fe39eso5004588b3a.1 for ; Mon, 08 Jun 2026 10:21:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1780939261; x=1781544061; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=8JXEaP0we+p3cefk1Csn6U/OyR2c7qgAlxITwtCdLPc=; b=f4FWeCO1WHlTCZ7RcyQkCOPKNpNbcizKA5FUWDvDr1WO3OrlXhMDeAggKq3e6f56RB CArBpsLpbh+vF6tpopleCa782frMWyF8JOAt0oD/AxR3/BhQZbQ8VAtOmz9wxMg2HDwJ RAlojw1QtDtUdW5os7nqZawcMAxTx4kiPmfT91e939jYf8G4e1vcrVH+z+m+ZIgMF3Hb s+Db7biDBzkYZCfea5oLVh/4LiPA+7IyyFZzYDEtBela7k5r+SoFXyLdpgyO1hTP/frA gQHGTxwXjohfp/DBcQZagCRanwhujZS1AiHFEUvWSrUn7/f5dOHVql+xo58hKDGvM84j +G8w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1780939261; x=1781544061; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=8JXEaP0we+p3cefk1Csn6U/OyR2c7qgAlxITwtCdLPc=; b=MN3kFnUJhRLrRFfVZXXTeK0JgCGNhOvp8+bkjMwB7YOld0b4Tf2vRPHI/Iz9ee46Ez WM/Z8ZkLz3n+wptA6IOgZXURW6D1Uuk5y+SaxygiVjc0lmNuoYZbNBIttmh1Y1S87RwG HCNv/gA3QvbxUQCuy0H8XuT5Kd3si8f8g4DrzE4wHXY1ICawx/yeNUEKe0gDB1Jip369 02h6Wb5ty7cxac2sGWE8BOfBYW1XcJFWsxb7I8W4M94TVe+FCyeY+0vjyzI6rTffPGqn 6Ym4+c/NLSJ2EdchmL84FgH8/agC4DM7BlMAaeWUtOiA5s5f6zVrWJAoVYIPoIuvHAIS D+1Q== X-Forwarded-Encrypted: i=1; AFNElJ/DRp06y8OUw2s574xswWkyBrxmV7qrPlk4RP8KuYFkL0VrIS+5rrNQCSM7dDYsO31ksRXvXeW864R9ULs=@vger.kernel.org X-Gm-Message-State: AOJu0YwhdjC8w9UUlHHIqaOcJx6P5ZMgl1kHVeCDovxQM+SRANEoFV3Z MPjkyqMrP9zzTIAqz5VEduvRJk3dS5PNux3zSqK/mCihWfvYkAjbnFHAn51yq0z9MLu30hhVi+u vaQipVGPU8lGcF8YUqiAy0ujEtwMaJMX8BCgj5TZunIXlDU68m6SxM4kpkmk8LyLB2I0= X-Gm-Gg: Acq92OHPseoRVH7bgkqEZI7CIvJZNxYtijsYgCFuMgqRXTssPDMGoU5V3uj+kcom5Te qxvN3/DK4LYdZ1bqAV1Rz/kmdSEan2B39XJbqcF5//vLoRVGhwAl97rFTaOCF6TkfN/vOywXeKJ 0Z5i9ex+zsGv9G/SO18ssotqq2I5NhxzayhVTO49cThs1cfJDAwpEdYWzvVkpwGKJnUheaoPLuZ yPgmtlP7OKWr/ROeF/2+w51gIgQjOyHiCSR4Ja7VfoAz1Vcd1bPlX6RnUuIc7Bm0Xwju3bv5qw7 VGTRJdGjt+iwD8g2k11X1RTaCUmRCMv9w4eXJrZzeYAAK6tLVVN+V4MTrVqkLKQQIQuLnHvyx8d gYFL78haLQ4KsvxS4iB3ESGAx01pQIcciTE2KjSbGVk8q6iNiVW/d0vNRNjV2a83AuL1B X-Received: by 2002:a05:6a00:bc81:b0:842:4907:d089 with SMTP id d2e1a72fcca58-842b0ef2b79mr16782229b3a.34.1780939260891; Mon, 08 Jun 2026 10:21:00 -0700 (PDT) X-Received: by 2002:a05:6a00:bc81:b0:842:4907:d089 with SMTP id d2e1a72fcca58-842b0ef2b79mr16782198b3a.34.1780939260430; Mon, 08 Jun 2026 10:21:00 -0700 (PDT) Received: from hu-mohs-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-84282221059sm17590409b3a.7.2026.06.08.10.20.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Jun 2026 10:21:00 -0700 (PDT) From: Mohammad Rafi Shaik To: Srinivas Kandagatla , Liam Girdwood , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jaroslav Kysela , Takashi Iwai Cc: linux-arm-msm@vger.kernel.org, linux-sound@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 3/3] ASoC: qcom: lpass-va-macro: Add shikra compatible Date: Mon, 8 Jun 2026 22:50:23 +0530 Message-Id: <20260608172023.2965292-4-mohammad.rafi.shaik@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260608172023.2965292-1-mohammad.rafi.shaik@oss.qualcomm.com> References: <20260608172023.2965292-1-mohammad.rafi.shaik@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjA4MDE2NCBTYWx0ZWRfXw/bsahu4Hugp Vp/xVSJA9JW35103TVfUx6m1gQG4OkRqwDqb57sMEvTwPQN92fnwLH+o3/+Pm9Xuh49WN+0Kmik 4FbYifI5/1rU76bR0bDYV1lOfTOZIhOvW1nGiAJeceyaYDUtmI+3GNWGdUC3pD9HjUHqW/dRqDq T2sqjGdPrrqyLJfil46wUmfmChHdDhXZVkqpkVFBnDFahXV8xO5d8NM+US4i3cR+T1cE3WvxsWb iNvQOE5mJojA9Tsan7gJzAKOzIggIP6iyYBZbxSUEud9rEmYYn0YmhR0a1DtoCiLqFkne02wkbd JIswOx0wsihuMj+RSyGuJTwHUsJFFLlvIHOrQvFt4ka1pCCGe4aMYKB0pzZunprbJGmDMgY7ZG5 UT9hkclP3HuWDjpIwUgiIWPfX9oQMMN4XS1+ei58wAgPCs0OqqBMOa29qIX6kYKCKDnnU3xUfau OB4ahK83rpH/6qREQ3g== X-Proofpoint-ORIG-GUID: DLb-xz-eVecs5ztj3nr6VgId2qnUiPIp X-Authority-Analysis: v=2.4 cv=UptT8ewB c=1 sm=1 tr=0 ts=6a26f9fd cx=c_pps a=m5Vt/hrsBiPMCU0y4gIsQw==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=EUspDBNiAAAA:8 a=PVzo0dxaLDckdvgPDkQA:9 a=IoOABgeZipijB_acs4fv:22 X-Proofpoint-GUID: DLb-xz-eVecs5ztj3nr6VgId2qnUiPIp X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-08_04,2026-06-05_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 spamscore=0 lowpriorityscore=0 bulkscore=0 adultscore=0 clxscore=1015 malwarescore=0 impostorscore=0 suspectscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605210000 definitions=main-2606080164 Content-Type: text/plain; charset="utf-8" Add shikra specific VA macro data and register programming needed by the LPASS codec v4.0 implementation. This adds a shikra regmap/default table covering the ADPT register range, wires new match data flags (bypass FS control and ADPT block presence), and enables the ADPT control programming path during TX decimator bring-up. Signed-off-by: Mohammad Rafi Shaik --- sound/soc/codecs/lpass-va-macro.c | 276 +++++++++++++++++++++++++++--- 1 file changed, 255 insertions(+), 21 deletions(-) diff --git a/sound/soc/codecs/lpass-va-macro.c b/sound/soc/codecs/lpass-va-= macro.c index 528d5b167ecf..4a8daa07ec1c 100644 --- a/sound/soc/codecs/lpass-va-macro.c +++ b/sound/soc/codecs/lpass-va-macro.c @@ -155,7 +155,57 @@ #define CDC_VA_TX3_TX_PATH_SEC5 (0x05A4) #define CDC_VA_TX3_TX_PATH_SEC6 (0x05A8) =20 +/* ADPT control registers - Shikra adaptive filter blocks */ +#define CDC_VA_CDC_ADPT0_ADPT_CTRL (0x0800) +#define CDC_VA_CDC_ADPT0_ADPT_GAIN_0 (0x0804) +#define CDC_VA_CDC_ADPT0_ADPT_GAIN_1 (0x0808) +#define CDC_VA_CDC_ADPT0_DH_FSM_CTRL (0x080C) +#define CDC_VA_CDC_ADPT0_CUTOFF_FSM_CTRL_0 (0x0810) +#define CDC_VA_CDC_ADPT0_CUTOFF_FSM_CTRL_1 (0x0814) +#define CDC_VA_CDC_ADPT0_CUTOFF_FSM_CTRL_2 (0x0818) +#define CDC_VA_CDC_ADPT0_CUTOFF_FSM_CTRL_3 (0x081C) +#define CDC_VA_CDC_ADPT0_CUTOFF_FSM_CTRL_4 (0x0820) +#define CDC_VA_CDC_ADPT0_CUTOFF_FSM_CTRL_5 (0x0824) + +#define CDC_VA_CDC_ADPT1_ADPT_CTRL (0x0880) +#define CDC_VA_CDC_ADPT1_ADPT_GAIN_0 (0x0884) +#define CDC_VA_CDC_ADPT1_ADPT_GAIN_1 (0x0888) +#define CDC_VA_CDC_ADPT1_DH_FSM_CTRL (0x088C) +#define CDC_VA_CDC_ADPT1_CUTOFF_FSM_CTRL_0 (0x0890) +#define CDC_VA_CDC_ADPT1_CUTOFF_FSM_CTRL_1 (0x0894) +#define CDC_VA_CDC_ADPT1_CUTOFF_FSM_CTRL_2 (0x0898) +#define CDC_VA_CDC_ADPT1_CUTOFF_FSM_CTRL_3 (0x089C) +#define CDC_VA_CDC_ADPT1_CUTOFF_FSM_CTRL_4 (0x08A0) +#define CDC_VA_CDC_ADPT1_CUTOFF_FSM_CTRL_5 (0x08A4) +#define CDC_VA_CDC_ADPT1_DBG_CTRL (0x08B0) +#define CDC_VA_CDC_ADPT1_DBG_PDM_RATE_CTRL_0 (0x08B2) +#define CDC_VA_CDC_ADPT1_DBG_PDM_RATE_CTRL_1 (0x08B4) +#define CDC_VA_CDC_ADPT1_SPARE0 (0x08B8) + +#define CDC_VA_CDC_ADPT2_ADPT_CTRL (0x0900) +#define CDC_VA_CDC_ADPT2_ADPT_GAIN_0 (0x0904) +#define CDC_VA_CDC_ADPT2_ADPT_GAIN_1 (0x0908) +#define CDC_VA_CDC_ADPT2_DH_FSM_CTRL (0x090C) +#define CDC_VA_CDC_ADPT2_CUTOFF_FSM_CTRL_0 (0x0910) +#define CDC_VA_CDC_ADPT2_CUTOFF_FSM_CTRL_1 (0x0914) +#define CDC_VA_CDC_ADPT2_CUTOFF_FSM_CTRL_2 (0x0918) +#define CDC_VA_CDC_ADPT2_CUTOFF_FSM_CTRL_3 (0x091C) +#define CDC_VA_CDC_ADPT2_CUTOFF_FSM_CTRL_4 (0x0920) +#define CDC_VA_CDC_ADPT2_CUTOFF_FSM_CTRL_5 (0x0924) + +#define CDC_VA_CDC_ADPT3_ADPT_CTRL (0x0980) +#define CDC_VA_CDC_ADPT3_ADPT_GAIN_0 (0x0984) +#define CDC_VA_CDC_ADPT3_ADPT_GAIN_1 (0x0988) +#define CDC_VA_CDC_ADPT3_DH_FSM_CTRL (0x098C) +#define CDC_VA_CDC_ADPT3_CUTOFF_FSM_CTRL_0 (0x0990) +#define CDC_VA_CDC_ADPT3_CUTOFF_FSM_CTRL_1 (0x0994) +#define CDC_VA_CDC_ADPT3_CUTOFF_FSM_CTRL_2 (0x0998) +#define CDC_VA_CDC_ADPT3_CUTOFF_FSM_CTRL_3 (0x099C) +#define CDC_VA_CDC_ADPT3_CUTOFF_FSM_CTRL_4 (0x09A0) +#define CDC_VA_CDC_ADPT3_CUTOFF_FSM_CTRL_5 (0x09A4) + #define VA_MAX_OFFSET (0x07A8) +#define VA_SHIKRA_MAX_OFFSET (0x0980) =20 #define VA_MACRO_NUM_DECIMATORS 4 #define VA_MACRO_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ @@ -209,6 +259,8 @@ struct va_macro { u16 dmic_clk_div; bool has_swr_master; bool has_npl_clk; + bool bypass_fs_control; + bool has_adpt_block; =20 int dec_mode[VA_MACRO_NUM_DECIMATORS]; struct regmap *regmap; @@ -235,24 +287,12 @@ struct va_macro { struct va_macro_data { bool has_swr_master; bool has_npl_clk; + bool bypass_fs_control; + bool has_adpt_block; int version; + const struct regmap_config *regmap_config; }; =20 -static const struct va_macro_data sm8250_va_data =3D { - .has_swr_master =3D false, - .has_npl_clk =3D false, - .version =3D LPASS_CODEC_VERSION_1_0, -}; - -static const struct va_macro_data sm8450_va_data =3D { - .has_swr_master =3D true, - .has_npl_clk =3D true, -}; - -static const struct va_macro_data sm8550_va_data =3D { - .has_swr_master =3D true, - .has_npl_clk =3D false, -}; =20 static bool va_is_volatile_register(struct device *dev, unsigned int reg) { @@ -424,6 +464,10 @@ static bool va_is_rw_register(struct device *dev, unsi= gned int reg) case CDC_VA_TX3_TX_PATH_SEC4: case CDC_VA_TX3_TX_PATH_SEC5: case CDC_VA_TX3_TX_PATH_SEC6: + case CDC_VA_CDC_ADPT0_ADPT_CTRL: + case CDC_VA_CDC_ADPT1_ADPT_CTRL: + case CDC_VA_CDC_ADPT2_ADPT_CTRL: + case CDC_VA_CDC_ADPT3_ADPT_CTRL: return true; } =20 @@ -457,6 +501,174 @@ static const struct regmap_config va_regmap_config = =3D { .writeable_reg =3D va_is_rw_register, }; =20 +static const struct reg_default va_shikra_defaults[] =3D { + /* VA macro */ + { CDC_VA_CLK_RST_CTRL_MCLK_CONTROL, 0x00}, + { CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL, 0x00}, + { CDC_VA_CLK_RST_CTRL_SWR_CONTROL, 0x00}, + { CDC_VA_TOP_CSR_TOP_CFG0, 0x00}, + { CDC_VA_TOP_CSR_DMIC0_CTL, 0x00}, + { CDC_VA_TOP_CSR_DMIC1_CTL, 0x00}, + { CDC_VA_TOP_CSR_DMIC2_CTL, 0x00}, + { CDC_VA_TOP_CSR_DMIC3_CTL, 0x00}, + { CDC_VA_TOP_CSR_DMIC_CFG, 0x80}, + { CDC_VA_TOP_CSR_DEBUG_BUS, 0x00}, + { CDC_VA_TOP_CSR_DEBUG_EN, 0x00}, + { CDC_VA_TOP_CSR_TX_I2S_CTL, 0x0C}, + { CDC_VA_TOP_CSR_I2S_CLK, 0x00}, + { CDC_VA_TOP_CSR_I2S_RESET, 0x00}, + { CDC_VA_TOP_CSR_CORE_ID_0, 0x00}, + { CDC_VA_TOP_CSR_CORE_ID_1, 0x00}, + { CDC_VA_TOP_CSR_CORE_ID_2, 0x00}, + { CDC_VA_TOP_CSR_CORE_ID_3, 0x00}, + { CDC_VA_TOP_CSR_SWR_MIC_CTL0, 0xEE}, + { CDC_VA_TOP_CSR_SWR_MIC_CTL1, 0xEE}, + { CDC_VA_TOP_CSR_SWR_MIC_CTL2, 0xEE}, + { CDC_VA_TOP_CSR_SWR_CTRL, 0x06}, + /* VA core */ + { CDC_VA_INP_MUX_ADC_MUX0_CFG0, 0x00}, + { CDC_VA_INP_MUX_ADC_MUX0_CFG1, 0x00}, + { CDC_VA_INP_MUX_ADC_MUX1_CFG0, 0x00}, + { CDC_VA_INP_MUX_ADC_MUX1_CFG1, 0x00}, + { CDC_VA_INP_MUX_ADC_MUX2_CFG0, 0x00}, + { CDC_VA_INP_MUX_ADC_MUX2_CFG1, 0x00}, + { CDC_VA_INP_MUX_ADC_MUX3_CFG0, 0x00}, + { CDC_VA_INP_MUX_ADC_MUX3_CFG1, 0x00}, + { CDC_VA_TX0_TX_PATH_CTL, 0x04}, + { CDC_VA_TX0_TX_PATH_CFG0, 0x10}, + { CDC_VA_TX0_TX_PATH_CFG1, 0x0B}, + { CDC_VA_TX0_TX_VOL_CTL, 0x00}, + { CDC_VA_TX0_TX_PATH_SEC0, 0x00}, + { CDC_VA_TX0_TX_PATH_SEC1, 0x00}, + { CDC_VA_TX0_TX_PATH_SEC2, 0x01}, + { CDC_VA_TX0_TX_PATH_SEC3, 0x3C}, + { CDC_VA_TX0_TX_PATH_SEC4, 0x20}, + { CDC_VA_TX0_TX_PATH_SEC5, 0x00}, + { CDC_VA_TX0_TX_PATH_SEC6, 0x00}, + { CDC_VA_TX0_TX_PATH_SEC7, 0x25}, + { CDC_VA_TX1_TX_PATH_CTL, 0x04}, + { CDC_VA_TX1_TX_PATH_CFG0, 0x10}, + { CDC_VA_TX1_TX_PATH_CFG1, 0x0B}, + { CDC_VA_TX1_TX_VOL_CTL, 0x00}, + { CDC_VA_TX1_TX_PATH_SEC0, 0x00}, + { CDC_VA_TX1_TX_PATH_SEC1, 0x00}, + { CDC_VA_TX1_TX_PATH_SEC2, 0x01}, + { CDC_VA_TX1_TX_PATH_SEC3, 0x3C}, + { CDC_VA_TX1_TX_PATH_SEC4, 0x20}, + { CDC_VA_TX1_TX_PATH_SEC5, 0x00}, + { CDC_VA_TX1_TX_PATH_SEC6, 0x00}, + { CDC_VA_TX2_TX_PATH_CTL, 0x04}, + { CDC_VA_TX2_TX_PATH_CFG0, 0x10}, + { CDC_VA_TX2_TX_PATH_CFG1, 0x0B}, + { CDC_VA_TX2_TX_VOL_CTL, 0x00}, + { CDC_VA_TX2_TX_PATH_SEC0, 0x00}, + { CDC_VA_TX2_TX_PATH_SEC1, 0x00}, + { CDC_VA_TX2_TX_PATH_SEC2, 0x01}, + { CDC_VA_TX2_TX_PATH_SEC3, 0x3C}, + { CDC_VA_TX2_TX_PATH_SEC4, 0x20}, + { CDC_VA_TX2_TX_PATH_SEC5, 0x00}, + { CDC_VA_TX2_TX_PATH_SEC6, 0x00}, + { CDC_VA_TX3_TX_PATH_CTL, 0x04}, + { CDC_VA_TX3_TX_PATH_CFG0, 0x10}, + { CDC_VA_TX3_TX_PATH_CFG1, 0x0B}, + { CDC_VA_TX3_TX_VOL_CTL, 0x00}, + { CDC_VA_TX3_TX_PATH_SEC0, 0x00}, + { CDC_VA_TX3_TX_PATH_SEC1, 0x00}, + { CDC_VA_TX3_TX_PATH_SEC2, 0x01}, + { CDC_VA_TX3_TX_PATH_SEC3, 0x3C}, + { CDC_VA_TX3_TX_PATH_SEC4, 0x20}, + { CDC_VA_TX3_TX_PATH_SEC5, 0x00}, + { CDC_VA_TX3_TX_PATH_SEC6, 0x00}, + /* ADPT blocks - Shikra adaptive filter control */ + + /* CDC ADPT0 - adaptive filter */ + { CDC_VA_CDC_ADPT0_ADPT_CTRL, 0x51}, + { CDC_VA_CDC_ADPT0_ADPT_GAIN_0, 0x11}, + { CDC_VA_CDC_ADPT0_ADPT_GAIN_1, 0x01}, + { CDC_VA_CDC_ADPT0_DH_FSM_CTRL, 0x02}, + { CDC_VA_CDC_ADPT0_CUTOFF_FSM_CTRL_0, 0x77}, + { CDC_VA_CDC_ADPT0_CUTOFF_FSM_CTRL_1, 0x64}, + { CDC_VA_CDC_ADPT0_CUTOFF_FSM_CTRL_2, 0x00}, + { CDC_VA_CDC_ADPT0_CUTOFF_FSM_CTRL_3, 0x41}, + { CDC_VA_CDC_ADPT0_CUTOFF_FSM_CTRL_4, 0x04}, + { CDC_VA_CDC_ADPT0_CUTOFF_FSM_CTRL_5, 0x01}, + + /* CDC ADPT1 */ + { CDC_VA_CDC_ADPT1_ADPT_CTRL, 0x51}, + { CDC_VA_CDC_ADPT1_ADPT_GAIN_0, 0x11}, + { CDC_VA_CDC_ADPT1_ADPT_GAIN_1, 0x01}, + { CDC_VA_CDC_ADPT1_DH_FSM_CTRL, 0x02}, + { CDC_VA_CDC_ADPT1_CUTOFF_FSM_CTRL_0, 0x77}, + { CDC_VA_CDC_ADPT1_CUTOFF_FSM_CTRL_1, 0x64}, + { CDC_VA_CDC_ADPT1_CUTOFF_FSM_CTRL_2, 0x00}, + { CDC_VA_CDC_ADPT1_CUTOFF_FSM_CTRL_3, 0x41}, + { CDC_VA_CDC_ADPT1_CUTOFF_FSM_CTRL_4, 0x04}, + { CDC_VA_CDC_ADPT1_CUTOFF_FSM_CTRL_5, 0x01}, + + /* CDC ADPT2 */ + { CDC_VA_CDC_ADPT2_ADPT_CTRL, 0x51}, + { CDC_VA_CDC_ADPT2_ADPT_GAIN_0, 0x11}, + { CDC_VA_CDC_ADPT2_ADPT_GAIN_1, 0x01}, + { CDC_VA_CDC_ADPT2_DH_FSM_CTRL, 0x02}, + { CDC_VA_CDC_ADPT2_CUTOFF_FSM_CTRL_0, 0x77}, + { CDC_VA_CDC_ADPT2_CUTOFF_FSM_CTRL_1, 0x64}, + { CDC_VA_CDC_ADPT2_CUTOFF_FSM_CTRL_2, 0x00}, + { CDC_VA_CDC_ADPT2_CUTOFF_FSM_CTRL_3, 0x41}, + { CDC_VA_CDC_ADPT2_CUTOFF_FSM_CTRL_4, 0x04}, + { CDC_VA_CDC_ADPT2_CUTOFF_FSM_CTRL_5, 0x01}, + + /* CDC ADPT3 */ + { CDC_VA_CDC_ADPT3_ADPT_CTRL, 0x51}, + { CDC_VA_CDC_ADPT3_ADPT_GAIN_0, 0x11}, + { CDC_VA_CDC_ADPT3_ADPT_GAIN_1, 0x01}, + { CDC_VA_CDC_ADPT3_DH_FSM_CTRL, 0x02}, + { CDC_VA_CDC_ADPT3_CUTOFF_FSM_CTRL_0, 0x77}, + { CDC_VA_CDC_ADPT3_CUTOFF_FSM_CTRL_1, 0x64}, + { CDC_VA_CDC_ADPT3_CUTOFF_FSM_CTRL_2, 0x00}, + { CDC_VA_CDC_ADPT3_CUTOFF_FSM_CTRL_3, 0x41}, + { CDC_VA_CDC_ADPT3_CUTOFF_FSM_CTRL_4, 0x04}, + { CDC_VA_CDC_ADPT3_CUTOFF_FSM_CTRL_5, 0x01}, +}; + +static const struct regmap_config shikra_va_regmap_config =3D { + .name =3D "va_macro", + .reg_bits =3D 32, + .val_bits =3D 32, + .reg_stride =3D 4, + .cache_type =3D REGCACHE_FLAT, + .reg_defaults =3D va_shikra_defaults, + .num_reg_defaults =3D ARRAY_SIZE(va_shikra_defaults), + .max_register =3D VA_SHIKRA_MAX_OFFSET, + .volatile_reg =3D va_is_volatile_register, + .readable_reg =3D va_is_readable_register, + .writeable_reg =3D va_is_rw_register, +}; + +static const struct va_macro_data sm8250_va_data =3D { + .has_swr_master =3D false, + .has_npl_clk =3D false, + .version =3D LPASS_CODEC_VERSION_1_0, +}; + +static const struct va_macro_data sm8450_va_data =3D { + .has_swr_master =3D true, + .has_npl_clk =3D true, +}; + +static const struct va_macro_data shikra_va_data =3D { + .has_swr_master =3D true, + .has_npl_clk =3D true, + .bypass_fs_control =3D true, + .has_adpt_block =3D true, + .version =3D LPASS_CODEC_VERSION_4_0, + .regmap_config =3D &shikra_va_regmap_config, +}; + +static const struct va_macro_data sm8550_va_data =3D { + .has_swr_master =3D true, + .has_npl_clk =3D false, +}; + static int va_clk_rsc_fs_gen_request(struct va_macro *va, bool enable) { struct regmap *regmap =3D va->regmap; @@ -469,6 +681,10 @@ static int va_clk_rsc_fs_gen_request(struct va_macro *= va, bool enable) regmap_update_bits(regmap, CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL, CDC_VA_FS_CONTROL_EN | CDC_VA_FS_COUNTER_CLR, CDC_VA_FS_CONTROL_EN | CDC_VA_FS_COUNTER_CLR); + + if (va->bypass_fs_control) + regmap_update_bits(regmap, CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL, + 0x80, 0x80); regmap_update_bits(regmap, CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL, CDC_VA_FS_CONTROL_EN | CDC_VA_FS_COUNTER_CLR, CDC_VA_FS_CONTROL_EN); @@ -497,7 +713,7 @@ static int va_macro_mclk_enable(struct va_macro *va, bo= ol mclk_enable) if (mclk_enable) { va_clk_rsc_fs_gen_request(va, true); regcache_mark_dirty(regmap); - regcache_sync_region(regmap, 0x0, VA_MAX_OFFSET); + regcache_sync_region(regmap, 0x0, regmap_get_max_register(regmap)); } else { va_clk_rsc_fs_gen_request(va, false); } @@ -743,6 +959,7 @@ static int va_macro_enable_dec(struct snd_soc_dapm_widg= et *w, unsigned int decimator; u16 tx_vol_ctl_reg, dec_cfg_reg, hpf_gate_reg; u16 tx_gain_ctl_reg; + u16 adapt_ctrl; u8 hpf_cut_off_freq; =20 struct va_macro *va =3D snd_soc_component_get_drvdata(comp); @@ -757,6 +974,8 @@ static int va_macro_enable_dec(struct snd_soc_dapm_widg= et *w, VA_MACRO_TX_PATH_OFFSET * decimator; tx_gain_ctl_reg =3D CDC_VA_TX0_TX_VOL_CTL + VA_MACRO_TX_PATH_OFFSET * decimator; + adapt_ctrl =3D CDC_VA_CDC_ADPT0_ADPT_CTRL + + (decimator * VA_MACRO_TX_PATH_OFFSET); =20 switch (event) { case SND_SOC_DAPM_PRE_PMU: @@ -766,6 +985,8 @@ static int va_macro_enable_dec(struct snd_soc_dapm_widg= et *w, /* Enable TX PGA Mute */ break; case SND_SOC_DAPM_POST_PMU: + if (va->has_adpt_block) + snd_soc_component_update_bits(comp, adapt_ctrl, 0xFF, 0x00); /* Enable TX CLK */ snd_soc_component_update_bits(comp, tx_vol_ctl_reg, CDC_VA_TX_PATH_CLK_EN_MASK, @@ -1511,6 +1732,14 @@ static int va_macro_set_lpass_codec_version(struct v= a_macro *va) default: break; } + } else if (maj =3D=3D 4) { + switch (min) { + case 0: + version =3D LPASS_CODEC_VERSION_4_0; + break; + default: + break; + } } =20 if (version =3D=3D LPASS_CODEC_VERSION_UNKNOWN) { @@ -1576,7 +1805,15 @@ static int va_macro_probe(struct platform_device *pd= ev) goto err; } =20 - va->regmap =3D devm_regmap_init_mmio(dev, base, &va_regmap_config); + data =3D of_device_get_match_data(dev); + va->has_swr_master =3D data->has_swr_master; + va->has_npl_clk =3D data->has_npl_clk; + va->bypass_fs_control =3D data->bypass_fs_control; + va->has_adpt_block =3D data->has_adpt_block; + + va->regmap =3D devm_regmap_init_mmio(dev, base, + data->regmap_config ? data->regmap_config + : &va_regmap_config); if (IS_ERR(va->regmap)) { ret =3D -EINVAL; goto err; @@ -1584,10 +1821,6 @@ static int va_macro_probe(struct platform_device *pd= ev) =20 dev_set_drvdata(dev, va); =20 - data =3D of_device_get_match_data(dev); - va->has_swr_master =3D data->has_swr_master; - va->has_npl_clk =3D data->has_npl_clk; - /* mclk rate */ clk_set_rate(va->mclk, 2 * VA_MACRO_MCLK_FREQ); =20 @@ -1761,6 +1994,7 @@ static const struct of_device_id va_macro_dt_match[] = =3D { { .compatible =3D "qcom,sm8450-lpass-va-macro", .data =3D &sm8450_va_data= }, { .compatible =3D "qcom,sm8550-lpass-va-macro", .data =3D &sm8550_va_data= }, { .compatible =3D "qcom,sc8280xp-lpass-va-macro", .data =3D &sm8450_va_da= ta }, + { .compatible =3D "qcom,shikra-lpass-va-macro", .data =3D &shikra_va_data= }, {} }; MODULE_DEVICE_TABLE(of, va_macro_dt_match); --=20 2.34.1