From nobody Mon Jun 8 18:55:14 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3389E3976BE for ; Mon, 8 Jun 2026 07:58:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780905509; cv=none; b=JIAlQ+gNPptwPl744pcgLzp8ONzpPRx77NRkE33D+TtA7//SJ+crWhVAcnuQCaoAACFcRFHCoyX+2a9L5k1/Ws9o5gRIBEYaaU8ETQ3BJWnDmWG2ZYeU7VzV4FU6fnVJyExWEA6Gw1Zt8IomdYuAHw96x9xH9b1//ZIZG9VSXYY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780905509; c=relaxed/simple; bh=fYUKQwXEODXgUL0RQCOezn0uRebdWFq8B2C9AOq7dsk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=PMgHEqIuRwYcbPaGJ86WPbk01N3kV25jHtVUVXmEDV0HntQljJLrgjiYqYbM+l7Ph3k/cN2PUSUjWGkWn0JT9KIJCHHUVXnIwsNpHC98pJzlZjdXzRhh1BsqRecrOcW9uUh2S8Ljmg4Egq+E/bqBuPG3/8XtnyZyF3HX+0GwgbU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=jGPw+iX/; arc=none smtp.client-ip=198.175.65.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="jGPw+iX/" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1780905507; x=1812441507; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=fYUKQwXEODXgUL0RQCOezn0uRebdWFq8B2C9AOq7dsk=; b=jGPw+iX/Ek1MXJbB1E7HQkK44mqXKnIw8N1ptl9RFm5xcCie1Ek7Vc+r oUwWB5aVLcKogXiIesx3V6mEZheI72y0CLRxi2ZLrAeTfe3lkgOVEVR2i k0kNBP3wgE4ldX4pH3zifpgIOSdn5z5RfSQo6rvN6cKEAWr7Okb/KBZlW SXae2oHeNV+NFk+Bj4kr3ajT7C0u1dqcT7UbxLMPGt5bSzg8ycFbH4dMe YTkMzGzhGu2pfM3dZkNjrtF+bWAT71l3lE4q+9z6rowYrLem2rZ9Y3ZnX oc7lQUWkcv2eY/b1hvSPlSM22oxLiJDCufPXgYfW7FkygwuHijx/2LT1X g==; X-CSE-ConnectionGUID: 9xHUEgAMT768u+K01oOsgQ== X-CSE-MsgGUID: PAfRms+WSh+IubeTDex4kQ== X-IronPort-AV: E=McAfee;i="6800,10657,11810"; a="85520146" X-IronPort-AV: E=Sophos;i="6.24,194,1774335600"; d="scan'208";a="85520146" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jun 2026 00:58:26 -0700 X-CSE-ConnectionGUID: vFGv5i0gQV+i7gVmywwqxw== X-CSE-MsgGUID: Lz5eIxhZQmad1lqFFCcwYg== X-ExtLoop1: 1 Received: from conormcd-mobl2.ger.corp.intel.com (HELO ahunter6-desk) ([10.245.244.114]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jun 2026 00:58:24 -0700 From: Adrian Hunter To: alexandre.belloni@bootlin.com Cc: Frank.Li@nxp.com, linux-i3c@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH V2 1/7] i3c: mipi-i3c-hci: Fix race in i3c_hci_addr_to_dev() Date: Mon, 8 Jun 2026 10:57:54 +0300 Message-ID: <20260608075801.16111-2-adrian.hunter@intel.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260608075801.16111-1-adrian.hunter@intel.com> References: <20260608075801.16111-1-adrian.hunter@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Organization: Intel Finland Oy, Registered Address: c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" i3c_hci_addr_to_dev() walks bus->devs.i3c, which is protected by bus.lock (rwsem). However, it is invoked from the MIPI I3C HCI IRQ handler, which cannot take bus.lock. This allows concurrent device addition/removal in the I3C core to modify the list while it is being traversed, potentially leading to use-after-free or crashes. Remove the dependency on the bus device list and introduce a dedicated lookup table. Add an ibi_devs[] array indexed by DAT entry, maintained under hci->lock. Update the array when IBIs are enabled or disabled, so that it always reflects the set of devices allowed to generate IBIs. Also update when IBIs are freed, to cover the corner case when an IBI is freed without first being disabled (e.g. oldedev in i3c_master_add_i3c_dev_locked()). Move i3c_hci_addr_to_dev() into core.c, reimplement it using the new array, and add a lockdep assertion to enforce that hci->lock is held by callers. Demote a message in PIO and DMA IBI handling, from an error to a debug message, because there is a race window when the condition can arise normally. Fixes: 9ad9a52cce282 ("i3c/master: introduce the mipi-i3c-hci driver") Signed-off-by: Adrian Hunter Reviewed-by: Frank Li --- Changes in V2: Factor out __i3c_hci_disable_ibi() to facilitate also clearing ibi_devs[dat_idx] upon IBI free, and update commit message accordingly. Demote a message in PIO and DMA IBI handling, and update commit message accordingly. drivers/i3c/master/mipi-i3c-hci/core.c | 37 ++++++++++++++++++++++++-- drivers/i3c/master/mipi-i3c-hci/dma.c | 7 +++-- drivers/i3c/master/mipi-i3c-hci/hci.h | 1 + drivers/i3c/master/mipi-i3c-hci/ibi.h | 13 +-------- drivers/i3c/master/mipi-i3c-hci/pio.c | 7 +++-- 5 files changed, 47 insertions(+), 18 deletions(-) diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mi= pi-i3c-hci/core.c index 53797841b63f..1e1f05aff092 100644 --- a/drivers/i3c/master/mipi-i3c-hci/core.c +++ b/drivers/i3c/master/mipi-i3c-hci/core.c @@ -22,6 +22,7 @@ #include "ext_caps.h" #include "cmd.h" #include "dat.h" +#include "ibi.h" =20 /* * Host Controller Capabilities and Operation Registers @@ -124,6 +125,7 @@ static void i3c_hci_set_master_dyn_addr(struct i3c_hci = *hci) static int i3c_hci_bus_init(struct i3c_master_controller *m) { struct i3c_hci *hci =3D to_i3c_hci(m); + struct device *dev =3D hci->master.dev.parent; struct i3c_device_info info; int ret; =20 @@ -144,6 +146,10 @@ static int i3c_hci_bus_init(struct i3c_master_controll= er *m) if (ret) return ret; =20 + hci->ibi_devs =3D devm_kcalloc(dev, hci->DAT_entries, sizeof(*hci->ibi_de= vs), GFP_KERNEL); + if (!hci->ibi_devs) + return -ENOMEM; + ret =3D hci->io->init(hci); if (ret) return ret; @@ -639,14 +645,40 @@ static int i3c_hci_request_ibi(struct i3c_dev_desc *d= ev, return hci->io->request_ibi(hci, dev, req); } =20 +static void __i3c_hci_disable_ibi(struct i3c_hci *hci, struct i3c_dev_desc= *dev) +{ + struct i3c_hci_dev_data *dev_data =3D i3c_dev_get_master_data(dev); + + mipi_i3c_hci_dat_v1.set_flags(hci, dev_data->dat_idx, DAT_0_SIR_REJECT, 0= ); + scoped_guard(spinlock_irqsave, &hci->lock) + hci->ibi_devs[dev_data->dat_idx] =3D NULL; +} + static void i3c_hci_free_ibi(struct i3c_dev_desc *dev) { struct i3c_master_controller *m =3D i3c_dev_get_master(dev); struct i3c_hci *hci =3D to_i3c_hci(m); =20 + /* Must ensure the IBI has been disabled */ + __i3c_hci_disable_ibi(hci, dev); hci->io->free_ibi(hci, dev); } =20 +struct i3c_dev_desc *i3c_hci_addr_to_dev(struct i3c_hci *hci, unsigned int= addr) +{ + int dat_idx; + + lockdep_assert_held(&hci->lock); + + for (dat_idx =3D 0; dat_idx < hci->DAT_entries; dat_idx++) { + struct i3c_dev_desc *dev =3D hci->ibi_devs[dat_idx]; + + if (dev && dev->info.dyn_addr =3D=3D addr) + return dev; + } + return NULL; +} + static int i3c_hci_enable_ibi(struct i3c_dev_desc *dev) { struct i3c_master_controller *m =3D i3c_dev_get_master(dev); @@ -654,6 +686,8 @@ static int i3c_hci_enable_ibi(struct i3c_dev_desc *dev) struct i3c_hci_dev_data *dev_data =3D i3c_dev_get_master_data(dev); =20 mipi_i3c_hci_dat_v1.clear_flags(hci, dev_data->dat_idx, DAT_0_SIR_REJECT,= 0); + scoped_guard(spinlock_irqsave, &hci->lock) + hci->ibi_devs[dev_data->dat_idx] =3D dev; return i3c_master_enec_locked(m, dev->info.dyn_addr, I3C_CCC_EVENT_SIR); } =20 @@ -661,9 +695,8 @@ static int i3c_hci_disable_ibi(struct i3c_dev_desc *dev) { struct i3c_master_controller *m =3D i3c_dev_get_master(dev); struct i3c_hci *hci =3D to_i3c_hci(m); - struct i3c_hci_dev_data *dev_data =3D i3c_dev_get_master_data(dev); =20 - mipi_i3c_hci_dat_v1.set_flags(hci, dev_data->dat_idx, DAT_0_SIR_REJECT, 0= ); + __i3c_hci_disable_ibi(hci, dev); return i3c_master_disec_locked(m, dev->info.dyn_addr, I3C_CCC_EVENT_SIR); } =20 diff --git a/drivers/i3c/master/mipi-i3c-hci/dma.c b/drivers/i3c/master/mip= i-i3c-hci/dma.c index 87622d6f817e..0672ed1132f8 100644 --- a/drivers/i3c/master/mipi-i3c-hci/dma.c +++ b/drivers/i3c/master/mipi-i3c-hci/dma.c @@ -967,8 +967,11 @@ static void hci_dma_process_ibi(struct i3c_hci *hci, s= truct hci_rh_data *rh) =20 dev =3D i3c_hci_addr_to_dev(hci, ibi_addr); if (!dev) { - dev_err(&hci->master.dev, - "IBI for unknown device %#x\n", ibi_addr); + /* + * Either an IBI received just before IBI's were disabled, or + * the controller is broken. Assume the former. + */ + dev_dbg(&hci->master.dev, "IBI when not enabled at address %#x\n", ibi_a= ddr); goto done; } =20 diff --git a/drivers/i3c/master/mipi-i3c-hci/hci.h b/drivers/i3c/master/mip= i-i3c-hci/hci.h index 41d31a53abd3..b3d9803b1968 100644 --- a/drivers/i3c/master/mipi-i3c-hci/hci.h +++ b/drivers/i3c/master/mipi-i3c-hci/hci.h @@ -65,6 +65,7 @@ struct i3c_hci { unsigned int DAT_entry_size; void *DAT_data; struct dat_words *DAT; + struct i3c_dev_desc **ibi_devs; unsigned int DCT_entries; unsigned int DCT_entry_size; u8 version_major; diff --git a/drivers/i3c/master/mipi-i3c-hci/ibi.h b/drivers/i3c/master/mip= i-i3c-hci/ibi.h index e1f98e264da0..073ca67b7d04 100644 --- a/drivers/i3c/master/mipi-i3c-hci/ibi.h +++ b/drivers/i3c/master/mipi-i3c-hci/ibi.h @@ -26,17 +26,6 @@ #define IBI_DATA_LENGTH GENMASK(7, 0) =20 /* handy helpers */ -static inline struct i3c_dev_desc * -i3c_hci_addr_to_dev(struct i3c_hci *hci, unsigned int addr) -{ - struct i3c_bus *bus =3D i3c_master_get_bus(&hci->master); - struct i3c_dev_desc *dev; - - i3c_bus_for_each_i3cdev(bus, dev) { - if (dev->info.dyn_addr =3D=3D addr) - return dev; - } - return NULL; -} +struct i3c_dev_desc *i3c_hci_addr_to_dev(struct i3c_hci *hci, unsigned int= addr); =20 #endif diff --git a/drivers/i3c/master/mipi-i3c-hci/pio.c b/drivers/i3c/master/mip= i-i3c-hci/pio.c index b5ae1cfaa9e0..ff2657ee220b 100644 --- a/drivers/i3c/master/mipi-i3c-hci/pio.c +++ b/drivers/i3c/master/mipi-i3c-hci/pio.c @@ -869,8 +869,11 @@ static bool hci_pio_prep_new_ibi(struct i3c_hci *hci, = struct hci_pio_data *pio) =20 dev =3D i3c_hci_addr_to_dev(hci, ibi->addr); if (!dev) { - dev_err(&hci->master.dev, - "IBI for unknown device %#x\n", ibi->addr); + /* + * Either an IBI received just before IBI's were disabled, or + * the controller is broken. Assume the former. + */ + dev_dbg(&hci->master.dev, "IBI when not enabled at address %#x\n", ibi->= addr); return true; } =20 --=20 2.51.0 From nobody Mon Jun 8 18:55:14 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A8CBD3955C6 for ; Mon, 8 Jun 2026 07:58:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780905509; cv=none; b=Bhek9E1WglY03OumUS67nov/KvZWn1uSCExX3exjKjW2jmpTQcGG9qd9/sQ2iYuxbbI6xcM60nwkzHBNA43Ve2zxwQhzkMEeXnzrdp1SIPs+vXmGnhR93yRhxcNKRvwexvy3sFjImPgnJyBx5UsggzLkIWXQkOJASpmq4IKOuDM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780905509; c=relaxed/simple; bh=KvsnUxNlENe/8t68Aly3yDXUNfe5o9kjNbO4x0qNTAs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=GpHXyaWx2P2V1QDww0WXhubRW3b6ds3uPp21Abnhr1DwKUjyev6oKacoLJPlKA9l+yu3JKTqEB8S/CQLgIgOkKKhNrM60JmCTNFg5Ybewq8smezdHsQ/sbnmTrg8Swj2Awj0Fa2I4vgFDF1V05VANj9DLzhD4l+llaVapMcuk+c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=XpBWBIkQ; arc=none smtp.client-ip=198.175.65.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="XpBWBIkQ" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1780905508; x=1812441508; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=KvsnUxNlENe/8t68Aly3yDXUNfe5o9kjNbO4x0qNTAs=; b=XpBWBIkQy+J4BnyTIf8nGe3Z9ZlkKp6aT2haNo2v2eCzqe6b+K87u6IC qoPvmPwbxs4OsljLwm4qZ8axyYletnnQPD9o08yy7auhW4xKSEcl552aR Ey2aNU4xtXWvbDj+gAjTFUWZZENfV7FBOEneXpvKUbOui5UXeENQE9Saf 9DeTkQCzpBOFLGKCS5xUcFkDoYzLAABGuL85ZiWAknqHlryQstv+Z7a76 Gc9+42y4H9SRtbqTOrM8NQRWdzwCNXENhPqcjNAjnggvVYooYQa1pssvj nKe8yeuyGPoPFQGzzoAO/t5C5JjIQswTCkYwSOYPUb7q2EtXZWoTHLcqJ Q==; X-CSE-ConnectionGUID: 2mirFFDjR7+YIHCHHIJnJQ== X-CSE-MsgGUID: qlOPyzOHRnqPqVWkHHkBow== X-IronPort-AV: E=McAfee;i="6800,10657,11810"; a="85520155" X-IronPort-AV: E=Sophos;i="6.24,194,1774335600"; d="scan'208";a="85520155" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jun 2026 00:58:28 -0700 X-CSE-ConnectionGUID: pYxwM8Z7TcqmVdiqPrZEWw== X-CSE-MsgGUID: Bq3gfeTAQsaP7kKFmac7Ug== X-ExtLoop1: 1 Received: from conormcd-mobl2.ger.corp.intel.com (HELO ahunter6-desk) ([10.245.244.114]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jun 2026 00:58:26 -0700 From: Adrian Hunter To: alexandre.belloni@bootlin.com Cc: Frank.Li@nxp.com, linux-i3c@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH V2 2/7] i3c: mipi-i3c-hci: Ignore DISEC failures when disabling IBIs Date: Mon, 8 Jun 2026 10:57:55 +0300 Message-ID: <20260608075801.16111-3-adrian.hunter@intel.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260608075801.16111-1-adrian.hunter@intel.com> References: <20260608075801.16111-1-adrian.hunter@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Organization: Intel Finland Oy, Registered Address: c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Content-Transfer-Encoding: quoted-printable Disabling IBIs currently returns the result of the DISEC CCC, causing i3c_hci_disable_ibi() to fail if the transfer errors out. However, the controller has already been programmed to reject IBIs by setting DAT_0_SIR_REJECT, so the target=E2=80=99s IBIs are effectively disa= bled from the host side regardless of the outcome of the DISEC command. At this point, teardown of the IBI infrastructure can safely proceed even if DISEC fails. Note, from then on, the MIPI I3C HCI not only NACKs the target's IBI but automatically sends another DISEC command. Make i3c_hci_disable_ibi() resilient by ignoring the return value of i3c_master_disec_locked() and always returning success. Signed-off-by: Adrian Hunter Reviewed-by: Frank Li --- Changes in V2: Re-base due to changes in previous patch. drivers/i3c/master/mipi-i3c-hci/core.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mi= pi-i3c-hci/core.c index 1e1f05aff092..fffbc1775ef9 100644 --- a/drivers/i3c/master/mipi-i3c-hci/core.c +++ b/drivers/i3c/master/mipi-i3c-hci/core.c @@ -697,7 +697,13 @@ static int i3c_hci_disable_ibi(struct i3c_dev_desc *de= v) struct i3c_hci *hci =3D to_i3c_hci(m); =20 __i3c_hci_disable_ibi(hci, dev); - return i3c_master_disec_locked(m, dev->info.dyn_addr, I3C_CCC_EVENT_SIR); + /* + * The DAT entry is now set to NACK and DISEC this target's IBIs, so + * the IBI teardown can proceed even if DISEC below fails, so ignore + * errors. + */ + i3c_master_disec_locked(m, dev->info.dyn_addr, I3C_CCC_EVENT_SIR); + return 0; } =20 static void i3c_hci_recycle_ibi_slot(struct i3c_dev_desc *dev, --=20 2.51.0 From nobody Mon Jun 8 18:55:14 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A541F397E9A for ; Mon, 8 Jun 2026 07:58:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780905511; cv=none; b=NWQvL6jD+o8uglHbMLBbz6uJ2V07E3ipAUPaNYvJlXEojaR1/di4gV5Xm6WVNh2X9dAxdtFu46ZGTOrCnT+rQVUrLVeCQDB3gWYrDwYvufAbeBl5fNXH92Gz32LVIujRPPp7/CxzvEV3DEezW6/p/ojVIPEwbTGNQMp8WAJImDk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780905511; c=relaxed/simple; bh=TroHJn8S3OibCjpk35ZIgDkqpK8FwCd59x0jWgKNUYE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=eNdXooVqE26uxeRp0NbCsaE+L57VcoV2J8WEHBNZmVlwJSg0DKRC7mRQ/wLZyNcBlsa/znklH9yrFqrx1FIZ+uNXyI+SnhLt5BXvfN567ngqwyNkZZPnrDmLPk7ZTu+zuyvCva5NjSAHHx5fuoW9jpH72lB1CX2GtfC3kCfwSMA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=VqF/G7Lg; arc=none smtp.client-ip=198.175.65.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="VqF/G7Lg" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1780905510; x=1812441510; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=TroHJn8S3OibCjpk35ZIgDkqpK8FwCd59x0jWgKNUYE=; b=VqF/G7LglHU7gb0KmsjujcAMpSft/W1XoWcY4538ueS1YF1+frUBtn5+ VxsBqGOage9P29GW1DGQhK5mttbbwm6ztfivahpl4l/IVBN/vbPp7DOYh bopBwDCeJSYFb8n5iEWzXys16YCXyGC9M/+5kb0MxKVcL4GaI0SgZOAD1 EfCTyaHk4wwNR2dVLKmbHfLNRDW29/t4WEYg1WnIFZFB2L+Q9AKB57Y/a 4Xf9F57xcpX0Hyclp/uUUFUzC0fYIPgBI+dGPh6sJvb/xzEuAStGP3+JJ PqUA348/8iDmLmnswdH/1vXMi4aAR6ZqcbzBrSQvR+nXAujO/J5IJnmls Q==; X-CSE-ConnectionGUID: kOuDmUdcTIuuK6qtn7x4GQ== X-CSE-MsgGUID: c8Rdfc8jRtC7hd60a2KtLA== X-IronPort-AV: E=McAfee;i="6800,10657,11810"; a="85520163" X-IronPort-AV: E=Sophos;i="6.24,194,1774335600"; d="scan'208";a="85520163" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jun 2026 00:58:30 -0700 X-CSE-ConnectionGUID: jJj8fnRsRfOsu66UFsd5gQ== X-CSE-MsgGUID: HPwtSjkLSkWPhjXQfG0/IQ== X-ExtLoop1: 1 Received: from conormcd-mobl2.ger.corp.intel.com (HELO ahunter6-desk) ([10.245.244.114]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jun 2026 00:58:28 -0700 From: Adrian Hunter To: alexandre.belloni@bootlin.com Cc: Frank.Li@nxp.com, linux-i3c@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH V2 3/7] i3c: master: Prevent reuse of dynamic address on device add failure Date: Mon, 8 Jun 2026 10:57:56 +0300 Message-ID: <20260608075801.16111-4-adrian.hunter@intel.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260608075801.16111-1-adrian.hunter@intel.com> References: <20260608075801.16111-1-adrian.hunter@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Organization: Intel Finland Oy, Registered Address: c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" i3c_master_add_i3c_dev_locked() is called after a device has already been assigned a dynamic address. If the function fails, the address remains marked as free and may be reallocated to another device, leading to address conflicts on the bus. Ensure the address is not marked as free on failure, by updating the address slot state to prevent the address from being re-used. Emit an error message to inform of the failure. Opportunistically remove the !master check because it is impossible. Fixes: 3a379bbcea0af ("i3c: Add core I3C infrastructure") Signed-off-by: Adrian Hunter --- Changes in V2: Fix 'if (IS_ERR(newdev)' error path. Be defensive and do not change the addr_slot_status if it is not free, and update commit message accordingly. Amend commit message to note removal of unnecesary 'if (!master)' check. Add Fixes tag. drivers/i3c/master.c | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/drivers/i3c/master.c b/drivers/i3c/master.c index f87bf0099d3c..7b60b0c7f646 100644 --- a/drivers/i3c/master.c +++ b/drivers/i3c/master.c @@ -2345,12 +2345,11 @@ int i3c_master_add_i3c_dev_locked(struct i3c_master= _controller *master, bool enable_ibi =3D false; int ret; =20 - if (!master) - return -EINVAL; - newdev =3D i3c_master_alloc_i3c_dev(master, &info); - if (IS_ERR(newdev)) - return PTR_ERR(newdev); + if (IS_ERR(newdev)) { + ret =3D PTR_ERR(newdev); + goto err_prevent_addr_reuse; + } =20 ret =3D i3c_master_attach_i3c_dev(master, newdev); if (ret) @@ -2472,6 +2471,16 @@ int i3c_master_add_i3c_dev_locked(struct i3c_master_= controller *master, err_free_dev: i3c_master_free_i3c_dev(newdev); =20 +err_prevent_addr_reuse: + /* + * Although the device has not been added, the address has been + * assigned. Prevent the address from being used again. + */ + if (i3c_bus_get_addr_slot_status(&master->bus, addr) =3D=3D I3C_ADDR_SLOT= _FREE) + i3c_bus_set_addr_slot_status(&master->bus, addr, I3C_ADDR_SLOT_I3C_DEV); + + dev_err(&master->dev, "Failed to add I3C device at address %u, error %d\n= ", addr, ret); + return ret; } EXPORT_SYMBOL_GPL(i3c_master_add_i3c_dev_locked); --=20 2.51.0 From nobody Mon Jun 8 18:55:14 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7935439A04B for ; Mon, 8 Jun 2026 07:58:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780905512; cv=none; b=KhBm+DuWpCIx7LfscWNpAdanUbY8obQSROG4WUL5uIXLhHmxYD56V8XRcSQbbyMRnKVvtVh8F6hxpg8IRMmQqqNtRQmn6CHiQM9r0T7TGxfjSwZRjeKBD2U9ikVZRMGpXVYYCMKrh/fHC7yZ+0f2WszY3/EeJN13vyuDSBMygA4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780905512; c=relaxed/simple; bh=XO4DeisrwcQtk5baWXSHoM5AXo8nYE21pzj0QPcZ7AA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=GomVAwuprDh/xNCGWRJXxGqD0p9fDdCoXk+BeChVavjBbOj9Xs9WKvilZPA3F4PjqPv10IKj5gt/tWwdCIB9XeC1v0VmhpCcfExaYHPl0pkGGuPKj5kIfU5OJi7xvBwb9uiLI26vvH8ijq/20kJOvY0lcJHOTpS6wKQVurVwLiU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=fdhNqpmR; arc=none smtp.client-ip=198.175.65.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="fdhNqpmR" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1780905512; x=1812441512; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=XO4DeisrwcQtk5baWXSHoM5AXo8nYE21pzj0QPcZ7AA=; b=fdhNqpmRDGBFceu72BxgN3ugSYD/k1cjW3ImKHQC0FTUfAU2+e2OywoI Nsab33Uo7a6VlDDaiqV5x+FEIk9LwV+r3E3wxa9U6wW2Mzq4SMhwceQnM f+0wbP1n6Ojvm3OZ9yGB8mIxMixjf1yfJIacvGEcaJ6/kEeAyNcigkgZ9 G1HgtrZHqwAQ1O1Y6HB06+p5ohCrxpMb+4DzeqJkwKaRS8B/Rj8FFBtlX 88VGalpIj2a50ZDtoKjX++21B4clocbbUwoKLwemJn7Yd0TIzfjDiGsNK 2Ses5mKw9quc6EHhvYCxBHe6Cv2sF5GZXTKT9UEAZXcGz4rRSLRRw0FzL A==; X-CSE-ConnectionGUID: D79VvYr7RKSHHnze3cenjg== X-CSE-MsgGUID: p50Wy1i1Q46910S34BqkTA== X-IronPort-AV: E=McAfee;i="6800,10657,11810"; a="85520169" X-IronPort-AV: E=Sophos;i="6.24,194,1774335600"; d="scan'208";a="85520169" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jun 2026 00:58:31 -0700 X-CSE-ConnectionGUID: dKWuDpKiTZ+YuZ0K6aJ/rw== X-CSE-MsgGUID: pBhpL7xKRQODLrqVlTwC7A== X-ExtLoop1: 1 Received: from conormcd-mobl2.ger.corp.intel.com (HELO ahunter6-desk) ([10.245.244.114]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jun 2026 00:58:29 -0700 From: Adrian Hunter To: alexandre.belloni@bootlin.com Cc: Frank.Li@nxp.com, linux-i3c@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH V2 4/7] i3c: mipi-i3c-hci: Tolerate i3c_master_add_i3c_dev_locked() failures in DAA Date: Mon, 8 Jun 2026 10:57:57 +0300 Message-ID: <20260608075801.16111-5-adrian.hunter@intel.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260608075801.16111-1-adrian.hunter@intel.com> References: <20260608075801.16111-1-adrian.hunter@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Organization: Intel Finland Oy, Registered Address: c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" i3c_master_add_i3c_dev_locked() no longer leaves the address marked as free on failure, so aborting the DAA sequence on its error is unnecessary. Failure to register a discovered device does not invalidate the entire Dynamic Address Assignment (DAA) procedure. Align with the behavior of other I3C master drivers by ignoring errors from i3c_master_add_i3c_dev_locked() and continuing enumeration. Signed-off-by: Adrian Hunter Reviewed-by: Frank Li --- Changes in V2: None drivers/i3c/master/mipi-i3c-hci/cmd_v1.c | 4 +--- drivers/i3c/master/mipi-i3c-hci/cmd_v2.c | 4 +--- 2 files changed, 2 insertions(+), 6 deletions(-) diff --git a/drivers/i3c/master/mipi-i3c-hci/cmd_v1.c b/drivers/i3c/master/= mipi-i3c-hci/cmd_v1.c index 75d452d7f6af..3b9345718d27 100644 --- a/drivers/i3c/master/mipi-i3c-hci/cmd_v1.c +++ b/drivers/i3c/master/mipi-i3c-hci/cmd_v1.c @@ -358,9 +358,7 @@ static int hci_cmd_v1_daa(struct i3c_hci *hci) * TODO: Extend the subsystem layer to allow for registering * new device and provide BCR/DCR/PID at the same time. */ - ret =3D i3c_master_add_i3c_dev_locked(&hci->master, next_addr); - if (ret) - break; + i3c_master_add_i3c_dev_locked(&hci->master, next_addr); } =20 if (dat_idx >=3D 0) diff --git a/drivers/i3c/master/mipi-i3c-hci/cmd_v2.c b/drivers/i3c/master/= mipi-i3c-hci/cmd_v2.c index 39eec26a363c..8d93748e858d 100644 --- a/drivers/i3c/master/mipi-i3c-hci/cmd_v2.c +++ b/drivers/i3c/master/mipi-i3c-hci/cmd_v2.c @@ -296,9 +296,7 @@ static int hci_cmd_v2_daa(struct i3c_hci *hci) * TODO: Extend the subsystem layer to allow for registering * new device and provide BCR/DCR/PID at the same time. */ - ret =3D i3c_master_add_i3c_dev_locked(&hci->master, next_addr); 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charset="utf-8" The return value of i3c_master_add_i3c_dev_locked() is not used by any caller, and callers are not in a position to recover from failures in this path. Change the function to return void. Amend the kernel-doc accordingly, fix some grammar and remove a stale paragraph. Signed-off-by: Adrian Hunter Reviewed-by: Frank Li --- Changes in V2: Re-base due to changes in previous patches. drivers/i3c/master.c | 17 ++++------------- include/linux/i3c/master.h | 3 +-- 2 files changed, 5 insertions(+), 15 deletions(-) diff --git a/drivers/i3c/master.c b/drivers/i3c/master.c index 7b60b0c7f646..57857a3351c7 100644 --- a/drivers/i3c/master.c +++ b/drivers/i3c/master.c @@ -2324,19 +2324,12 @@ i3c_master_search_i3c_dev_duplicate(struct i3c_dev_= desc *refdev) * @master: master used to send frames on the bus * @addr: I3C slave dynamic address assigned to the device * - * This function is instantiating an I3C device object and adding it to the - * I3C device list. All device information are automatically retrieved usi= ng - * standard CCC commands. - * - * The I3C device object is returned in case the master wants to attach - * private data to it using i3c_dev_set_master_data(). + * This function instantiates an I3C device object and adds it to the I3C = device + * list. All device information is retrieved using standard CCC commands. * * This function must be called with the bus lock held in write mode. - * - * Return: a 0 in case of success, an negative error code otherwise. */ -int i3c_master_add_i3c_dev_locked(struct i3c_master_controller *master, - u8 addr) +void i3c_master_add_i3c_dev_locked(struct i3c_master_controller *master, u= 8 addr) { struct i3c_device_info info =3D { .dyn_addr =3D addr }; struct i3c_dev_desc *newdev, *olddev; @@ -2460,7 +2453,7 @@ int i3c_master_add_i3c_dev_locked(struct i3c_master_c= ontroller *master, mutex_unlock(&newdev->ibi_lock); } =20 - return 0; + return; =20 err_detach_dev: if (newdev->dev && newdev->dev->desc) @@ -2480,8 +2473,6 @@ int i3c_master_add_i3c_dev_locked(struct i3c_master_c= ontroller *master, i3c_bus_set_addr_slot_status(&master->bus, addr, I3C_ADDR_SLOT_I3C_DEV); =20 dev_err(&master->dev, "Failed to add I3C device at address %u, error %d\n= ", addr, ret); - - return ret; } EXPORT_SYMBOL_GPL(i3c_master_add_i3c_dev_locked); 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a="85520181" X-IronPort-AV: E=Sophos;i="6.24,194,1774335600"; d="scan'208";a="85520181" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jun 2026 00:58:35 -0700 X-CSE-ConnectionGUID: i2sJbUHNRzukRfKknfgZGQ== X-CSE-MsgGUID: FE3L0oZ8TnqSq0Am3n9cvA== X-ExtLoop1: 1 Received: from conormcd-mobl2.ger.corp.intel.com (HELO ahunter6-desk) ([10.245.244.114]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jun 2026 00:58:33 -0700 From: Adrian Hunter To: alexandre.belloni@bootlin.com Cc: Frank.Li@nxp.com, linux-i3c@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH V2 6/7] i3c: master: Move DAA API functions after i3c_master_add_i3c_dev_locked() Date: Mon, 8 Jun 2026 10:57:59 +0300 Message-ID: <20260608075801.16111-7-adrian.hunter@intel.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260608075801.16111-1-adrian.hunter@intel.com> References: <20260608075801.16111-1-adrian.hunter@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Organization: Intel Finland Oy, Registered Address: c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Relocate i3c_master_do_daa_ext() and i3c_master_do_daa() so they appear after i3c_master_add_i3c_dev_locked(). This ordering is required for upcoming changes where the DAA flow will (indirectly) rely on i3c_master_add_i3c_dev_locked() functionality. Reordering avoids forward dependency issues and keeps related code paths logically arranged. No functional change. Signed-off-by: Adrian Hunter Reviewed-by: Frank Li --- Changes in V2: None drivers/i3c/master.c | 128 +++++++++++++++++++++---------------------- 1 file changed, 64 insertions(+), 64 deletions(-) diff --git a/drivers/i3c/master.c b/drivers/i3c/master.c index 57857a3351c7..5021d25b718a 100644 --- a/drivers/i3c/master.c +++ b/drivers/i3c/master.c @@ -1870,70 +1870,6 @@ static void i3c_master_reg_work_fn(struct work_struc= t *work) i3c_bus_normaluse_unlock(&master->bus); } =20 -/** - * i3c_master_do_daa_ext() - Dynamic Address Assignment (extended version) - * @master: controller - * @rstdaa: whether to first perform Reset of Dynamic Addresses (RSTDAA) - * - * Perform Dynamic Address Assignment with optional support for System - * Hibernation (@rstdaa is true). - * - * After System Hibernation, Dynamic Addresses can have been reassigned at= boot - * time to different values. A simple strategy is followed to handle that. - * Perform a Reset of Dynamic Addresses (RSTDAA) followed by the normal DAA - * procedure which has provision for reassigning addresses that differ fro= m the - * previously recorded addresses. - * - * Return: a 0 in case of success, an negative error code otherwise. - */ -int i3c_master_do_daa_ext(struct i3c_master_controller *master, bool rstda= a) -{ - int rstret =3D 0; - int ret; - - ret =3D i3c_master_rpm_get(master); - if (ret) - return ret; - - i3c_bus_maintenance_lock(&master->bus); - - if (master->shutting_down) { - ret =3D -ENODEV; - } else { - if (rstdaa) - rstret =3D i3c_master_rstdaa_locked(master, I3C_BROADCAST_ADDR); - ret =3D master->ops->do_daa(master); - } - - i3c_bus_maintenance_unlock(&master->bus); - - if (ret) - goto out; - - queue_work(master->wq, &master->reg_work); -out: - i3c_master_rpm_put(master); - - return rstret ?: ret; -} -EXPORT_SYMBOL_GPL(i3c_master_do_daa_ext); - -/** - * i3c_master_do_daa() - do a DAA (Dynamic Address Assignment) - * @master: master doing the DAA - * - * This function instantiates I3C device objects and adds them to the - * I3C device list. All device information is automatically retrieved using - * standard CCC commands. - * - * Return: a 0 in case of success, an negative error code otherwise. - */ -int i3c_master_do_daa(struct i3c_master_controller *master) -{ - return i3c_master_do_daa_ext(master, false); -} -EXPORT_SYMBOL_GPL(i3c_master_do_daa); - /** * i3c_master_dma_map_single() - Map buffer for single DMA transfer * @dev: device object of a device doing DMA @@ -2476,6 +2412,70 @@ void i3c_master_add_i3c_dev_locked(struct i3c_master= _controller *master, u8 addr } EXPORT_SYMBOL_GPL(i3c_master_add_i3c_dev_locked); =20 +/** + * i3c_master_do_daa_ext() - Dynamic Address Assignment (extended version) + * @master: controller + * @rstdaa: whether to first perform Reset of Dynamic Addresses (RSTDAA) + * + * Perform Dynamic Address Assignment with optional support for System + * Hibernation (@rstdaa is true). + * + * After System Hibernation, Dynamic Addresses can have been reassigned at= boot + * time to different values. A simple strategy is followed to handle that. + * Perform a Reset of Dynamic Addresses (RSTDAA) followed by the normal DAA + * procedure which has provision for reassigning addresses that differ fro= m the + * previously recorded addresses. + * + * Return: a 0 in case of success, an negative error code otherwise. + */ +int i3c_master_do_daa_ext(struct i3c_master_controller *master, bool rstda= a) +{ + int rstret =3D 0; + int ret; + + ret =3D i3c_master_rpm_get(master); + if (ret) + return ret; + + i3c_bus_maintenance_lock(&master->bus); + + if (master->shutting_down) { + ret =3D -ENODEV; + } else { + if (rstdaa) + rstret =3D i3c_master_rstdaa_locked(master, I3C_BROADCAST_ADDR); + ret =3D master->ops->do_daa(master); + } + + i3c_bus_maintenance_unlock(&master->bus); + + if (ret) + goto out; + + queue_work(master->wq, &master->reg_work); +out: + i3c_master_rpm_put(master); + + return rstret ?: ret; +} +EXPORT_SYMBOL_GPL(i3c_master_do_daa_ext); + +/** + * i3c_master_do_daa() - do a DAA (Dynamic Address Assignment) + * @master: master doing the DAA + * + * This function instantiates I3C device objects and adds them to the + * I3C device list. All device information is automatically retrieved using + * standard CCC commands. + * + * Return: a 0 in case of success, an negative error code otherwise. + */ +int i3c_master_do_daa(struct i3c_master_controller *master) +{ + return i3c_master_do_daa_ext(master, false); +} +EXPORT_SYMBOL_GPL(i3c_master_do_daa); + #define OF_I3C_REG1_IS_I2C_DEV BIT(31) =20 static int --=20 2.51.0 From nobody Mon Jun 8 18:55:14 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C11E039EF01 for ; Mon, 8 Jun 2026 07:58:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780905518; cv=none; b=eP+k31lqHEfnf+hVZYG5/aUSdJ3n0CKkWp2z/GkLgAGU2j2We+G/ykQNx7vQ3J5yNlU/TknW0n4mwHLLjoU41wt8C4C0CBIqlKsDmqvtlXUwKiiLw3QkNCfSv6tSNBlQB0N356uhncImGZV61kmmOVLjPTJ0dzRwpKZACXtWGQk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780905518; c=relaxed/simple; bh=/K778kDQiYfBKcoTakZhRrXmBNRAUTzaDUM7r1a03Hc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Rcd2QCT/X5+ai0fbLGpAp62X7pUnubHxhCobXO9U2JoXxngEfPzhbpf9igH9ye/fg+TZg2+ZSVYf6pFTdX/lQaDRUP2bm05tqpqDW6H3gPNIK18QyHJmaqolmNZWkumdYs+JHy57i2xlvEI070rgwHaOx8VA0XG+qo37ZF2Dwl4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Q6hW0ReT; arc=none smtp.client-ip=198.175.65.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Q6hW0ReT" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1780905517; x=1812441517; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=/K778kDQiYfBKcoTakZhRrXmBNRAUTzaDUM7r1a03Hc=; b=Q6hW0ReTFYxUTlPLhIrDwA5hCay3Bebqf8UnCKyVyHzP2dlRRlMvrZMY 3CBStuqOJXt3CyPRbE5sBZtbHlhOwy5LA8jfQI4fAh35NROVpdkozsNIU jEAAscviQAFH7R+HEf0WzEqV4x4NHYCgjWoxWSEvLBj/HN3KqcRymdKWv ntTrAnYSNHt3K5nDMwDhjgoXNC/hVJgjVXeeWSsxlrNutekSceQfgN8Z1 rQW5JcD75FQeY3zuTyHauyk3R/UYxBYY/YQzjp1jOjtNY4ALf0ceVZTpB fmvuJZEwu5EDnjpOeeU4+163dTS6Yh8yHmNVilvqujwYHmm6Rve8U5PRT w==; X-CSE-ConnectionGUID: 6SPPiMbDSBylVX0nsay2Yw== X-CSE-MsgGUID: vER4+6oTRciEJrw0yDOuXA== X-IronPort-AV: E=McAfee;i="6800,10657,11810"; a="85520186" X-IronPort-AV: E=Sophos;i="6.24,194,1774335600"; d="scan'208";a="85520186" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jun 2026 00:58:37 -0700 X-CSE-ConnectionGUID: 0hqzpw7PRTuYrZMAkD07Dg== X-CSE-MsgGUID: G+SS3NhLTmu6PLMRDAfVeg== X-ExtLoop1: 1 Received: from conormcd-mobl2.ger.corp.intel.com (HELO ahunter6-desk) ([10.245.244.114]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Jun 2026 00:58:35 -0700 From: Adrian Hunter To: alexandre.belloni@bootlin.com Cc: Frank.Li@nxp.com, linux-i3c@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH V2 7/7] i3c: master: Reconcile dynamic addresses after DAA Date: Mon, 8 Jun 2026 10:58:00 +0300 Message-ID: <20260608075801.16111-8-adrian.hunter@intel.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260608075801.16111-1-adrian.hunter@intel.com> References: <20260608075801.16111-1-adrian.hunter@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Organization: Intel Finland Oy, Registered Address: c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" After Dynamic Address Assignment (DAA), there may be cases where devices have been assigned dynamic addresses on the bus, but are not successfully registered in the device model. This can happen, for example, if errors occur during device addition, leaving the bus state and software state inconsistent. Introduce a reconciliation step to resolve such inconsistencies. Scan all address slots marked as I3C devices by the bus, and compare them against the set of devices currently registered. For any dynamic address that is marked occupied but has no corresponding i3c_dev_desc, probe for device presence using a GETSTATUS CCC. Retry the probe (with exponential backoff delay) to handle transient NACK conditions. If a device responds, register it via i3c_master_add_i3c_dev_locked(). Otherwise, free the address slot so it may be reused in future DAA operations. Note, i3c_master_add_i3c_dev_locked() may fail (again), in which case the dynamic address remains marked as occupied. A future DAA will try again. This also handles a corner case where a device is assigned a dynamic address but not successfully added, and subsequently loses that address (e.g. due to power management). If DAA is run again, the device may receive a new dynamic address while the old one remains marked as occupied. Repeated occurrences of this scenario could eventually exhaust the dynamic address space. The reconciliation step ensures that stale addresses are detected and freed, preventing address leakage. Signed-off-by: Adrian Hunter --- Changes in V2: Add bitmap.h include for bitmap_zero() etc. Re-base due to changes in previous patches. drivers/i3c/master.c | 115 ++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 113 insertions(+), 2 deletions(-) diff --git a/drivers/i3c/master.c b/drivers/i3c/master.c index 5021d25b718a..6656c8591fab 100644 --- a/drivers/i3c/master.c +++ b/drivers/i3c/master.c @@ -6,7 +6,9 @@ */ =20 #include +#include #include +#include #include #include #include @@ -1613,6 +1615,56 @@ static int i3c_master_retrieve_dev_info(struct i3c_d= ev_desc *dev) return 0; } =20 +static int i3c_master_getstatus_locked(struct i3c_master_controller *maste= r, + u8 addr, u16 *status) +{ + struct i3c_ccc_getstatus *getstatus; + struct i3c_ccc_cmd_dest dest; + struct i3c_ccc_cmd cmd; + int ret; + + getstatus =3D i3c_ccc_cmd_dest_init(&dest, addr, sizeof(*getstatus)); + if (!getstatus) + return -ENOMEM; + + i3c_ccc_cmd_init(&cmd, true, I3C_CCC_GETSTATUS, &dest, 1); + ret =3D i3c_master_send_ccc_cmd_locked(master, &cmd); + if (ret) + goto out; + + if (dest.payload.len !=3D sizeof(*getstatus)) { + ret =3D -EIO; + goto out; + } + + if (status) + *status =3D be16_to_cpu(getstatus->status); +out: + i3c_ccc_cmd_dest_cleanup(&dest); + + return ret; +} + +#define I3C_DEV_PROBE_INITIAL_DELAY_US 20 +#define I3C_DEV_PROBE_DELAY_FACTOR 2 +#define I3C_DEV_PROBE_CNT 5 + +static bool i3c_master_i3c_dev_present(struct i3c_master_controller *maste= r, unsigned int addr) +{ + int delay =3D I3C_DEV_PROBE_INITIAL_DELAY_US; + + for (int i =3D 0; i < I3C_DEV_PROBE_CNT; i++) { + if (i) { + fsleep(delay); + delay *=3D I3C_DEV_PROBE_DELAY_FACTOR; + } + if (!i3c_master_getstatus_locked(master, addr, NULL)) + return true; + } + + return false; +} + static void i3c_master_put_i3c_addrs(struct i3c_dev_desc *dev) { struct i3c_master_controller *master =3D i3c_dev_get_master(dev); @@ -2256,22 +2308,25 @@ i3c_master_search_i3c_dev_duplicate(struct i3c_dev_= desc *refdev) } =20 /** - * i3c_master_add_i3c_dev_locked() - add an I3C slave to the bus + * __i3c_master_add_i3c_dev_locked() - add an I3C slave to the bus * @master: master used to send frames on the bus * @addr: I3C slave dynamic address assigned to the device + * @probe: probe to see if the device is really present at @addr * * This function instantiates an I3C device object and adds it to the I3C = device * list. All device information is retrieved using standard CCC commands. * * This function must be called with the bus lock held in write mode. */ -void i3c_master_add_i3c_dev_locked(struct i3c_master_controller *master, u= 8 addr) +static void __i3c_master_add_i3c_dev_locked(struct i3c_master_controller *= master, + u8 addr, bool probe) { struct i3c_device_info info =3D { .dyn_addr =3D addr }; struct i3c_dev_desc *newdev, *olddev; u8 old_dyn_addr =3D addr, expected_dyn_addr; struct i3c_ibi_setup ibireq =3D { }; bool enable_ibi =3D false; + bool no_dev =3D false; int ret; =20 newdev =3D i3c_master_alloc_i3c_dev(master, &info); @@ -2284,6 +2339,18 @@ void i3c_master_add_i3c_dev_locked(struct i3c_master= _controller *master, u8 addr if (ret) goto err_free_dev; =20 + /* + * When a dynamic address is first assigned, there is no need to check + * whether it is still assigned, however, if adding the device fails, + * it will be attempted again later, at which point the address may + * have been lost (e.g. due to power management), so for that case, + * probe to see if the device is still present at the assigned address. + */ + if (probe && !i3c_master_i3c_dev_present(master, addr)) { + no_dev =3D true; + goto err_detach_dev; + } + ret =3D i3c_master_retrieve_dev_info(newdev); if (ret) goto err_detach_dev; @@ -2401,6 +2468,8 @@ void i3c_master_add_i3c_dev_locked(struct i3c_master_= controller *master, u8 addr i3c_master_free_i3c_dev(newdev); =20 err_prevent_addr_reuse: + if (no_dev) + return; /* * Although the device has not been added, the address has been * assigned. Prevent the address from being used again. @@ -2410,8 +2479,45 @@ void i3c_master_add_i3c_dev_locked(struct i3c_master= _controller *master, u8 addr =20 dev_err(&master->dev, "Failed to add I3C device at address %u, error %d\n= ", addr, ret); } + +/** + * i3c_master_add_i3c_dev_locked() - add an I3C slave to the bus + * @master: master used to send frames on the bus + * @addr: I3C slave dynamic address assigned to the device + * + * This function instantiates an I3C device object and adds it to the + * I3C device list. All device information is automatically retrieved using + * standard CCC commands. + * + * This function must be called with the bus lock held in write mode. + */ +void i3c_master_add_i3c_dev_locked(struct i3c_master_controller *master, u= 8 addr) +{ + __i3c_master_add_i3c_dev_locked(master, addr, false); +} EXPORT_SYMBOL_GPL(i3c_master_add_i3c_dev_locked); =20 +static void i3c_master_reconcile_dyn_addrs(struct i3c_master_controller *m= aster) +{ + DECLARE_BITMAP(dev_dyn_addrs, I2C_MAX_ADDR + 1); + enum i3c_addr_slot_status status; + struct i3c_dev_desc *desc; + + /* Mark all devices' dynamic addresses in the bitmap */ + bitmap_zero(dev_dyn_addrs, I2C_MAX_ADDR + 1); + i3c_bus_for_each_i3cdev(&master->bus, desc) + __set_bit(desc->info.dyn_addr, dev_dyn_addrs); + /* Reconcile the bitmap with the bus address slot status */ + for (unsigned int addr =3D 0; addr <=3D I2C_MAX_ADDR; addr++) { + status =3D i3c_bus_get_addr_slot_status(&master->bus, addr); + if (status !=3D I3C_ADDR_SLOT_I3C_DEV || test_bit(addr, dev_dyn_addrs)) + continue; + i3c_bus_set_addr_slot_status(&master->bus, addr, I3C_ADDR_SLOT_FREE); + /* Try to add the device, but probe to see if it is really present */ + __i3c_master_add_i3c_dev_locked(master, addr, true); + } +} + /** * i3c_master_do_daa_ext() - Dynamic Address Assignment (extended version) * @master: controller @@ -2445,6 +2551,11 @@ int i3c_master_do_daa_ext(struct i3c_master_controll= er *master, bool rstdaa) if (rstdaa) rstret =3D i3c_master_rstdaa_locked(master, I3C_BROADCAST_ADDR); ret =3D master->ops->do_daa(master); + /* + * Handle cases where a dynamic address was assigned but the + * device was not successfully added. + */ + i3c_master_reconcile_dyn_addrs(master); } =20 i3c_bus_maintenance_unlock(&master->bus); --=20 2.51.0