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charset="utf-8" From: Tanmay Jagdale The TAD PMU exposes counters that can be filtered by MPAM partition id for a subset of allocation and hit events. Add a 16-bit partid format attribute (config1) and route counter programming through variant-specific ops so CN10K keeps MPAM-capable programming while Odyssey keeps the reduced event set without advertising partid in sysfs. Example: perf stat -e tad/tad_alloc_any,partid=3D0x12/ -- Signed-off-by: Tanmay Jagdale Signed-off-by: Geetha sowjanya --- drivers/perf/marvell_cn10k_tad_pmu.c | 151 ++++++++++++++++++++------- 1 file changed, 112 insertions(+), 39 deletions(-) diff --git a/drivers/perf/marvell_cn10k_tad_pmu.c b/drivers/perf/marvell_cn= 10k_tad_pmu.c index 51ccb0befa05..7a3b659c999a 100644 --- a/drivers/perf/marvell_cn10k_tad_pmu.c +++ b/drivers/perf/marvell_cn10k_tad_pmu.c @@ -7,6 +7,7 @@ #define pr_fmt(fmt) "tad_pmu: " fmt =20 #include +#include #include #include #include @@ -14,11 +15,13 @@ #include #include =20 -#define TAD_PFC_OFFSET 0x800 -#define TAD_PFC(counter) (TAD_PFC_OFFSET | (counter << 3)) #define TAD_PRF_OFFSET 0x900 -#define TAD_PRF(counter) (TAD_PRF_OFFSET | (counter << 3)) +#define TAD_PFC_OFFSET 0x800 +#define TAD_PFC(base, counter) ((base) | ((u64)(counter) << 3)) +#define TAD_PRF(base, counter) ((base) | ((u64)(counter) << 3)) #define TAD_PRF_CNTSEL_MASK 0xFF +#define TAD_PRF_MATCH_PARTID BIT(8) +#define TAD_PRF_PARTID_NS BIT(10) #define TAD_MAX_COUNTERS 8 =20 #define to_tad_pmu(p) (container_of(p, struct tad_pmu, pmu)) @@ -27,30 +30,92 @@ struct tad_region { void __iomem *base; }; =20 +enum mrvl_tad_pmu_version { + TAD_PMU_V1 =3D 1, + TAD_PMU_V2, +}; + +struct tad_pmu_data { + int id; + u64 tad_prf_offset; + u64 tad_pfc_offset; +}; + struct tad_pmu { struct pmu pmu; struct tad_region *regions; u32 region_cnt; unsigned int cpu; + const struct tad_pmu_ops *ops; + const struct tad_pmu_data *pdata; struct hlist_node node; struct perf_event *events[TAD_MAX_COUNTERS]; DECLARE_BITMAP(counters_map, TAD_MAX_COUNTERS); }; =20 -enum mrvl_tad_pmu_version { - TAD_PMU_V1 =3D 1, - TAD_PMU_V2, -}; - -struct tad_pmu_data { - int id; +struct tad_pmu_ops { + void (*start_counter)(struct tad_pmu *pmu, struct perf_event *event); }; =20 static int tad_pmu_cpuhp_state; =20 +static void tad_pmu_start_counter(struct tad_pmu *pmu, + struct perf_event *event) +{ + const struct tad_pmu_data *pdata =3D pmu->pdata; + struct hw_perf_event *hwc =3D &event->hw; + u32 event_idx =3D event->attr.config; + u32 counter_idx =3D hwc->idx; + u64 partid_filter =3D 0; + u64 reg_val; + u32 partid; + int i; + + partid =3D (u32)(event->attr.config1 & GENMASK(15, 0)); + + for (i =3D 0; i < pmu->region_cnt; i++) + writeq_relaxed(0, pmu->regions[i].base + + TAD_PFC(pdata->tad_pfc_offset, counter_idx)); + + if (partid && event_idx > 0x19 && event_idx < 0x21) { + partid_filter =3D TAD_PRF_MATCH_PARTID | TAD_PRF_PARTID_NS | + ((u64)partid << 11); + } + + + for (i =3D 0; i < pmu->region_cnt; i++) { + reg_val =3D event_idx & 0xFF; + reg_val |=3D partid_filter; + writeq_relaxed(reg_val, pmu->regions[i].base + + TAD_PRF(pdata->tad_prf_offset, counter_idx)); + } +} + +static void tad_pmu_v2_start_counter(struct tad_pmu *pmu, + struct perf_event *event) +{ + const struct tad_pmu_data *pdata =3D pmu->pdata; + struct hw_perf_event *hwc =3D &event->hw; + u32 event_idx =3D event->attr.config; + u32 counter_idx =3D hwc->idx; + u64 reg_val; + int i; + + for (i =3D 0; i < pmu->region_cnt; i++) + writeq_relaxed(0, pmu->regions[i].base + + TAD_PFC(pdata->tad_pfc_offset, counter_idx)); + + for (i =3D 0; i < pmu->region_cnt; i++) { + reg_val =3D event_idx & 0xFF; + writeq_relaxed(reg_val, pmu->regions[i].base + + TAD_PRF(pdata->tad_prf_offset, counter_idx)); + } +} + static void tad_pmu_event_counter_read(struct perf_event *event) { struct tad_pmu *tad_pmu =3D to_tad_pmu(event->pmu); + const struct tad_pmu_data *pdata =3D tad_pmu->pdata; struct hw_perf_event *hwc =3D &event->hw; u32 counter_idx =3D hwc->idx; u64 prev, new; @@ -60,7 +125,7 @@ static void tad_pmu_event_counter_read(struct perf_event= *event) prev =3D local64_read(&hwc->prev_count); for (i =3D 0, new =3D 0; i < tad_pmu->region_cnt; i++) new +=3D readq(tad_pmu->regions[i].base + - TAD_PFC(counter_idx)); + TAD_PFC(pdata->tad_pfc_offset, counter_idx)); } while (local64_cmpxchg(&hwc->prev_count, prev, new) !=3D prev); =20 local64_add(new - prev, &event->count); @@ -69,16 +134,14 @@ static void tad_pmu_event_counter_read(struct perf_eve= nt *event) static void tad_pmu_event_counter_stop(struct perf_event *event, int flags) { struct tad_pmu *tad_pmu =3D to_tad_pmu(event->pmu); + const struct tad_pmu_data *pdata =3D tad_pmu->pdata; struct hw_perf_event *hwc =3D &event->hw; u32 counter_idx =3D hwc->idx; int i; =20 - /* TAD()_PFC() stop counting on the write - * which sets TAD()_PRF()[CNTSEL] =3D=3D 0 - */ for (i =3D 0; i < tad_pmu->region_cnt; i++) { writeq_relaxed(0, tad_pmu->regions[i].base + - TAD_PRF(counter_idx)); + TAD_PRF(pdata->tad_prf_offset, counter_idx)); } =20 tad_pmu_event_counter_read(event); @@ -89,26 +152,10 @@ static void tad_pmu_event_counter_start(struct perf_ev= ent *event, int flags) { struct tad_pmu *tad_pmu =3D to_tad_pmu(event->pmu); struct hw_perf_event *hwc =3D &event->hw; - u32 event_idx =3D event->attr.config; - u32 counter_idx =3D hwc->idx; - u64 reg_val; - int i; =20 hwc->state =3D 0; =20 - /* Typically TAD_PFC() are zeroed to start counting */ - for (i =3D 0; i < tad_pmu->region_cnt; i++) - writeq_relaxed(0, tad_pmu->regions[i].base + - TAD_PFC(counter_idx)); - - /* TAD()_PFC() start counting on the write - * which sets TAD()_PRF()[CNTSEL] !=3D 0 - */ - for (i =3D 0; i < tad_pmu->region_cnt; i++) { - reg_val =3D event_idx & 0xFF; - writeq_relaxed(reg_val, tad_pmu->regions[i].base + - TAD_PRF(counter_idx)); - } + tad_pmu->ops->start_counter(tad_pmu, event); } =20 static void tad_pmu_event_counter_del(struct perf_event *event, int flags) @@ -128,7 +175,6 @@ static int tad_pmu_event_counter_add(struct perf_event = *event, int flags) struct hw_perf_event *hwc =3D &event->hw; int idx; =20 - /* Get a free counter for this event */ idx =3D find_first_zero_bit(tad_pmu->counters_map, TAD_MAX_COUNTERS); if (idx =3D=3D TAD_MAX_COUNTERS) return -EAGAIN; @@ -232,7 +278,7 @@ static struct attribute *ody_tad_pmu_event_attrs[] =3D { TAD_PMU_EVENT_ATTR(tad_hit_ltg, 0x1e), TAD_PMU_EVENT_ATTR(tad_hit_any, 0x1f), TAD_PMU_EVENT_ATTR(tad_tag_rd, 0x20), - TAD_PMU_EVENT_ATTR(tad_tot_cycle, 0xFF), + TAD_PMU_EVENT_ATTR(tad_tot_cycle, 0xff), NULL }; =20 @@ -242,9 +288,11 @@ static const struct attribute_group ody_tad_pmu_events= _attr_group =3D { }; =20 PMU_FORMAT_ATTR(event, "config:0-7"); +PMU_FORMAT_ATTR(partid, "config1:0-15"); =20 static struct attribute *tad_pmu_format_attrs[] =3D { &format_attr_event.attr, + &format_attr_partid.attr, NULL }; =20 @@ -253,6 +301,16 @@ static struct attribute_group tad_pmu_format_attr_grou= p =3D { .attrs =3D tad_pmu_format_attrs, }; =20 +static struct attribute *ody_tad_pmu_format_attrs[] =3D { + &format_attr_event.attr, + NULL +}; + +static struct attribute_group ody_tad_pmu_format_attr_group =3D { + .name =3D "format", + .attrs =3D ody_tad_pmu_format_attrs, +}; + static ssize_t tad_pmu_cpumask_show(struct device *dev, struct device_attribute *attr, char *buf) { @@ -281,11 +339,19 @@ static const struct attribute_group *tad_pmu_attr_gro= ups[] =3D { =20 static const struct attribute_group *ody_tad_pmu_attr_groups[] =3D { &ody_tad_pmu_events_attr_group, - &tad_pmu_format_attr_group, + &ody_tad_pmu_format_attr_group, &tad_pmu_cpumask_attr_group, NULL }; =20 +static const struct tad_pmu_ops tad_pmu_ops =3D { + .start_counter =3D tad_pmu_start_counter, +}; + +static const struct tad_pmu_ops tad_pmu_v2_ops =3D { + .start_counter =3D tad_pmu_v2_start_counter, +}; + static int tad_pmu_probe(struct platform_device *pdev) { const struct tad_pmu_data *dev_data; @@ -312,6 +378,7 @@ static int tad_pmu_probe(struct platform_device *pdev) return -ENODEV; } version =3D dev_data->id; + tad_pmu->pdata =3D dev_data; =20 res =3D platform_get_resource(pdev, IORESOURCE_MEM, 0); if (!res) { @@ -344,7 +411,6 @@ static int tad_pmu_probe(struct platform_device *pdev) if (!regions) return -ENOMEM; =20 - /* ioremap the distributed TAD pmu regions */ for (i =3D 0; i < tad_cnt && res->start < res->end; i++) { regions[i].base =3D devm_ioremap(&pdev->dev, res->start, @@ -374,14 +440,16 @@ static int tad_pmu_probe(struct platform_device *pdev) .read =3D tad_pmu_event_counter_read, }; =20 - if (version =3D=3D TAD_PMU_V1) + if (version =3D=3D TAD_PMU_V1) { tad_pmu->pmu.attr_groups =3D tad_pmu_attr_groups; - else + tad_pmu->ops =3D &tad_pmu_ops; + } else { tad_pmu->pmu.attr_groups =3D ody_tad_pmu_attr_groups; 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Sun, 07 Jun 2026 05:51:12 -0700 (PDT) Received: from DC5-EXCH05.marvell.com (10.69.176.209) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.25; Sun, 7 Jun 2026 05:51:12 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server id 15.2.1544.25 via Frontend Transport; Sun, 7 Jun 2026 05:51:12 -0700 Received: from hyd1soter3.marvell.com (unknown [10.29.37.12]) by maili.marvell.com (Postfix) with ESMTP id 8AACA3F70BA; Sun, 7 Jun 2026 05:51:09 -0700 (PDT) From: Geetha sowjanya To: , , , CC: , , , Subject: [PATCH 2/3] perf: marvell: Add CN20K LLC-TAD PMU support Date: Sun, 7 Jun 2026 18:21:00 +0530 Message-ID: <20260607125101.17778-3-gakula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20260607125101.17778-1-gakula@marvell.com> References: <20260607125101.17778-1-gakula@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjA3MDEyOCBTYWx0ZWRfX9JdUTYcp82bL 04KFZ4at+fUzy9XdhIm6QpSporQPY3PtzMkZPHLN6awae6GiTFzoKMKgP+1r7Ad++Egke5qh761 MN2ydUVlkY0DLqDRaVKzCVc+QfnHcXBsik8iGqqIUYJ7l/EiX9nBjy67VWgrSDZVohMfTwvaCfh XRQmHUj6tREwbfXqq5XS4/awV1jYukX/Q0w8mUDkVboTS48nsBgH+TIpaeUfOoiBkgju8Ll2gfI 421vsU6qLqR3UdeRHrEaUh0GMnOz91jpLeF7Ux3/xvuOmsV6ewu5918uZ9EgVj8Xo6VpjCT+4J0 w3FdaNNpS8fGvcnsbr6ONCKb5ENsCYGz9LkIO42gtj/k+ulbt6ouU01PWldDu+7FE26t8T0dy3R oFGBvBR4hE11xAJBNJz/32w/AAns+DwGs3BxPAJlnz2lulfxPVbQBra3gE2MFfEd9uKLErJWJhr rIMkfSzHrqgJ7rVfSlQ== X-Authority-Analysis: v=2.4 cv=evLvCIpX c=1 sm=1 tr=0 ts=6a256940 cx=c_pps a=rEv8fa4AjpPjGxpoe8rlIQ==:117 a=rEv8fa4AjpPjGxpoe8rlIQ==:17 a=FelO9ux0wxsA:10 a=VkNPw1HP01LnGYTKEx00:22 a=l0iWHRpgs5sLHlkKQ1IR:22 a=TtqV-g6YmW1Jfm2GSLaY:22 a=M5GUcnROAAAA:8 a=Ye5975JmM4DBnxqCyIMA:9 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-ORIG-GUID: QybdIdM_cGL4jEs5nNVnnEq9doSuyz9m X-Proofpoint-GUID: QybdIdM_cGL4jEs5nNVnnEq9doSuyz9m X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-07_03,2026-06-05_02,2025-10-01_01 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" CN20K LLC-TAD uses non-standard PFC/PRF page offsets relative to each TAD region base. Add a TAD_PMU_V3 profile with per-platform register bases, extend the CN10K event map for new counters, and match the block via OF and ACPI. Signed-off-by: Geetha sowjanya --- drivers/perf/marvell_cn10k_tad_pmu.c | 33 +++++++++++++++++++++++++--- 1 file changed, 30 insertions(+), 3 deletions(-) diff --git a/drivers/perf/marvell_cn10k_tad_pmu.c b/drivers/perf/marvell_cn= 10k_tad_pmu.c index 7a3b659c999a..4daf109b89ee 100644 --- a/drivers/perf/marvell_cn10k_tad_pmu.c +++ b/drivers/perf/marvell_cn10k_tad_pmu.c @@ -17,6 +17,8 @@ =20 #define TAD_PRF_OFFSET 0x900 #define TAD_PFC_OFFSET 0x800 +#define TAD_PRF_NS_OFFSET 0x30900 +#define TAD_PFC_NS_OFFSET 0x30800 #define TAD_PFC(base, counter) ((base) | ((u64)(counter) << 3)) #define TAD_PRF(base, counter) ((base) | ((u64)(counter) << 3)) #define TAD_PRF_CNTSEL_MASK 0xFF @@ -33,6 +35,7 @@ struct tad_region { enum mrvl_tad_pmu_version { TAD_PMU_V1 =3D 1, TAD_PMU_V2, + TAD_PMU_V3, }; =20 struct tad_pmu_data { @@ -80,8 +83,14 @@ static void tad_pmu_start_counter(struct tad_pmu *pmu, if (partid && event_idx > 0x19 && event_idx < 0x21) { partid_filter =3D TAD_PRF_MATCH_PARTID | TAD_PRF_PARTID_NS | ((u64)partid << 11); + + if (pdata->id =3D=3D TAD_PMU_V3) + partid_filter =3D TAD_PRF_MATCH_PARTID | BIT_ULL(25) | + ((u64)partid << 10); } =20 + if (pdata->id =3D=3D TAD_PMU_V1 && event_idx > 0x24) + return; =20 for (i =3D 0; i < pmu->region_cnt; i++) { reg_val =3D event_idx & 0xFF; @@ -261,6 +270,18 @@ static struct attribute *tad_pmu_event_attrs[] =3D { TAD_PMU_EVENT_ATTR(tad_dat_rd_byp, 0x22), TAD_PMU_EVENT_ATTR(tad_ifb_occ, 0x23), TAD_PMU_EVENT_ATTR(tad_req_occ, 0x24), + TAD_PMU_EVENT_ATTR(tad_req_msh_out_dtg_evict, 0x25), + TAD_PMU_EVENT_ATTR(tad_req_msh_out_ltg_evict, 0x26), + TAD_PMU_EVENT_ATTR(tad_rsp_msh_out_mpam, 0x28), + TAD_PMU_EVENT_ATTR(tad_replays, 0x29), + TAD_PMU_EVENT_ATTR(tad_req_byp0, 0x2a), + TAD_PMU_EVENT_ATTR(tad_req_byp1, 0x2b), + TAD_PMU_EVENT_ATTR(tad_txreq_byp, 0x2c), + TAD_PMU_EVENT_ATTR(tad_time_in_dslp, 0x2d), + TAD_PMU_EVENT_ATTR(tad_time_elapsed, 0x2e), + TAD_PMU_EVENT_ATTR(tad_req_msh_out_dss_rd_128mrg, 0x2f), + TAD_PMU_EVENT_ATTR(tad_req_msh_out_dss_wr_128mrg, 0x30), + TAD_PMU_EVENT_ATTR(tad_tot_cycle, 0xff), NULL }; =20 @@ -426,7 +447,6 @@ static int tad_pmu_probe(struct platform_device *pdev) tad_pmu->region_cnt =3D tad_cnt; =20 tad_pmu->pmu =3D (struct pmu) { - .module =3D THIS_MODULE, .capabilities =3D PERF_PMU_CAP_NO_EXCLUDE | PERF_PMU_CAP_NO_INTERRUPT, @@ -440,7 +460,7 @@ static int tad_pmu_probe(struct platform_device *pdev) .read =3D tad_pmu_event_counter_read, }; =20 - if (version =3D=3D TAD_PMU_V1) { + if (version =3D=3D TAD_PMU_V1 || version =3D=3D TAD_PMU_V3) { tad_pmu->pmu.attr_groups =3D tad_pmu_attr_groups; tad_pmu->ops =3D &tad_pmu_ops; } else { @@ -482,6 +502,11 @@ static const struct tad_pmu_data tad_pmu_data =3D { .tad_pfc_offset =3D TAD_PFC_OFFSET, }; =20 +static const struct tad_pmu_data tad_pmu_cn20k_data =3D { + .id =3D TAD_PMU_V3, + .tad_prf_offset =3D TAD_PRF_NS_OFFSET, + .tad_pfc_offset =3D TAD_PFC_NS_OFFSET, +}; #endif =20 #ifdef CONFIG_ACPI @@ -495,6 +520,7 @@ static const struct tad_pmu_data tad_pmu_v2_data =3D { #ifdef CONFIG_OF static const struct of_device_id tad_pmu_of_match[] =3D { { .compatible =3D "marvell,cn10k-tad-pmu", .data =3D &tad_pmu_data }, + { .compatible =3D "marvell,cn20k-tad-pmu", .data =3D &tad_pmu_cn20k_data = }, {}, }; #endif @@ -503,6 +529,7 @@ static const struct of_device_id tad_pmu_of_match[] =3D= { static const struct acpi_device_id tad_pmu_acpi_match[] =3D { {"MRVL000B", (kernel_ulong_t)&tad_pmu_data}, {"MRVL000D", (kernel_ulong_t)&tad_pmu_v2_data}, + {"MRVL000F", (kernel_ulong_t)&tad_pmu_cn20k_data}, {}, }; MODULE_DEVICE_TABLE(acpi, tad_pmu_acpi_match); @@ -564,6 +591,6 @@ static void __exit tad_pmu_exit(void) module_init(tad_pmu_init); module_exit(tad_pmu_exit); =20 -MODULE_DESCRIPTION("Marvell CN10K LLC-TAD Perf driver"); +MODULE_DESCRIPTION("Marvell CN10K/CN20K LLC-TAD Perf driver"); MODULE_AUTHOR("Bhaskara Budiredla "); MODULE_LICENSE("GPL v2"); --=20 2.25.1 From nobody Mon Jun 8 04:20:40 2026 Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 301CA1A6822; Sun, 7 Jun 2026 13:05:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Sun, 07 Jun 2026 05:51:16 -0700 (PDT) Received: from DC5-EXCH05.marvell.com (10.69.176.209) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.25; Sun, 7 Jun 2026 05:51:15 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server id 15.2.1544.25 via Frontend Transport; Sun, 7 Jun 2026 05:51:15 -0700 Received: from hyd1soter3.marvell.com (unknown [10.29.37.12]) by maili.marvell.com (Postfix) with ESMTP id AEE213F70C5; Sun, 7 Jun 2026 05:51:12 -0700 (PDT) From: Geetha sowjanya To: , , , CC: , , , Subject: [PATCH 3/3] dt-bindings: perf: marvell: Extend CN10K TAD PMU binding for CN20K Date: Sun, 7 Jun 2026 18:21:01 +0530 Message-ID: <20260607125101.17778-4-gakula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20260607125101.17778-1-gakula@marvell.com> References: <20260607125101.17778-1-gakula@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjA3MDEyOCBTYWx0ZWRfX7i5rzTf4t3Bz k6XEnIA6TnTI+IBPSxZScs0dLR6I9MigGv8ogGoXd9SXOujlSmQpE4MnYBFBzhRbnLJ5N6rqKoc cSL/V9GUlNnpZQ4Q348eJdpHsXWEK89Z0LuELtyMBX8uhSm3y7imjHnfuzH2RkwnLU2IyWNn/++ t6i0alma3eR7M8ym41ptMWlTXis6LICnw9MAB+nus453guVFDPVL/RMFzUgMTXc/VSHpU3zMEtQ Wyi77hsRc9gMuypqmMMcq8YtDWY0sR/D7WucOZq12eY0gtqzMS0uzWQgyD83P5oPzUpG+kJWzoH mgwSgMzZ9663HP3IoFW8TIbbiEyQXh4MfpU3HMXM5E6g7V/vZy1Logrc1ll4RYIB0Owl3vUAvuw tMjoaPdjFU8rUI9j4rLaNh2qPTHm6SUKF7//DlOOg8pg+sjQHlMeU7J8HEtW8V+h88Zz/B4IRSI aGgBcfWJelhxraapTVw== X-Proofpoint-GUID: Knqm4btXgidxs7KvtiAQGoPwpMAezOuj X-Authority-Analysis: v=2.4 cv=bJUm5v+Z c=1 sm=1 tr=0 ts=6a256944 cx=c_pps a=rEv8fa4AjpPjGxpoe8rlIQ==:117 a=rEv8fa4AjpPjGxpoe8rlIQ==:17 a=FelO9ux0wxsA:10 a=VkNPw1HP01LnGYTKEx00:22 a=l0iWHRpgs5sLHlkKQ1IR:22 a=QXcCYyLzdtTjyudCfB6f:22 a=gEfo2CItAAAA:8 a=M5GUcnROAAAA:8 a=rc1d4UPXP1xlpl8uFC8A:9 a=sptkURWiP4Gy88Gu7hUp:22 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-ORIG-GUID: Knqm4btXgidxs7KvtiAQGoPwpMAezOuj X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-07_03,2026-06-05_02,2025-10-01_01 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Allow marvell,cn20k-tad-pmu alongside marvell,cn10k-tad-pmu, document CN20K in the title and description, add a maintainer, and include a CN20K example node with the same required properties as CN10K. Signed-off-by: Geetha sowjanya --- .../bindings/perf/marvell-cn10k-tad.yaml | 20 +++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-) diff --git a/Documentation/devicetree/bindings/perf/marvell-cn10k-tad.yaml = b/Documentation/devicetree/bindings/perf/marvell-cn10k-tad.yaml index 362142252667..1612052b59ae 100644 --- a/Documentation/devicetree/bindings/perf/marvell-cn10k-tad.yaml +++ b/Documentation/devicetree/bindings/perf/marvell-cn10k-tad.yaml @@ -4,23 +4,27 @@ $id: http://devicetree.org/schemas/perf/marvell-cn10k-tad.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# =20 -title: Marvell CN10K LLC-TAD performance monitor +title: Marvell CN10K / CN20K LLC-TAD performance monitor =20 maintainers: - Bhaskara Budiredla + - Geetha sowjanya =20 description: | - The Tag-and-Data units (TADs) maintain coherence and contain CN10K - shared on-chip last level cache (LLC). The tad pmu measures the - performance of last-level cache. Each tad pmu supports up to eight - counters. + The Tag-and-Data units (TADs) maintain coherence and contain the + shared on-chip last level cache (LLC) on Marvell CN10K and CN20K SoCs. + The TAD PMU measures last-level cache performance. Each TAD PMU + supports up to eight counters. =20 - The DT setup comprises of number of tad blocks, the sizes of pmu - regions, tad blocks and overall base address of the HW. + The DT setup describes the number of TAD blocks, the sizes of PMU + regions and TAD pages, and the overall MMIO base of the hardware. =20 properties: compatible: - const: marvell,cn10k-tad-pmu + items: + - enum: + - marvell,cn10k-tad-pmu + - marvell,cn20k-tad-pmu =20 reg: maxItems: 1 --=20 2.25.1