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Sun, 07 Jun 2026 01:11:19 -0700 (PDT) From: Inochi Amaoto To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Anup Patel , Atish Patra , Paolo Bonzini , Shuah Khan , Thomas Huth , Deepak Gupta , Inochi Amaoto , Charlie Jenkins , Sergey Matyukevich Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org, Yixun Lan , Longbin Li , Quan Zhou Subject: [PATCH v3 1/8] RISC-V: KVM: Add support for Svadu FWFT features Date: Sun, 7 Jun 2026 16:10:57 +0800 Message-ID: <20260607081105.993908-2-inochiama@gmail.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260607081105.993908-1-inochiama@gmail.com> References: <20260607081105.993908-1-inochiama@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Hardware updating of PTE A/D bits is controlled through ADUE bit in henvcfg Expose the feature only if both Svadu and Svade are supported for VS-mode. Allow the VMM to enable/disable this feature by change the ISA extension state in the guest. Assisted-by: YuanSheng:claude-4.7-opus Co-developed-by: Quan Zhou Signed-off-by: Quan Zhou Signed-off-by: Inochi Amaoto --- arch/riscv/include/uapi/asm/kvm.h | 1 + arch/riscv/kvm/vcpu_sbi_fwft.c | 75 +++++++++++++++++++++++++++++++ 2 files changed, 76 insertions(+) diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/as= m/kvm.h index 504e73305343..7bbea8812d92 100644 --- a/arch/riscv/include/uapi/asm/kvm.h +++ b/arch/riscv/include/uapi/asm/kvm.h @@ -240,6 +240,7 @@ struct kvm_riscv_sbi_fwft_feature { struct kvm_riscv_sbi_fwft { struct kvm_riscv_sbi_fwft_feature misaligned_deleg; struct kvm_riscv_sbi_fwft_feature pointer_masking; + struct kvm_riscv_sbi_fwft_feature pte_ad_hw_updating; }; =20 /* If you need to interpret the index values, here is the key: */ diff --git a/arch/riscv/kvm/vcpu_sbi_fwft.c b/arch/riscv/kvm/vcpu_sbi_fwft.c index ab39ac464ffd..7192c229a19e 100644 --- a/arch/riscv/kvm/vcpu_sbi_fwft.c +++ b/arch/riscv/kvm/vcpu_sbi_fwft.c @@ -94,6 +94,45 @@ static bool kvm_fwft_is_defined_feature(enum sbi_fwft_fe= ature_t feature) return false; } =20 +static void kvm_sbi_fwft_env_flag_reset_helper(struct kvm_vcpu *vcpu, + u64 flag) +{ + vcpu->arch.cfg.henvcfg &=3D ~flag; +} + +static long kvm_sbi_fwft_env_flag_set_helper(struct kvm_vcpu *vcpu, + struct kvm_sbi_fwft_config *conf, + bool one_reg_access, + unsigned long value, u64 flag) +{ + struct kvm_vcpu_config *cfg =3D &vcpu->arch.cfg; + + if (value =3D=3D 0) + cfg->henvcfg &=3D ~flag; + else if (value =3D=3D 1) + cfg->henvcfg |=3D flag; + else + return SBI_ERR_INVALID_PARAM; + + if (!one_reg_access) { + csr_write(CSR_HENVCFG, vcpu->arch.cfg.henvcfg); + if (IS_ENABLED(CONFIG_32BIT)) + csr_write(CSR_HENVCFGH, vcpu->arch.cfg.henvcfg >> 32); + } + + return SBI_SUCCESS; +} + +static long kvm_sbi_fwft_env_flag_get_helper(struct kvm_vcpu *vcpu, + struct kvm_sbi_fwft_config *conf, + bool one_reg_access, + unsigned long *value, u64 flag) +{ + *value =3D (vcpu->arch.cfg.henvcfg & flag) =3D=3D flag; + + return SBI_SUCCESS; +} + static bool kvm_sbi_fwft_misaligned_delegation_supported(struct kvm_vcpu *= vcpu) { return misaligned_traps_can_delegate(); @@ -137,6 +176,33 @@ static long kvm_sbi_fwft_get_misaligned_delegation(str= uct kvm_vcpu *vcpu, return SBI_SUCCESS; } =20 +static bool kvm_sbi_fwft_pte_ad_hw_updating_supported(struct kvm_vcpu *vcp= u) +{ + return riscv_isa_extension_available(vcpu->arch.isa, SVADU) && + riscv_isa_extension_available(vcpu->arch.isa, SVADE); +} + +static void kvm_sbi_fwft_reset_pte_ad_hw_updating(struct kvm_vcpu *vcpu) +{ + kvm_sbi_fwft_env_flag_reset_helper(vcpu, ENVCFG_ADUE); +} + +static long kvm_sbi_fwft_set_pte_ad_hw_updating(struct kvm_vcpu *vcpu, + struct kvm_sbi_fwft_config *conf, + bool one_reg_access, unsigned long value) +{ + return kvm_sbi_fwft_env_flag_set_helper(vcpu, conf, one_reg_access, + value, ENVCFG_ADUE); +} + +static long kvm_sbi_fwft_get_pte_ad_hw_updating(struct kvm_vcpu *vcpu, + struct kvm_sbi_fwft_config *conf, + bool one_reg_access, unsigned long *value) +{ + return kvm_sbi_fwft_env_flag_get_helper(vcpu, conf, one_reg_access, + value, ENVCFG_ADUE); +} + #ifndef CONFIG_32BIT =20 static bool try_to_set_pmm(unsigned long value) @@ -246,6 +312,15 @@ static const struct kvm_sbi_fwft_feature features[] = =3D { .set =3D kvm_sbi_fwft_set_misaligned_delegation, .get =3D kvm_sbi_fwft_get_misaligned_delegation, }, + { + .id =3D SBI_FWFT_PTE_AD_HW_UPDATING, + .first_reg_num =3D offsetof(struct kvm_riscv_sbi_fwft, pte_ad_hw_updatin= g.enable) / + sizeof(unsigned long), + .supported =3D kvm_sbi_fwft_pte_ad_hw_updating_supported, + .reset =3D kvm_sbi_fwft_reset_pte_ad_hw_updating, + .set =3D kvm_sbi_fwft_set_pte_ad_hw_updating, + .get =3D kvm_sbi_fwft_get_pte_ad_hw_updating, + }, #ifndef CONFIG_32BIT { .id =3D SBI_FWFT_POINTER_MASKING_PMLEN, --=20 2.54.0 From nobody Mon Jun 8 04:25:38 2026 Received: from mail-pl1-f176.google.com (mail-pl1-f176.google.com [209.85.214.176]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B70CE36BCCA for ; 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Sun, 07 Jun 2026 01:11:21 -0700 (PDT) Received: from localhost ([2001:19f0:8000:3e6e:5400:6ff:fe38:3d01]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2c24edbb49bsm15223135ad.38.2026.06.07.01.11.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Jun 2026 01:11:21 -0700 (PDT) From: Inochi Amaoto To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Anup Patel , Atish Patra , Paolo Bonzini , Shuah Khan , Thomas Huth , Deepak Gupta , Inochi Amaoto , Charlie Jenkins , Sergey Matyukevich Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org, Yixun Lan , Longbin Li , Quan Zhou Subject: [PATCH v3 2/8] KVM: riscv: selftests: add Svadu FWFT extension to get-reg-list test Date: Sun, 7 Jun 2026 16:10:58 +0800 Message-ID: <20260607081105.993908-3-inochiama@gmail.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260607081105.993908-1-inochiama@gmail.com> References: <20260607081105.993908-1-inochiama@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The KVM RISC-V allows Svadu FWFT for Guest/VM so add this extension to get-reg-list test. Assisted-by: YuanSheng:claude-4.7-opus Co-developed-by: Quan Zhou Signed-off-by: Quan Zhou Signed-off-by: Inochi Amaoto --- .../selftests/kvm/riscv/get-reg-list.c | 21 +++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c b/tools/testi= ng/selftests/kvm/riscv/get-reg-list.c index cb86cb6b3635..94e33b2ee796 100644 --- a/tools/testing/selftests/kvm/riscv/get-reg-list.c +++ b/tools/testing/selftests/kvm/riscv/get-reg-list.c @@ -745,6 +745,9 @@ static const char *sbi_fwft_id_to_str(__u64 reg_off) case 3: return "KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(point= er_masking.enable)"; case 4: return "KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(point= er_masking.flags)"; case 5: return "KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(point= er_masking.value)"; + case 6: return "KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(pte_a= d_hw_updating.enable)"; + case 7: return "KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(pte_a= d_hw_updating.flags)"; + case 8: return "KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(pte_a= d_hw_updating.value)"; } return strdup_printf("KVM_REG_RISCV_SBI_FWFT | %lld /* UNKNOWN */", reg_o= ff); } @@ -944,6 +947,13 @@ static __u64 sbi_fwft_pointer_masking_regs[] =3D { KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RI= SCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(pointer_masking.value), }; =20 +static __u64 sbi_fwft_pte_ad_hw_updating_regs[] =3D { + KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISC= V_SBI_SINGLE | KVM_RISCV_SBI_EXT_FWFT, + KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RI= SCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(pte_ad_hw_updating.enable), + KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RI= SCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(pte_ad_hw_updating.flags), + KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RI= SCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(pte_ad_hw_updating.value), +}; + static __u64 zicbom_regs[] =3D { KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CONFIG | KVM_REG_RISCV= _CONFIG_REG(zicbom_block_size), KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_REG_RISC= V_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICBOM, @@ -1259,6 +1269,16 @@ static struct vcpu_reg_list config_sbi_fwft_pointer_= masking =3D { }, }; =20 +static struct vcpu_reg_list config_sbi_fwft_pte_ad_hw_updating =3D { + .sublists =3D { + SUBLIST_BASE, + SUBLIST_ISA(svade, SVADE), + SUBLIST_ISA(svadu, SVADU), + SUBLIST_SBI(fwft_pte_ad_hw_updating, FWFT), + {0}, + }, +}; + struct vcpu_reg_list *vcpu_configs[] =3D { &config_sbi_base, &config_sbi_sta, @@ -1268,6 +1288,7 @@ struct vcpu_reg_list *vcpu_configs[] =3D { &config_sbi_mpxy, &config_sbi_fwft_misaligned_deleg, &config_sbi_fwft_pointer_masking, + &config_sbi_fwft_pte_ad_hw_updating, &config_aia, &config_fp_f, &config_fp_d, --=20 2.54.0 From nobody Mon Jun 8 04:25:38 2026 Received: from mail-pj1-f46.google.com (mail-pj1-f46.google.com [209.85.216.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 420CA347BAF for ; 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charset="utf-8" Extend the KVM ISA extension array to allow KVM userspace to detect and enable Zicfiss/Zicfilp extensions for Guest/VM. Assisted-by: YuanSheng:claude-4.7-opus Co-developed-by: Quan Zhou Signed-off-by: Quan Zhou Signed-off-by: Inochi Amaoto --- arch/riscv/include/uapi/asm/kvm.h | 2 ++ arch/riscv/kvm/isa.c | 2 ++ 2 files changed, 4 insertions(+) diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/as= m/kvm.h index 7bbea8812d92..a27de850fa4c 100644 --- a/arch/riscv/include/uapi/asm/kvm.h +++ b/arch/riscv/include/uapi/asm/kvm.h @@ -199,6 +199,8 @@ enum KVM_RISCV_ISA_EXT_ID { KVM_RISCV_ISA_EXT_ZCLSD, KVM_RISCV_ISA_EXT_ZILSD, KVM_RISCV_ISA_EXT_ZALASR, + KVM_RISCV_ISA_EXT_ZICFILP, + KVM_RISCV_ISA_EXT_ZICFISS, KVM_RISCV_ISA_EXT_MAX, }; =20 diff --git a/arch/riscv/kvm/isa.c b/arch/riscv/kvm/isa.c index 1132d909cc25..9852a91fdecc 100644 --- a/arch/riscv/kvm/isa.c +++ b/arch/riscv/kvm/isa.c @@ -65,6 +65,8 @@ static const unsigned long kvm_isa_ext_arr[] =3D { KVM_ISA_EXT_ARR(ZICBOP), KVM_ISA_EXT_ARR(ZICBOZ), KVM_ISA_EXT_ARR(ZICCRSE), + KVM_ISA_EXT_ARR(ZICFILP), + KVM_ISA_EXT_ARR(ZICFISS), KVM_ISA_EXT_ARR(ZICNTR), KVM_ISA_EXT_ARR(ZICOND), KVM_ISA_EXT_ARR(ZICSR), --=20 2.54.0 From nobody Mon Jun 8 04:25:38 2026 Received: from mail-pf1-f181.google.com (mail-pf1-f181.google.com [209.85.210.181]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3D43336BCC4 for ; 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Sun, 07 Jun 2026 01:11:27 -0700 (PDT) Received: from localhost ([2001:19f0:8000:3e6e:5400:6ff:fe38:3d01]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-8428325d9a3sm14192864b3a.34.2026.06.07.01.11.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Jun 2026 01:11:26 -0700 (PDT) From: Inochi Amaoto To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Anup Patel , Atish Patra , Paolo Bonzini , Shuah Khan , Thomas Huth , Deepak Gupta , Inochi Amaoto , Charlie Jenkins , Sergey Matyukevich Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org, Yixun Lan , Longbin Li Subject: [PATCH v3 4/8] RISC-V: KVM: Add ssp context save/restore Date: Sun, 7 Jun 2026 16:11:00 +0800 Message-ID: <20260607081105.993908-5-inochiama@gmail.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260607081105.993908-1-inochiama@gmail.com> References: <20260607081105.993908-1-inochiama@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add ssp context save/restore for guest VCPUs and also add it to the ONE_REG interface to allow its access from user space. Signed-off-by: Inochi Amaoto --- arch/riscv/include/asm/kvm_host.h | 7 ++++ arch/riscv/include/uapi/asm/kvm.h | 8 ++++ arch/riscv/kvm/vcpu.c | 6 +++ arch/riscv/kvm/vcpu_onereg.c | 66 ++++++++++++++++++++++++++++++- 4 files changed, 85 insertions(+), 2 deletions(-) diff --git a/arch/riscv/include/asm/kvm_host.h b/arch/riscv/include/asm/kvm= _host.h index 75b0a951c1bc..54ef83ac2d1e 100644 --- a/arch/riscv/include/asm/kvm_host.h +++ b/arch/riscv/include/asm/kvm_host.h @@ -161,6 +161,10 @@ struct kvm_vcpu_smstateen_csr { unsigned long sstateen0; }; =20 +struct kvm_vcpu_zicfiss_csr { + unsigned long ssp; +}; + struct kvm_vcpu_reset_state { spinlock_t lock; unsigned long pc; @@ -201,6 +205,9 @@ struct kvm_vcpu_arch { /* CPU Smstateen CSR context of Guest VCPU */ struct kvm_vcpu_smstateen_csr smstateen_csr; =20 + /* CPU Zicfiss CSR context of Guest VCPU */ + struct kvm_vcpu_zicfiss_csr zicfiss_csr; + /* CPU reset state of Guest VCPU */ struct kvm_vcpu_reset_state reset_state; =20 diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/as= m/kvm.h index a27de850fa4c..fd4c81697617 100644 --- a/arch/riscv/include/uapi/asm/kvm.h +++ b/arch/riscv/include/uapi/asm/kvm.h @@ -102,6 +102,11 @@ struct kvm_riscv_smstateen_csr { unsigned long sstateen0; }; =20 +/* Zicfiss CSR for KVM_GET_ONE_REG and KVM_SET_ONE_REG */ +struct kvm_riscv_zicfiss_csr { + unsigned long ssp; +}; + /* TIMER registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */ struct kvm_riscv_timer { __u64 frequency; @@ -266,12 +271,15 @@ struct kvm_riscv_sbi_fwft { #define KVM_REG_RISCV_CSR_GENERAL (0x0 << KVM_REG_RISCV_SUBTYPE_SHIFT) #define KVM_REG_RISCV_CSR_AIA (0x1 << KVM_REG_RISCV_SUBTYPE_SHIFT) #define KVM_REG_RISCV_CSR_SMSTATEEN (0x2 << KVM_REG_RISCV_SUBTYPE_SHIFT) +#define KVM_REG_RISCV_CSR_ZICFISS (0x3 << KVM_REG_RISCV_SUBTYPE_SHIFT) #define KVM_REG_RISCV_CSR_REG(name) \ (offsetof(struct kvm_riscv_csr, name) / sizeof(unsigned long)) #define KVM_REG_RISCV_CSR_AIA_REG(name) \ (offsetof(struct kvm_riscv_aia_csr, name) / sizeof(unsigned long)) #define KVM_REG_RISCV_CSR_SMSTATEEN_REG(name) \ (offsetof(struct kvm_riscv_smstateen_csr, name) / sizeof(unsigned long)) +#define KVM_REG_RISCV_CSR_ZICFISS_REG(name) \ + (offsetof(struct kvm_riscv_zicfiss_csr, name) / sizeof(unsigned long)) =20 /* Timer registers are mapped as type 4 */ #define KVM_REG_RISCV_TIMER (0x04 << KVM_REG_RISCV_TYPE_SHIFT) diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c index a73690eda84b..783455db1d4d 100644 --- a/arch/riscv/kvm/vcpu.c +++ b/arch/riscv/kvm/vcpu.c @@ -719,6 +719,7 @@ static void kvm_riscv_update_hvip(struct kvm_vcpu *vcpu) =20 static __always_inline void kvm_riscv_vcpu_swap_in_guest_state(struct kvm_= vcpu *vcpu) { + struct kvm_vcpu_zicfiss_csr *zicficsr =3D &vcpu->arch.zicfiss_csr; struct kvm_vcpu_smstateen_csr *smcsr =3D &vcpu->arch.smstateen_csr; struct kvm_vcpu_csr *csr =3D &vcpu->arch.guest_csr; =20 @@ -726,10 +727,13 @@ static __always_inline void kvm_riscv_vcpu_swap_in_gu= est_state(struct kvm_vcpu * vcpu->arch.host_senvcfg =3D csr_swap(CSR_SENVCFG, csr->senvcfg); if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SMSTATEEN)) vcpu->arch.host_sstateen0 =3D csr_swap(CSR_SSTATEEN0, smcsr->sstateen0); + if (riscv_has_extension_unlikely(RISCV_ISA_EXT_ZICFISS)) + csr_write(CSR_SSP, zicficsr->ssp); } =20 static __always_inline void kvm_riscv_vcpu_swap_in_host_state(struct kvm_v= cpu *vcpu) { + struct kvm_vcpu_zicfiss_csr *zicficsr =3D &vcpu->arch.zicfiss_csr; struct kvm_vcpu_smstateen_csr *smcsr =3D &vcpu->arch.smstateen_csr; struct kvm_vcpu_csr *csr =3D &vcpu->arch.guest_csr; =20 @@ -737,6 +741,8 @@ static __always_inline void kvm_riscv_vcpu_swap_in_host= _state(struct kvm_vcpu *v csr->senvcfg =3D csr_swap(CSR_SENVCFG, vcpu->arch.host_senvcfg); if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SMSTATEEN)) smcsr->sstateen0 =3D csr_swap(CSR_SSTATEEN0, vcpu->arch.host_sstateen0); + if (riscv_has_extension_unlikely(RISCV_ISA_EXT_ZICFISS)) + zicficsr->ssp =3D csr_swap(CSR_SSP, 0); } =20 /* diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c index bb920e8923c9..bd59aebc8b2e 100644 --- a/arch/riscv/kvm/vcpu_onereg.c +++ b/arch/riscv/kvm/vcpu_onereg.c @@ -355,6 +355,44 @@ static int kvm_riscv_vcpu_smstateen_get_csr(struct kvm= _vcpu *vcpu, return 0; } =20 +static inline int kvm_riscv_vcpu_zicfiss_set_csr(struct kvm_vcpu *vcpu, + unsigned long reg_num, + unsigned long reg_val) +{ + struct kvm_vcpu_zicfiss_csr *csr =3D &vcpu->arch.zicfiss_csr; + unsigned long regs_max =3D sizeof(struct kvm_vcpu_zicfiss_csr) / + sizeof(unsigned long); + + if (!riscv_isa_extension_available(vcpu->arch.isa, ZICFISS)) + return -ENOENT; + if (reg_num >=3D regs_max) + return -ENOENT; + + reg_num =3D array_index_nospec(reg_num, regs_max); + + ((unsigned long *)csr)[reg_num] =3D reg_val; + return 0; +} + +static int kvm_riscv_vcpu_zicfiss_get_csr(struct kvm_vcpu *vcpu, + unsigned long reg_num, + unsigned long *out_val) +{ + struct kvm_vcpu_zicfiss_csr *csr =3D &vcpu->arch.zicfiss_csr; + unsigned long regs_max =3D sizeof(struct kvm_vcpu_zicfiss_csr) / + sizeof(unsigned long); + + if (!riscv_isa_extension_available(vcpu->arch.isa, ZICFISS)) + return -ENOENT; + if (reg_num >=3D regs_max) + return -ENOENT; + + reg_num =3D array_index_nospec(reg_num, regs_max); + + *out_val =3D ((unsigned long *)csr)[reg_num]; + return 0; +} + static int kvm_riscv_vcpu_get_reg_csr(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) { @@ -381,6 +419,9 @@ static int kvm_riscv_vcpu_get_reg_csr(struct kvm_vcpu *= vcpu, case KVM_REG_RISCV_CSR_SMSTATEEN: rc =3D kvm_riscv_vcpu_smstateen_get_csr(vcpu, reg_num, ®_val); break; + case KVM_REG_RISCV_CSR_ZICFISS: + rc =3D kvm_riscv_vcpu_zicfiss_get_csr(vcpu, reg_num, ®_val); + break; default: rc =3D -ENOENT; break; @@ -423,6 +464,9 @@ static int kvm_riscv_vcpu_set_reg_csr(struct kvm_vcpu *= vcpu, case KVM_REG_RISCV_CSR_SMSTATEEN: rc =3D kvm_riscv_vcpu_smstateen_set_csr(vcpu, reg_num, reg_val); break; + case KVM_REG_RISCV_CSR_ZICFISS: + rc =3D kvm_riscv_vcpu_zicfiss_set_csr(vcpu, reg_num, reg_val); + break; default: rc =3D -ENOENT; break; @@ -688,7 +732,7 @@ static int copy_csr_reg_indices(const struct kvm_vcpu *= vcpu, u64 __user *uindices) { int n1 =3D sizeof(struct kvm_riscv_csr) / sizeof(unsigned long); - int n2 =3D 0, n3 =3D 0; + int n2 =3D 0, n3 =3D 0, n4 =3D 0; =20 /* copy general csr regs */ for (int i =3D 0; i < n1; i++) { @@ -740,7 +784,25 @@ static int copy_csr_reg_indices(const struct kvm_vcpu = *vcpu, } } =20 - return n1 + n2 + n3; + /* copy Zicfiss csr regs */ + if (riscv_isa_extension_available(vcpu->arch.isa, ZICFISS)) { + n4 =3D sizeof(struct kvm_riscv_zicfiss_csr) / sizeof(unsigned long); + + for (int i =3D 0; i < n4; i++) { + u64 size =3D IS_ENABLED(CONFIG_32BIT) ? + KVM_REG_SIZE_U32 : KVM_REG_SIZE_U64; + u64 reg =3D KVM_REG_RISCV | size | KVM_REG_RISCV_CSR | + KVM_REG_RISCV_CSR_ZICFISS | i; + + if (uindices) { + if (put_user(reg, uindices)) + return -EFAULT; + uindices++; + } + } + } + + return n1 + n2 + n3 + n4; } =20 static inline unsigned long num_timer_regs(void) --=20 2.54.0 From nobody Mon Jun 8 04:25:38 2026 Received: from mail-pj1-f46.google.com (mail-pj1-f46.google.com [209.85.216.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F400836BCCA for ; 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charset="utf-8" The extension Zicfiss/Zicfilp introduces a software-check exception to the privilege architecture. Delegate this exception to VS mode when vCPU enable Zicfiss/Zicfilp so the CFI violations in VU/VS could be reported. Assisted-by: YuanSheng:claude-4.7-opus Co-developed-by: Quan Zhou Signed-off-by: Quan Zhou Signed-off-by: Inochi Amaoto --- arch/riscv/include/asm/csr.h | 1 + arch/riscv/kvm/vcpu_exit.c | 4 ++++ 2 files changed, 5 insertions(+) diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 31b8988f4488..224af9facf1f 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -117,6 +117,7 @@ #define EXC_INST_PAGE_FAULT 12 #define EXC_LOAD_PAGE_FAULT 13 #define EXC_STORE_PAGE_FAULT 15 +#define EXC_SOFTWARE_CHECK 18 #define EXC_INST_GUEST_PAGE_FAULT 20 #define EXC_LOAD_GUEST_PAGE_FAULT 21 #define EXC_VIRTUAL_INST_FAULT 22 diff --git a/arch/riscv/kvm/vcpu_exit.c b/arch/riscv/kvm/vcpu_exit.c index 0bb0c51e3c89..12eebeabdf14 100644 --- a/arch/riscv/kvm/vcpu_exit.c +++ b/arch/riscv/kvm/vcpu_exit.c @@ -243,6 +243,10 @@ int kvm_riscv_vcpu_exit(struct kvm_vcpu *vcpu, struct = kvm_run *run, run->exit_reason =3D KVM_EXIT_DEBUG; ret =3D 0; break; + case EXC_SOFTWARE_CHECK: + if (vcpu->arch.cfg.henvcfg & (ENVCFG_LPE | ENVCFG_SSE)) + ret =3D vcpu_redirect(vcpu, trap); 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Sun, 07 Jun 2026 01:11:31 -0700 (PDT) From: Inochi Amaoto To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Anup Patel , Atish Patra , Paolo Bonzini , Shuah Khan , Thomas Huth , Deepak Gupta , Inochi Amaoto , Charlie Jenkins , Sergey Matyukevich Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org, Yixun Lan , Longbin Li Subject: [PATCH v3 6/8] RISC-V: KVM: Delegate SPELP bit to VS/VU mode if landing pad is enabled. Date: Sun, 7 Jun 2026 16:11:02 +0800 Message-ID: <20260607081105.993908-7-inochiama@gmail.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260607081105.993908-1-inochiama@gmail.com> References: <20260607081105.993908-1-inochiama@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Delegate the newly added SPELP bit from Zicfilp extension to VS/VU mode if it enables landing pad support. Signed-off-by: Inochi Amaoto --- arch/riscv/kvm/vcpu_exit.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/riscv/kvm/vcpu_exit.c b/arch/riscv/kvm/vcpu_exit.c index 12eebeabdf14..61305da5256d 100644 --- a/arch/riscv/kvm/vcpu_exit.c +++ b/arch/riscv/kvm/vcpu_exit.c @@ -154,6 +154,12 @@ void kvm_riscv_vcpu_trap_redirect(struct kvm_vcpu *vcp= u, /* Clear Guest SSTATUS.SIE bit */ vsstatus &=3D ~SR_SIE; =20 + /* Change Guest SSTATUS.SPELP bit */ + if (vcpu->arch.cfg.henvcfg & ENVCFG_LPE) { + vsstatus &=3D ~SR_SPELP; + vsstatus |=3D vcpu->arch.guest_context.sstatus & SR_SPELP; + } + /* Update Guest SSTATUS */ ncsr_write(CSR_VSSTATUS, vsstatus); =20 --=20 2.54.0 From nobody Mon Jun 8 04:25:38 2026 Received: from mail-pf1-f177.google.com (mail-pf1-f177.google.com [209.85.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 910DE1A6803 for ; Sun, 7 Jun 2026 08:11:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Sun, 07 Jun 2026 01:11:33 -0700 (PDT) Received: from localhost ([2001:19f0:8000:3e6e:5400:6ff:fe38:3d01]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-84282882170sm15725254b3a.30.2026.06.07.01.11.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Jun 2026 01:11:33 -0700 (PDT) From: Inochi Amaoto To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Anup Patel , Atish Patra , Paolo Bonzini , Shuah Khan , Thomas Huth , Deepak Gupta , Inochi Amaoto , Charlie Jenkins , Sergey Matyukevich Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org, Yixun Lan , Longbin Li , Quan Zhou Subject: [PATCH v3 7/8] RISC-V: KVM: Add support for control-flow integrity FWFT features Date: Sun, 7 Jun 2026 16:11:03 +0800 Message-ID: <20260607081105.993908-8-inochiama@gmail.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260607081105.993908-1-inochiama@gmail.com> References: <20260607081105.993908-1-inochiama@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Control-flow integrity is controlled through a WARL field in henvcfg. Expose the feature only if the Zicfilp/Zicfiss is supported for VS-mode. Allow the VMM to block access to the feature by disabling the ISA extension in the guest. Assisted-by: YuanSheng:claude-4.7-opus Co-developed-by: Quan Zhou Signed-off-by: Quan Zhou Signed-off-by: Inochi Amaoto --- arch/riscv/include/uapi/asm/kvm.h | 2 + arch/riscv/kvm/vcpu_sbi_fwft.c | 107 ++++++++++++++++++++++++++++++ 2 files changed, 109 insertions(+) diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/as= m/kvm.h index fd4c81697617..20d9959ca44f 100644 --- a/arch/riscv/include/uapi/asm/kvm.h +++ b/arch/riscv/include/uapi/asm/kvm.h @@ -248,6 +248,8 @@ struct kvm_riscv_sbi_fwft { struct kvm_riscv_sbi_fwft_feature misaligned_deleg; struct kvm_riscv_sbi_fwft_feature pointer_masking; struct kvm_riscv_sbi_fwft_feature pte_ad_hw_updating; + struct kvm_riscv_sbi_fwft_feature landing_pad; + struct kvm_riscv_sbi_fwft_feature shadow_stack; }; =20 /* If you need to interpret the index values, here is the key: */ diff --git a/arch/riscv/kvm/vcpu_sbi_fwft.c b/arch/riscv/kvm/vcpu_sbi_fwft.c index 7192c229a19e..cb9b9721ec88 100644 --- a/arch/riscv/kvm/vcpu_sbi_fwft.c +++ b/arch/riscv/kvm/vcpu_sbi_fwft.c @@ -176,6 +176,95 @@ static long kvm_sbi_fwft_get_misaligned_delegation(str= uct kvm_vcpu *vcpu, return SBI_SUCCESS; } =20 +static long kvm_sbi_fwft_set_cfi(struct kvm_vcpu *vcpu, + struct kvm_sbi_fwft_config *conf, + bool one_reg_access, unsigned long value, + u64 flag) +{ + struct kvm_vcpu_config *cfg =3D &vcpu->arch.cfg; + + if (value =3D=3D 0) + cfg->henvcfg &=3D ~flag; + else if (value =3D=3D 1) + cfg->henvcfg |=3D flag; + else + return SBI_ERR_INVALID_PARAM; + + if (cfg->henvcfg & (ENVCFG_LPE | ENVCFG_SSE)) + cfg->hedeleg |=3D EXC_SOFTWARE_CHECK; + else + cfg->hedeleg &=3D ~EXC_SOFTWARE_CHECK; + + if (!one_reg_access) { + csr_write(CSR_HEDELEG, cfg->hedeleg); + /* + * Both Bit LPE and SSE are in the lower part, so it is safe + * to only write the henvcfg + */ + csr_write(CSR_HENVCFG, vcpu->arch.cfg.henvcfg); + } + + return SBI_SUCCESS; +} + +static bool kvm_sbi_fwft_landing_pad_supported(struct kvm_vcpu *vcpu) +{ + return riscv_isa_extension_available(vcpu->arch.isa, ZICFILP); +} + +static void kvm_sbi_fwft_reset_landing_pad(struct kvm_vcpu *vcpu) +{ + struct kvm_vcpu_config *cfg =3D &vcpu->arch.cfg; + + kvm_sbi_fwft_env_flag_reset_helper(vcpu, ENVCFG_LPE); + if ((cfg->henvcfg & (ENVCFG_LPE | ENVCFG_SSE)) =3D=3D 0) + cfg->hedeleg &=3D ~EXC_SOFTWARE_CHECK; +} + +static long kvm_sbi_fwft_set_landing_pad(struct kvm_vcpu *vcpu, + struct kvm_sbi_fwft_config *conf, + bool one_reg_access, unsigned long value) +{ + return kvm_sbi_fwft_set_cfi(vcpu, conf, one_reg_access, value, ENVCFG_LPE= ); +} + +static long kvm_sbi_fwft_get_landing_pad(struct kvm_vcpu *vcpu, + struct kvm_sbi_fwft_config *conf, + bool one_reg_access, unsigned long *value) +{ + return kvm_sbi_fwft_env_flag_get_helper(vcpu, conf, one_reg_access, + value, ENVCFG_LPE); +} + +static bool kvm_sbi_fwft_shadow_stack_supported(struct kvm_vcpu *vcpu) +{ + return riscv_isa_extension_available(vcpu->arch.isa, ZICFISS); +} + +static void kvm_sbi_fwft_reset_shadow_stack(struct kvm_vcpu *vcpu) +{ + struct kvm_vcpu_config *cfg =3D &vcpu->arch.cfg; + + kvm_sbi_fwft_env_flag_reset_helper(vcpu, ENVCFG_SSE); + if ((cfg->henvcfg & (ENVCFG_LPE | ENVCFG_SSE)) =3D=3D 0) + cfg->hedeleg &=3D ~EXC_SOFTWARE_CHECK; +} + +static long kvm_sbi_fwft_set_shadow_stack(struct kvm_vcpu *vcpu, + struct kvm_sbi_fwft_config *conf, + bool one_reg_access, unsigned long value) +{ + return kvm_sbi_fwft_set_cfi(vcpu, conf, one_reg_access, value, ENVCFG_SSE= ); +} + +static long kvm_sbi_fwft_get_shadow_stack(struct kvm_vcpu *vcpu, + struct kvm_sbi_fwft_config *conf, + bool one_reg_access, unsigned long *value) +{ + return kvm_sbi_fwft_env_flag_get_helper(vcpu, conf, one_reg_access, + value, ENVCFG_SSE); +} + static bool kvm_sbi_fwft_pte_ad_hw_updating_supported(struct kvm_vcpu *vcp= u) { return riscv_isa_extension_available(vcpu->arch.isa, SVADU) && @@ -312,6 +401,24 @@ static const struct kvm_sbi_fwft_feature features[] = =3D { .set =3D kvm_sbi_fwft_set_misaligned_delegation, .get =3D kvm_sbi_fwft_get_misaligned_delegation, }, + { + .id =3D SBI_FWFT_LANDING_PAD, + .first_reg_num =3D offsetof(struct kvm_riscv_sbi_fwft, landing_pad.enabl= e) / + sizeof(unsigned long), + .supported =3D kvm_sbi_fwft_landing_pad_supported, + .reset =3D kvm_sbi_fwft_reset_landing_pad, + .set =3D kvm_sbi_fwft_set_landing_pad, + .get =3D kvm_sbi_fwft_get_landing_pad, + }, + { + .id =3D SBI_FWFT_SHADOW_STACK, + .first_reg_num =3D offsetof(struct kvm_riscv_sbi_fwft, shadow_stack.enab= le) / + sizeof(unsigned long), + .supported =3D kvm_sbi_fwft_shadow_stack_supported, + .reset =3D kvm_sbi_fwft_reset_shadow_stack, + .set =3D kvm_sbi_fwft_set_shadow_stack, + .get =3D kvm_sbi_fwft_get_shadow_stack, + }, { .id =3D SBI_FWFT_PTE_AD_HW_UPDATING, .first_reg_num =3D offsetof(struct kvm_riscv_sbi_fwft, pte_ad_hw_updatin= g.enable) / --=20 2.54.0 From nobody Mon Jun 8 04:25:38 2026 Received: from mail-pf1-f178.google.com (mail-pf1-f178.google.com [209.85.210.178]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0A20236C9E5 for ; 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Sun, 07 Jun 2026 01:11:36 -0700 (PDT) Received: from localhost ([2001:19f0:8000:3e6e:5400:6ff:fe38:3d01]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-8428221c3e4sm14946343b3a.5.2026.06.07.01.11.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Jun 2026 01:11:36 -0700 (PDT) From: Inochi Amaoto To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Anup Patel , Atish Patra , Paolo Bonzini , Shuah Khan , Thomas Huth , Deepak Gupta , Inochi Amaoto , Charlie Jenkins , Sergey Matyukevich Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org, Yixun Lan , Longbin Li , Quan Zhou Subject: [PATCH v3 8/8] KVM: riscv: selftests: add Zicfiss/Zicfilp extension to get-reg-list test Date: Sun, 7 Jun 2026 16:11:04 +0800 Message-ID: <20260607081105.993908-9-inochiama@gmail.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260607081105.993908-1-inochiama@gmail.com> References: <20260607081105.993908-1-inochiama@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The KVM RISC-V allows Zicfiss/Zicfilp extensions for Guest/VM so add these extensions to get-reg-list test. Assisted-by: YuanSheng:claude-4.7-opus Co-developed-by: Quan Zhou Signed-off-by: Quan Zhou Signed-off-by: Inochi Amaoto --- .../selftests/kvm/riscv/get-reg-list.c | 67 +++++++++++++++++++ 1 file changed, 67 insertions(+) diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c b/tools/testi= ng/selftests/kvm/riscv/get-reg-list.c index 94e33b2ee796..5963f62ce730 100644 --- a/tools/testing/selftests/kvm/riscv/get-reg-list.c +++ b/tools/testing/selftests/kvm/riscv/get-reg-list.c @@ -90,6 +90,8 @@ bool filter_reg(__u64 reg) case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT= _ZICBOP: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT= _ZICBOZ: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT= _ZICCRSE: + case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT= _ZICFILP: + case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT= _ZICFISS: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT= _ZICNTR: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT= _ZICOND: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT= _ZICSR: @@ -358,6 +360,8 @@ static const char *core_id_to_str(const char *prefix, _= _u64 id) "KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_REG(" #csr ")" #define RISCV_CSR_SMSTATEEN(csr) \ "KVM_REG_RISCV_CSR_SMSTATEEN | KVM_REG_RISCV_CSR_REG(" #csr ")" +#define RISCV_CSR_ZICFISS(csr) \ + "KVM_REG_RISCV_CSR_ZICFISS | KVM_REG_RISCV_CSR_REG(" #csr ")" =20 static const char *general_csr_id_to_str(__u64 reg_off) { @@ -425,6 +429,18 @@ static const char *smstateen_csr_id_to_str(__u64 reg_o= ff) return NULL; } =20 +static const char *zicfiss_csr_id_to_str(__u64 reg_off) +{ + /* reg_off is the offset into struct kvm_riscv_cfi_csr */ + switch (reg_off) { + case KVM_REG_RISCV_CSR_ZICFISS_REG(ssp): + return RISCV_CSR_ZICFISS(ssp); + } + + TEST_FAIL("Unknown zicfiss csr reg: 0x%llx", reg_off); + return NULL; +} + static const char *csr_id_to_str(const char *prefix, __u64 id) { __u64 reg_off =3D id & ~(REG_MASK | KVM_REG_RISCV_CSR); @@ -441,6 +457,8 @@ static const char *csr_id_to_str(const char *prefix, __= u64 id) return aia_csr_id_to_str(reg_off); case KVM_REG_RISCV_CSR_SMSTATEEN: return smstateen_csr_id_to_str(reg_off); + case KVM_REG_RISCV_CSR_ZICFISS: + return zicfiss_csr_id_to_str(reg_off); } =20 return strdup_printf("%lld | %lld /* UNKNOWN */", reg_subtype, reg_off); @@ -585,6 +603,8 @@ static const char *isa_ext_single_id_to_str(__u64 reg_o= ff) KVM_ISA_EXT_ARR(ZICBOP), KVM_ISA_EXT_ARR(ZICBOZ), KVM_ISA_EXT_ARR(ZICCRSE), + KVM_ISA_EXT_ARR(ZICFILP), + KVM_ISA_EXT_ARR(ZICFISS), KVM_ISA_EXT_ARR(ZICNTR), KVM_ISA_EXT_ARR(ZICOND), KVM_ISA_EXT_ARR(ZICSR), @@ -748,6 +768,12 @@ static const char *sbi_fwft_id_to_str(__u64 reg_off) case 6: return "KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(pte_a= d_hw_updating.enable)"; case 7: return "KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(pte_a= d_hw_updating.flags)"; case 8: return "KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(pte_a= d_hw_updating.value)"; + case 9: return "KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(landi= ng_pad.enable)"; + case 10: return "KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(land= ing_pad.flags)"; + case 11: return "KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(land= ing_pad.value)"; + case 12: return "KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(shad= ow_stack.enable)"; + case 13: return "KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(shad= ow_stack.flags)"; + case 14: return "KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(shad= ow_stack.value)"; } return strdup_printf("KVM_REG_RISCV_SBI_FWFT | %lld /* UNKNOWN */", reg_o= ff); } @@ -954,6 +980,18 @@ static __u64 sbi_fwft_pte_ad_hw_updating_regs[] =3D { KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RI= SCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(pte_ad_hw_updating.value), }; =20 +static __u64 sbi_fwft_landing_pad_regs[] =3D { + KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RI= SCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(landing_pad.enable), + KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RI= SCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(landing_pad.flags), + KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RI= SCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(landing_pad.value), +}; + +static __u64 sbi_fwft_shadow_stack_regs[] =3D { + KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RI= SCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(shadow_stack.enable), + KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RI= SCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(shadow_stack.flags), + KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RI= SCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(shadow_stack.value), +}; + static __u64 zicbom_regs[] =3D { KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CONFIG | KVM_REG_RISCV= _CONFIG_REG(zicbom_block_size), KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_REG_RISC= V_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICBOM, @@ -969,6 +1007,11 @@ static __u64 zicboz_regs[] =3D { KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_REG_RISC= V_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICBOZ, }; =20 +static __u64 zicfiss_regs[] =3D { + KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CS= R_ZICFISS | KVM_REG_RISCV_CSR_ZICFISS_REG(ssp), + KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_REG_RISC= V_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICFISS, +}; + static __u64 aia_regs[] =3D { KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CS= R_AIA | KVM_REG_RISCV_CSR_AIA_REG(siselect), KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CS= R_AIA | KVM_REG_RISCV_CSR_AIA_REG(iprio1), @@ -1220,6 +1263,8 @@ KVM_ISA_EXT_SUBLIST_CONFIG(zicbom, ZICBOM); KVM_ISA_EXT_SUBLIST_CONFIG(zicbop, ZICBOP); KVM_ISA_EXT_SUBLIST_CONFIG(zicboz, ZICBOZ); KVM_ISA_EXT_SIMPLE_CONFIG(ziccrse, ZICCRSE); +KVM_ISA_EXT_SIMPLE_CONFIG(zicfilp, ZICFILP); +KVM_ISA_EXT_SUBLIST_CONFIG(zicfiss, ZICFISS); KVM_ISA_EXT_SIMPLE_CONFIG(zicntr, ZICNTR); KVM_ISA_EXT_SIMPLE_CONFIG(zicond, ZICOND); KVM_ISA_EXT_SIMPLE_CONFIG(zicsr, ZICSR); @@ -1279,6 +1324,24 @@ static struct vcpu_reg_list config_sbi_fwft_pte_ad_h= w_updating =3D { }, }; =20 +static struct vcpu_reg_list config_sbi_fwft_landing_pad =3D { + .sublists =3D { + SUBLIST_BASE, + SUBLIST_ISA(zicfilp, ZICFILP), + SUBLIST_SBI(fwft_landing_pad, FWFT), + {0}, + }, +}; + +static struct vcpu_reg_list config_sbi_fwft_shadow_stack =3D { + .sublists =3D { + SUBLIST_BASE, + SUBLIST_ISA(zicfiss, ZICFISS), + SUBLIST_SBI(fwft_shadow_stack, FWFT), + {0}, + }, +}; + struct vcpu_reg_list *vcpu_configs[] =3D { &config_sbi_base, &config_sbi_sta, @@ -1289,6 +1352,8 @@ struct vcpu_reg_list *vcpu_configs[] =3D { &config_sbi_fwft_misaligned_deleg, &config_sbi_fwft_pointer_masking, &config_sbi_fwft_pte_ad_hw_updating, + &config_sbi_fwft_landing_pad, + &config_sbi_fwft_shadow_stack, &config_aia, &config_fp_f, &config_fp_d, @@ -1332,6 +1397,8 @@ struct vcpu_reg_list *vcpu_configs[] =3D { &config_zicbop, &config_zicboz, &config_ziccrse, + &config_zicfilp, + &config_zicfiss, &config_zicntr, &config_zicond, &config_zicsr, --=20 2.54.0